2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/acx/if_acxvar.h,v 1.14 2008/06/08 10:06:05 sephe Exp $
41 #define DPRINTF(x) if_printf x
43 #define DPRINTF(x) ((void)0)
46 #define ACX_FRAME_HDRLEN sizeof(struct ieee80211_frame)
47 #define ACX_MEMBLOCK_SIZE 256
49 #define ACX_TX_DESC_CNT 16
50 #define ACX_RX_DESC_CNT 16
52 #define ACX_TX_RING_SIZE \
53 (2 * ACX_TX_DESC_CNT * sizeof(struct acx_host_desc))
54 #define ACX_RX_RING_SIZE \
55 (ACX_RX_DESC_CNT * sizeof(struct acx_host_desc))
57 #define CSR_READ_1(sc, reg) \
58 bus_space_read_1((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
59 (sc)->chip_ioreg[(reg)])
60 #define CSR_READ_2(sc, reg) \
61 bus_space_read_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
62 (sc)->chip_ioreg[(reg)])
63 #define CSR_READ_4(sc, reg) \
64 bus_space_read_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
65 (sc)->chip_ioreg[(reg)])
67 #define CSR_WRITE_2(sc, reg, val) \
68 bus_space_write_2((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
69 (sc)->chip_ioreg[(reg)], val)
70 #define CSR_WRITE_4(sc, reg, val) \
71 bus_space_write_4((sc)->sc_mem1_bt, (sc)->sc_mem1_bh, \
72 (sc)->chip_ioreg[(reg)], val)
74 #define CSR_SETB_2(sc, reg, b) \
75 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
76 #define CSR_CLRB_2(sc, reg, b) \
77 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
79 #define DESC_READ_1(sc, off) \
80 bus_space_read_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
81 #define DESC_READ_2(sc, off) \
82 bus_space_read_2((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
83 #define DESC_READ_4(sc, off) \
84 bus_space_read_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off))
86 #define DESC_WRITE_1(sc, off, val) \
87 bus_space_write_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
88 #define DESC_WRITE_2(sc, off, val) \
89 bus_space_write_2((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
90 #define DESC_WRITE_4(sc, off, val) \
91 bus_space_write_4((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, (off), (val))
92 #define DESC_WRITE_REGION_1(sc, off, d, dlen) \
93 bus_space_write_region_1((sc)->sc_mem2_bt, (sc)->sc_mem2_bh, \
94 (off), (const uint8_t *)(d), (dlen))
96 #define FW_TXDESC_SETFIELD(sc, mb, field, val, sz) \
97 DESC_WRITE_##sz((sc), (mb)->tb_fwdesc_ofs + \
98 __offsetof(struct acx_fw_txdesc, field), (val))
100 #define FW_TXDESC_GETFIELD(sc, mb, field, sz) \
101 DESC_READ_##sz((sc), (mb)->tb_fwdesc_ofs + \
102 __offsetof(struct acx_fw_txdesc, field))
104 #define FW_TXDESC_SETFIELD_1(sc, mb, field, val) \
105 FW_TXDESC_SETFIELD(sc, mb, field, val, 1)
106 #define FW_TXDESC_SETFIELD_2(sc, mb, field, val) \
107 FW_TXDESC_SETFIELD(sc, mb, field, htole16(val), 2)
108 #define FW_TXDESC_SETFIELD_4(sc, mb, field, val) \
109 FW_TXDESC_SETFIELD(sc, mb, field, htole32(val), 4)
111 #define FW_TXDESC_GETFIELD_1(sc, mb, field) \
112 FW_TXDESC_GETFIELD(sc, mb, field, 1)
113 #define FW_TXDESC_GETFIELD_2(sc, mb, field) \
114 le16toh(FW_TXDESC_GETFIELD(sc, mb, field, 2))
115 #define FW_TXDESC_GETFIELD_4(sc, mb, field) \
116 le32toh(FW_TXDESC_GETFIELD(sc, mb, field, 4))
119 * Firmware TX descriptor
120 * Fields are little endian
122 struct acx_fw_txdesc {
123 uint32_t f_tx_next_desc; /* next acx_fw_txdesc phyaddr */
124 uint32_t f_tx_host_desc; /* acx_host_desc phyaddr */
125 uint32_t f_tx_acx_ptr;
128 uint16_t f_tx_reserved;
130 uint32_t f_tx_dev_spec[4];
132 uint8_t f_tx_ctrl; /* see DESC_CTRL_ */
134 uint8_t f_tx_error; /* see DESC_ERR_ */
135 uint8_t f_tx_data_nretry; /* non-RTS retries */
136 uint8_t f_tx_rts_nretry; /* RTS retries */
139 /* XXX should be moved to chip specific file */
142 uint8_t rate100; /* acx100 tx rate */
146 uint16_t rate111; /* acx111 tx rate */
149 #define f_tx_rate100 u.r1.rate100
150 #define f_tx_queue_ctrl u.r1.queue_ctrl
151 #define f_tx_rate111 u.r2.rate111
152 uint32_t f_tx_queue_info;
156 * Firmware RX descriptor
157 * Fields are little endian
159 struct acx_fw_rxdesc {
160 uint32_t f_rx_next_desc; /* next acx_fw_rxdesc phyaddr */
161 uint32_t f_rx_host_desc; /* acx_host_desc phyaddr */
162 uint32_t f_rx_acx_ptr;
165 uint16_t f_rx_wep_len;
166 uint32_t f_rx_wep_ofs;
168 uint8_t f_rx_dev_spec[16];
170 uint8_t f_rx_ctrl; /* see DESC_CTRL_ */
173 uint8_t f_rx_snr; /* signal noise ratio */
175 uint8_t f_rx_queue_ctrl;
176 uint16_t f_rx_unknown0;
177 uint32_t f_rx_unknown1;
181 * Host TX/RX descriptor
182 * Fields are little endian
184 struct acx_host_desc {
185 uint32_t h_data_paddr; /* data phyaddr */
188 uint16_t h_ctrl; /* see DESC_CTRL_ */
189 uint16_t h_data_len; /* data length */
190 uint32_t h_next_desc; /* next acx_host_desc phyaddr */
192 uint32_t h_status; /* see DESC_STATUS_ */
195 #define DESC_STATUS_FULL 0x80000000
197 #define DESC_CTRL_SHORT_PREAMBLE 0x01
198 #define DESC_CTRL_FIRST_FRAG 0x02
199 #define DESC_CTRL_AUTODMA 0x04
200 #define DESC_CTRL_RECLAIM 0x08
201 #define DESC_CTRL_HOSTDONE 0x20 /* host finished buf proc */
202 #define DESC_CTRL_ACXDONE 0x40 /* chip finished buf proc */
203 #define DESC_CTRL_HOSTOWN 0x80 /* host controls desc */
205 #define DESC_ERR_OTHER_FRAG 0x01
206 #define DESC_ERR_ABORT 0x02
207 #define DESC_ERR_PARAM 0x04
208 #define DESC_ERR_NO_WEPKEY 0x08
209 #define DESC_ERR_MSDU_TIMEOUT 0x10
210 #define DESC_ERR_EXCESSIVE_RETRY 0x20
211 #define DESC_ERR_BUF_OVERFLOW 0x40
212 #define DESC_ERR_DMA 0x80
215 * Extra header in receiving buffer
216 * Fields are little endian
218 struct acx_rxbuf_hdr {
219 uint16_t rbh_len; /* ACX_RXBUG_LEN_MASK part is len */
220 uint8_t rbh_memblk_cnt;
222 uint8_t rbh_bbp_stat; /* see ACX_RXBUF_STAT_ */
224 uint8_t rbh_level; /* signal level */
225 uint8_t rbh_snr; /* signal noise ratio */
226 uint32_t rbh_time; /* recv timestamp */
229 * XXX may have 4~8 byte here which
230 * depends on firmware version
234 #define ACX_RXBUF_LEN_MASK 0xfff
236 #define ACX_RXBUF_STAT_OFDM 0x04
237 #define ACX_RXBUF_STAT_ANT1 0x10
238 #define ACX_RXBUF_STAT_SHPRE 0x80
240 struct acx_ring_data {
241 struct acx_host_desc *rx_ring;
242 bus_dma_tag_t rx_ring_dma_tag;
243 bus_dmamap_t rx_ring_dmamap;
244 uint32_t rx_ring_paddr;
246 struct acx_host_desc *tx_ring;
247 bus_dma_tag_t tx_ring_dma_tag;
248 bus_dmamap_t tx_ring_dmamap;
249 uint32_t tx_ring_paddr;
253 struct mbuf *tb_mbuf;
254 bus_dmamap_t tb_mbuf_dmamap;
256 struct acx_host_desc *tb_desc1;
257 struct acx_host_desc *tb_desc2;
259 uint32_t tb_fwdesc_ofs;
264 struct ieee80211_node *tb_node;
266 int tb_rateidx[IEEE80211_RATEIDX_MAX];
270 struct mbuf *rb_mbuf;
271 bus_dmamap_t rb_mbuf_dmamap;
273 struct acx_host_desc *rb_desc;
276 struct acx_buf_data {
277 struct acx_rxbuf rx_buf[ACX_RX_DESC_CNT];
278 struct acx_txbuf tx_buf[ACX_TX_DESC_CNT];
279 bus_dma_tag_t mbuf_dma_tag;
280 bus_dmamap_t mbuf_tmp_dmamap;
289 struct acx_firmware_hdr {
294 struct acx_firmware {
295 struct fw_image *base_fw_image;
296 const uint8_t *base_fw;
299 struct fw_image *radio_fw_image;
300 const uint8_t *radio_fw;
303 int combined_radio_fw;
308 uint8_t eaddr[IEEE80211_ADDR_LEN];
311 uint8_t cca_mode; /* acx100 */
312 uint8_t ed_thresh; /* acx100 */
316 uint64_t err_oth_frag; /* XXX error in other frag?? */
317 uint64_t err_abort; /* tx abortion */
318 uint64_t err_param; /* tx desc contains invalid param */
319 uint64_t err_no_wepkey; /* no WEP key exists */
320 uint64_t err_msdu_timeout; /* MSDU timed out */
321 uint64_t err_ex_retry; /* excessive tx retry */
322 uint64_t err_buf_oflow; /* buffer overflow */
323 uint64_t err_dma; /* DMA error */
324 uint64_t err_unkn; /* XXX unknown error */
327 #define ACX_RX_RADIOTAP_PRESENT \
328 ((1 << IEEE80211_RADIOTAP_TSFT) | \
329 (1 << IEEE80211_RADIOTAP_FLAGS) | \
330 (1 << IEEE80211_RADIOTAP_RATE) | \
331 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
332 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)| \
333 (1 << IEEE80211_RADIOTAP_ANTENNA))
335 struct acx_rx_radiotap_header {
336 struct ieee80211_radiotap_header wr_ihdr;
340 uint16_t wr_chan_freq;
341 uint16_t wr_chan_flags;
342 uint8_t wr_antsignal;
346 #define ACX_TX_RADIOTAP_PRESENT \
347 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
348 (1 << IEEE80211_RADIOTAP_RATE) | \
349 (1 << IEEE80211_RADIOTAP_CHANNEL))
351 struct acx_tx_radiotap_header {
352 struct ieee80211_radiotap_header wt_ihdr;
355 uint16_t wt_chan_freq;
356 uint16_t wt_chan_flags;
361 * sc_xxx are filled in by common code
362 * chip_xxx are filled in by chip specific code
364 struct ieee80211com sc_ic;
369 struct bpf_if *sc_drvbpf;
371 struct acx_tx_radiotap_header u_tx_th;
372 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
376 struct acx_rx_radiotap_header u_rx_th;
377 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
380 #define sc_tx_th sc_u_tx_th.u_tx_th
381 #define sc_rx_th sc_u_rx_th.u_rx_th
383 struct callout sc_scan_timer;
384 uint32_t sc_flags; /* see ACX_FLAG_ */
387 struct acx_firmware sc_firmware;
388 uint32_t sc_firmware_ver;
389 uint32_t sc_hardware_id;
394 struct resource *sc_mem1_res;
395 bus_space_tag_t sc_mem1_bt;
396 bus_space_handle_t sc_mem1_bh;
402 struct resource *sc_mem2_res;
403 bus_space_tag_t sc_mem2_bt;
404 bus_space_handle_t sc_mem2_bh;
407 struct resource *sc_irq_res;
411 uint32_t sc_cmd; /* cmd reg (MMIO 2) */
412 uint32_t sc_cmd_param; /* cmd param reg (MMIO 2) */
413 uint32_t sc_info; /* unused */
414 uint32_t sc_info_param; /* unused */
416 const uint16_t *chip_ioreg; /* reg map (MMIO 1) */
420 * chip_intr_enable is not necessarily same as
423 uint16_t chip_intr_enable;
424 uint16_t chip_intr_disable;
427 uint16_t chip_gpio_pled; /* power led */
428 uint16_t chip_chan_flags; /* see IEEE80211_CHAN_ */
429 uint16_t chip_txdesc1_len;
430 int chip_rxbuf_exhdr; /* based on fw ver */
431 uint32_t chip_ee_eaddr_ofs;
432 enum ieee80211_phymode chip_phymode; /* see IEEE80211_MODE_ */
433 uint8_t chip_fw_txdesc_ctrl;
436 uint8_t sc_eeprom_ver; /* unused */
437 uint8_t sc_form_factor; /* unused */
438 uint8_t sc_radio_type; /* see ACX_RADIO_TYPE_ */
440 struct acx_ring_data sc_ring_data;
441 struct acx_buf_data sc_buf_data;
443 struct acx_stats sc_stats; /* statistics */
445 struct sysctl_ctx_list sc_sysctl_ctx;
446 struct sysctl_oid *sc_sysctl_tree;
451 struct ieee80211_onoe_param sc_onoe_param;
452 struct ieee80211_amrr_param sc_amrr_param;
453 int sc_long_retry_limit;
454 int chip_short_retry_limit;
455 int chip_rate_fallback;
458 * Per interface sysctl variables
460 int sc_msdu_lifetime;
461 int sc_scan_dwell; /* unit: millisecond */
462 int sc_calib_intvl; /* unit: minute */
465 (struct ieee80211com *,
466 enum ieee80211_state, int);
468 int (*chip_init) /* non-NULL */
469 (struct acx_softc *);
471 int (*chip_set_wepkey)
473 struct ieee80211_key *, int);
475 int (*chip_read_config)
476 (struct acx_softc *, struct acx_config *);
478 int (*chip_write_config)
479 (struct acx_softc *, struct acx_config *);
481 uint8_t (*chip_set_fw_txdesc_rate) /* non-NULL */
482 (struct acx_softc *, struct acx_txbuf *,
483 struct ieee80211_node *, int);
485 void (*chip_tx_complete) /* non-NULL */
486 (struct acx_softc *, struct acx_txbuf *,
489 void (*chip_set_bss_join_param) /* non-NULL */
490 (struct acx_softc *, void *, int);
492 void (*chip_proc_wep_rxbuf)
493 (struct acx_softc *, struct mbuf *, int *);
495 struct callout sc_calibrate_timer;
496 int (*chip_calibrate)
497 (struct acx_softc *);
500 #define ACX_FLAG_FW_LOADED 0x1
501 #define ACX_FLAG_PROMISC 0x2
503 #define ACX_RADIO_TYPE_MAXIM 0x0d
504 #define ACX_RADIO_TYPE_RFMD 0x11
505 #define ACX_RADIO_TYPE_RALINK 0x15
506 #define ACX_RADIO_TYPE_RADIA 0x16
507 #define ACX_RADIO_TYPE_UNKN17 0x17
508 #define ACX_RADIO_TYPE_UNKN19 0x19
510 #define ACX_BASE_FW_PATH "acx/%s/wlangen.bin"
511 #define ACX_RADIO_FW_PATH "acx/%s/radio%02x.bin"
512 #define ACX_BASE_RADIO_FW_PATH "acx/%s/FwRad%02x.bin"
514 extern const struct ieee80211_rateset acx_rates_11b;
515 extern const struct ieee80211_rateset acx_rates_11b_pbcc;
516 extern const struct ieee80211_rateset acx_rates_11g;
517 extern const struct ieee80211_rateset acx_rates_11g_pbcc;
518 extern int acx_enable_pbcc;
520 void acx100_set_param(device_t);
521 void acx111_set_param(device_t);
523 int acx_init_tmplt_ordered(struct acx_softc *);
524 void acx_write_phyreg(struct acx_softc *, uint32_t, uint8_t);
526 #endif /* !_IF_ACXVAR_H */