1 /* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
38 * Driver for the RealTek 8211B/8169S/8110S internal 10/100/1000 PHY.
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/socket.h>
48 #include <machine/clock.h>
51 #include <net/if_arp.h>
52 #include <net/if_media.h>
54 #include <dev/netif/mii_layer/mii.h>
55 #include <dev/netif/mii_layer/miivar.h>
56 #include <dev/netif/mii_layer/miidevs.h>
58 #include <dev/netif/re/if_rereg.h>
59 #include <dev/netif/mii_layer/rgephyreg.h>
61 #include "miibus_if.h"
63 static int rgephy_probe(device_t);
64 static int rgephy_attach(device_t);
66 static device_method_t rgephy_methods[] = {
67 /* device interface */
68 DEVMETHOD(device_probe, rgephy_probe),
69 DEVMETHOD(device_attach, rgephy_attach),
70 DEVMETHOD(device_detach, ukphy_detach),
71 DEVMETHOD(device_shutdown, bus_generic_shutdown),
75 static const struct mii_phydesc rgephys[] = {
76 MII_PHYDESC(REALTEK2, RTL8169S),
77 MII_PHYDESC(xxREALTEK, RTL8169S),
81 static devclass_t rgephy_devclass;
83 static driver_t rgephy_driver = {
86 sizeof(struct mii_softc)
89 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, NULL, NULL);
91 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
92 static void rgephy_status(struct mii_softc *);
93 static int rgephy_mii_phy_auto(struct mii_softc *);
94 static void rgephy_reset(struct mii_softc *);
95 static void rgephy_loop(struct mii_softc *);
96 static void rgephy_load_dspcode(struct mii_softc *);
99 rgephy_probe(device_t dev)
101 struct mii_attach_args *ma = device_get_ivars(dev);
102 const struct mii_phydesc *mpd;
104 mpd = mii_phy_match(ma, rgephys);
106 device_set_desc(dev, mpd->mpd_name);
108 device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2));
115 rgephy_attach(device_t dev)
117 struct mii_softc *sc;
118 struct mii_attach_args *ma;
119 struct mii_data *mii;
121 sc = device_get_softc(dev);
122 ma = device_get_ivars(dev);
123 mii_softc_init(sc, ma);
124 sc->mii_dev = device_get_parent(dev);
126 mii = device_get_softc(sc->mii_dev);
127 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
129 sc->mii_inst = mii->mii_instance;
130 sc->mii_service = rgephy_service;
131 sc->mii_reset = rgephy_reset;
134 sc->mii_flags |= MIIF_NOISOLATE;
139 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
140 if (sc->mii_capabilities & BMSR_EXTSTAT)
141 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
143 device_printf(dev, " ");
144 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
145 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
146 kprintf("no media present");
148 mii_phy_add_media(sc);
151 MIIBUS_MEDIAINIT(sc->mii_dev);
156 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
158 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
165 * If we're not polling our PHY instance, just return.
167 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
173 * If the media indicates a different PHY instance,
176 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
177 reg = PHY_READ(sc, MII_BMCR);
178 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
183 * If the interface is not up, don't do anything.
185 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
188 rgephy_reset(sc); /* XXX hardware bug work-around */
190 switch (IFM_SUBTYPE(ife->ifm_media)) {
194 * If we're already in auto mode, just return.
196 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
199 rgephy_mii_phy_auto(sc);
202 speed = RGEPHY_S1000;
211 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
212 speed |= RGEPHY_BMCR_FDX;
213 gig = RGEPHY_1000CTL_AFD;
215 gig = RGEPHY_1000CTL_AHD;
218 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
219 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
220 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
222 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
225 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
226 PHY_WRITE(sc, RGEPHY_MII_BMCR,
227 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
230 * When settning the link manually, one side must
231 * be the master and the other the slave. However
232 * ifmedia doesn't give us a good way to specify
233 * this, so we fake it by using one of the LINK
234 * flags. If LINK0 is set, we program the PHY to
235 * be a master, otherwise it's a slave.
237 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
238 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
239 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
241 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
242 gig|RGEPHY_1000CTL_MSE);
247 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
258 * If we're not currently selected, just return.
260 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
264 * Is the interface even up?
266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
270 * Only used for autonegotiation.
272 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
276 * Check to see if we have link. If we do, we don't
277 * need to restart the autonegotiation process.
279 * XXX Read the BMSR twice in case it's latched?
281 id2 = PHY_READ(sc, MII_PHYIDR2);
283 if (MII_REV(id2) < 2) {
284 reg = PHY_READ(sc, RE_GMEDIASTAT);
285 if (reg & RE_GMEDIASTAT_LINK) {
290 reg = PHY_READ(sc, RGEPHY_SR);
291 if (reg & RGEPHY_SR_LINK) {
298 * Only retry autonegotiation every mii_anegticks seconds.
300 if (++sc->mii_ticks <= sc->mii_anegticks)
306 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN,
307 * we should not rely on that.
309 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN)
314 /* Update the media status. */
318 * Callback if something changed. Note that we need to poke
319 * the DSP on the RealTek PHYs if the media changes.
321 if (sc->mii_media_active != mii->mii_media_active ||
322 sc->mii_media_status != mii->mii_media_status ||
324 rgephy_load_dspcode(sc);
325 mii_phy_update(sc, cmd);
330 rgephy_status(struct mii_softc *sc)
332 struct mii_data *mii = sc->mii_pdata;
336 mii->mii_media_status = IFM_AVALID;
337 mii->mii_media_active = IFM_ETHER;
339 id2 = PHY_READ(sc, MII_PHYIDR2);
341 if (MII_REV(id2) < 2) {
342 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
343 if (bmsr & RE_GMEDIASTAT_LINK)
344 mii->mii_media_status |= IFM_ACTIVE;
346 bmsr = PHY_READ(sc, RGEPHY_SR);
347 if (bmsr & RGEPHY_SR_LINK)
348 mii->mii_media_status |= IFM_ACTIVE;
351 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
353 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
355 if (bmcr & RGEPHY_BMCR_LOOP)
356 mii->mii_media_active |= IFM_LOOP;
358 if (bmcr & RGEPHY_BMCR_AUTOEN) {
359 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
360 /* Erg, still trying, I guess... */
361 mii->mii_media_active |= IFM_NONE;
366 if (MII_REV(id2) < 2) {
367 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
368 if (bmsr & RE_GMEDIASTAT_1000MBPS)
369 mii->mii_media_active |= IFM_1000_T;
370 else if (bmsr & RE_GMEDIASTAT_100MBPS)
371 mii->mii_media_active |= IFM_100_TX;
372 else if (bmsr & RE_GMEDIASTAT_10MBPS)
373 mii->mii_media_active |= IFM_10_T;
375 mii->mii_media_active |= IFM_NONE;
376 if (bmsr & RE_GMEDIASTAT_FDX)
377 mii->mii_media_active |= IFM_FDX;
379 bmsr = PHY_READ(sc, RGEPHY_SR);
380 if (RGEPHY_SR_SPEED(bmsr) == 2)
381 mii->mii_media_active |= IFM_1000_T;
382 else if (RGEPHY_SR_SPEED(bmsr) == 1)
383 mii->mii_media_active |= IFM_100_TX;
384 else if (RGEPHY_SR_SPEED(bmsr) == 0)
385 mii->mii_media_active |= IFM_10_T;
387 mii->mii_media_active |= IFM_NONE;
388 if (bmsr & RGEPHY_SR_FDX)
389 mii->mii_media_active |= IFM_FDX;
394 rgephy_mii_phy_auto(struct mii_softc *sc)
398 id2 = PHY_READ(sc, MII_PHYIDR2);
399 if (MII_REV(id2) < 2) {
404 PHY_WRITE(sc, RGEPHY_MII_ANAR,
405 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
407 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
408 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
410 PHY_WRITE(sc, RGEPHY_MII_BMCR,
411 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
414 return (EJUSTRETURN);
418 rgephy_loop(struct mii_softc *sc)
424 id2 = PHY_READ(sc, MII_PHYIDR2);
425 if (MII_REV(id2) < 2) {
426 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
430 for (i = 0; i < 15000; i++) {
431 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
432 if (!(bmsr & RGEPHY_BMSR_LINK)) {
434 device_printf(sc->mii_dev, "looped %d\n", i);
442 #define PHY_SETBIT(x, y, z) \
443 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
444 #define PHY_CLRBIT(x, y, z) \
445 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
448 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
449 * existing revisions of the 8169S/8110S chips need to be tuned in
450 * order to reliably negotiate a 1000Mbps link. This is only needed
451 * for rev 0 and rev 1 of the PHY. Later versions work without
455 rgephy_load_dspcode(struct mii_softc *sc)
462 PHY_WRITE(sc, 31, 0x0001);
463 PHY_WRITE(sc, 21, 0x1000);
464 PHY_WRITE(sc, 24, 0x65C7);
465 PHY_CLRBIT(sc, 4, 0x0800);
466 val = PHY_READ(sc, 4) & 0xFFF;
467 PHY_WRITE(sc, 4, val);
468 PHY_WRITE(sc, 3, 0x00A1);
469 PHY_WRITE(sc, 2, 0x0008);
470 PHY_WRITE(sc, 1, 0x1020);
471 PHY_WRITE(sc, 0, 0x1000);
472 PHY_SETBIT(sc, 4, 0x0800);
473 PHY_CLRBIT(sc, 4, 0x0800);
474 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
475 PHY_WRITE(sc, 4, val);
476 PHY_WRITE(sc, 3, 0xFF41);
477 PHY_WRITE(sc, 2, 0xDE60);
478 PHY_WRITE(sc, 1, 0x0140);
479 PHY_WRITE(sc, 0, 0x0077);
480 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
481 PHY_WRITE(sc, 4, val);
482 PHY_WRITE(sc, 3, 0xDF01);
483 PHY_WRITE(sc, 2, 0xDF20);
484 PHY_WRITE(sc, 1, 0xFF95);
485 PHY_WRITE(sc, 0, 0xFA00);
486 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
487 PHY_WRITE(sc, 4, val);
488 PHY_WRITE(sc, 3, 0xFF41);
489 PHY_WRITE(sc, 2, 0xDE20);
490 PHY_WRITE(sc, 1, 0x0140);
491 PHY_WRITE(sc, 0, 0x00BB);
492 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
493 PHY_WRITE(sc, 4, val);
494 PHY_WRITE(sc, 3, 0xDF01);
495 PHY_WRITE(sc, 2, 0xDF20);
496 PHY_WRITE(sc, 1, 0xFF95);
497 PHY_WRITE(sc, 0, 0xBF00);
498 PHY_SETBIT(sc, 4, 0x0800);
499 PHY_CLRBIT(sc, 4, 0x0800);
500 PHY_WRITE(sc, 31, 0x0000);
506 rgephy_reset(struct mii_softc *sc)
512 id2 = PHY_READ(sc, MII_PHYIDR2);
513 if (MII_REV(id2) < 2) {
515 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
518 rgephy_load_dspcode(sc);