2 * Copyright (c) 1999 FreeBSD Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/ic/rsa.h,v 1.1.2.1 2002/02/03 14:52:02 nyan Exp $
27 * $DragonFly: src/sys/dev/serial/ic_layer/rsa.h,v 1.2 2003/06/17 04:28:27 dillon Exp $
31 * RSA Mode Driver Data Sheet
35 * Mode Select Register(Read/Write)
36 * bit4=interrupt type(1: level, 0: edge)
37 * bit3=Auto RTS-CTS Flow Control Enable
38 * bit2=External FIFO Enable
39 * bit1=Reserved(Default 0)Don't Change!!
40 * bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
43 * Interrupt Enable Register(Read/Write)
44 * bit4=Hardware Timer Interrupt Enable
45 * bit3=Character Time-Out Interrupt Enable
46 * bit2=Tx FIFO Empty Interrupt Enable
47 * bit1=Tx FIFO Half Full Interrupt Enable
48 * bit0=Rx FIFO Half Full Interrupt Enable
51 * Status Read Register(Read)
52 * bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
53 * bit6=Character Time Out Interrupt Status
54 * bit5=Rx FIFO Full Flag(0: True, 1: False)
55 * bit4=Rx FIFO Half Full Flag
56 * bit3=Rx FIFO Empty Flag
57 * bit2=Tx FIFO Full Flag
58 * bit1=Tx FIFO Half Full Flag
59 * bit0=Tx FIFO Empty Flag
62 * FIFO Reset Register(Write)
66 * Timer Interval Value Set Register(Read/Write)
68 * Interval Value: n * 0.2ms
71 * Timer Control Register(Read/Write)
77 * Special Regisgter in RSA Mode
78 * UART Data Register(Base + 0x08)
79 * Data transfer between Extrnal FIFO
81 * UART MCR(Base + 0x0c)
82 * bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
83 * bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
85 * <<Intrrupt and Intrrupt Reset>>
86 * o Reciver Line Status(from UART16550)
89 * o Modem Status(from UART16550)
92 * o Rx FIFO Half Full(from Extrnal FIFO)
93 * Reset: Read Rx FIFO under Hall Full
95 * o Character Time Out(from Extrnal FIFO)
96 * Reset: Read Rx FIFO or SRR
98 * o Tx FIFO Empty(from Extrnal FIFO)
99 * Reset: Write Tx FIFO or Read SRR
101 * o Tx FIFO Half Full(from Extrnal FIFO)
102 * Reset: Write Tx FIFO until Hall Full or Read SRR
104 * o Hardware Timer(from Extrnal FIFO)
105 * Reset: Disable Timer in TCR
106 * Notes: If you want to use Timer for next intrrupt,
107 * you must enable Timer in TCR
110 * Auto RTS-CTS: Enable or Disable
111 * External FIFO: Enable
112 * Swap 8bytes: Disable
113 * Haredware Timer: Disable
114 * interrupt type: edge
123 /* I/O-DATA RSA Serise Exrension Register */
124 #define rsa_msr 0 /* Mode Status Register (R/W) */
125 #define rsa_ier 1 /* Interrupt Enable Register (R/W) */
126 #define rsa_srr 2 /* Status Read Register (R) */
127 #define rsa_frr 2 /* FIFO Reset Register (W) */
128 #define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
129 #define rsa_tcr 4 /* Timer Control Register (W) */