2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 * promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/dev/rp/rp_pci.c,v 1.3.2.1 2002/06/18 03:11:46 obrien Exp $
36 * $DragonFly: src/sys/dev/serial/rp/rp_pci.c,v 1.4 2004/09/18 20:02:36 dillon Exp $
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/fcntl.h>
42 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
55 #include <bus/pci/pcireg.h>
56 #include <bus/pci/pcivar.h>
59 #define RP_VENDOR_ID 0x11FE
60 #define RP_DEVICE_ID_32I 0x0001
61 #define RP_DEVICE_ID_8I 0x0002
62 #define RP_DEVICE_ID_16I 0x0003
63 #define RP_DEVICE_ID_4Q 0x0004
64 #define RP_DEVICE_ID_8O 0x0005
65 #define RP_DEVICE_ID_8J 0x0006
66 #define RP_DEVICE_ID_4J 0x0007
67 #define RP_DEVICE_ID_6M 0x000C
68 #define RP_DEVICE_ID_4M 0x000D
70 /**************************************************************************
71 MUDBAC remapped for PCI
72 **************************************************************************/
74 #define _CFG_INT_PCI 0x40
75 #define _PCI_INT_FUNC 0x3A
77 #define PCI_STROB 0x2000
78 #define INTR_EN_PCI 0x0010
80 /***************************************************************************
81 Function: sPCIControllerEOI
82 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
83 Call: sPCIControllerEOI(CtlP)
84 CONTROLLER_T *CtlP; Ptr to controller structure
86 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
88 /***************************************************************************
89 Function: sPCIGetControllerIntStatus
90 Purpose: Get the controller interrupt status
91 Call: sPCIGetControllerIntStatus(CtlP)
92 CONTROLLER_T *CtlP; Ptr to controller structure
93 Return: Byte_t: The controller interrupt status in the lower 4
94 bits. Bits 0 through 3 represent AIOP's 0
95 through 3 respectively. If a bit is set that
96 AIOP is interrupting. Bits 4 through 7 will
99 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
101 static devclass_t rp_devclass;
103 static int rp_pciprobe(device_t dev);
104 static int rp_pciattach(device_t dev);
106 static int rp_pcidetach(device_t dev);
107 static int rp_pcishutdown(device_t dev);
109 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
110 static int sPCIInitController( CONTROLLER_t *CtlP,
116 static rp_aiop2rid_t rp_pci_aiop2rid;
117 static rp_aiop2off_t rp_pci_aiop2off;
118 static rp_ctlmask_t rp_pci_ctlmask;
121 * The following functions are the pci-specific part
126 rp_pciprobe(device_t dev)
131 if ((pci_get_devid(dev) & 0xffff) == RP_VENDOR_ID)
132 s = "RocketPort PCI";
135 device_set_desc(dev, s);
143 rp_pciattach(device_t dev)
145 int num_ports, num_aiops;
152 ctlp = device_get_softc(dev);
153 bzero(ctlp, sizeof(*ctlp));
155 unit = device_get_unit(dev);
156 ctlp->aiop2rid = rp_pci_aiop2rid;
157 ctlp->aiop2off = rp_pci_aiop2off;
158 ctlp->ctlmask = rp_pci_ctlmask;
160 /* Wake up the device. */
161 stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
162 if ((stcmd & PCIM_CMD_PORTEN) == 0) {
163 stcmd |= (PCIM_CMD_PORTEN);
164 pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
167 /* The IO ports of AIOPs for a PCI controller are continuous. */
169 ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num,
170 M_DEVBUF, M_WAITOK | M_ZERO);
171 ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num,
172 M_DEVBUF, M_WAITOK | M_ZERO);
174 ctlp->bus_ctlp = NULL;
176 ctlp->io_rid[0] = 0x10;
177 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 1, RF_ACTIVE);
178 if(ctlp->io[0] == NULL) {
179 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
184 num_aiops = sPCIInitController(ctlp,
185 MAX_AIOPS_PER_BOARD, 0,
186 FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff);
189 for(aiop=0; aiop < num_aiops; aiop++) {
190 sResetAiopByNum(ctlp, aiop);
191 num_ports += sGetAiopNumChan(ctlp, aiop);
194 retval = rp_attachcommon(ctlp, num_aiops, num_ports);
201 rp_pcireleaseresource(ctlp);
208 rp_pcidetach(device_t dev)
212 if (device_get_state(dev) == DS_BUSY)
215 ctlp = device_get_softc(dev);
217 rp_pcireleaseresource(ctlp);
223 rp_pcishutdown(device_t dev)
227 if (device_get_state(dev) == DS_BUSY)
230 ctlp = device_get_softc(dev);
232 rp_pcireleaseresource(ctlp);
239 rp_pcireleaseresource(CONTROLLER_t *ctlp)
241 rp_releaseresource(ctlp);
243 if (ctlp->io != NULL) {
244 if (ctlp->io[0] != NULL)
245 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
246 free(ctlp->io, M_DEVBUF);
248 if (ctlp->io_rid != NULL)
249 free(ctlp->io_rid, M_DEVBUF);
253 sPCIInitController( CONTROLLER_t *CtlP,
262 CtlP->CtlID = CTLID_0001; /* controller release 1 */
264 sPCIControllerEOI(CtlP);
268 for(i=0; i < AiopNum; i++)
270 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
271 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
272 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
273 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
275 break; /* done looking for AIOPs */
278 switch( VendorDevice ) {
279 case RP_DEVICE_ID_4Q:
280 case RP_DEVICE_ID_4J:
281 case RP_DEVICE_ID_4M:
282 CtlP->AiopNumChan[i] = 4;
284 case RP_DEVICE_ID_6M:
285 CtlP->AiopNumChan[i] = 6;
287 case RP_DEVICE_ID_8O:
288 case RP_DEVICE_ID_8J:
289 case RP_DEVICE_ID_8I:
290 case RP_DEVICE_ID_16I:
291 case RP_DEVICE_ID_32I:
292 CtlP->AiopNumChan[i] = 8;
296 CtlP->AiopNumChan[i] = 8;
298 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
302 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
303 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE); /* clock prescaler */
304 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
305 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
306 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
307 CtlP->NumAiop++; /* bump count of AIOPs */
310 if(CtlP->NumAiop == 0)
313 return(CtlP->NumAiop);
318 * Maps (aiop, offset) to rid.
321 rp_pci_aiop2rid(int aiop, int offset)
323 /* Always return zero for a PCI controller. */
329 * Maps (aiop, offset) to the offset of resource.
332 rp_pci_aiop2off(int aiop, int offset)
334 /* Each AIOP reserves 0x40 bytes. */
335 return aiop * 0x40 + offset;
338 /* Read the int status for a PCI controller. */
340 rp_pci_ctlmask(CONTROLLER_t *ctlp)
342 return sPCIGetControllerIntStatus(ctlp);
345 static device_method_t rp_pcimethods[] = {
346 /* Device interface */
347 DEVMETHOD(device_probe, rp_pciprobe),
348 DEVMETHOD(device_attach, rp_pciattach),
350 DEVMETHOD(device_detach, rp_pcidetach),
351 DEVMETHOD(device_shutdown, rp_pcishutdown),
357 static driver_t rp_pcidriver = {
360 sizeof(CONTROLLER_t),
364 * rp can be attached to a pci bus.
366 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);