2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.24 2005/06/11 08:50:21 joerg Exp $
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
42 * Written using the following four documents:
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
55 * Some notes about the ThunderLAN:
57 * The ThunderLAN controller is a single chip containing PCI controller
58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
62 * to act as a complete ethernet interface.
64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
66 * in full or half duplex. Some of the Compaq Deskpro machines use a
67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
69 * concert with the ThunderLAN's internal PHY to provide full 10/100
70 * support. This is cheaper than using a standalone external PHY for both
71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
72 * A serial EEPROM is also attached to the ThunderLAN chip to provide
73 * power-up default register settings and for storing the adapter's
74 * station address. Although not supported by this driver, the ThunderLAN
75 * chip can also be connected to token ring PHYs.
77 * The ThunderLAN has a set of registers which can be used to issue
78 * commands, acknowledge interrupts, and to manipulate other internal
79 * registers on its DIO bus. The primary registers can be accessed
80 * using either programmed I/O (inb/outb) or via PCI memory mapping,
81 * depending on how the card is configured during the PCI probing
82 * phase. It is even possible to have both PIO and memory mapped
83 * access turned on at the same time.
85 * Frame reception and transmission with the ThunderLAN chip is done
86 * using frame 'lists.' A list structure looks more or less like this:
89 * u_int32_t fragment_address;
90 * u_int32_t fragment_size;
93 * u_int32_t forward_pointer;
95 * u_int16_t frame_size;
96 * struct tl_frag fragments[10];
99 * The forward pointer in the list header can be either a 0 or the address
100 * of another list, which allows several lists to be linked together. Each
101 * list contains up to 10 fragment descriptors. This means the chip allows
102 * ethernet frames to be broken up into up to 10 chunks for transfer to
103 * and from the SRAM. Note that the forward pointer and fragment buffer
104 * addresses are physical memory addresses, not virtual. Note also that
105 * a single ethernet frame can not span lists: if the host wants to
106 * transmit a frame and the frame data is split up over more than 10
107 * buffers, the frame has to collapsed before it can be transmitted.
109 * To receive frames, the driver sets up a number of lists and populates
110 * the fragment descriptors, then it sends an RX GO command to the chip.
111 * When a frame is received, the chip will DMA it into the memory regions
112 * specified by the fragment descriptors and then trigger an RX 'end of
113 * frame interrupt' when done. The driver may choose to use only one
114 * fragment per list; this may result is slighltly less efficient use
115 * of memory in exchange for improving performance.
117 * To transmit frames, the driver again sets up lists and fragment
118 * descriptors, only this time the buffers contain frame data that
119 * is to be DMA'ed into the chip instead of out of it. Once the chip
120 * has transfered the data into its on-board SRAM, it will trigger a
121 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
122 * interrupt when it reaches the end of the list.
126 * Some notes about this driver:
128 * The ThunderLAN chip provides a couple of different ways to organize
129 * reception, transmission and interrupt handling. The simplest approach
130 * is to use one list each for transmission and reception. In this mode,
131 * the ThunderLAN will generate two interrupts for every received frame
132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
134 * performance to have to handle so many interrupts.
136 * Initially I wanted to create a circular list of receive buffers so
137 * that the ThunderLAN chip would think there was an infinitely long
138 * receive channel and never deliver an RXEOC interrupt. However this
139 * doesn't work correctly under heavy load: while the manual says the
140 * chip will trigger an RXEOF interrupt each time a frame is copied into
141 * memory, you can't count on the chip waiting around for you to acknowledge
142 * the interrupt before it starts trying to DMA the next frame. The result
143 * is that the chip might traverse the entire circular list and then wrap
144 * around before you have a chance to do anything about it. Consequently,
145 * the receive list is terminated (with a 0 in the forward pointer in the
146 * last element). Each time an RXEOF interrupt arrives, the used list
147 * is shifted to the end of the list. This gives the appearance of an
148 * infinitely large RX chain so long as the driver doesn't fall behind
149 * the chip and allow all of the lists to be filled up.
151 * If all the lists are filled, the adapter will deliver an RX 'end of
152 * channel' interrupt when it hits the 0 forward pointer at the end of
153 * the chain. The RXEOC handler then cleans out the RX chain and resets
154 * the list head pointer in the ch_parm register and restarts the receiver.
156 * For frame transmission, it is possible to program the ThunderLAN's
157 * transmit interrupt threshold so that the chip can acknowledge multiple
158 * lists with only a single TX EOF interrupt. This allows the driver to
159 * queue several frames in one shot, and only have to handle a total
160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
161 * are transmitted. Frame transmission is done directly out of the
162 * mbufs passed to the tl_start() routine via the interface send queue.
163 * The driver simply sets up the fragment descriptors in the transmit
164 * lists to point to the mbuf data regions and sends a TX GO command.
166 * Note that since the RX and TX lists themselves are always used
167 * only by the driver, the are malloc()ed once at driver initialization
168 * time and never free()ed.
170 * Also, in order to remain as platform independent as possible, this
171 * driver uses memory mapped register access to manipulate the card
172 * as opposed to programmed I/O. This avoids the use of the inb/outb
173 * (and related) instructions which are specific to the i386 platform.
175 * Using these techniques, this driver achieves very high performance
176 * by minimizing the amount of interrupts generated during large
177 * transfers and by completely avoiding buffer copies. Frame transfer
178 * to and from the ThunderLAN chip is performed entirely by the chip
179 * itself thereby reducing the load on the host CPU.
182 #include <sys/param.h>
183 #include <sys/systm.h>
184 #include <sys/sockio.h>
185 #include <sys/mbuf.h>
186 #include <sys/malloc.h>
187 #include <sys/kernel.h>
188 #include <sys/socket.h>
189 #include <sys/thread2.h>
192 #include <net/ifq_var.h>
193 #include <net/if_arp.h>
194 #include <net/ethernet.h>
195 #include <net/if_dl.h>
196 #include <net/if_media.h>
200 #include <vm/vm.h> /* for vtophys */
201 #include <vm/pmap.h> /* for vtophys */
202 #include <machine/clock.h> /* for DELAY */
203 #include <machine/bus_memio.h>
204 #include <machine/bus_pio.h>
205 #include <machine/bus.h>
206 #include <machine/resource.h>
208 #include <sys/rman.h>
210 #include "../mii_layer/mii.h"
211 #include "../mii_layer/miivar.h"
213 #include <bus/pci/pcireg.h>
214 #include <bus/pci/pcivar.h>
217 * Default to using PIO register access mode to pacify certain
218 * laptop docking stations with built-in ThunderLAN chips that
219 * don't seem to handle memory mapped mode properly.
221 #define TL_USEIOSPACE
223 #include "if_tlreg.h"
225 /* "controller miibus0" required. See GENERIC if you get errors here. */
226 #include "miibus_if.h"
229 * Various supported device vendors/types and their names.
232 static struct tl_type tl_devs[] = {
233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
234 "Texas Instruments ThunderLAN" },
235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
236 "Compaq Netelligent 10" },
237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
238 "Compaq Netelligent 10/100" },
239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
240 "Compaq Netelligent 10/100 Proliant" },
241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
242 "Compaq Netelligent 10/100 Dual Port" },
243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
244 "Compaq NetFlex-3/P Integrated" },
245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
246 "Compaq NetFlex-3/P" },
247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
248 "Compaq NetFlex 3/P w/ BNC" },
249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
250 "Compaq Netelligent 10/100 TX Embedded UTP" },
251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
254 "Compaq Netelligent 10/100 TX UTP" },
255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
256 "Olicom OC-2183/2185" },
257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
260 "Olicom OC-2326 10/100 TX UTP" },
264 static int tl_probe (device_t);
265 static int tl_attach (device_t);
266 static int tl_detach (device_t);
267 static int tl_intvec_rxeoc (void *, u_int32_t);
268 static int tl_intvec_txeoc (void *, u_int32_t);
269 static int tl_intvec_txeof (void *, u_int32_t);
270 static int tl_intvec_rxeof (void *, u_int32_t);
271 static int tl_intvec_adchk (void *, u_int32_t);
272 static int tl_intvec_netsts (void *, u_int32_t);
274 static int tl_newbuf (struct tl_softc *,
275 struct tl_chain_onefrag *);
276 static void tl_stats_update (void *);
277 static int tl_encap (struct tl_softc *, struct tl_chain *,
280 static void tl_intr (void *);
281 static void tl_start (struct ifnet *);
282 static int tl_ioctl (struct ifnet *, u_long, caddr_t,
284 static void tl_init (void *);
285 static void tl_stop (struct tl_softc *);
286 static void tl_watchdog (struct ifnet *);
287 static void tl_shutdown (device_t);
288 static int tl_ifmedia_upd (struct ifnet *);
289 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
291 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
292 static u_int8_t tl_eeprom_getbyte (struct tl_softc *,
294 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
296 static void tl_mii_sync (struct tl_softc *);
297 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
298 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
299 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
300 static int tl_miibus_readreg (device_t, int, int);
301 static int tl_miibus_writereg (device_t, int, int, int);
302 static void tl_miibus_statchg (device_t);
304 static void tl_setmode (struct tl_softc *, int);
305 static int tl_calchash (caddr_t);
306 static void tl_setmulti (struct tl_softc *);
307 static void tl_setfilt (struct tl_softc *, caddr_t, int);
308 static void tl_softreset (struct tl_softc *, int);
309 static void tl_hardreset (device_t);
310 static int tl_list_rx_init (struct tl_softc *);
311 static int tl_list_tx_init (struct tl_softc *);
313 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
314 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
315 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
316 static void tl_dio_write8 (struct tl_softc *, int, int);
317 static void tl_dio_write16 (struct tl_softc *, int, int);
318 static void tl_dio_write32 (struct tl_softc *, int, int);
319 static void tl_dio_setbit (struct tl_softc *, int, int);
320 static void tl_dio_clrbit (struct tl_softc *, int, int);
321 static void tl_dio_setbit16 (struct tl_softc *, int, int);
322 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
325 #define TL_RES SYS_RES_IOPORT
326 #define TL_RID TL_PCI_LOIO
328 #define TL_RES SYS_RES_MEMORY
329 #define TL_RID TL_PCI_LOMEM
332 static device_method_t tl_methods[] = {
333 /* Device interface */
334 DEVMETHOD(device_probe, tl_probe),
335 DEVMETHOD(device_attach, tl_attach),
336 DEVMETHOD(device_detach, tl_detach),
337 DEVMETHOD(device_shutdown, tl_shutdown),
340 DEVMETHOD(bus_print_child, bus_generic_print_child),
341 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
344 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
345 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
346 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
351 static driver_t tl_driver = {
354 sizeof(struct tl_softc)
357 static devclass_t tl_devclass;
359 DECLARE_DUMMY_MODULE(if_tl);
360 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
361 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
363 static u_int8_t tl_dio_read8(sc, reg)
367 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
368 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
371 static u_int16_t tl_dio_read16(sc, reg)
375 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
376 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
379 static u_int32_t tl_dio_read32(sc, reg)
383 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
384 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
387 static void tl_dio_write8(sc, reg, val)
392 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
393 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
397 static void tl_dio_write16(sc, reg, val)
402 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
403 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
407 static void tl_dio_write32(sc, reg, val)
412 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
413 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
417 static void tl_dio_setbit(sc, reg, bit)
424 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
425 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
427 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
432 static void tl_dio_clrbit(sc, reg, bit)
439 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
440 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
442 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
447 static void tl_dio_setbit16(sc, reg, bit)
454 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
455 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
457 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
462 static void tl_dio_clrbit16(sc, reg, bit)
469 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
470 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
472 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
478 * Send an instruction or address to the EEPROM, check for ACK.
480 static u_int8_t tl_eeprom_putbyte(sc, byte)
487 * Make sure we're in TX mode.
489 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
492 * Feed in each bit and stobe the clock.
494 for (i = 0x80; i; i >>= 1) {
496 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
498 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
501 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
503 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
509 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
514 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
515 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
516 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
522 * Read a byte of data stored in the EEPROM at address 'addr.'
524 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
532 tl_dio_write8(sc, TL_NETSIO, 0);
537 * Send write control code to EEPROM.
539 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
540 printf("tl%d: failed to send write command, status: %x\n",
541 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
546 * Send address of byte we want to read.
548 if (tl_eeprom_putbyte(sc, addr)) {
549 printf("tl%d: failed to send address, status: %x\n",
550 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
557 * Send read control code to EEPROM.
559 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
560 printf("tl%d: failed to send write command, status: %x\n",
561 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
566 * Start reading bits from EEPROM.
568 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
569 for (i = 0x80; i; i >>= 1) {
570 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
572 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
574 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
581 * No ACK generated for read, so just return byte.
590 * Read a sequence of bytes from the EEPROM.
592 static int tl_read_eeprom(sc, dest, off, cnt)
601 for (i = 0; i < cnt; i++) {
602 err = tl_eeprom_getbyte(sc, off + i, &byte);
611 static void tl_mii_sync(sc)
616 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
618 for (i = 0; i < 32; i++) {
619 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
620 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
626 static void tl_mii_send(sc, bits, cnt)
633 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
634 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
636 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
640 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
644 static int tl_mii_readreg(sc, frame)
646 struct tl_mii_frame *frame;
657 * Set up frame for RX.
659 frame->mii_stdelim = TL_MII_STARTDELIM;
660 frame->mii_opcode = TL_MII_READOP;
661 frame->mii_turnaround = 0;
665 * Turn off MII interrupt by forcing MINTEN low.
667 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
669 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
675 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
678 * Send command/address info.
680 tl_mii_send(sc, frame->mii_stdelim, 2);
681 tl_mii_send(sc, frame->mii_opcode, 2);
682 tl_mii_send(sc, frame->mii_phyaddr, 5);
683 tl_mii_send(sc, frame->mii_regaddr, 5);
688 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
692 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
695 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
696 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
698 /* Complete the cycle */
699 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
702 * Now try reading data bits. If the ack failed, we still
703 * need to clock through 16 cycles to keep the PHYs in sync.
706 for(i = 0; i < 16; i++) {
707 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
708 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
713 for (i = 0x8000; i; i >>= 1) {
714 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
716 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
717 frame->mii_data |= i;
719 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
724 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
725 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
727 /* Reenable interrupts */
729 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
739 static int tl_mii_writereg(sc, frame)
741 struct tl_mii_frame *frame;
750 * Set up frame for TX.
753 frame->mii_stdelim = TL_MII_STARTDELIM;
754 frame->mii_opcode = TL_MII_WRITEOP;
755 frame->mii_turnaround = TL_MII_TURNAROUND;
758 * Turn off MII interrupt by forcing MINTEN low.
760 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
762 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
766 * Turn on data output.
768 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
770 tl_mii_send(sc, frame->mii_stdelim, 2);
771 tl_mii_send(sc, frame->mii_opcode, 2);
772 tl_mii_send(sc, frame->mii_phyaddr, 5);
773 tl_mii_send(sc, frame->mii_regaddr, 5);
774 tl_mii_send(sc, frame->mii_turnaround, 2);
775 tl_mii_send(sc, frame->mii_data, 16);
777 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
778 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
785 /* Reenable interrupts */
787 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
794 static int tl_miibus_readreg(dev, phy, reg)
799 struct tl_mii_frame frame;
801 sc = device_get_softc(dev);
802 bzero((char *)&frame, sizeof(frame));
804 frame.mii_phyaddr = phy;
805 frame.mii_regaddr = reg;
806 tl_mii_readreg(sc, &frame);
808 return(frame.mii_data);
811 static int tl_miibus_writereg(dev, phy, reg, data)
816 struct tl_mii_frame frame;
818 sc = device_get_softc(dev);
819 bzero((char *)&frame, sizeof(frame));
821 frame.mii_phyaddr = phy;
822 frame.mii_regaddr = reg;
823 frame.mii_data = data;
825 tl_mii_writereg(sc, &frame);
830 static void tl_miibus_statchg(dev)
834 struct mii_data *mii;
836 sc = device_get_softc(dev);
837 mii = device_get_softc(sc->tl_miibus);
839 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
840 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
842 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
849 * Set modes for bitrate devices.
851 static void tl_setmode(sc, media)
855 if (IFM_SUBTYPE(media) == IFM_10_5)
856 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
857 if (IFM_SUBTYPE(media) == IFM_10_T) {
858 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
859 if ((media & IFM_GMASK) == IFM_FDX) {
860 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
861 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
863 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
864 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
872 * Calculate the hash of a MAC address for programming the multicast hash
873 * table. This hash is simply the address split into 6-bit chunks
875 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
876 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
877 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
878 * the folded 24-bit value is split into 6-bit portions and XOR'd.
880 static int tl_calchash(addr)
885 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
887 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
891 * The ThunderLAN has a perfect MAC address filter in addition to
892 * the multicast hash filter. The perfect filter can be programmed
893 * with up to four MAC addresses. The first one is always used to
894 * hold the station address, which leaves us free to use the other
895 * three for multicast addresses.
897 static void tl_setfilt(sc, addr, slot)
905 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
907 for (i = 0; i < ETHER_ADDR_LEN; i++)
908 tl_dio_write8(sc, regaddr + i, *(addr + i));
914 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
915 * linked list. This is fine, except addresses are added from the head
916 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
917 * group to always be in the perfect filter, but as more groups are added,
918 * the 224.0.0.1 entry (which is always added first) gets pushed down
919 * the list and ends up at the tail. So after 3 or 4 multicast groups
920 * are added, the all-hosts entry gets pushed out of the perfect filter
921 * and into the hash table.
923 * Because the multicast list is a doubly-linked list as opposed to a
924 * circular queue, we don't have the ability to just grab the tail of
925 * the list and traverse it backwards. Instead, we have to traverse
926 * the list once to find the tail, then traverse it again backwards to
927 * update the multicast filter.
929 static void tl_setmulti(sc)
933 u_int32_t hashes[2] = { 0, 0 };
935 struct ifmultiaddr *ifma;
936 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
937 ifp = &sc->arpcom.ac_if;
939 /* First, zot all the existing filters. */
940 for (i = 1; i < 4; i++)
941 tl_setfilt(sc, (caddr_t)&dummy, i);
942 tl_dio_write32(sc, TL_HASH1, 0);
943 tl_dio_write32(sc, TL_HASH2, 0);
945 /* Now program new ones. */
946 if (ifp->if_flags & IFF_ALLMULTI) {
947 hashes[0] = 0xFFFFFFFF;
948 hashes[1] = 0xFFFFFFFF;
951 /* First find the tail of the list. */
952 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
953 ifma = ifma->ifma_link.le_next) {
954 if (ifma->ifma_link.le_next == NULL)
957 /* Now traverse the list backwards. */
958 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
959 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
960 if (ifma->ifma_addr->sa_family != AF_LINK)
963 * Program the first three multicast groups
964 * into the perfect filter. For all others,
965 * use the hash table.
969 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
975 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
977 hashes[0] |= (1 << h);
979 hashes[1] |= (1 << (h - 32));
983 tl_dio_write32(sc, TL_HASH1, hashes[0]);
984 tl_dio_write32(sc, TL_HASH2, hashes[1]);
990 * This routine is recommended by the ThunderLAN manual to insure that
991 * the internal PHY is powered up correctly. It also recommends a one
992 * second pause at the end to 'wait for the clocks to start' but in my
993 * experience this isn't necessary.
995 static void tl_hardreset(dev)
1002 sc = device_get_softc(dev);
1006 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1008 for (i = 0; i < MII_NPHY; i++)
1009 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1011 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1013 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1015 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1021 static void tl_softreset(sc, internal)
1022 struct tl_softc *sc;
1025 u_int32_t cmd, dummy, i;
1027 /* Assert the adapter reset bit. */
1028 CMD_SET(sc, TL_CMD_ADRST);
1030 /* Turn off interrupts */
1031 CMD_SET(sc, TL_CMD_INTSOFF);
1033 /* First, clear the stats registers. */
1034 for (i = 0; i < 5; i++)
1035 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1037 /* Clear Areg and Hash registers */
1038 for (i = 0; i < 8; i++)
1039 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1042 * Set up Netconfig register. Enable one channel and
1043 * one fragment mode.
1045 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1046 if (internal && !sc->tl_bitrate) {
1047 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1049 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1052 /* Handle cards with bitrate devices. */
1054 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1057 * Load adapter irq pacing timer and tx threshold.
1058 * We make the transmit threshold 1 initially but we may
1059 * change that later.
1061 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1063 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1064 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1065 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1067 /* Unreset the MII */
1068 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1070 /* Take the adapter out of reset */
1071 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1073 /* Wait for things to settle down a little. */
1080 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1081 * against our list and return its name if we find a match.
1083 static int tl_probe(dev)
1090 while(t->tl_name != NULL) {
1091 if ((pci_get_vendor(dev) == t->tl_vid) &&
1092 (pci_get_device(dev) == t->tl_did)) {
1093 device_set_desc(dev, t->tl_name);
1102 static int tl_attach(dev)
1110 struct tl_softc *sc;
1111 int unit, error = 0, rid;
1115 vid = pci_get_vendor(dev);
1116 did = pci_get_device(dev);
1117 sc = device_get_softc(dev);
1118 unit = device_get_unit(dev);
1119 bzero(sc, sizeof(struct tl_softc));
1122 while(t->tl_name != NULL) {
1123 if (vid == t->tl_vid && did == t->tl_did)
1128 KKASSERT(t->tl_name != NULL);
1131 * Map control/status registers.
1133 command = pci_read_config(dev, PCIR_COMMAND, 4);
1134 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1135 pci_write_config(dev, PCIR_COMMAND, command, 4);
1136 command = pci_read_config(dev, PCIR_COMMAND, 4);
1138 #ifdef TL_USEIOSPACE
1139 if (!(command & PCIM_CMD_PORTEN)) {
1140 printf("tl%d: failed to enable I/O ports!\n", unit);
1146 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1150 * Some cards have the I/O and memory mapped address registers
1151 * reversed. Try both combinations before giving up.
1153 if (sc->tl_res == NULL) {
1155 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1159 if (!(command & PCIM_CMD_MEMEN)) {
1160 printf("tl%d: failed to enable memory mapping!\n", unit);
1166 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1168 if (sc->tl_res == NULL) {
1170 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1175 if (sc->tl_res == NULL) {
1176 printf("tl%d: couldn't map ports/memory\n", unit);
1181 sc->tl_btag = rman_get_bustag(sc->tl_res);
1182 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1186 * The ThunderLAN manual suggests jacking the PCI latency
1187 * timer all the way up to its maximum value. I'm not sure
1188 * if this is really necessary, but what the manual wants,
1191 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1192 command |= 0x0000FF00;
1193 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1196 /* Allocate interrupt */
1198 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1199 RF_SHAREABLE | RF_ACTIVE);
1201 if (sc->tl_irq == NULL) {
1202 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1203 printf("tl%d: couldn't map interrupt\n", unit);
1208 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1209 tl_intr, sc, &sc->tl_intrhand, NULL);
1212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1213 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1214 printf("tl%d: couldn't set up irq\n", unit);
1219 * Now allocate memory for the TX and RX lists.
1221 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1222 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1224 if (sc->tl_ldata == NULL) {
1225 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1226 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1227 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1228 printf("tl%d: no memory for list buffers!\n", unit);
1233 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1237 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1238 sc->tl_eeaddr = TL_EEPROM_EADDR;
1239 if (t->tl_vid == OLICOM_VENDORID)
1240 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1242 /* Reset the adapter. */
1243 tl_softreset(sc, 1);
1245 tl_softreset(sc, 1);
1248 * Get station address from the EEPROM.
1250 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1251 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1252 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1253 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1254 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1255 contigfree(sc->tl_ldata,
1256 sizeof(struct tl_list_data), M_DEVBUF);
1257 printf("tl%d: failed to read station address\n", unit);
1263 * XXX Olicom, in its desire to be different from the
1264 * rest of the world, has done strange things with the
1265 * encoding of the station address in the EEPROM. First
1266 * of all, they store the address at offset 0xF8 rather
1267 * than at 0x83 like the ThunderLAN manual suggests.
1268 * Second, they store the address in three 16-bit words in
1269 * network byte order, as opposed to storing it sequentially
1270 * like all the other ThunderLAN cards. In order to get
1271 * the station address in a form that matches what the Olicom
1272 * diagnostic utility specifies, we have to byte-swap each
1273 * word. To make things even more confusing, neither 00:00:28
1274 * nor 00:00:24 appear in the IEEE OUI database.
1276 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1277 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1279 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1284 ifp = &sc->arpcom.ac_if;
1286 if_initname(ifp, "tl", sc->tl_unit);
1287 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1288 ifp->if_ioctl = tl_ioctl;
1289 ifp->if_start = tl_start;
1290 ifp->if_watchdog = tl_watchdog;
1291 ifp->if_init = tl_init;
1292 ifp->if_mtu = ETHERMTU;
1293 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1294 ifq_set_ready(&ifp->if_snd);
1295 callout_init(&sc->tl_stat_timer);
1297 /* Reset the adapter again. */
1298 tl_softreset(sc, 1);
1300 tl_softreset(sc, 1);
1303 * Do MII setup. If no PHYs are found, then this is a
1304 * bitrate ThunderLAN chip that only supports 10baseT
1307 if (mii_phy_probe(dev, &sc->tl_miibus,
1308 tl_ifmedia_upd, tl_ifmedia_sts)) {
1309 struct ifmedia *ifm;
1311 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1312 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1313 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1314 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1315 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1316 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1317 /* Reset again, this time setting bitrate mode. */
1318 tl_softreset(sc, 1);
1320 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1321 tl_ifmedia_upd(ifp);
1325 * Call MI attach routine.
1327 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1334 static int tl_detach(dev)
1337 struct tl_softc *sc;
1342 sc = device_get_softc(dev);
1343 ifp = &sc->arpcom.ac_if;
1346 ether_ifdetach(ifp);
1348 bus_generic_detach(dev);
1349 device_delete_child(dev, sc->tl_miibus);
1351 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1353 ifmedia_removeall(&sc->ifmedia);
1355 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1356 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1357 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1365 * Initialize the transmit lists.
1367 static int tl_list_tx_init(sc)
1368 struct tl_softc *sc;
1370 struct tl_chain_data *cd;
1371 struct tl_list_data *ld;
1376 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1377 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1378 if (i == (TL_TX_LIST_CNT - 1))
1379 cd->tl_tx_chain[i].tl_next = NULL;
1381 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1384 cd->tl_tx_free = &cd->tl_tx_chain[0];
1385 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1392 * Initialize the RX lists and allocate mbufs for them.
1394 static int tl_list_rx_init(sc)
1395 struct tl_softc *sc;
1397 struct tl_chain_data *cd;
1398 struct tl_list_data *ld;
1404 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1405 cd->tl_rx_chain[i].tl_ptr =
1406 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1407 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1409 if (i == (TL_RX_LIST_CNT - 1)) {
1410 cd->tl_rx_chain[i].tl_next = NULL;
1411 ld->tl_rx_list[i].tlist_fptr = 0;
1413 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1414 ld->tl_rx_list[i].tlist_fptr =
1415 vtophys(&ld->tl_rx_list[i + 1]);
1419 cd->tl_rx_head = &cd->tl_rx_chain[0];
1420 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1425 static int tl_newbuf(sc, c)
1426 struct tl_softc *sc;
1427 struct tl_chain_onefrag *c;
1431 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1437 c->tl_ptr->tlist_frsize = MCLBYTES;
1438 c->tl_ptr->tlist_fptr = 0;
1439 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1440 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1441 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1446 * Interrupt handler for RX 'end of frame' condition (EOF). This
1447 * tells us that a full ethernet frame has been captured and we need
1450 * Reception is done using 'lists' which consist of a header and a
1451 * series of 10 data count/data address pairs that point to buffers.
1452 * Initially you're supposed to create a list, populate it with pointers
1453 * to buffers, then load the physical address of the list into the
1454 * ch_parm register. The adapter is then supposed to DMA the received
1455 * frame into the buffers for you.
1457 * To make things as fast as possible, we have the chip DMA directly
1458 * into mbufs. This saves us from having to do a buffer copy: we can
1459 * just hand the mbufs directly to ether_input(). Once the frame has
1460 * been sent on its way, the 'list' structure is assigned a new buffer
1461 * and moved to the end of the RX chain. As long we we stay ahead of
1462 * the chip, it will always think it has an endless receive channel.
1464 * If we happen to fall behind and the chip manages to fill up all of
1465 * the buffers, it will generate an end of channel interrupt and wait
1466 * for us to empty the chain and restart the receiver.
1468 static int tl_intvec_rxeof(xsc, type)
1472 struct tl_softc *sc;
1473 int r = 0, total_len = 0;
1474 struct ether_header *eh;
1477 struct tl_chain_onefrag *cur_rx;
1480 ifp = &sc->arpcom.ac_if;
1482 while(sc->tl_cdata.tl_rx_head != NULL) {
1483 cur_rx = sc->tl_cdata.tl_rx_head;
1484 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1487 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1488 m = cur_rx->tl_mbuf;
1489 total_len = cur_rx->tl_ptr->tlist_frsize;
1491 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1493 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1494 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1495 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1499 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1500 vtophys(cur_rx->tl_ptr);
1501 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1502 sc->tl_cdata.tl_rx_tail = cur_rx;
1504 eh = mtod(m, struct ether_header *);
1505 m->m_pkthdr.rcvif = ifp;
1508 * Note: when the ThunderLAN chip is in 'capture all
1509 * frames' mode, it will receive its own transmissions.
1510 * We drop don't need to process our own transmissions,
1511 * so we drop them here and continue.
1513 /*if (ifp->if_flags & IFF_PROMISC && */
1514 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1520 (*ifp->if_input)(ifp, m);
1527 * The RX-EOC condition hits when the ch_parm address hasn't been
1528 * initialized or the adapter reached a list with a forward pointer
1529 * of 0 (which indicates the end of the chain). In our case, this means
1530 * the card has hit the end of the receive buffer chain and we need to
1531 * empty out the buffers and shift the pointer back to the beginning again.
1533 static int tl_intvec_rxeoc(xsc, type)
1537 struct tl_softc *sc;
1539 struct tl_chain_data *cd;
1545 /* Flush out the receive queue and ack RXEOF interrupts. */
1546 r = tl_intvec_rxeof(xsc, type);
1547 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1549 cd->tl_rx_head = &cd->tl_rx_chain[0];
1550 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1551 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1552 r |= (TL_CMD_GO|TL_CMD_RT);
1556 static int tl_intvec_txeof(xsc, type)
1560 struct tl_softc *sc;
1562 struct tl_chain *cur_tx;
1567 * Go through our tx list and free mbufs for those
1568 * frames that have been sent.
1570 while (sc->tl_cdata.tl_tx_head != NULL) {
1571 cur_tx = sc->tl_cdata.tl_tx_head;
1572 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1574 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1577 m_freem(cur_tx->tl_mbuf);
1578 cur_tx->tl_mbuf = NULL;
1580 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1581 sc->tl_cdata.tl_tx_free = cur_tx;
1582 if (!cur_tx->tl_ptr->tlist_fptr)
1590 * The transmit end of channel interrupt. The adapter triggers this
1591 * interrupt to tell us it hit the end of the current transmit list.
1593 * A note about this: it's possible for a condition to arise where
1594 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1595 * You have to avoid this since the chip expects things to go in a
1596 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1597 * When the TXEOF handler is called, it will free all of the transmitted
1598 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1599 * interrupt should be received and acknowledged before any more frames
1600 * are queued for transmission. If tl_statrt() is called after TXEOF
1601 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1602 * it could attempt to issue a transmit command prematurely.
1604 * To guard against this, tl_start() will only issue transmit commands
1605 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1606 * can set this flag once tl_start() has cleared it.
1608 static int tl_intvec_txeoc(xsc, type)
1612 struct tl_softc *sc;
1617 ifp = &sc->arpcom.ac_if;
1619 /* Clear the timeout timer. */
1622 if (sc->tl_cdata.tl_tx_head == NULL) {
1623 ifp->if_flags &= ~IFF_OACTIVE;
1624 sc->tl_cdata.tl_tx_tail = NULL;
1628 /* First we have to ack the EOC interrupt. */
1629 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1630 /* Then load the address of the next TX list. */
1631 CSR_WRITE_4(sc, TL_CH_PARM,
1632 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1633 /* Restart TX channel. */
1634 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1636 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1644 static int tl_intvec_adchk(xsc, type)
1648 struct tl_softc *sc;
1653 printf("tl%d: adapter check: %x\n", sc->tl_unit,
1654 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1656 tl_softreset(sc, 1);
1659 CMD_SET(sc, TL_CMD_INTSON);
1664 static int tl_intvec_netsts(xsc, type)
1668 struct tl_softc *sc;
1673 netsts = tl_dio_read16(sc, TL_NETSTS);
1674 tl_dio_write16(sc, TL_NETSTS, netsts);
1676 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
1681 static void tl_intr(xsc)
1684 struct tl_softc *sc;
1693 /* Disable interrupts */
1694 ints = CSR_READ_2(sc, TL_HOST_INT);
1695 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1696 type = (ints << 16) & 0xFFFF0000;
1697 ivec = (ints & TL_VEC_MASK) >> 5;
1698 ints = (ints & TL_INT_MASK) >> 2;
1700 ifp = &sc->arpcom.ac_if;
1703 case (TL_INTR_INVALID):
1705 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
1707 /* Re-enable interrupts but don't ack this one. */
1711 case (TL_INTR_TXEOF):
1712 r = tl_intvec_txeof((void *)sc, type);
1714 case (TL_INTR_TXEOC):
1715 r = tl_intvec_txeoc((void *)sc, type);
1717 case (TL_INTR_STATOFLOW):
1718 tl_stats_update(sc);
1721 case (TL_INTR_RXEOF):
1722 r = tl_intvec_rxeof((void *)sc, type);
1724 case (TL_INTR_DUMMY):
1725 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
1728 case (TL_INTR_ADCHK):
1730 r = tl_intvec_adchk((void *)sc, type);
1732 r = tl_intvec_netsts((void *)sc, type);
1734 case (TL_INTR_RXEOC):
1735 r = tl_intvec_rxeoc((void *)sc, type);
1738 printf("%s: bogus interrupt type\n", ifp->if_xname);
1742 /* Re-enable interrupts */
1744 CMD_PUT(sc, TL_CMD_ACK | r | type);
1747 if (!ifq_is_empty(&ifp->if_snd))
1753 static void tl_stats_update(xsc)
1756 struct tl_softc *sc;
1758 struct tl_stats tl_stats;
1759 struct mii_data *mii;
1764 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1767 ifp = &sc->arpcom.ac_if;
1769 p = (u_int32_t *)&tl_stats;
1771 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1772 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1773 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1774 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1775 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1776 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1778 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1779 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1780 tl_stats.tl_tx_multi_collision;
1781 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1782 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1783 tl_rx_overrun(tl_stats);
1784 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1786 if (tl_tx_underrun(tl_stats)) {
1788 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1789 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1792 printf("tl%d: tx underrun -- increasing "
1793 "tx threshold to %d bytes\n", sc->tl_unit,
1794 (64 * (tx_thresh * 4)));
1795 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1796 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1800 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1802 if (!sc->tl_bitrate) {
1803 mii = device_get_softc(sc->tl_miibus);
1813 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1814 * pointers to the fragment pointers.
1816 static int tl_encap(sc, c, m_head)
1817 struct tl_softc *sc;
1819 struct mbuf *m_head;
1822 struct tl_frag *f = NULL;
1827 * Start packing the mbufs in this chain into
1828 * the fragment pointers. Stop when we run out
1829 * of fragments or hit the end of the mbuf chain.
1834 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1835 if (m->m_len != 0) {
1836 if (frag == TL_MAXFRAGS)
1838 total_len+= m->m_len;
1839 c->tl_ptr->tl_frag[frag].tlist_dadr =
1840 vtophys(mtod(m, vm_offset_t));
1841 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1847 * Handle special cases.
1848 * Special case #1: we used up all 10 fragments, but
1849 * we have more mbufs left in the chain. Copy the
1850 * data into an mbuf cluster. Note that we don't
1851 * bother clearing the values in the other fragment
1852 * pointers/counters; it wouldn't gain us anything,
1853 * and would waste cycles.
1858 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA,
1860 if (m_new == NULL) {
1861 printf("tl%d: no memory for tx list\n", sc->tl_unit);
1864 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1865 mtod(m_new, caddr_t));
1866 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1869 f = &c->tl_ptr->tl_frag[0];
1870 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1871 f->tlist_dcnt = total_len = m_new->m_len;
1876 * Special case #2: the frame is smaller than the minimum
1877 * frame size. We have to pad it to make the chip happy.
1879 if (total_len < TL_MIN_FRAMELEN) {
1880 if (frag == TL_MAXFRAGS)
1881 printf("tl%d: all frags filled but "
1882 "frame still to small!\n", sc->tl_unit);
1883 f = &c->tl_ptr->tl_frag[frag];
1884 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1885 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1886 total_len += f->tlist_dcnt;
1890 c->tl_mbuf = m_head;
1891 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1892 c->tl_ptr->tlist_frsize = total_len;
1893 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1894 c->tl_ptr->tlist_fptr = 0;
1900 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1901 * to the mbuf data regions directly in the transmit lists. We also save a
1902 * copy of the pointers since the transmit list fragment pointers are
1903 * physical addresses.
1905 static void tl_start(ifp)
1908 struct tl_softc *sc;
1909 struct mbuf *m_head = NULL;
1911 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1916 * Check for an available queue slot. If there are none,
1919 if (sc->tl_cdata.tl_tx_free == NULL) {
1920 ifp->if_flags |= IFF_OACTIVE;
1924 start_tx = sc->tl_cdata.tl_tx_free;
1926 while(sc->tl_cdata.tl_tx_free != NULL) {
1927 m_head = ifq_dequeue(&ifp->if_snd);
1931 /* Pick a chain member off the free list. */
1932 cur_tx = sc->tl_cdata.tl_tx_free;
1933 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1935 cur_tx->tl_next = NULL;
1937 /* Pack the data into the list. */
1938 tl_encap(sc, cur_tx, m_head);
1940 /* Chain it together */
1942 prev->tl_next = cur_tx;
1943 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1947 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1951 * If there are no packets queued, bail.
1957 * That's all we can stands, we can't stands no more.
1958 * If there are no other transfers pending, then issue the
1959 * TX GO command to the adapter to start things moving.
1960 * Otherwise, just leave the data in the queue and let
1961 * the EOF/EOC interrupt handler send.
1963 if (sc->tl_cdata.tl_tx_head == NULL) {
1964 sc->tl_cdata.tl_tx_head = start_tx;
1965 sc->tl_cdata.tl_tx_tail = cur_tx;
1969 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1970 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1972 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1976 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1977 sc->tl_cdata.tl_tx_tail = cur_tx;
1981 * Set a timeout in case the chip goes out to lunch.
1988 static void tl_init(xsc)
1991 struct tl_softc *sc = xsc;
1992 struct ifnet *ifp = &sc->arpcom.ac_if;
1993 struct mii_data *mii;
1998 * Cancel pending I/O.
2002 /* Initialize TX FIFO threshold */
2003 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2004 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2006 /* Set PCI burst size */
2007 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2010 * Set 'capture all frames' bit for promiscuous mode.
2012 if (ifp->if_flags & IFF_PROMISC)
2013 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2015 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2018 * Set capture broadcast bit to capture broadcast frames.
2020 if (ifp->if_flags & IFF_BROADCAST)
2021 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2023 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2025 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2027 /* Init our MAC address */
2028 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2030 /* Init multicast filter, if needed. */
2033 /* Init circular RX list. */
2034 if (tl_list_rx_init(sc) == ENOBUFS) {
2035 printf("tl%d: initialization failed: no "
2036 "memory for rx buffers\n", sc->tl_unit);
2041 /* Init TX pointers. */
2042 tl_list_tx_init(sc);
2044 /* Enable PCI interrupts. */
2045 CMD_SET(sc, TL_CMD_INTSON);
2047 /* Load the address of the rx list */
2048 CMD_SET(sc, TL_CMD_RT);
2049 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2051 if (!sc->tl_bitrate) {
2052 if (sc->tl_miibus != NULL) {
2053 mii = device_get_softc(sc->tl_miibus);
2058 /* Send the RX go command */
2059 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2061 ifp->if_flags |= IFF_RUNNING;
2062 ifp->if_flags &= ~IFF_OACTIVE;
2064 /* Start the stats update counter */
2065 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
2071 * Set media options.
2073 static int tl_ifmedia_upd(ifp)
2076 struct tl_softc *sc;
2077 struct mii_data *mii = NULL;
2082 tl_setmode(sc, sc->ifmedia.ifm_media);
2084 mii = device_get_softc(sc->tl_miibus);
2092 * Report current media status.
2094 static void tl_ifmedia_sts(ifp, ifmr)
2096 struct ifmediareq *ifmr;
2098 struct tl_softc *sc;
2099 struct mii_data *mii;
2103 ifmr->ifm_active = IFM_ETHER;
2105 if (sc->tl_bitrate) {
2106 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2107 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2109 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2110 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2111 ifmr->ifm_active |= IFM_HDX;
2113 ifmr->ifm_active |= IFM_FDX;
2116 mii = device_get_softc(sc->tl_miibus);
2118 ifmr->ifm_active = mii->mii_media_active;
2119 ifmr->ifm_status = mii->mii_media_status;
2125 static int tl_ioctl(ifp, command, data, cr)
2131 struct tl_softc *sc = ifp->if_softc;
2132 struct ifreq *ifr = (struct ifreq *) data;
2139 if (ifp->if_flags & IFF_UP) {
2140 if (ifp->if_flags & IFF_RUNNING &&
2141 ifp->if_flags & IFF_PROMISC &&
2142 !(sc->tl_if_flags & IFF_PROMISC)) {
2143 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2145 } else if (ifp->if_flags & IFF_RUNNING &&
2146 !(ifp->if_flags & IFF_PROMISC) &&
2147 sc->tl_if_flags & IFF_PROMISC) {
2148 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2153 if (ifp->if_flags & IFF_RUNNING) {
2157 sc->tl_if_flags = ifp->if_flags;
2168 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2170 struct mii_data *mii;
2171 mii = device_get_softc(sc->tl_miibus);
2172 error = ifmedia_ioctl(ifp, ifr,
2173 &mii->mii_media, command);
2177 error = ether_ioctl(ifp, command, data);
2186 static void tl_watchdog(ifp)
2189 struct tl_softc *sc;
2193 printf("tl%d: device timeout\n", sc->tl_unit);
2197 tl_softreset(sc, 1);
2204 * Stop the adapter and free any mbufs allocated to the
2207 static void tl_stop(sc)
2208 struct tl_softc *sc;
2213 ifp = &sc->arpcom.ac_if;
2215 /* Stop the stats updater. */
2216 callout_stop(&sc->tl_stat_timer);
2218 /* Stop the transmitter */
2219 CMD_CLR(sc, TL_CMD_RT);
2220 CMD_SET(sc, TL_CMD_STOP);
2221 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2223 /* Stop the receiver */
2224 CMD_SET(sc, TL_CMD_RT);
2225 CMD_SET(sc, TL_CMD_STOP);
2226 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2229 * Disable host interrupts.
2231 CMD_SET(sc, TL_CMD_INTSOFF);
2234 * Clear list pointer.
2236 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2239 * Free the RX lists.
2241 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2242 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2243 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2244 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2247 bzero((char *)&sc->tl_ldata->tl_rx_list,
2248 sizeof(sc->tl_ldata->tl_rx_list));
2251 * Free the TX list buffers.
2253 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2254 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2255 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2256 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2259 bzero((char *)&sc->tl_ldata->tl_tx_list,
2260 sizeof(sc->tl_ldata->tl_tx_list));
2262 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2268 * Stop all chip I/O so that the kernel's probe routines don't
2269 * get confused by errant DMAs when rebooting.
2271 static void tl_shutdown(dev)
2274 struct tl_softc *sc;
2276 sc = device_get_softc(dev);