sys/dev/netif/sk/if_sk.c

   1 /*
   2  * Copyright (c) 1997, 1998, 1999, 2000
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
  33  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
  34  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.52 2006/12/22 23:26:22 swildner Exp $
  35  */
  36
  37 /*
  38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  39  *
  40  * Permission to use, copy, modify, and distribute this software for any
  41  * purpose with or without fee is hereby granted, provided that the above
  42  * copyright notice and this permission notice appear in all copies.
  43  *
  44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  51  */
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71
  72 /*
  73  * The SysKonnect gigabit ethernet adapters consist of two main
  74  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  75  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  76  * components and a PHY while the GEnesis controller provides a PCI
  77  * interface with DMA support. Each card may have between 512K and
  78  * 2MB of SRAM on board depending on the configuration.
  79  *
  80  * The SysKonnect GEnesis controller can have either one or two XMAC
  81  * chips connected to it, allowing single or dual port NIC configurations.
  82  * SysKonnect has the distinction of being the only vendor on the market
  83  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  84  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  85  * XMAC registers. This driver takes advantage of these features to allow
  86  * both XMACs to operate as independent interfaces.
  87  */
  88
  89 #include <sys/param.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/in_cksum.h>
  93 #include <sys/kernel.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/queue.h>
  97 #include <sys/rman.h>
  98 #include <sys/serialize.h>
  99 #include <sys/socket.h>
 100 #include <sys/sockio.h>
 101
 102 #include <net/bpf.h>
 103 #include <net/ethernet.h>
 104 #include <net/if.h>
 105 #include <net/if_arp.h>
 106 #include <net/if_dl.h>
 107 #include <net/if_media.h>
 108 #include <net/ifq_var.h>
 109 #include <net/vlan/if_vlan_var.h>
 110
 111 #include <netinet/ip.h>
 112 #include <netinet/udp.h>
 113
 114 #include <dev/netif/mii_layer/mii.h>
 115 #include <dev/netif/mii_layer/miivar.h>
 116 #include <dev/netif/mii_layer/brgphyreg.h>
 117
 118 #include <bus/pci/pcireg.h>
 119 #include <bus/pci/pcivar.h>
 120 #include <bus/pci/pcidevs.h>
 121
 122 #include <dev/netif/sk/if_skreg.h>
 123 #include <dev/netif/sk/yukonreg.h>
 124 #include <dev/netif/sk/xmaciireg.h>
 125 #include <dev/netif/sk/if_skvar.h>
 126
 127 #include "miibus_if.h"
 128
 129 #if 0
 130 #define SK_DEBUG
 131 #endif
 132
 133 #if 0
 134 #define SK_RXCSUM
 135 #endif
 136
 137 /* supported device vendors */
 138 static const struct skc_type {
 139         uint16_t        skc_vid;
 140         uint16_t        skc_did;
 141         const char      *skc_name;
 142 } skc_devs[] = {
 143         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940,
 144           "3Com 3C940" },
 145         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940B,
 146           "3Com 3C940B" },
 147
 148         { PCI_VENDOR_CNET,              PCI_PRODUCT_CNET_GIGACARD,
 149           "CNet GigaCard" },
 150
 151         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_A1,
 152           "D-Link DGE-530T A1" },
 153         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_B1,
 154           "D-Link DGE-530T B1" },
 155
 156         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1032,
 157           "Linksys EG1032 v2" },
 158         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1064,
 159           "Linksys EG1064" },
 160
 161         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON,
 162           "Marvell Yukon 88E8001/8003/8010" },
 163         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_BELKIN,
 164           "Belkin F5D5005" },
 165
 166         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
 167           "SysKonnect SK-NET" },
 168         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
 169           "SysKonnect SK9821 v2" },
 170
 171         { 0, 0, NULL }
 172 };
 173
 174 static int      skc_probe(device_t);
 175 static int      skc_attach(device_t);
 176 static int      skc_detach(device_t);
 177 static void     skc_shutdown(device_t);
 178 static int      sk_probe(device_t);
 179 static int      sk_attach(device_t);
 180 static int      sk_detach(device_t);
 181 static void     sk_tick(void *);
 182 static void     sk_yukon_tick(void *);
 183 static void     sk_intr(void *);
 184 static void     sk_intr_bcom(struct sk_if_softc *);
 185 static void     sk_intr_xmac(struct sk_if_softc *);
 186 static void     sk_intr_yukon(struct sk_if_softc *);
 187 static void     sk_rxeof(struct sk_if_softc *);
 188 static void     sk_txeof(struct sk_if_softc *);
 189 static int      sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
 190 static void     sk_start(struct ifnet *);
 191 static int      sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 192 static void     sk_init(void *);
 193 static void     sk_init_xmac(struct sk_if_softc *);
 194 static void     sk_init_yukon(struct sk_if_softc *);
 195 static void     sk_stop(struct sk_if_softc *);
 196 static void     sk_watchdog(struct ifnet *);
 197 static int      sk_ifmedia_upd(struct ifnet *);
 198 static void     sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 199 static void     sk_reset(struct sk_softc *);
 200 static int      sk_newbuf_jumbo(struct sk_if_softc *, int, int);
 201 static int      sk_newbuf_std(struct sk_if_softc *, int, int);
 202 static int      sk_jpool_alloc(device_t);
 203 static void     sk_jpool_free(struct sk_if_softc *);
 204 static struct sk_jpool_entry
 205                 *sk_jalloc(struct sk_if_softc *);
 206 static void     sk_jfree(void *);
 207 static void     sk_jref(void *);
 208 static int      sk_init_rx_ring(struct sk_if_softc *);
 209 static int      sk_init_tx_ring(struct sk_if_softc *);
 210
 211 static int      sk_miibus_readreg(device_t, int, int);
 212 static int      sk_miibus_writereg(device_t, int, int, int);
 213 static void     sk_miibus_statchg(device_t);
 214
 215 static int      sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 216 static int      sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
 217 static void     sk_xmac_miibus_statchg(struct sk_if_softc *);
 218
 219 static int      sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 220 static int      sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
 221 static void     sk_marv_miibus_statchg(struct sk_if_softc *);
 222
 223 static void     sk_setfilt(struct sk_if_softc *, caddr_t, int);
 224 static void     sk_setmulti(struct sk_if_softc *);
 225 static void     sk_setpromisc(struct sk_if_softc *);
 226
 227 #ifdef SK_RXCSUM
 228 static void     sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
 229                           const uint16_t);
 230 #endif
 231 static int      sk_dma_alloc(device_t);
 232 static void     sk_dma_free(device_t);
 233
 234 static void     sk_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
 235                                 int);
 236 static void     sk_dmamem_addr(void *, bus_dma_segment_t *, int, int);
 237
 238 #ifdef SK_DEBUG
 239 #define DPRINTF(x)      if (skdebug) kprintf x
 240 #define DPRINTFN(n,x)   if (skdebug >= (n)) kprintf x
 241 static int      skdebug = 2;
 242
 243 static void     sk_dump_txdesc(struct sk_tx_desc *, int);
 244 static void     sk_dump_mbuf(struct mbuf *);
 245 static void     sk_dump_bytes(const char *, int);
 246 #else
 247 #define DPRINTF(x)
 248 #define DPRINTFN(n,x)
 249 #endif
 250
 251 /*
 252  * Note that we have newbus methods for both the GEnesis controller
 253  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 254  * the miibus code is a child of the XMACs. We need to do it this way
 255  * so that the miibus drivers can access the PHY registers on the
 256  * right PHY. It's not quite what I had in mind, but it's the only
 257  * design that achieves the desired effect.
 258  */
 259 static device_method_t skc_methods[] = {
 260         /* Device interface */
 261         DEVMETHOD(device_probe,         skc_probe),
 262         DEVMETHOD(device_attach,        skc_attach),
 263         DEVMETHOD(device_detach,        skc_detach),
 264         DEVMETHOD(device_shutdown,      skc_shutdown),
 265
 266         /* bus interface */
 267         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 268         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 269
 270         { 0, 0 }
 271 };
 272
 273 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
 274 static devclass_t skc_devclass;
 275
 276 static device_method_t sk_methods[] = {
 277         /* Device interface */
 278         DEVMETHOD(device_probe,         sk_probe),
 279         DEVMETHOD(device_attach,        sk_attach),
 280         DEVMETHOD(device_detach,        sk_detach),
 281         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 282
 283         /* bus interface */
 284         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 285         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 286
 287         /* MII interface */
 288         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 289         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 290         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 291
 292         { 0, 0 }
 293 };
 294
 295 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
 296 static devclass_t sk_devclass;
 297
 298 DECLARE_DUMMY_MODULE(if_sk);
 299 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 300 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 301 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 302
 303 static __inline uint32_t
 304 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
 305 {
 306         return CSR_READ_4(sc, reg);
 307 }
 308
 309 static __inline uint16_t
 310 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
 311 {
 312         return CSR_READ_2(sc, reg);
 313 }
 314
 315 static __inline uint8_t
 316 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
 317 {
 318         return CSR_READ_1(sc, reg);
 319 }
 320
 321 static __inline void
 322 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
 323 {
 324         CSR_WRITE_4(sc, reg, x);
 325 }
 326
 327 static __inline void
 328 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
 329 {
 330         CSR_WRITE_2(sc, reg, x);
 331 }
 332
 333 static __inline void
 334 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
 335 {
 336         CSR_WRITE_1(sc, reg, x);
 337 }
 338
 339 static __inline int
 340 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
 341 {
 342         int ret;
 343
 344         if (sc_if->sk_use_jumbo)
 345                 ret = sk_newbuf_jumbo(sc_if, idx, wait);
 346         else
 347                 ret = sk_newbuf_std(sc_if, idx, wait);
 348         return ret;
 349 }
 350
 351 static int
 352 sk_miibus_readreg(device_t dev, int phy, int reg)
 353 {
 354         struct sk_if_softc *sc_if = device_get_softc(dev);
 355
 356         if (SK_IS_GENESIS(sc_if->sk_softc))
 357                 return sk_xmac_miibus_readreg(sc_if, phy, reg);
 358         else
 359                 return sk_marv_miibus_readreg(sc_if, phy, reg);
 360 }
 361
 362 static int
 363 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
 364 {
 365         struct sk_if_softc *sc_if = device_get_softc(dev);
 366
 367         if (SK_IS_GENESIS(sc_if->sk_softc))
 368                 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 369         else
 370                 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
 371 }
 372
 373 static void
 374 sk_miibus_statchg(device_t dev)
 375 {
 376         struct sk_if_softc *sc_if = device_get_softc(dev);
 377
 378         if (SK_IS_GENESIS(sc_if->sk_softc))
 379                 sk_xmac_miibus_statchg(sc_if);
 380         else
 381                 sk_marv_miibus_statchg(sc_if);
 382 }
 383
 384 static int
 385 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 386 {
 387         int i;
 388
 389         DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
 390
 391         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 392                 return(0);
 393
 394         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 395         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 396         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 397                 for (i = 0; i < SK_TIMEOUT; i++) {
 398                         DELAY(1);
 399                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 400                             XM_MMUCMD_PHYDATARDY)
 401                                 break;
 402                 }
 403
 404                 if (i == SK_TIMEOUT) {
 405                         if_printf(&sc_if->arpcom.ac_if,
 406                                   "phy failed to come ready\n");
 407                         return(0);
 408                 }
 409         }
 410         DELAY(1);
 411         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 412 }
 413
 414 static int
 415 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 416 {
 417         int i;
 418
 419         DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
 420
 421         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 422         for (i = 0; i < SK_TIMEOUT; i++) {
 423                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 424                         break;
 425         }
 426
 427         if (i == SK_TIMEOUT) {
 428                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 429                 return(ETIMEDOUT);
 430         }
 431
 432         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 433         for (i = 0; i < SK_TIMEOUT; i++) {
 434                 DELAY(1);
 435                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 436                         break;
 437         }
 438
 439         if (i == SK_TIMEOUT)
 440                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 441         return(0);
 442 }
 443
 444 static void
 445 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
 446 {
 447         struct mii_data *mii;
 448
 449         mii = device_get_softc(sc_if->sk_miibus);
 450         DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
 451
 452         /*
 453          * If this is a GMII PHY, manually set the XMAC's
 454          * duplex mode accordingly.
 455          */
 456         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 457                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 458                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 459                 else
 460                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 461         }
 462 }
 463
 464 static int
 465 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 466 {
 467         uint16_t val;
 468         int i;
 469
 470         if (phy != 0 ||
 471             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 472              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 473                 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
 474                              phy, reg));
 475                 return(0);
 476         }
 477
 478         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 479                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 480
 481         for (i = 0; i < SK_TIMEOUT; i++) {
 482                 DELAY(1);
 483                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 484                 if (val & YU_SMICR_READ_VALID)
 485                         break;
 486         }
 487
 488         if (i == SK_TIMEOUT) {
 489                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 490                 return(0);
 491         }
 492
 493         DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
 494                      SK_TIMEOUT));
 495
 496         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 497
 498         DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
 499                      phy, reg, val));
 500
 501         return(val);
 502 }
 503
 504 static int
 505 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 506 {
 507         int i;
 508
 509         DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
 510                      phy, reg, val));
 511
 512         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 513         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 514                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 515
 516         for (i = 0; i < SK_TIMEOUT; i++) {
 517                 DELAY(1);
 518                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 519                         break;
 520         }
 521
 522         if (i == SK_TIMEOUT)
 523                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 524
 525         return(0);
 526 }
 527
 528 static void
 529 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
 530 {
 531         DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
 532                      SK_YU_READ_2(sc_if, YUKON_GPCR)));
 533 }
 534
 535 #define HASH_BITS       6
 536
 537 static uint32_t
 538 sk_xmac_hash(caddr_t addr)
 539 {
 540         uint32_t crc;
 541
 542         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 543         return (~crc & ((1 << HASH_BITS) - 1));
 544 }
 545
 546 static uint32_t
 547 sk_yukon_hash(caddr_t addr)
 548 {
 549         uint32_t crc;
 550
 551         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
 552         return (crc & ((1 << HASH_BITS) - 1));
 553 }
 554
 555 static void
 556 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
 557 {
 558         int base;
 559
 560         base = XM_RXFILT_ENTRY(slot);
 561
 562         SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
 563         SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
 564         SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
 565 }
 566
 567 static void
 568 sk_setmulti(struct sk_if_softc *sc_if)
 569 {
 570         struct sk_softc *sc = sc_if->sk_softc;
 571         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 572         uint32_t hashes[2] = { 0, 0 };
 573         int h = 0, i;
 574         struct ifmultiaddr *ifma;
 575         uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
 576
 577         /* First, zot all the existing filters. */
 578         switch(sc->sk_type) {
 579         case SK_GENESIS:
 580                 for (i = 1; i < XM_RXFILT_MAX; i++)
 581                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 582
 583                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 584                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 585                 break;
 586         case SK_YUKON:
 587         case SK_YUKON_LITE:
 588         case SK_YUKON_LP:
 589                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 590                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 591                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 592                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 593                 break;
 594         }
 595
 596         /* Now program new ones. */
 597         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 598                 hashes[0] = 0xFFFFFFFF;
 599                 hashes[1] = 0xFFFFFFFF;
 600         } else {
 601                 i = 1;
 602                 /* First find the tail of the list. */
 603                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 604                         if (ifma->ifma_link.le_next == NULL)
 605                                 break;
 606                 }
 607                 /* Now traverse the list backwards. */
 608                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 609                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 610                         caddr_t maddr;
 611
 612                         if (ifma->ifma_addr->sa_family != AF_LINK)
 613                                 continue;
 614
 615                         maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 616
 617                         /*
 618                          * Program the first XM_RXFILT_MAX multicast groups
 619                          * into the perfect filter. For all others,
 620                          * use the hash table.
 621                          */
 622                         if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
 623                                 sk_setfilt(sc_if, maddr, i);
 624                                 i++;
 625                                 continue;
 626                         }
 627
 628                         switch(sc->sk_type) {
 629                         case SK_GENESIS:
 630                                 h = sk_xmac_hash(maddr);
 631                                 break;
 632
 633                         case SK_YUKON:
 634                         case SK_YUKON_LITE:
 635                         case SK_YUKON_LP:
 636                                 h = sk_yukon_hash(maddr);
 637                                 break;
 638                         }
 639                         if (h < 32)
 640                                 hashes[0] |= (1 << h);
 641                         else
 642                                 hashes[1] |= (1 << (h - 32));
 643                 }
 644         }
 645
 646         switch(sc->sk_type) {
 647         case SK_GENESIS:
 648                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 649                                XM_MODE_RX_USE_PERFECT);
 650                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 651                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 652                 break;
 653         case SK_YUKON:
 654         case SK_YUKON_LITE:
 655         case SK_YUKON_LP:
 656                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 657                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 658                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 659                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 660                 break;
 661         }
 662 }
 663
 664 static void
 665 sk_setpromisc(struct sk_if_softc *sc_if)
 666 {
 667         struct sk_softc *sc = sc_if->sk_softc;
 668         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 669
 670         switch(sc->sk_type) {
 671         case SK_GENESIS:
 672                 if (ifp->if_flags & IFF_PROMISC)
 673                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 674                 else
 675                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 676                 break;
 677         case SK_YUKON:
 678         case SK_YUKON_LITE:
 679         case SK_YUKON_LP:
 680                 if (ifp->if_flags & IFF_PROMISC) {
 681                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 682                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 683                 } else {
 684                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 685                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 686                 }
 687                 break;
 688         }
 689 }
 690
 691 static int
 692 sk_init_rx_ring(struct sk_if_softc *sc_if)
 693 {
 694         struct sk_chain_data *cd = &sc_if->sk_cdata;
 695         struct sk_ring_data *rd = sc_if->sk_rdata;
 696         int i, nexti, error;
 697
 698         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 699
 700         for (i = 0; i < SK_RX_RING_CNT; i++) {
 701                 if (i == (SK_RX_RING_CNT - 1))
 702                         nexti = 0;
 703                 else
 704                         nexti = i + 1;
 705                 rd->sk_rx_ring[i].sk_next =
 706                         htole32(SK_RX_RING_ADDR(sc_if, nexti));
 707                 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
 708                 rd->sk_rx_ring[i].sk_csum2_start =
 709                         htole16(ETHER_HDR_LEN + sizeof(struct ip));
 710
 711                 error = sk_newbuf(sc_if, i, 1);
 712                 if (error) {
 713                         if_printf(&sc_if->arpcom.ac_if,
 714                                   "failed alloc of %dth mbuf\n", i);
 715                         return error;
 716                 }
 717         }
 718
 719         cd->sk_rx_prod = 0;
 720         cd->sk_rx_cons = 0;
 721
 722         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
 723                         BUS_DMASYNC_PREWRITE);
 724
 725         return (0);
 726 }
 727
 728 static int
 729 sk_init_tx_ring(struct sk_if_softc *sc_if)
 730 {
 731         struct sk_ring_data *rd = sc_if->sk_rdata;
 732         int i, nexti;
 733
 734         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 735
 736         for (i = 0; i < SK_TX_RING_CNT; i++) {
 737                 if (i == (SK_TX_RING_CNT - 1))
 738                         nexti = 0;
 739                 else
 740                         nexti = i + 1;
 741                 rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti));
 742         }
 743
 744         sc_if->sk_cdata.sk_tx_prod = 0;
 745         sc_if->sk_cdata.sk_tx_cons = 0;
 746         sc_if->sk_cdata.sk_tx_cnt = 0;
 747
 748         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
 749                         BUS_DMASYNC_PREWRITE);
 750
 751         return (0);
 752 }
 753
 754 static int
 755 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
 756 {
 757         struct sk_jpool_entry *entry;
 758         struct mbuf *m_new = NULL;
 759         struct sk_rx_desc *r;
 760
 761         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 762
 763         MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 764         if (m_new == NULL)
 765                 return ENOBUFS;
 766
 767         /* Allocate the jumbo buffer */
 768         entry = sk_jalloc(sc_if);
 769         if (entry == NULL) {
 770                 m_freem(m_new);
 771                 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
 772                     "dropped!\n", sc_if->arpcom.ac_if.if_xname));
 773                 return ENOBUFS;
 774         }
 775
 776         m_new->m_ext.ext_arg = entry;
 777         m_new->m_ext.ext_buf = entry->buf;
 778         m_new->m_ext.ext_free = sk_jfree;
 779         m_new->m_ext.ext_ref = sk_jref;
 780         m_new->m_ext.ext_size = SK_JLEN;
 781
 782         m_new->m_flags |= M_EXT;
 783
 784         m_new->m_data = m_new->m_ext.ext_buf;
 785         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 786
 787         /*
 788          * Adjust alignment so packet payload begins on a
 789          * longword boundary. Mandatory for Alpha, useful on
 790          * x86 too.
 791          */
 792         m_adj(m_new, ETHER_ALIGN);
 793
 794         sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
 795
 796         r = &sc_if->sk_rdata->sk_rx_ring[idx];
 797         r->sk_data_lo = htole32(entry->paddr + ETHER_ALIGN);
 798         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 799
 800         return 0;
 801 }
 802
 803 static int
 804 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
 805 {
 806         struct mbuf *m_new = NULL;
 807         struct sk_chain_data *cd = &sc_if->sk_cdata;
 808         struct sk_rx_desc *r;
 809         struct sk_dma_ctx ctx;
 810         bus_dma_segment_t seg;
 811         bus_dmamap_t map;
 812         int error;
 813
 814         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 815
 816         m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 817         if (m_new == NULL)
 818                 return ENOBUFS;
 819
 820         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 821
 822         /*
 823          * Adjust alignment so packet payload begins on a
 824          * longword boundary. Mandatory for Alpha, useful on
 825          * x86 too.
 826          */
 827         m_adj(m_new, ETHER_ALIGN);
 828
 829         bzero(&ctx, sizeof(ctx));
 830         ctx.nsegs = 1;
 831         ctx.segs = &seg;
 832         error = bus_dmamap_load_mbuf(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
 833                                      m_new, sk_buf_dma_addr, &ctx,
 834                                      wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
 835         if (error) {
 836                 if_printf(&sc_if->arpcom.ac_if, "could not map RX mbuf\n");
 837                 m_freem(m_new);
 838                 return error;
 839         }
 840
 841         /* Unload originally mapped mbuf */
 842         if (cd->sk_rx_mbuf[idx] != NULL)
 843                 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
 844
 845         /* Switch DMA map with tmp DMA map */
 846         map = cd->sk_rx_dmap_tmp;
 847         cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
 848         cd->sk_rx_dmap[idx] = map;
 849
 850         cd->sk_rx_mbuf[idx] = m_new;
 851
 852         r = &sc_if->sk_rdata->sk_rx_ring[idx];
 853         r->sk_data_lo = htole32(seg.ds_addr);
 854         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 855
 856         return 0;
 857 }
 858
 859 /*
 860  * Allocate a jumbo buffer.
 861  */
 862 struct sk_jpool_entry *
 863 sk_jalloc(struct sk_if_softc *sc_if)
 864 {
 865         struct sk_chain_data *cd = &sc_if->sk_cdata;
 866         struct sk_jpool_entry *entry;
 867
 868         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 869
 870         entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
 871         if (entry != NULL) {
 872                 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
 873                 entry->inuse = 1;
 874         } else {
 875                 DPRINTF(("no free jumbo buffer\n"));
 876         }
 877
 878         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 879         return entry;
 880 }
 881
 882 /*
 883  * Release a jumbo buffer.
 884  */
 885 void
 886 sk_jfree(void *arg)
 887 {
 888         struct sk_jpool_entry *entry = arg;
 889         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 890
 891         if (&cd->sk_jpool_ent[entry->slot] != entry)
 892                 panic("%s: free wrong jumbo buffer\n", __func__);
 893         else if (entry->inuse == 0)
 894                 panic("%s: jumbo buffer already freed\n", __func__);
 895
 896         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 897
 898         atomic_subtract_int(&entry->inuse, 1);
 899         if (entry->inuse == 0)
 900                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
 901
 902         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 903 }
 904
 905 static void
 906 sk_jref(void *arg)
 907 {
 908         struct sk_jpool_entry *entry = arg;
 909         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 910
 911         if (&cd->sk_jpool_ent[entry->slot] != entry)
 912                 panic("%s: free wrong jumbo buffer\n", __func__);
 913         else if (entry->inuse == 0)
 914                 panic("%s: jumbo buffer already freed\n", __func__);
 915
 916         atomic_add_int(&entry->inuse, 1);
 917 }
 918
 919 /*
 920  * Set media options.
 921  */
 922 static int
 923 sk_ifmedia_upd(struct ifnet *ifp)
 924 {
 925         struct sk_if_softc *sc_if = ifp->if_softc;
 926         struct mii_data *mii;
 927
 928         mii = device_get_softc(sc_if->sk_miibus);
 929         sk_init(sc_if);
 930         mii_mediachg(mii);
 931
 932         return(0);
 933 }
 934
 935 /*
 936  * Report current media status.
 937  */
 938 static void
 939 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 940 {
 941         struct sk_if_softc *sc_if;
 942         struct mii_data *mii;
 943
 944         sc_if = ifp->if_softc;
 945         mii = device_get_softc(sc_if->sk_miibus);
 946
 947         mii_pollstat(mii);
 948         ifmr->ifm_active = mii->mii_media_active;
 949         ifmr->ifm_status = mii->mii_media_status;
 950 }
 951
 952 static int
 953 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 954 {
 955         struct sk_if_softc *sc_if = ifp->if_softc;
 956         struct ifreq *ifr = (struct ifreq *)data;
 957         struct mii_data *mii;
 958         int error = 0;
 959
 960         ASSERT_SERIALIZED(ifp->if_serializer);
 961
 962         switch(command) {
 963         case SIOCSIFMTU:
 964                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
 965                         error = EINVAL;
 966                 else {
 967                         ifp->if_mtu = ifr->ifr_mtu;
 968                         ifp->if_flags &= ~IFF_RUNNING;
 969                         sk_init(sc_if);
 970                 }
 971                 break;
 972         case SIOCSIFFLAGS:
 973                 if (ifp->if_flags & IFF_UP) {
 974                         if (ifp->if_flags & IFF_RUNNING) {
 975                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
 976                                     & IFF_PROMISC) {
 977                                         sk_setpromisc(sc_if);
 978                                         sk_setmulti(sc_if);
 979                                 }
 980                         } else
 981                                 sk_init(sc_if);
 982                 } else {
 983                         if (ifp->if_flags & IFF_RUNNING)
 984                                 sk_stop(sc_if);
 985                 }
 986                 sc_if->sk_if_flags = ifp->if_flags;
 987                 break;
 988         case SIOCADDMULTI:
 989         case SIOCDELMULTI:
 990                 sk_setmulti(sc_if);
 991                 break;
 992         case SIOCGIFMEDIA:
 993         case SIOCSIFMEDIA:
 994                 mii = device_get_softc(sc_if->sk_miibus);
 995                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 996                 break;
 997         default:
 998                 error = ether_ioctl(ifp, command, data);
 999                 break;
1000         }
1001
1002         return(error);
1003 }
1004
1005 /*
1006  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1007  * IDs against our list and return a device name if we find a match.
1008  */
1009 static int
1010 skc_probe(device_t dev)
1011 {
1012         const struct skc_type *t;
1013         uint16_t vid, did;
1014
1015         vid = pci_get_vendor(dev);
1016         did = pci_get_device(dev);
1017
1018         /*
1019          * Only attach to rev.2 of the Linksys EG1032 adapter.
1020          * Rev.3 is supported by re(4).
1021          */
1022         if (vid == PCI_VENDOR_LINKSYS &&
1023             did == PCI_PRODUCT_LINKSYS_EG1032 &&
1024             pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1025                 return ENXIO;
1026
1027         for (t = skc_devs; t->skc_name != NULL; t++) {
1028                 if (vid == t->skc_vid && did == t->skc_did) {
1029                         device_set_desc(dev, t->skc_name);
1030                         return 0;
1031                 }
1032         }
1033         return ENXIO;
1034 }
1035
1036 /*
1037  * Force the GEnesis into reset, then bring it out of reset.
1038  */
1039 static void
1040 sk_reset(struct sk_softc *sc)
1041 {
1042         uint32_t imtimer_ticks;
1043
1044         DPRINTFN(2, ("sk_reset\n"));
1045
1046         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1047         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1048         if (SK_IS_YUKON(sc))
1049                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1050
1051         DELAY(1000);
1052         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1053         DELAY(2);
1054         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1055         if (SK_IS_YUKON(sc))
1056                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1057
1058         DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1059         DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1060                      CSR_READ_2(sc, SK_LINK_CTRL)));
1061
1062         if (SK_IS_GENESIS(sc)) {
1063                 /* Configure packet arbiter */
1064                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1065                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1066                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1067                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1068                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1069         }
1070
1071         /* Enable RAM interface */
1072         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1073
1074         /*
1075          * Configure interrupt moderation. The moderation timer
1076          * defers interrupts specified in the interrupt moderation
1077          * timer mask based on the timeout specified in the interrupt
1078          * moderation timer init register. Each bit in the timer
1079          * register represents one tick, so to specify a timeout in
1080          * microseconds, we have to multiply by the correct number of
1081          * ticks-per-microsecond.
1082          */
1083         switch (sc->sk_type) {
1084         case SK_GENESIS:
1085                 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1086                 break;
1087         default:
1088                 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1089         }
1090         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100));
1091         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1092             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1093         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1094 }
1095
1096 static int
1097 sk_probe(device_t dev)
1098 {
1099         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1100         const char *revstr = "", *name = NULL;
1101         char devname[80];
1102
1103         switch (sc->sk_type) {
1104         case SK_GENESIS:
1105                 name = "SysKonnect GEnesis";
1106                 break;
1107         case SK_YUKON:
1108                 name = "Marvell Yukon";
1109                 break;
1110         case SK_YUKON_LITE:
1111                 name = "Marvell Yukon Lite";
1112                 switch (sc->sk_rev) {
1113                 case SK_YUKON_LITE_REV_A0:
1114                         revstr = " rev.A0";
1115                         break;
1116                 case SK_YUKON_LITE_REV_A1:
1117                         revstr = " rev.A1";
1118                         break;
1119                 case SK_YUKON_LITE_REV_A3:
1120                         revstr = " rev.A3";
1121                         break;
1122                 }
1123                 break;
1124         case SK_YUKON_LP:
1125                 name = "Marvell Yukon LP";
1126                 break;
1127         default:
1128                 return ENXIO;
1129         }
1130
1131         ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1132                  name, revstr, sc->sk_rev);
1133         device_set_desc_copy(dev, devname);
1134         return 0;
1135 }
1136
1137 /*
1138  * Each XMAC chip is attached as a separate logical IP interface.
1139  * Single port cards will have only one logical interface of course.
1140  */
1141 static int
1142 sk_attach(device_t dev)
1143 {
1144         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1145         struct sk_if_softc *sc_if = device_get_softc(dev);
1146         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1147         int i, error;
1148
1149         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1150
1151         sc_if->sk_port = *(int *)device_get_ivars(dev);
1152         KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1153
1154         sc_if->sk_softc = sc;
1155         sc->sk_if[sc_if->sk_port] = sc_if;
1156
1157         kfree(device_get_ivars(dev), M_DEVBUF);
1158         device_set_ivars(dev, NULL);
1159
1160         if (sc_if->sk_port == SK_PORT_A)
1161                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1162         if (sc_if->sk_port == SK_PORT_B)
1163                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1164
1165         DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1166
1167         /*
1168          * Get station address for this interface. Note that
1169          * dual port cards actually come with three station
1170          * addresses: one for each port, plus an extra. The
1171          * extra one is used by the SysKonnect driver software
1172          * as a 'virtual' station address for when both ports
1173          * are operating in failover mode. Currently we don't
1174          * use this extra address.
1175          */
1176         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1177                 /* XXX */
1178                 sc_if->arpcom.ac_enaddr[i] =
1179                     sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1180         }
1181
1182         /*
1183          * Set up RAM buffer addresses. The NIC will have a certain
1184          * amount of SRAM on it, somewhere between 512K and 2MB. We
1185          * need to divide this up a) between the transmitter and
1186          * receiver and b) between the two XMACs, if this is a
1187          * dual port NIC. Our algorithm is to divide up the memory
1188          * evenly so that everyone gets a fair share.
1189          */
1190         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1191                 uint32_t chunk, val;
1192
1193                 chunk = sc->sk_ramsize / 2;
1194                 val = sc->sk_rboff / sizeof(uint64_t);
1195                 sc_if->sk_rx_ramstart = val;
1196                 val += (chunk / sizeof(uint64_t));
1197                 sc_if->sk_rx_ramend = val - 1;
1198                 sc_if->sk_tx_ramstart = val;
1199                 val += (chunk / sizeof(uint64_t));
1200                 sc_if->sk_tx_ramend = val - 1;
1201         } else {
1202                 uint32_t chunk, val;
1203
1204                 chunk = sc->sk_ramsize / 4;
1205                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1206                     sizeof(uint64_t);
1207                 sc_if->sk_rx_ramstart = val;
1208                 val += (chunk / sizeof(uint64_t));
1209                 sc_if->sk_rx_ramend = val - 1;
1210                 sc_if->sk_tx_ramstart = val;
1211                 val += (chunk / sizeof(uint64_t));
1212                 sc_if->sk_tx_ramend = val - 1;
1213         }
1214
1215         DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1216                      "           tx_ramstart=%#x tx_ramend=%#x\n",
1217                      sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1218                      sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1219
1220         /* Read and save PHY type */
1221         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1222
1223         /* Set PHY address */
1224         if (SK_IS_GENESIS(sc)) {
1225                 switch (sc_if->sk_phytype) {
1226                 case SK_PHYTYPE_XMAC:
1227                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1228                         break;
1229                 case SK_PHYTYPE_BCOM:
1230                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1231                         break;
1232                 default:
1233                         device_printf(dev, "unsupported PHY type: %d\n",
1234                             sc_if->sk_phytype);
1235                         error = ENXIO;
1236                         goto fail;
1237                 }
1238         }
1239
1240         if (SK_IS_YUKON(sc)) {
1241                 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1242                     sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1243                         /* not initialized, punt */
1244                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1245                         sc->sk_coppertype = 1;
1246                 }
1247
1248                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1249
1250                 if (!(sc->sk_coppertype))
1251                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1252         }
1253
1254         error = sk_dma_alloc(dev);
1255         if (error)
1256                 goto fail;
1257
1258         ifp->if_softc = sc_if;
1259         ifp->if_mtu = ETHERMTU;
1260         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1261         ifp->if_ioctl = sk_ioctl;
1262         ifp->if_start = sk_start;
1263         ifp->if_watchdog = sk_watchdog;
1264         ifp->if_init = sk_init;
1265         ifp->if_baudrate = 1000000000;
1266         ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1267         ifq_set_ready(&ifp->if_snd);
1268
1269         ifp->if_capabilities = IFCAP_VLAN_MTU;
1270
1271         /* Don't use jumbo buffers by default */
1272         sc_if->sk_use_jumbo = 0;
1273
1274         /*
1275          * Do miibus setup.
1276          */
1277         switch (sc->sk_type) {
1278         case SK_GENESIS:
1279                 sk_init_xmac(sc_if);
1280                 break;
1281         case SK_YUKON:
1282         case SK_YUKON_LITE:
1283         case SK_YUKON_LP:
1284                 sk_init_yukon(sc_if);
1285                 break;
1286         default:
1287                 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1288                 error = ENXIO;
1289                 goto fail;
1290         }
1291
1292         DPRINTFN(2, ("sk_attach: 1\n"));
1293
1294         error = mii_phy_probe(dev, &sc_if->sk_miibus,
1295                               sk_ifmedia_upd, sk_ifmedia_sts);
1296         if (error) {
1297                 device_printf(dev, "no PHY found!\n");
1298                 goto fail;
1299         }
1300
1301         callout_init(&sc_if->sk_tick_timer);
1302
1303         /*
1304          * Call MI attach routines.
1305          */
1306         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1307
1308         DPRINTFN(2, ("sk_attach: end\n"));
1309         return 0;
1310 fail:
1311         sk_detach(dev);
1312         sc->sk_if[sc_if->sk_port] = NULL;
1313         return error;
1314 }
1315
1316 /*
1317  * Attach the interface. Allocate softc structures, do ifmedia
1318  * setup and ethernet/BPF attach.
1319  */
1320 static int
1321 skc_attach(device_t dev)
1322 {
1323         struct sk_softc *sc = device_get_softc(dev);
1324         uint8_t skrs;
1325         int *port;
1326         int error;
1327
1328         DPRINTFN(2, ("begin skc_attach\n"));
1329
1330         lwkt_serialize_init(&sc->sk_serializer);
1331
1332 #ifndef BURN_BRIDGES
1333         /*
1334          * Handle power management nonsense.
1335          */
1336         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1337                 uint32_t iobase, membase, irq;
1338
1339                 /* Save important PCI config data. */
1340                 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1341                 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1342                 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1343
1344                 /* Reset the power state. */
1345                 device_printf(dev, "chip is in D%d power mode "
1346                               "-- setting to D0\n", pci_get_powerstate(dev));
1347
1348                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1349
1350                 /* Restore PCI config data. */
1351                 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1352                 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1353                 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1354         }
1355 #endif  /* BURN_BRIDGES */
1356
1357         /*
1358          * Map control/status registers.
1359          */
1360         pci_enable_busmaster(dev);
1361
1362         sc->sk_res_rid = SK_PCI_LOMEM;
1363         sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1364                                             &sc->sk_res_rid, RF_ACTIVE);
1365         if (sc->sk_res == NULL) {
1366                 device_printf(dev, "couldn't map memory\n");
1367                 error = ENXIO;
1368                 goto fail;
1369         }
1370         sc->sk_btag = rman_get_bustag(sc->sk_res);
1371         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1372
1373         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1374         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1375
1376         /* Bail out here if chip is not recognized */
1377         if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1378                 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1379                 error = ENXIO;
1380                 goto fail;
1381         }
1382
1383         DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1384
1385         /* Allocate interrupt */
1386         sc->sk_irq_rid = 0;
1387         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1388                                             RF_SHAREABLE | RF_ACTIVE);
1389         if (sc->sk_irq == NULL) {
1390                 device_printf(dev, "couldn't map interrupt\n");
1391                 error = ENXIO;
1392                 goto fail;
1393         }
1394
1395         /* Reset the adapter. */
1396         sk_reset(sc);
1397
1398         skrs = sk_win_read_1(sc, SK_EPROM0);
1399         if (SK_IS_GENESIS(sc)) {
1400                 /* Read and save RAM size and RAMbuffer offset */
1401                 switch(skrs) {
1402                 case SK_RAMSIZE_512K_64:
1403                         sc->sk_ramsize = 0x80000;
1404                         sc->sk_rboff = SK_RBOFF_0;
1405                         break;
1406                 case SK_RAMSIZE_1024K_64:
1407                         sc->sk_ramsize = 0x100000;
1408                         sc->sk_rboff = SK_RBOFF_80000;
1409                         break;
1410                 case SK_RAMSIZE_1024K_128:
1411                         sc->sk_ramsize = 0x100000;
1412                         sc->sk_rboff = SK_RBOFF_0;
1413                         break;
1414                 case SK_RAMSIZE_2048K_128:
1415                         sc->sk_ramsize = 0x200000;
1416                         sc->sk_rboff = SK_RBOFF_0;
1417                         break;
1418                 default:
1419                         device_printf(dev, "unknown ram size: %d\n", skrs);
1420                         error = ENXIO;
1421                         goto fail;
1422                 }
1423         } else {
1424                 if (skrs == 0x00)
1425                         sc->sk_ramsize = 0x20000;
1426                 else
1427                         sc->sk_ramsize = skrs * (1<<12);
1428                 sc->sk_rboff = SK_RBOFF_0;
1429         }
1430
1431         DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1432                      sc->sk_ramsize, sc->sk_ramsize / 1024,
1433                      sc->sk_rboff));
1434
1435         /* Read and save physical media type */
1436         sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1437
1438         if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1439                 sc->sk_coppertype = 1;
1440         else
1441                 sc->sk_coppertype = 0;
1442
1443         /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1444         if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1445                 uint32_t flashaddr;
1446                 uint8_t testbyte;
1447
1448                 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1449
1450                 /* Test Flash-Address Register */
1451                 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1452                 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1453
1454                 if (testbyte != 0) {
1455                         /* This is a Yukon Lite Rev A0 */
1456                         sc->sk_type = SK_YUKON_LITE;
1457                         sc->sk_rev = SK_YUKON_LITE_REV_A0;
1458                         /* Restore Flash-Address Register */
1459                         sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1460                 }
1461         }
1462
1463         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1464         port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1465         *port = SK_PORT_A;
1466         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1467
1468         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1469                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1470                 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1471                 *port = SK_PORT_B;
1472                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1473         }
1474
1475         /* Turn on the 'driver is loaded' LED. */
1476         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1477
1478         bus_generic_attach(dev);
1479
1480         error = bus_setup_intr(dev, sc->sk_irq, INTR_NETSAFE, sk_intr, sc,
1481                                &sc->sk_intrhand, &sc->sk_serializer);
1482         if (error) {
1483                 device_printf(dev, "couldn't set up irq\n");
1484                 goto fail;
1485         }
1486         return 0;
1487 fail:
1488         skc_detach(dev);
1489         return error;
1490 }
1491
1492 static int
1493 sk_detach(device_t dev)
1494 {
1495         struct sk_if_softc *sc_if = device_get_softc(dev);
1496         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1497
1498         if (device_is_attached(dev))
1499                 ether_ifdetach(ifp);
1500
1501         bus_generic_detach(dev);
1502         if (sc_if->sk_miibus != NULL)
1503                 device_delete_child(dev, sc_if->sk_miibus);
1504
1505         sk_dma_free(dev);
1506         return 0;
1507 }
1508
1509 static int
1510 skc_detach(device_t dev)
1511 {
1512         struct sk_softc *sc = device_get_softc(dev);
1513         int *port;
1514
1515         if (device_is_attached(dev)) {
1516                 lwkt_serialize_enter(&sc->sk_serializer);
1517
1518                 if (sc->sk_if[SK_PORT_A] != NULL)
1519                         sk_stop(sc->sk_if[SK_PORT_A]);
1520                 if (sc->sk_if[SK_PORT_B] != NULL)
1521                         sk_stop(sc->sk_if[SK_PORT_B]);
1522
1523                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1524
1525                 lwkt_serialize_exit(&sc->sk_serializer);
1526         }
1527
1528         bus_generic_detach(dev);
1529         if (sc->sk_devs[SK_PORT_A] != NULL) {
1530                 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1531                 if (port != NULL) {
1532                         kfree(port, M_DEVBUF);
1533                         device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1534                 }
1535                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1536         }
1537         if (sc->sk_devs[SK_PORT_B] != NULL) {
1538                 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1539                 if (port != NULL) {
1540                         kfree(port, M_DEVBUF);
1541                         device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1542                 }
1543                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1544         }
1545
1546         if (sc->sk_irq != NULL) {
1547                 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1548                                      sc->sk_irq);
1549         }
1550         if (sc->sk_res != NULL) {
1551                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1552                                      sc->sk_res);
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int
1559 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1560 {
1561         struct sk_chain_data *cd = &sc_if->sk_cdata;
1562         struct sk_ring_data *rd = sc_if->sk_rdata;
1563         struct sk_tx_desc *f = NULL;
1564         uint32_t frag, cur, sk_ctl;
1565         struct sk_dma_ctx ctx;
1566         bus_dma_segment_t segs[SK_NTXSEG];
1567         bus_dmamap_t map;
1568         int i, error;
1569
1570         DPRINTFN(2, ("sk_encap\n"));
1571
1572         cur = frag = *txidx;
1573
1574 #ifdef SK_DEBUG
1575         if (skdebug >= 2)
1576                 sk_dump_mbuf(m_head);
1577 #endif
1578
1579         map = cd->sk_tx_dmap[*txidx];
1580
1581         /*
1582          * Start packing the mbufs in this chain into
1583          * the fragment pointers. Stop when we run out
1584          * of fragments or hit the end of the mbuf chain.
1585          */
1586         ctx.nsegs = SK_NTXSEG;
1587         ctx.segs = segs;
1588         error = bus_dmamap_load_mbuf(cd->sk_tx_dtag, map, m_head,
1589                                      sk_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1590         if (error) {
1591                 if_printf(&sc_if->arpcom.ac_if, "could not map TX mbuf\n");
1592                 return ENOBUFS;
1593         }
1594
1595         if ((SK_TX_RING_CNT - (cd->sk_tx_cnt + ctx.nsegs)) < 2) {
1596                 bus_dmamap_unload(cd->sk_tx_dtag, map);
1597                 DPRINTFN(2, ("sk_encap: too few descriptors free\n"));
1598                 return ENOBUFS;
1599         }
1600
1601         DPRINTFN(2, ("sk_encap: nsegs=%d\n", ctx.nsegs));
1602
1603         /* Sync the DMA map. */
1604         bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1605
1606         for (i = 0; i < ctx.nsegs; i++) {
1607                 f = &rd->sk_tx_ring[frag];
1608                 f->sk_data_lo = htole32(segs[i].ds_addr);
1609                 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1610                 if (i == 0)
1611                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
1612                 else
1613                         sk_ctl |= SK_TXCTL_OWN;
1614                 f->sk_ctl = htole32(sk_ctl);
1615                 cur = frag;
1616                 SK_INC(frag, SK_TX_RING_CNT);
1617         }
1618
1619         cd->sk_tx_mbuf[cur] = m_head;
1620         /* Switch DMA map */
1621         cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1622         cd->sk_tx_dmap[cur] = map;
1623
1624         rd->sk_tx_ring[cur].sk_ctl |=
1625                 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1626         rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1627
1628         /* Sync first descriptor to hand it off */
1629         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1630                         BUS_DMASYNC_PREWRITE);
1631
1632         sc_if->sk_cdata.sk_tx_cnt += ctx.nsegs;
1633
1634 #ifdef SK_DEBUG
1635         if (skdebug >= 2) {
1636                 struct sk_tx_desc *desc;
1637                 uint32_t idx;
1638
1639                 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1640                         desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1641                         sk_dump_txdesc(desc, idx);
1642                 }
1643         }
1644 #endif
1645
1646         *txidx = frag;
1647
1648         DPRINTFN(2, ("sk_encap: completed successfully\n"));
1649
1650         return (0);
1651 }
1652
1653 static void
1654 sk_start(struct ifnet *ifp)
1655 {
1656         struct sk_if_softc *sc_if = ifp->if_softc;
1657         struct sk_softc *sc = sc_if->sk_softc;
1658         struct mbuf *m_head = NULL;
1659         uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1660         int pkts = 0;
1661
1662         DPRINTFN(2, ("sk_start\n"));
1663
1664         while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1665                 m_head = ifq_poll(&ifp->if_snd);
1666                 if (m_head == NULL)
1667                         break;
1668
1669                 /*
1670                  * Pack the data into the transmit ring. If we
1671                  * don't have room, set the OACTIVE flag and wait
1672                  * for the NIC to drain the ring.
1673                  */
1674                 if (sk_encap(sc_if, m_head, &idx)) {
1675                         ifp->if_flags |= IFF_OACTIVE;
1676                         break;
1677                 }
1678
1679                 /* now we are committed to transmit the packet */
1680                 ifq_dequeue(&ifp->if_snd, m_head);
1681                 pkts++;
1682
1683                 BPF_MTAP(ifp, m_head);
1684         }
1685         if (pkts == 0)
1686                 return;
1687
1688         /* Transmit */
1689         if (idx != sc_if->sk_cdata.sk_tx_prod) {
1690                 sc_if->sk_cdata.sk_tx_prod = idx;
1691                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1692
1693                 /* Set a timeout in case the chip goes out to lunch. */
1694                 ifp->if_timer = 5;
1695         }
1696 }
1697
1698 static void
1699 sk_watchdog(struct ifnet *ifp)
1700 {
1701         struct sk_if_softc *sc_if = ifp->if_softc;
1702
1703         ASSERT_SERIALIZED(ifp->if_serializer);
1704         /*
1705          * Reclaim first as there is a possibility of losing Tx completion
1706          * interrupts.
1707          */
1708         sk_txeof(sc_if);
1709         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1710                 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1711                 ifp->if_oerrors++;
1712                 ifp->if_flags &= ~IFF_RUNNING;
1713                 sk_init(sc_if);
1714         }
1715 }
1716
1717 static void
1718 skc_shutdown(device_t dev)
1719 {
1720         struct sk_softc *sc = device_get_softc(dev);
1721
1722         DPRINTFN(2, ("sk_shutdown\n"));
1723
1724         lwkt_serialize_enter(&sc->sk_serializer);
1725
1726         /* Turn off the 'driver is loaded' LED. */
1727         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1728
1729         /*
1730          * Reset the GEnesis controller. Doing this should also
1731          * assert the resets on the attached XMAC(s).
1732          */
1733         sk_reset(sc);
1734
1735         lwkt_serialize_exit(&sc->sk_serializer);
1736 }
1737
1738 static __inline int
1739 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1740 {
1741         if (sc->sk_type == SK_GENESIS) {
1742                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1743                     XM_RXSTAT_BYTES(stat) != len)
1744                         return (0);
1745         } else {
1746                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1747                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1748                     YU_RXSTAT_JABBER)) != 0 ||
1749                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1750                     YU_RXSTAT_BYTES(stat) != len)
1751                         return (0);
1752         }
1753
1754         return (1);
1755 }
1756
1757 static void
1758 sk_rxeof(struct sk_if_softc *sc_if)
1759 {
1760         struct sk_softc *sc = sc_if->sk_softc;
1761         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1762         struct sk_chain_data *cd = &sc_if->sk_cdata;
1763         struct sk_ring_data *rd = sc_if->sk_rdata;
1764         int i, reap, max_frmlen;
1765
1766         DPRINTFN(2, ("sk_rxeof\n"));
1767
1768         i = cd->sk_rx_prod;
1769
1770         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1771                         BUS_DMASYNC_POSTREAD);
1772         if (sc_if->sk_use_jumbo) {
1773                 bus_dmamap_sync(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
1774                                 BUS_DMASYNC_POSTREAD);
1775                 max_frmlen = SK_JUMBO_FRAMELEN;
1776         } else {
1777                 max_frmlen = ETHER_MAX_LEN;
1778         }
1779
1780         reap = 0;
1781         for (;;) {
1782                 struct sk_rx_desc *cur_desc;
1783                 uint32_t rxstat, sk_ctl;
1784 #ifdef SK_RXCSUM
1785                 uint16_t csum1, csum2;
1786 #endif
1787                 int cur, total_len;
1788                 struct mbuf *m;
1789
1790                 cur = i;
1791                 cur_desc = &rd->sk_rx_ring[cur];
1792
1793                 sk_ctl = le32toh(cur_desc->sk_ctl);
1794                 if (sk_ctl & SK_RXCTL_OWN) {
1795                         /* Invalidate the descriptor -- it's not ready yet */
1796                         cd->sk_rx_prod = cur;
1797                         break;
1798                 }
1799
1800                 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1801                 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1802
1803 #ifdef SK_RXCSUM
1804                 csum1 = le16toh(cur_desc->sk_csum1);
1805                 csum2 = le16toh(cur_desc->sk_csum2);
1806 #endif
1807
1808                 m = cd->sk_rx_mbuf[cur];
1809
1810                 /*
1811                  * Bump 'i' here, so we can keep going, even if the current
1812                  * RX descriptor reaping fails later.  'i' shoult NOT be used
1813                  * in the following processing any more.
1814                  */
1815                 SK_INC(i, SK_RX_RING_CNT);
1816                 reap = 1;
1817
1818                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1819                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1820                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1821                     total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1822                     sk_rxvalid(sc, rxstat, total_len) == 0) {
1823                         ifp->if_ierrors++;
1824                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1825                         continue;
1826                 }
1827
1828                 if (!sc_if->sk_use_jumbo) {
1829                         bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[cur],
1830                                         BUS_DMASYNC_POSTREAD);
1831                 }
1832
1833                 /*
1834                  * Try to allocate a new RX buffer. If that fails,
1835                  * copy the packet to mbufs and put the RX buffer
1836                  * back in the ring so it can be re-used. If
1837                  * allocating mbufs fails, then we have to drop
1838                  * the packet.
1839                  */
1840                 if (sk_newbuf(sc_if, cur, 0)) {
1841                         struct mbuf *m0;
1842
1843                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1844
1845                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1846                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1847                         if (m0 == NULL) {
1848                                 ifp->if_ierrors++;
1849                                 continue;
1850                         }
1851                         m_adj(m0, ETHER_ALIGN);
1852                         m = m0;
1853                 } else {
1854                         m->m_pkthdr.rcvif = ifp;
1855                         m->m_pkthdr.len = m->m_len = total_len;
1856                 }
1857
1858 #ifdef SK_RXCSUM
1859                 sk_rxcsum(ifp, m, csum1, csum2);
1860 #endif
1861
1862                 ifp->if_ipackets++;
1863                 ifp->if_input(ifp, m);
1864         }
1865
1866         if (reap) {
1867                 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1868                                 BUS_DMASYNC_PREWRITE);
1869         }
1870 }
1871
1872 #ifdef SK_RXCSUM
1873 static void
1874 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1875           const uint16_t csum1, const uint16_t csum2)
1876 {
1877         struct ether_header *eh;
1878         struct ip *ip;
1879         uint8_t *pp;
1880         int hlen, len, plen;
1881         uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1882
1883         pp = mtod(m, uint8_t *);
1884         plen = m->m_pkthdr.len;
1885         if (plen < sizeof(*eh))
1886                 return;
1887         eh = (struct ether_header *)pp;
1888         iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1889
1890         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1891                 uint16_t *xp = (uint16_t *)pp;
1892
1893                 xp = (uint16_t *)pp;
1894                 if (xp[1] != htons(ETHERTYPE_IP))
1895                         return;
1896                 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1897                 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1898                 xp = (uint16_t *)(pp + sizeof(struct ip));
1899                 iph_csum = in_addword(iph_csum, xp[0]);
1900                 iph_csum = in_addword(iph_csum, xp[1]);
1901                 pp += EVL_ENCAPLEN;
1902         } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1903                 return;
1904         }
1905
1906         pp += sizeof(*eh);
1907         plen -= sizeof(*eh);
1908
1909         ip = (struct ip *)pp;
1910
1911         if (ip->ip_v != IPVERSION)
1912                 return;
1913
1914         hlen = ip->ip_hl << 2;
1915         if (hlen < sizeof(struct ip))
1916                 return;
1917         if (hlen > ntohs(ip->ip_len))
1918                 return;
1919
1920         /* Don't deal with truncated or padded packets. */
1921         if (plen != ntohs(ip->ip_len))
1922                 return;
1923
1924         len = hlen - sizeof(struct ip);
1925         if (len > 0) {
1926                 uint16_t *p;
1927
1928                 p = (uint16_t *)(ip + 1);
1929                 ipo_csum = 0;
1930                 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1931                         ipo_csum = in_addword(ipo_csum, *p);
1932                 iph_csum = in_addword(iph_csum, ipo_csum);
1933                 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1934         } else {
1935                 ipd_csum = csum2;
1936         }
1937
1938         if (iph_csum != 0xffff)
1939                 return;
1940         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1941
1942         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1943                 return;                 /* ip frag, we're done for now */
1944
1945         pp += hlen;
1946
1947         /* Only know checksum protocol for udp/tcp */
1948         if (ip->ip_p == IPPROTO_UDP) {
1949                 struct udphdr *uh = (struct udphdr *)pp;
1950
1951                 if (uh->uh_sum == 0)    /* udp with no checksum */
1952                         return;
1953         } else if (ip->ip_p != IPPROTO_TCP) {
1954                 return;
1955         }
1956
1957         csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1958             htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1959         if (csum == 0xffff) {
1960                 m->m_pkthdr.csum_data = csum;
1961                 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1962         }
1963 }
1964 #endif
1965
1966 static void
1967 sk_txeof(struct sk_if_softc *sc_if)
1968 {
1969         struct sk_chain_data *cd = &sc_if->sk_cdata;
1970         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1971         uint32_t idx;
1972         int reap = 0;
1973
1974         DPRINTFN(2, ("sk_txeof\n"));
1975
1976         bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
1977                         BUS_DMASYNC_POSTREAD);
1978
1979         /*
1980          * Go through our tx ring and free mbufs for those
1981          * frames that have been sent.
1982          */
1983         idx = cd->sk_tx_cons;
1984         while (idx != cd->sk_tx_prod) {
1985                 struct sk_tx_desc *cur_tx;
1986                 uint32_t sk_ctl;
1987
1988                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1989                 sk_ctl = le32toh(cur_tx->sk_ctl);
1990 #ifdef SK_DEBUG
1991                 if (skdebug >= 2)
1992                         sk_dump_txdesc(cur_tx, idx);
1993 #endif
1994                 if (sk_ctl & SK_TXCTL_OWN)
1995                         break;
1996                 if (sk_ctl & SK_TXCTL_LASTFRAG)
1997                         ifp->if_opackets++;
1998                 if (cd->sk_tx_mbuf[idx] != NULL) {
1999                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2000                         m_freem(cd->sk_tx_mbuf[idx]);
2001                         cd->sk_tx_mbuf[idx] = NULL;
2002                 }
2003                 sc_if->sk_cdata.sk_tx_cnt--;
2004                 reap = 1;
2005                 SK_INC(idx, SK_TX_RING_CNT);
2006         }
2007         ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2008
2009         if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
2010                 ifp->if_flags &= ~IFF_OACTIVE;
2011
2012         sc_if->sk_cdata.sk_tx_cons = idx;
2013
2014         if (reap) {
2015                 bus_dmamap_sync(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
2016                                 BUS_DMASYNC_PREWRITE);
2017         }
2018 }
2019
2020 static void
2021 sk_tick(void *xsc_if)
2022 {
2023         struct sk_if_softc *sc_if = xsc_if;
2024         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2025         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2026         int i;
2027
2028         DPRINTFN(2, ("sk_tick\n"));
2029
2030         lwkt_serialize_enter(ifp->if_serializer);
2031
2032         if ((ifp->if_flags & IFF_UP) == 0) {
2033                 lwkt_serialize_exit(ifp->if_serializer);
2034                 return;
2035         }
2036
2037         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2038                 sk_intr_bcom(sc_if);
2039                 lwkt_serialize_exit(ifp->if_serializer);
2040                 return;
2041         }
2042
2043         /*
2044          * According to SysKonnect, the correct way to verify that
2045          * the link has come back up is to poll bit 0 of the GPIO
2046          * register three times. This pin has the signal from the
2047          * link sync pin connected to it; if we read the same link
2048          * state 3 times in a row, we know the link is up.
2049          */
2050         for (i = 0; i < 3; i++) {
2051                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2052                         break;
2053         }
2054
2055         if (i != 3) {
2056                 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2057                 lwkt_serialize_exit(ifp->if_serializer);
2058                 return;
2059         }
2060
2061         /* Turn the GP0 interrupt back on. */
2062         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2063         SK_XM_READ_2(sc_if, XM_ISR);
2064         mii_tick(mii);
2065         callout_stop(&sc_if->sk_tick_timer);
2066         lwkt_serialize_exit(ifp->if_serializer);
2067 }
2068
2069 static void
2070 sk_yukon_tick(void *xsc_if)
2071 {
2072         struct sk_if_softc *sc_if = xsc_if;
2073         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2074         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2075
2076         lwkt_serialize_enter(ifp->if_serializer);
2077         mii_tick(mii);
2078         callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2079         lwkt_serialize_exit(ifp->if_serializer);
2080 }
2081
2082 static void
2083 sk_intr_bcom(struct sk_if_softc *sc_if)
2084 {
2085         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2086         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2087         int status;
2088
2089         DPRINTFN(2, ("sk_intr_bcom\n"));
2090
2091         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2092
2093         /*
2094          * Read the PHY interrupt register to make sure
2095          * we clear any pending interrupts.
2096          */
2097         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2098
2099         if ((ifp->if_flags & IFF_RUNNING) == 0) {
2100                 sk_init_xmac(sc_if);
2101                 return;
2102         }
2103
2104         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2105                 int lstat;
2106
2107                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2108                     BRGPHY_MII_AUXSTS);
2109
2110                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2111                         mii_mediachg(mii);
2112                         /* Turn off the link LED. */
2113                         SK_IF_WRITE_1(sc_if, 0,
2114                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2115                         sc_if->sk_link = 0;
2116                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2117                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2118                             BRGPHY_MII_IMR, 0xFF00);
2119                         mii_tick(mii);
2120                         sc_if->sk_link = 1;
2121                         /* Turn on the link LED. */
2122                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2123                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2124                             SK_LINKLED_BLINK_OFF);
2125                 } else {
2126                         mii_tick(mii);
2127                         callout_reset(&sc_if->sk_tick_timer, hz,
2128                                       sk_tick, sc_if);
2129                 }
2130         }
2131
2132         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2133 }
2134
2135 static void
2136 sk_intr_xmac(struct sk_if_softc *sc_if)
2137 {
2138         uint16_t status;
2139
2140         status = SK_XM_READ_2(sc_if, XM_ISR);
2141         DPRINTFN(2, ("sk_intr_xmac\n"));
2142
2143         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2144             (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2145                 if (status & XM_ISR_GP0_SET)
2146                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2147
2148                 callout_reset(&sc_if->sk_tick_timer, hz,
2149                               sk_tick, sc_if);
2150         }
2151
2152         if (status & XM_IMR_TX_UNDERRUN)
2153                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2154
2155         if (status & XM_IMR_RX_OVERRUN)
2156                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2157 }
2158
2159 static void
2160 sk_intr_yukon(struct sk_if_softc *sc_if)
2161 {
2162         uint8_t status;
2163
2164         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2165         /* RX overrun */
2166         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2167                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2168                     SK_RFCTL_RX_FIFO_OVER);
2169         }
2170         /* TX underrun */
2171         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2172                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2173                     SK_TFCTL_TX_FIFO_UNDER);
2174         }
2175
2176         DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2177 }
2178
2179 static void
2180 sk_intr(void *xsc)
2181 {
2182         struct sk_softc *sc = xsc;
2183         struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2184         struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2185         struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2186         uint32_t status;
2187
2188         ASSERT_SERIALIZED(&sc->sk_serializer);
2189
2190         status = CSR_READ_4(sc, SK_ISSR);
2191         if (status == 0 || status == 0xffffffff)
2192                 return;
2193
2194         if (sc_if0 != NULL)
2195                 ifp0 = &sc_if0->arpcom.ac_if;
2196         if (sc_if1 != NULL)
2197                 ifp1 = &sc_if1->arpcom.ac_if;
2198
2199         for (; (status &= sc->sk_intrmask) != 0;) {
2200                 /* Handle receive interrupts first. */
2201                 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2202                         sk_rxeof(sc_if0);
2203                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2204                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2205                 }
2206                 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2207                         sk_rxeof(sc_if1);
2208                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2209                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2210                 }
2211
2212                 /* Then transmit interrupts. */
2213                 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2214                         sk_txeof(sc_if0);
2215                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2216                             SK_TXBMU_CLR_IRQ_EOF);
2217                 }
2218                 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2219                         sk_txeof(sc_if1);
2220                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2221                             SK_TXBMU_CLR_IRQ_EOF);
2222                 }
2223
2224                 /* Then MAC interrupts. */
2225                 if (sc_if0 && (status & SK_ISR_MAC1) &&
2226                     (ifp0->if_flags & IFF_RUNNING)) {
2227                         if (SK_IS_GENESIS(sc))
2228                                 sk_intr_xmac(sc_if0);
2229                         else
2230                                 sk_intr_yukon(sc_if0);
2231                 }
2232
2233                 if (sc_if1 && (status & SK_ISR_MAC2) &&
2234                     (ifp1->if_flags & IFF_RUNNING)) {
2235                         if (SK_IS_GENESIS(sc))
2236                                 sk_intr_xmac(sc_if1);
2237                         else
2238                                 sk_intr_yukon(sc_if1);
2239                 }
2240
2241                 if (status & SK_ISR_EXTERNAL_REG) {
2242                         if (sc_if0 != NULL &&
2243                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2244                                 sk_intr_bcom(sc_if0);
2245
2246                         if (sc_if1 != NULL &&
2247                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2248                                 sk_intr_bcom(sc_if1);
2249                 }
2250                 status = CSR_READ_4(sc, SK_ISSR);
2251         }
2252
2253         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2254
2255         if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2256                 sk_start(ifp0);
2257         if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2258                 sk_start(ifp1);
2259 }
2260
2261 static void
2262 sk_init_xmac(struct sk_if_softc *sc_if)
2263 {
2264         struct sk_softc *sc = sc_if->sk_softc;
2265         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2266         static const struct sk_bcom_hack bhack[] = {
2267         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2268         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2269         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2270         { 0, 0 } };
2271
2272         DPRINTFN(2, ("sk_init_xmac\n"));
2273
2274         /* Unreset the XMAC. */
2275         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2276         DELAY(1000);
2277
2278         /* Reset the XMAC's internal state. */
2279         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2280
2281         /* Save the XMAC II revision */
2282         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2283
2284         /*
2285          * Perform additional initialization for external PHYs,
2286          * namely for the 1000baseTX cards that use the XMAC's
2287          * GMII mode.
2288          */
2289         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2290                 int i = 0;
2291                 uint32_t val;
2292
2293                 /* Take PHY out of reset. */
2294                 val = sk_win_read_4(sc, SK_GPIO);
2295                 if (sc_if->sk_port == SK_PORT_A)
2296                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2297                 else
2298                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2299                 sk_win_write_4(sc, SK_GPIO, val);
2300
2301                 /* Enable GMII mode on the XMAC. */
2302                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2303
2304                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2305                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2306                 DELAY(10000);
2307                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2308                     BRGPHY_MII_IMR, 0xFFF0);
2309
2310                 /*
2311                  * Early versions of the BCM5400 apparently have
2312                  * a bug that requires them to have their reserved
2313                  * registers initialized to some magic values. I don't
2314                  * know what the numbers do, I'm just the messenger.
2315                  */
2316                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2317                     == 0x6041) {
2318                         while(bhack[i].reg) {
2319                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2320                                     bhack[i].reg, bhack[i].val);
2321                                 i++;
2322                         }
2323                 }
2324         }
2325
2326         /* Set station address */
2327         SK_XM_WRITE_2(sc_if, XM_PAR0,
2328             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2329         SK_XM_WRITE_2(sc_if, XM_PAR1,
2330             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2331         SK_XM_WRITE_2(sc_if, XM_PAR2,
2332             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2333         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2334
2335         if (ifp->if_flags & IFF_BROADCAST)
2336                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2337         else
2338                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2339
2340         /* We don't need the FCS appended to the packet. */
2341         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2342
2343         /* We want short frames padded to 60 bytes. */
2344         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2345
2346         /*
2347          * Enable the reception of all error frames. This is
2348          * a necessary evil due to the design of the XMAC. The
2349          * XMAC's receive FIFO is only 8K in size, however jumbo
2350          * frames can be up to 9000 bytes in length. When bad
2351          * frame filtering is enabled, the XMAC's RX FIFO operates
2352          * in 'store and forward' mode. For this to work, the
2353          * entire frame has to fit into the FIFO, but that means
2354          * that jumbo frames larger than 8192 bytes will be
2355          * truncated. Disabling all bad frame filtering causes
2356          * the RX FIFO to operate in streaming mode, in which
2357          * case the XMAC will start transfering frames out of the
2358          * RX FIFO as soon as the FIFO threshold is reached.
2359          */
2360         if (sc_if->sk_use_jumbo) {
2361                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2362                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2363                     XM_MODE_RX_INRANGELEN);
2364         }
2365
2366         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2367
2368         /*
2369          * Bump up the transmit threshold. This helps hold off transmit
2370          * underruns when we're blasting traffic from both ports at once.
2371          */
2372         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2373
2374         /* Set promiscuous mode */
2375         sk_setpromisc(sc_if);
2376
2377         /* Set multicast filter */
2378         sk_setmulti(sc_if);
2379
2380         /* Clear and enable interrupts */
2381         SK_XM_READ_2(sc_if, XM_ISR);
2382         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2383                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2384         else
2385                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2386
2387         /* Configure MAC arbiter */
2388         switch(sc_if->sk_xmac_rev) {
2389         case XM_XMAC_REV_B2:
2390                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2391                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2392                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2393                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2394                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2395                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2396                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2397                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2398                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2399                 break;
2400         case XM_XMAC_REV_C1:
2401                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2402                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2403                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2404                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2405                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2406                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2407                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2408                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2409                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2410                 break;
2411         default:
2412                 break;
2413         }
2414         sk_win_write_2(sc, SK_MACARB_CTL,
2415             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2416
2417         sc_if->sk_link = 1;
2418 }
2419
2420 static void
2421 sk_init_yukon(struct sk_if_softc *sc_if)
2422 {
2423         uint32_t phy, v;
2424         uint16_t reg;
2425         struct sk_softc *sc;
2426         int i;
2427
2428         sc = sc_if->sk_softc;
2429
2430         DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2431                      CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2432
2433         if (sc->sk_type == SK_YUKON_LITE &&
2434             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2435                 /*
2436                  * Workaround code for COMA mode, set PHY reset.
2437                  * Otherwise it will not correctly take chip out of
2438                  * powerdown (coma)
2439                  */
2440                 v = sk_win_read_4(sc, SK_GPIO);
2441                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2442                 sk_win_write_4(sc, SK_GPIO, v);
2443         }
2444
2445         DPRINTFN(6, ("sk_init_yukon: 1\n"));
2446
2447         /* GMAC and GPHY Reset */
2448         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2449         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2450         DELAY(1000);
2451
2452         DPRINTFN(6, ("sk_init_yukon: 2\n"));
2453
2454         if (sc->sk_type == SK_YUKON_LITE &&
2455             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2456                 /*
2457                  * Workaround code for COMA mode, clear PHY reset
2458                  */
2459                 v = sk_win_read_4(sc, SK_GPIO);
2460                 v |= SK_GPIO_DIR9;
2461                 v &= ~SK_GPIO_DAT9;
2462                 sk_win_write_4(sc, SK_GPIO, v);
2463         }
2464
2465         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2466                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2467
2468         if (sc->sk_coppertype)
2469                 phy |= SK_GPHY_COPPER;
2470         else
2471                 phy |= SK_GPHY_FIBER;
2472
2473         DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2474
2475         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2476         DELAY(1000);
2477         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2478         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2479                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2480
2481         DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2482                      SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2483
2484         DPRINTFN(6, ("sk_init_yukon: 3\n"));
2485
2486         /* unused read of the interrupt source register */
2487         DPRINTFN(6, ("sk_init_yukon: 4\n"));
2488         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2489
2490         DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2491         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2492         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2493
2494         /* MIB Counter Clear Mode set */
2495         reg |= YU_PAR_MIB_CLR;
2496         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2497         DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2498         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2499
2500         /* MIB Counter Clear Mode clear */
2501         DPRINTFN(6, ("sk_init_yukon: 5\n"));
2502         reg &= ~YU_PAR_MIB_CLR;
2503         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2504
2505         /* receive control reg */
2506         DPRINTFN(6, ("sk_init_yukon: 7\n"));
2507         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2508
2509         /* transmit parameter register */
2510         DPRINTFN(6, ("sk_init_yukon: 8\n"));
2511         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2512                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2513
2514         /* serial mode register */
2515         DPRINTFN(6, ("sk_init_yukon: 9\n"));
2516         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2517         if (sc_if->sk_use_jumbo)
2518                 reg |= YU_SMR_MFL_JUMBO;
2519         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2520
2521         DPRINTFN(6, ("sk_init_yukon: 10\n"));
2522         /* Setup Yukon's address */
2523         for (i = 0; i < 3; i++) {
2524                 /* Write Source Address 1 (unicast filter) */
2525                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2526                               sc_if->arpcom.ac_enaddr[i * 2] |
2527                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2528         }
2529
2530         for (i = 0; i < 3; i++) {
2531                 reg = sk_win_read_2(sc_if->sk_softc,
2532                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2533                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2534         }
2535
2536         /* Set promiscuous mode */
2537         sk_setpromisc(sc_if);
2538
2539         /* Set multicast filter */
2540         DPRINTFN(6, ("sk_init_yukon: 11\n"));
2541         sk_setmulti(sc_if);
2542
2543         /* enable interrupt mask for counter overflows */
2544         DPRINTFN(6, ("sk_init_yukon: 12\n"));
2545         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2546         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2547         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2548
2549         /* Configure RX MAC FIFO Flush Mask */
2550         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2551             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2552             YU_RXSTAT_JABBER;
2553         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2554
2555         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2556         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2557                 v = SK_TFCTL_OPERATION_ON;
2558         else
2559                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2560         /* Configure RX MAC FIFO */
2561         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2562         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2563
2564         /* Increase flush threshould to 64 bytes */
2565         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2566             SK_RFCTL_FIFO_THRESHOLD + 1);
2567
2568         /* Configure TX MAC FIFO */
2569         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2570         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2571
2572         DPRINTFN(6, ("sk_init_yukon: end\n"));
2573 }
2574
2575 /*
2576  * Note that to properly initialize any part of the GEnesis chip,
2577  * you first have to take it out of reset mode.
2578  */
2579 static void
2580 sk_init(void *xsc_if)
2581 {
2582         struct sk_if_softc *sc_if = xsc_if;
2583         struct sk_softc *sc = sc_if->sk_softc;
2584         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2585         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2586
2587         DPRINTFN(2, ("sk_init\n"));
2588
2589         ASSERT_SERIALIZED(ifp->if_serializer);
2590
2591         if (ifp->if_flags & IFF_RUNNING)
2592                 return;
2593
2594         /* Cancel pending I/O and free all RX/TX buffers. */
2595         sk_stop(sc_if);
2596
2597         /*
2598          * NOTE: Change sk_use_jumbo after sk_stop(),
2599          *       but before real initialization.
2600          */
2601         if (ifp->if_mtu > ETHER_MAX_LEN)
2602                 sc_if->sk_use_jumbo = 1;
2603         else
2604                 sc_if->sk_use_jumbo = 0;
2605         DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2606
2607         if (SK_IS_GENESIS(sc)) {
2608                 /* Configure LINK_SYNC LED */
2609                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2610                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2611                         SK_LINKLED_LINKSYNC_ON);
2612
2613                 /* Configure RX LED */
2614                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2615                         SK_RXLEDCTL_COUNTER_START);
2616
2617                 /* Configure TX LED */
2618                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2619                         SK_TXLEDCTL_COUNTER_START);
2620         }
2621
2622         /*
2623          * Configure descriptor poll timer
2624          *
2625          * SK-NET GENESIS data sheet says that possibility of losing Start
2626          * transmit command due to CPU/cache related interim storage problems
2627          * under certain conditions. The document recommends a polling
2628          * mechanism to send a Start transmit command to initiate transfer
2629          * of ready descriptors regulary. To cope with this issue sk(4) now
2630          * enables descriptor poll timer to initiate descriptor processing
2631          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2632          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2633          * command instead of waiting for next descriptor polling time.
2634          * The same rule may apply to Rx side too but it seems that is not
2635          * needed at the moment.
2636          * Since sk(4) uses descriptor polling as a last resort there is no
2637          * need to set smaller polling time than maximum allowable one.
2638          */
2639         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2640
2641         /* Configure I2C registers */
2642
2643         /* Configure XMAC(s) */
2644         switch (sc->sk_type) {
2645         case SK_GENESIS:
2646                 sk_init_xmac(sc_if);
2647                 break;
2648         case SK_YUKON:
2649         case SK_YUKON_LITE:
2650         case SK_YUKON_LP:
2651                 sk_init_yukon(sc_if);
2652                 break;
2653         }
2654         mii_mediachg(mii);
2655
2656         if (SK_IS_GENESIS(sc)) {
2657                 /* Configure MAC FIFOs */
2658                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2659                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2660                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2661
2662                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2663                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2664                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2665         }
2666
2667         /* Configure transmit arbiter(s) */
2668         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2669             SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2670
2671         /* Configure RAMbuffers */
2672         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2673         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2674         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2675         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2676         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2677         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2678
2679         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2680         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2681         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2682         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2683         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2684         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2685         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2686
2687         /* Configure BMUs */
2688         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2689         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2690             SK_RX_RING_ADDR(sc_if, 0));
2691         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2692
2693         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2694         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2695             SK_TX_RING_ADDR(sc_if, 0));
2696         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2697
2698         /* Init descriptors */
2699         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2700                 if_printf(ifp, "initialization failed: "
2701                           "no memory for rx buffers\n");
2702                 sk_stop(sc_if);
2703                 return;
2704         }
2705
2706         if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2707                 if_printf(ifp, "initialization failed: "
2708                           "no memory for tx buffers\n");
2709                 sk_stop(sc_if);
2710                 return;
2711         }
2712
2713         /* Configure interrupt handling */
2714         CSR_READ_4(sc, SK_ISSR);
2715         if (sc_if->sk_port == SK_PORT_A)
2716                 sc->sk_intrmask |= SK_INTRS1;
2717         else
2718                 sc->sk_intrmask |= SK_INTRS2;
2719
2720         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2721
2722         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2723
2724         /* Start BMUs. */
2725         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2726
2727         if (SK_IS_GENESIS(sc)) {
2728                 /* Enable XMACs TX and RX state machines */
2729                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2730                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2731                                XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2732         }
2733
2734         if (SK_IS_YUKON(sc)) {
2735                 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2736                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2737 #if 0
2738                 /* XXX disable 100Mbps and full duplex mode? */
2739                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2740 #endif
2741                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2742         }
2743
2744         /* Activate descriptor polling timer */
2745         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2746         /* Start transfer of Tx descriptors */
2747         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2748
2749         ifp->if_flags |= IFF_RUNNING;
2750         ifp->if_flags &= ~IFF_OACTIVE;
2751
2752         if (SK_IS_YUKON(sc))
2753                 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2754 }
2755
2756 static void
2757 sk_stop(struct sk_if_softc *sc_if)
2758 {
2759         struct sk_softc *sc = sc_if->sk_softc;
2760         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2761         struct sk_chain_data *cd = &sc_if->sk_cdata;
2762         uint32_t val;
2763         int i;
2764
2765         ASSERT_SERIALIZED(ifp->if_serializer);
2766
2767         DPRINTFN(2, ("sk_stop\n"));
2768
2769         callout_stop(&sc_if->sk_tick_timer);
2770
2771         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2772
2773         /* Stop Tx descriptor polling timer */
2774         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2775
2776         /* Stop transfer of Tx descriptors */
2777         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2778         for (i = 0; i < SK_TIMEOUT; i++) {
2779                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2780                 if (!(val & SK_TXBMU_TX_STOP))
2781                         break;
2782                 DELAY(1);
2783         }
2784         if (i == SK_TIMEOUT)
2785                 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2786
2787         /* Stop transfer of Rx descriptors */
2788         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2789         for (i = 0; i < SK_TIMEOUT; i++) {
2790                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2791                 if (!(val & SK_RXBMU_RX_STOP))
2792                         break;
2793                 DELAY(1);
2794         }
2795         if (i == SK_TIMEOUT)
2796                 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2797
2798         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2799                 /* Put PHY back into reset. */
2800                 val = sk_win_read_4(sc, SK_GPIO);
2801                 if (sc_if->sk_port == SK_PORT_A) {
2802                         val |= SK_GPIO_DIR0;
2803                         val &= ~SK_GPIO_DAT0;
2804                 } else {
2805                         val |= SK_GPIO_DIR2;
2806                         val &= ~SK_GPIO_DAT2;
2807                 }
2808                 sk_win_write_4(sc, SK_GPIO, val);
2809         }
2810
2811         /* Turn off various components of this interface. */
2812         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2813         switch (sc->sk_type) {
2814         case SK_GENESIS:
2815                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2816                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2817                 break;
2818         case SK_YUKON:
2819         case SK_YUKON_LITE:
2820         case SK_YUKON_LP:
2821                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2822                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2823                 break;
2824         }
2825         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2826         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2827         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2828         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2829             SK_RBCTL_RESET | SK_RBCTL_OFF);
2830         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2831         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2832         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2833         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2834         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2835
2836         /* Disable interrupts */
2837         if (sc_if->sk_port == SK_PORT_A)
2838                 sc->sk_intrmask &= ~SK_INTRS1;
2839         else
2840                 sc->sk_intrmask &= ~SK_INTRS2;
2841         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2842
2843         SK_XM_READ_2(sc_if, XM_ISR);
2844         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2845
2846         /* Free RX and TX mbufs still in the queues. */
2847         for (i = 0; i < SK_RX_RING_CNT; i++) {
2848                 if (cd->sk_rx_mbuf[i] != NULL) {
2849                         if (!sc_if->sk_use_jumbo) {
2850                                 bus_dmamap_unload(cd->sk_rx_dtag,
2851                                                   cd->sk_rx_dmap[i]);
2852                         }
2853                         m_freem(cd->sk_rx_mbuf[i]);
2854                         cd->sk_rx_mbuf[i] = NULL;
2855                 }
2856         }
2857         for (i = 0; i < SK_TX_RING_CNT; i++) {
2858                 if (cd->sk_tx_mbuf[i] != NULL) {
2859                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2860                         m_freem(cd->sk_tx_mbuf[i]);
2861                         cd->sk_tx_mbuf[i] = NULL;
2862                 }
2863         }
2864 }
2865
2866 #ifdef SK_DEBUG
2867 static void
2868 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2869 {
2870 #define DESC_PRINT(X)                                   \
2871         if (X)                                  \
2872                 kprintf("txdesc[%d]." #X "=%#x\n",      \
2873                        idx, X);
2874
2875         DESC_PRINT(le32toh(desc->sk_ctl));
2876         DESC_PRINT(le32toh(desc->sk_next));
2877         DESC_PRINT(le32toh(desc->sk_data_lo));
2878         DESC_PRINT(le32toh(desc->sk_data_hi));
2879         DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2880         DESC_PRINT(le16toh(desc->sk_rsvd0));
2881         DESC_PRINT(le16toh(desc->sk_csum_startval));
2882         DESC_PRINT(le16toh(desc->sk_csum_startpos));
2883         DESC_PRINT(le16toh(desc->sk_csum_writepos));
2884         DESC_PRINT(le16toh(desc->sk_rsvd1));
2885 #undef PRINT
2886 }
2887
2888 static void
2889 sk_dump_bytes(const char *data, int len)
2890 {
2891         int c, i, j;
2892
2893         for (i = 0; i < len; i += 16) {
2894                 kprintf("%08x  ", i);
2895                 c = len - i;
2896                 if (c > 16) c = 16;
2897
2898                 for (j = 0; j < c; j++) {
2899                         kprintf("%02x ", data[i + j] & 0xff);
2900                         if ((j & 0xf) == 7 && j > 0)
2901                                 kprintf(" ");
2902                 }
2903
2904                 for (; j < 16; j++)
2905                         kprintf("   ");
2906                 kprintf("  ");
2907
2908                 for (j = 0; j < c; j++) {
2909                         int ch = data[i + j] & 0xff;
2910                         kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2911                 }
2912
2913                 kprintf("\n");
2914
2915                 if (c < 16)
2916                         break;
2917         }
2918 }
2919
2920 static void
2921 sk_dump_mbuf(struct mbuf *m)
2922 {
2923         int count = m->m_pkthdr.len;
2924
2925         kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2926
2927         while (count > 0 && m) {
2928                 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2929                        m, m->m_data, m->m_len);
2930                 sk_dump_bytes(mtod(m, char *), m->m_len);
2931
2932                 count -= m->m_len;
2933                 m = m->m_next;
2934         }
2935 }
2936 #endif
2937
2938 /*
2939  * Allocate jumbo buffer storage. The SysKonnect adapters support
2940  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2941  * use them in their drivers. In order for us to use them, we need
2942  * large 9K receive buffers, however standard mbuf clusters are only
2943  * 2048 bytes in size. Consequently, we need to allocate and manage
2944  * our own jumbo buffer pool. Fortunately, this does not require an
2945  * excessive amount of additional code.
2946  */
2947 static int
2948 sk_jpool_alloc(device_t dev)
2949 {
2950         struct sk_if_softc *sc_if = device_get_softc(dev);
2951         struct sk_chain_data *cd = &sc_if->sk_cdata;
2952         bus_addr_t paddr;
2953         caddr_t buf;
2954         int error, i;
2955
2956         lwkt_serialize_init(&cd->sk_jpool_serializer);
2957
2958         error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
2959                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2960                                    NULL, NULL, SK_JMEM, 1, SK_JMEM,
2961                                    0, &cd->sk_jpool_dtag);
2962         if (error) {
2963                 device_printf(dev, "can't create jpool DMA tag\n");
2964                 return error;
2965         }
2966
2967         error = bus_dmamem_alloc(cd->sk_jpool_dtag, &cd->sk_jpool,
2968                                  BUS_DMA_WAITOK, &cd->sk_jpool_dmap);
2969         if (error) {
2970                 device_printf(dev, "can't alloc jpool DMA mem\n");
2971                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
2972                 cd->sk_jpool_dtag = NULL;
2973                 return error;
2974         }
2975
2976         error = bus_dmamap_load(cd->sk_jpool_dtag, cd->sk_jpool_dmap,
2977                                 cd->sk_jpool, SK_JMEM,
2978                                 sk_dmamem_addr, &paddr, BUS_DMA_WAITOK);
2979         if (error) {
2980                 device_printf(dev, "can't load DMA mem\n");
2981                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
2982                                 cd->sk_jpool_dmap);
2983                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
2984                 cd->sk_jpool_dtag = NULL;
2985                 return error;
2986         }
2987
2988         SLIST_INIT(&cd->sk_jpool_free_ent);
2989         buf = cd->sk_jpool;
2990
2991         /*
2992          * Now divide it up into SK_JLEN pieces.
2993          */
2994         for (i = 0; i < SK_JSLOTS; i++) {
2995                 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
2996
2997                 entry->sc_if = sc_if;
2998                 entry->inuse = 0;
2999                 entry->slot = i;
3000                 entry->buf = buf;
3001                 entry->paddr = paddr;
3002
3003                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3004
3005                 buf += SK_JLEN;
3006                 paddr += SK_JLEN;
3007         }
3008         return 0;
3009 }
3010
3011 static void
3012 sk_jpool_free(struct sk_if_softc *sc_if)
3013 {
3014         struct sk_chain_data *cd = &sc_if->sk_cdata;
3015
3016         if (cd->sk_jpool_dtag != NULL) {
3017                 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3018                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3019                                 cd->sk_jpool_dmap);
3020                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3021                 cd->sk_jpool_dtag = NULL;
3022         }
3023 }
3024
3025 static int
3026 sk_dma_alloc(device_t dev)
3027 {
3028         struct sk_if_softc *sc_if = device_get_softc(dev);
3029         struct sk_chain_data *cd = &sc_if->sk_cdata;
3030         int i, j, error;
3031
3032         /*
3033          * Allocate the descriptor queues.
3034          * TODO: split into RX/TX rings
3035          */
3036         error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
3037                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3038                                    NULL, NULL,
3039                                    sizeof(struct sk_ring_data), 1,
3040                                    sizeof(struct sk_ring_data), 0,
3041                                    &sc_if->sk_rdata_dtag);
3042         if (error) {
3043                 device_printf(dev, "can't create desc DMA tag\n");
3044                 return error;
3045         }
3046
3047         error = bus_dmamem_alloc(sc_if->sk_rdata_dtag,
3048                                  (void **)&sc_if->sk_rdata,
3049                                  BUS_DMA_WAITOK | BUS_DMA_ZERO,
3050                                  &sc_if->sk_rdata_dmap);
3051         if (error) {
3052                 device_printf(dev, "can't alloc desc DMA mem\n");
3053                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3054                 sc_if->sk_rdata_dtag = NULL;
3055                 return error;
3056         }
3057
3058         error = bus_dmamap_load(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap,
3059                                 sc_if->sk_rdata, sizeof(struct sk_ring_data),
3060                                 sk_dmamem_addr, &sc_if->sk_rdata_paddr,
3061                                 BUS_DMA_WAITOK);
3062         if (error) {
3063                 device_printf(dev, "can't load desc DMA mem\n");
3064                 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3065                                 sc_if->sk_rdata_dmap);
3066                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3067                 sc_if->sk_rdata_dtag = NULL;
3068                 return error;
3069         }
3070
3071         /* Try to allocate memory for jumbo buffers. */
3072         error = sk_jpool_alloc(dev);
3073         if (error) {
3074                 device_printf(dev, "jumbo buffer allocation failed\n");
3075                 return error;
3076         }
3077
3078         /* Create DMA tag for TX. */
3079         error = bus_dma_tag_create(NULL, 1, 0,
3080                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3081                                    NULL, NULL,
3082                                    SK_JLEN, SK_NTXSEG, SK_JLEN,
3083                                    0, &cd->sk_tx_dtag);
3084         if (error) {
3085                 device_printf(dev, "can't create TX DMA tag\n");
3086                 return error;
3087         }
3088
3089         /* Create DMA maps for TX. */
3090         for (i = 0; i < SK_TX_RING_CNT; i++) {
3091                 error = bus_dmamap_create(cd->sk_tx_dtag, 0,
3092                                           &cd->sk_tx_dmap[i]);
3093                 if (error) {
3094                         device_printf(dev, "can't create %dth TX DMA map\n", i);
3095
3096                         for (j = 0; j < i; ++j) {
3097                                 bus_dmamap_destroy(cd->sk_tx_dtag,
3098                                                    cd->sk_tx_dmap[i]);
3099                         }
3100                         bus_dma_tag_destroy(cd->sk_tx_dtag);
3101                         cd->sk_tx_dtag = NULL;
3102                         return error;
3103                 }
3104         }
3105
3106         /* Create DMA tag for RX. */
3107         error = bus_dma_tag_create(NULL, 1, 0,
3108                                    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3109                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3110                                    0, &cd->sk_rx_dtag);
3111         if (error) {
3112                 device_printf(dev, "can't create RX DMA tag\n");
3113                 return error;
3114         }
3115
3116         /* Create a spare RX DMA map. */
3117         error = bus_dmamap_create(cd->sk_rx_dtag, 0, &cd->sk_rx_dmap_tmp);
3118         if (error) {
3119                 device_printf(dev, "can't create spare RX DMA map\n");
3120                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3121                 cd->sk_rx_dtag = NULL;
3122                 return error;
3123         }
3124
3125         /* Create DMA maps for RX. */
3126         for (i = 0; i < SK_RX_RING_CNT; ++i) {
3127                 error = bus_dmamap_create(cd->sk_rx_dtag, 0,
3128                                           &cd->sk_rx_dmap[i]);
3129                 if (error) {
3130                         device_printf(dev, "can't create %dth RX DMA map\n", i);
3131
3132                         for (j = 0; j < i; ++j) {
3133                                 bus_dmamap_destroy(cd->sk_rx_dtag,
3134                                                    cd->sk_rx_dmap[i]);
3135                         }
3136                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3137                         bus_dma_tag_destroy(cd->sk_rx_dtag);
3138                         cd->sk_rx_dtag = NULL;
3139                         return error;
3140                 }
3141         }
3142         return 0;
3143 }
3144
3145 static void
3146 sk_dma_free(device_t dev)
3147 {
3148         struct sk_if_softc *sc_if = device_get_softc(dev);
3149         struct sk_chain_data *cd = &sc_if->sk_cdata;
3150         int i;
3151
3152         if (cd->sk_tx_dtag != NULL) {
3153                 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3154                         KASSERT(cd->sk_tx_mbuf[i] == NULL,
3155                                 ("sk_stop() is not called before %s()",
3156                                  __func__));
3157                         bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3158                 }
3159                 bus_dma_tag_destroy(cd->sk_tx_dtag);
3160                 cd->sk_tx_dtag = NULL;
3161         }
3162
3163         if (cd->sk_rx_dtag != NULL) {
3164                 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3165                         KASSERT(cd->sk_rx_mbuf[i] == NULL,
3166                                 ("sk_stop() is not called before %s()",
3167                                  __func__));
3168                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3169                 }
3170                 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3171                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3172                 cd->sk_rx_dtag = NULL;
3173         }
3174
3175         sk_jpool_free(sc_if);
3176
3177         if (sc_if->sk_rdata_dtag != NULL) {
3178                 bus_dmamap_unload(sc_if->sk_rdata_dtag, sc_if->sk_rdata_dmap);
3179                 bus_dmamem_free(sc_if->sk_rdata_dtag, sc_if->sk_rdata,
3180                                 sc_if->sk_rdata_dmap);
3181                 bus_dma_tag_destroy(sc_if->sk_rdata_dtag);
3182                 sc_if->sk_rdata_dtag = NULL;
3183         }
3184 }
3185
3186 static void
3187 sk_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
3188                 bus_size_t mapsz __unused, int error)
3189 {
3190         struct sk_dma_ctx *ctx = arg;
3191         int i;
3192
3193         if (error)
3194                 return;
3195
3196         KASSERT(nsegs <= ctx->nsegs,
3197                 ("too many segments(%d), should be <= %d\n",
3198                  nsegs, ctx->nsegs));
3199
3200         ctx->nsegs = nsegs;
3201         for (i = 0; i < nsegs; ++i)
3202                 ctx->segs[i] = segs[i];
3203 }
3204
3205 static void
3206 sk_dmamem_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3207 {
3208         KASSERT(nseg == 1, ("too many segments %d", nseg));
3209         *((bus_addr_t *)arg) = seg->ds_addr;
3210 }