sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
   2  * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  31  */
  32
  33 #include <dev/drm/drmP.h>
  34 #include <dev/drm/drm.h>
  35 #include <dev/drm/drm_mm.h>
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include <dev/drm/drm_pciids.h>
  39 #include "intel_drv.h"
  40
  41 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
  42 static drm_pci_id_list_t i915_pciidlist[] = {
  43         i915_PCI_IDS
  44 };
  45
  46 static const struct intel_device_info intel_i830_info = {
  47         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  48         .has_overlay = 1, .overlay_needs_physical = 1,
  49 };
  50
  51 static const struct intel_device_info intel_845g_info = {
  52         .gen = 2,
  53         .has_overlay = 1, .overlay_needs_physical = 1,
  54 };
  55
  56 static const struct intel_device_info intel_i85x_info = {
  57         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  58         .cursor_needs_physical = 1,
  59         .has_overlay = 1, .overlay_needs_physical = 1,
  60 };
  61
  62 static const struct intel_device_info intel_i865g_info = {
  63         .gen = 2,
  64         .has_overlay = 1, .overlay_needs_physical = 1,
  65 };
  66
  67 static const struct intel_device_info intel_i915g_info = {
  68         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  69         .has_overlay = 1, .overlay_needs_physical = 1,
  70 };
  71 static const struct intel_device_info intel_i915gm_info = {
  72         .gen = 3, .is_mobile = 1,
  73         .cursor_needs_physical = 1,
  74         .has_overlay = 1, .overlay_needs_physical = 1,
  75         .supports_tv = 1,
  76 };
  77 static const struct intel_device_info intel_i945g_info = {
  78         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  79         .has_overlay = 1, .overlay_needs_physical = 1,
  80 };
  81 static const struct intel_device_info intel_i945gm_info = {
  82         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  83         .has_hotplug = 1, .cursor_needs_physical = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85         .supports_tv = 1,
  86 };
  87
  88 static const struct intel_device_info intel_i965g_info = {
  89         .gen = 4, .is_broadwater = 1,
  90         .has_hotplug = 1,
  91         .has_overlay = 1,
  92 };
  93
  94 static const struct intel_device_info intel_i965gm_info = {
  95         .gen = 4, .is_crestline = 1,
  96         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  97         .has_overlay = 1,
  98         .supports_tv = 1,
  99 };
 100
 101 static const struct intel_device_info intel_g33_info = {
 102         .gen = 3, .is_g33 = 1,
 103         .need_gfx_hws = 1, .has_hotplug = 1,
 104         .has_overlay = 1,
 105 };
 106
 107 static const struct intel_device_info intel_g45_info = {
 108         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 109         .has_pipe_cxsr = 1, .has_hotplug = 1,
 110         .has_bsd_ring = 1,
 111 };
 112
 113 static const struct intel_device_info intel_gm45_info = {
 114         .gen = 4, .is_g4x = 1,
 115         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 116         .has_pipe_cxsr = 1, .has_hotplug = 1,
 117         .supports_tv = 1,
 118         .has_bsd_ring = 1,
 119 };
 120
 121 static const struct intel_device_info intel_pineview_info = {
 122         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 123         .need_gfx_hws = 1, .has_hotplug = 1,
 124         .has_overlay = 1,
 125 };
 126
 127 static const struct intel_device_info intel_ironlake_d_info = {
 128         .gen = 5,
 129         .need_gfx_hws = 1, .has_hotplug = 1,
 130         .has_bsd_ring = 1,
 131 };
 132
 133 static const struct intel_device_info intel_ironlake_m_info = {
 134         .gen = 5, .is_mobile = 1,
 135         .need_gfx_hws = 1, .has_hotplug = 1,
 136         .has_fbc = 0, /* disabled due to buggy hardware */
 137         .has_bsd_ring = 1,
 138 };
 139
 140 static const struct intel_device_info intel_sandybridge_d_info = {
 141         .gen = 6,
 142         .need_gfx_hws = 1, .has_hotplug = 1,
 143         .has_bsd_ring = 1,
 144         .has_blt_ring = 1,
 145         .has_llc = 1,
 146 };
 147
 148 static const struct intel_device_info intel_sandybridge_m_info = {
 149         .gen = 6, .is_mobile = 1,
 150         .need_gfx_hws = 1, .has_hotplug = 1,
 151         .has_fbc = 1,
 152         .has_bsd_ring = 1,
 153         .has_blt_ring = 1,
 154         .has_llc = 1,
 155 };
 156
 157 static const struct intel_device_info intel_ivybridge_d_info = {
 158         .is_ivybridge = 1, .gen = 7,
 159         .need_gfx_hws = 1, .has_hotplug = 1,
 160         .has_bsd_ring = 1,
 161         .has_blt_ring = 1,
 162         .has_llc = 1,
 163 };
 164
 165 static const struct intel_device_info intel_ivybridge_m_info = {
 166         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 167         .need_gfx_hws = 1, .has_hotplug = 1,
 168         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 169         .has_bsd_ring = 1,
 170         .has_blt_ring = 1,
 171         .has_llc = 1,
 172 };
 173
 174 #define INTEL_VGA_DEVICE(id, info_) {           \
 175         .device = id,                           \
 176         .info = info_,                          \
 177 }
 178
 179 static const struct intel_gfx_device_id {
 180         int device;
 181         const struct intel_device_info *info;
 182 } pciidlist[] = {               /* aka */
 183         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
 184         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
 185         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
 186         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 187         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
 188         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
 189         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
 190         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
 191         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
 192         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
 193         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
 194         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
 195         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
 196         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
 197         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
 198         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
 199         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
 200         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
 201         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
 202         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
 203         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
 204         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
 205         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
 206         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
 207         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
 208         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
 209         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),
 210         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 211         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 212         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 213         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 214         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 215         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 216         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 217         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 218         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 219         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 220         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 221         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 222         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 223         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 224         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 225         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 226         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 227         {0, 0}
 228 };
 229
 230 static int i915_drm_freeze(struct drm_device *dev)
 231 {
 232         struct drm_i915_private *dev_priv;
 233         int error;
 234
 235         dev_priv = dev->dev_private;
 236         drm_kms_helper_poll_disable(dev);
 237
 238 #if 0
 239         pci_save_state(dev->pdev);
 240 #endif
 241
 242         DRM_LOCK(dev);
 243         /* If KMS is active, we do the leavevt stuff here */
 244         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 245                 error = -i915_gem_idle(dev);
 246                 if (error) {
 247                         DRM_UNLOCK(dev);
 248                         device_printf(dev->device,
 249                             "GEM idle failed, resume might fail\n");
 250                         return (error);
 251                 }
 252                 drm_irq_uninstall(dev);
 253         }
 254
 255         i915_save_state(dev);
 256
 257         intel_opregion_fini(dev);
 258
 259         /* Modeset on resume, not lid events */
 260         dev_priv->modeset_on_lid = 0;
 261         DRM_UNLOCK(dev);
 262
 263         return 0;
 264 }
 265
 266 static int
 267 i915_suspend(device_t kdev)
 268 {
 269         struct drm_device *dev;
 270         int error;
 271
 272         dev = device_get_softc(kdev);
 273         if (dev == NULL || dev->dev_private == NULL) {
 274                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 275                 return -ENODEV;
 276         }
 277
 278         DRM_DEBUG_KMS("starting suspend\n");
 279         error = i915_drm_freeze(dev);
 280         if (error)
 281                 return (error);
 282
 283         error = bus_generic_suspend(kdev);
 284         DRM_DEBUG_KMS("finished suspend %d\n", error);
 285         return (error);
 286 }
 287
 288 static int i915_drm_thaw(struct drm_device *dev)
 289 {
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291         int error = 0;
 292
 293         DRM_LOCK(dev);
 294         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 295                 i915_gem_restore_gtt_mappings(dev);
 296         }
 297
 298         i915_restore_state(dev);
 299         intel_opregion_setup(dev);
 300
 301         /* KMS EnterVT equivalent */
 302         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 303                 dev_priv->mm.suspended = 0;
 304
 305                 error = i915_gem_init_hw(dev);
 306
 307                 if (HAS_PCH_SPLIT(dev))
 308                         ironlake_init_pch_refclk(dev);
 309
 310                 DRM_UNLOCK(dev);
 311                 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
 312                 drm_mode_config_reset(dev);
 313                 lockmgr(&dev->mode_config.lock, LK_RELEASE);
 314                 drm_irq_install(dev);
 315
 316                 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
 317                 /* Resume the modeset for every activated CRTC */
 318                 drm_helper_resume_force_mode(dev);
 319                 lockmgr(&dev->mode_config.lock, LK_RELEASE);
 320
 321                 if (IS_IRONLAKE_M(dev))
 322                         ironlake_enable_rc6(dev);
 323                 DRM_LOCK(dev);
 324         }
 325
 326         intel_opregion_init(dev);
 327
 328         dev_priv->modeset_on_lid = 0;
 329
 330         DRM_UNLOCK(dev);
 331
 332         return error;
 333 }
 334
 335 static int
 336 i915_resume(device_t kdev)
 337 {
 338         struct drm_device *dev;
 339         int ret;
 340
 341         dev = device_get_softc(kdev);
 342         DRM_DEBUG_KMS("starting resume\n");
 343 #if 0
 344         if (pci_enable_device(dev->pdev))
 345                 return -EIO;
 346
 347         pci_set_master(dev->pdev);
 348 #endif
 349
 350         ret = -i915_drm_thaw(dev);
 351         if (ret != 0)
 352                 return (ret);
 353
 354         drm_kms_helper_poll_enable(dev);
 355         ret = bus_generic_resume(kdev);
 356         DRM_DEBUG_KMS("finished resume %d\n", ret);
 357         return (ret);
 358 }
 359
 360 static int
 361 i915_probe(device_t kdev)
 362 {
 363
 364         return drm_probe(kdev, i915_pciidlist);
 365 }
 366
 367 int i915_modeset;
 368
 369 static int
 370 i915_attach(device_t kdev)
 371 {
 372         struct drm_device *dev;
 373
 374         dev = device_get_softc(kdev);
 375         if (i915_modeset == 1)
 376                 i915_driver_info.driver_features |= DRIVER_MODESET;
 377         dev->driver = &i915_driver_info;
 378         return (drm_attach(kdev, i915_pciidlist));
 379 }
 380
 381 const struct intel_device_info *
 382 i915_get_device_id(int device)
 383 {
 384         const struct intel_gfx_device_id *did;
 385
 386         for (did = &pciidlist[0]; did->device != 0; did++) {
 387                 if (did->device != device)
 388                         continue;
 389                 return (did->info);
 390         }
 391         return (NULL);
 392 }
 393
 394 static device_method_t i915_methods[] = {
 395         /* Device interface */
 396         DEVMETHOD(device_probe,         i915_probe),
 397         DEVMETHOD(device_attach,        i915_attach),
 398         DEVMETHOD(device_suspend,       i915_suspend),
 399         DEVMETHOD(device_resume,        i915_resume),
 400         DEVMETHOD(device_detach,        drm_detach),
 401         DEVMETHOD_END
 402 };
 403
 404 static driver_t i915_driver = {
 405         "drm",
 406         i915_methods,
 407         sizeof(struct drm_device)
 408 };
 409
 410 extern devclass_t drm_devclass;
 411 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
 412     SI_ORDER_ANY);
 413 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
 414 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
 415 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
 416 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
 417 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
 418
 419 int intel_iommu_enabled = 0;
 420 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
 421
 422 int i915_semaphores = -1;
 423 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
 424 static int i915_try_reset = 1;
 425 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
 426 unsigned int i915_lvds_downclock = 0;
 427 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
 428 int i915_vbt_sdvo_panel_type = -1;
 429 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
 430 unsigned int i915_powersave = 1;
 431 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
 432 int i915_enable_fbc = 0;
 433 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
 434 int i915_enable_rc6 = 0;
 435 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
 436 int i915_panel_use_ssc = -1;
 437 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
 438 int i915_panel_ignore_lid = 0;
 439 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
 440 int i915_modeset = 1;
 441 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
 442 int i915_enable_ppgtt = -1;
 443 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 444 int i915_enable_hangcheck = 1;
 445 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
 446
 447 #define PCI_VENDOR_INTEL                0x8086
 448 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 449 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 450 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 451 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 452
 453 void
 454 intel_detect_pch(struct drm_device *dev)
 455 {
 456         struct drm_i915_private *dev_priv;
 457         device_t pch;
 458         uint32_t id;
 459
 460         dev_priv = dev->dev_private;
 461         pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
 462         if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 463                 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 464                 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 465                         dev_priv->pch_type = PCH_IBX;
 466                         DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 467                 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 468                         dev_priv->pch_type = PCH_CPT;
 469                         DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 470                 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 471                         /* PantherPoint is CPT compatible */
 472                         dev_priv->pch_type = PCH_CPT;
 473                         DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 474                 } else
 475                         DRM_DEBUG_KMS("No PCH detected\n");
 476         } else
 477                 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
 478 }
 479
 480 void
 481 __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 482 {
 483         int count;
 484
 485         count = 0;
 486         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 487                 DELAY(10);
 488
 489         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 490         POSTING_READ(FORCEWAKE);
 491
 492         count = 0;
 493         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 494                 DELAY(10);
 495 }
 496
 497 void
 498 __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 499 {
 500         int count;
 501
 502         count = 0;
 503         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 504                 DELAY(10);
 505
 506         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 507         POSTING_READ(FORCEWAKE_MT);
 508
 509         count = 0;
 510         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 511                 DELAY(10);
 512 }
 513
 514 void
 515 gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 516 {
 517
 518         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 519         if (dev_priv->forcewake_count++ == 0)
 520                 dev_priv->display.force_wake_get(dev_priv);
 521         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 522 }
 523
 524 static void
 525 gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 526 {
 527         u32 gtfifodbg;
 528
 529         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 530         if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
 531                 kprintf("MMIO read or write has been dropped %x\n", gtfifodbg);
 532                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 533         }
 534 }
 535
 536 void
 537 __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 538 {
 539
 540         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 541         /* The below doubles as a POSTING_READ */
 542         gen6_gt_check_fifodbg(dev_priv);
 543 }
 544
 545 void
 546 __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 547 {
 548
 549         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 550         /* The below doubles as a POSTING_READ */
 551         gen6_gt_check_fifodbg(dev_priv);
 552 }
 553
 554 void
 555 gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 556 {
 557
 558         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 559         if (--dev_priv->forcewake_count == 0)
 560                 dev_priv->display.force_wake_put(dev_priv);
 561         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 562 }
 563
 564 int
 565 __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 566 {
 567         int ret = 0;
 568
 569         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 570                 int loop = 500;
 571                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 572                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 573                         DELAY(10);
 574                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 575                 }
 576                 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 577                         kprintf("%s loop\n", __func__);
 578                         ++ret;
 579                 }
 580                 dev_priv->gt_fifo_count = fifo;
 581         }
 582         dev_priv->gt_fifo_count--;
 583
 584         return (ret);
 585 }
 586
 587 static int
 588 i8xx_do_reset(struct drm_device *dev, u8 flags)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591
 592         if (IS_I85X(dev))
 593                 return -ENODEV;
 594
 595         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 596         POSTING_READ(D_STATE);
 597
 598         if (IS_I830(dev) || IS_845G(dev)) {
 599                 I915_WRITE(DEBUG_RESET_I830,
 600                            DEBUG_RESET_DISPLAY |
 601                            DEBUG_RESET_RENDER |
 602                            DEBUG_RESET_FULL);
 603                 POSTING_READ(DEBUG_RESET_I830);
 604                 DELAY(1000);
 605
 606                 I915_WRITE(DEBUG_RESET_I830, 0);
 607                 POSTING_READ(DEBUG_RESET_I830);
 608         }
 609
 610         DELAY(1000);
 611
 612         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 613         POSTING_READ(D_STATE);
 614
 615         return 0;
 616 }
 617
 618 static int
 619 i965_reset_complete(struct drm_device *dev)
 620 {
 621         u8 gdrst;
 622
 623         gdrst = pci_read_config(dev->device, I965_GDRST, 1);
 624         return (gdrst & 0x1);
 625 }
 626
 627 static int
 628 i965_do_reset(struct drm_device *dev, u8 flags)
 629 {
 630         u8 gdrst;
 631
 632         /*
 633          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 634          * well as the reset bit (GR/bit 0).  Setting the GR bit
 635          * triggers the reset; when done, the hardware will clear it.
 636          */
 637         gdrst = pci_read_config(dev->device, I965_GDRST, 1);
 638         pci_write_config(dev->device, I965_GDRST, gdrst | flags | 0x1, 1);
 639
 640         return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
 641             "915rst"));
 642 }
 643
 644 static int
 645 ironlake_do_reset(struct drm_device *dev, u8 flags)
 646 {
 647         struct drm_i915_private *dev_priv;
 648         u32 gdrst;
 649
 650         dev_priv = dev->dev_private;
 651         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 652         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 653         return (_intel_wait_for(dev,
 654             (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
 655             500, 1, "915rst"));
 656 }
 657
 658 static int
 659 gen6_do_reset(struct drm_device *dev, u8 flags)
 660 {
 661         struct drm_i915_private *dev_priv;
 662         int ret;
 663
 664         dev_priv = dev->dev_private;
 665
 666         /* Hold gt_lock across reset to prevent any register access
 667          * with forcewake not set correctly
 668          */
 669         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 670
 671         /* Reset the chip */
 672
 673         /* GEN6_GDRST is not in the gt power well, no need to check
 674          * for fifo space for the write or forcewake the chip for
 675          * the read
 676          */
 677         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 678
 679         /* Spin waiting for the device to ack the reset request */
 680         ret = _intel_wait_for(dev,
 681             (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
 682             500, 1, "915rst");
 683
 684         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 685         if (dev_priv->forcewake_count)
 686                 dev_priv->display.force_wake_get(dev_priv);
 687         else
 688                 dev_priv->display.force_wake_put(dev_priv);
 689
 690         /* Restore fifo count */
 691         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 692
 693         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 694         return (ret);
 695 }
 696
 697 int
 698 i915_reset(struct drm_device *dev, u8 flags)
 699 {
 700         drm_i915_private_t *dev_priv = dev->dev_private;
 701         /*
 702          * We really should only reset the display subsystem if we actually
 703          * need to
 704          */
 705         bool need_display = true;
 706         int ret;
 707
 708         if (!i915_try_reset)
 709                 return (0);
 710
 711         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
 712                 return (-EBUSY);
 713
 714         i915_gem_reset(dev);
 715
 716         ret = -ENODEV;
 717         if (time_uptime - dev_priv->last_gpu_reset < 5) {
 718                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 719         } else {
 720                 switch (INTEL_INFO(dev)->gen) {
 721                 case 7:
 722                 case 6:
 723                 ret = gen6_do_reset(dev, flags);
 724                 break;
 725         case 5:
 726                 ret = ironlake_do_reset(dev, flags);
 727                         break;
 728                 case 4:
 729                         ret = i965_do_reset(dev, flags);
 730                         break;
 731                 case 2:
 732                         ret = i8xx_do_reset(dev, flags);
 733                         break;
 734                 }
 735         }
 736         dev_priv->last_gpu_reset = time_uptime;
 737         if (ret) {
 738                 DRM_ERROR("Failed to reset chip.\n");
 739                 DRM_UNLOCK(dev);
 740                 return (ret);
 741         }
 742
 743         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 744             !dev_priv->mm.suspended) {
 745                 dev_priv->mm.suspended = 0;
 746
 747                 i915_gem_init_swizzling(dev);
 748
 749                 dev_priv->rings[RCS].init(&dev_priv->rings[RCS]);
 750                 if (HAS_BSD(dev))
 751                         dev_priv->rings[VCS].init(&dev_priv->rings[VCS]);
 752                 if (HAS_BLT(dev))
 753                         dev_priv->rings[BCS].init(&dev_priv->rings[BCS]);
 754
 755                 i915_gem_init_ppgtt(dev);
 756
 757                 drm_irq_uninstall(dev);
 758                 drm_mode_config_reset(dev);
 759                 DRM_UNLOCK(dev);
 760                 drm_irq_install(dev);
 761                 DRM_LOCK(dev);
 762         }
 763         DRM_UNLOCK(dev);
 764
 765         if (need_display) {
 766                 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
 767                 drm_helper_resume_force_mode(dev);
 768                 lockmgr(&dev->mode_config.lock, LK_RELEASE);
 769         }
 770
 771         return (0);
 772 }
 773
 774 #define __i915_read(x, y) \
 775 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 776         u##x val = 0; \
 777         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 778                 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
 779                 if (dev_priv->forcewake_count == 0) \
 780                         dev_priv->display.force_wake_get(dev_priv); \
 781                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 782                 if (dev_priv->forcewake_count == 0) \
 783                         dev_priv->display.force_wake_put(dev_priv); \
 784                 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
 785         } else { \
 786                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
 787         } \
 788         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 789         return val; \
 790 }
 791
 792 __i915_read(8, 8)
 793 __i915_read(16, 16)
 794 __i915_read(32, 32)
 795 __i915_read(64, 64)
 796 #undef __i915_read
 797
 798 #define __i915_write(x, y) \
 799 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 800         u32 __fifo_ret = 0; \
 801         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 802         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 803                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 804         } \
 805         DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
 806         if (__predict_false(__fifo_ret)) { \
 807                 gen6_gt_check_fifodbg(dev_priv); \
 808         } \
 809 }
 810 __i915_write(8, 8)
 811 __i915_write(16, 16)
 812 __i915_write(32, 32)
 813 __i915_write(64, 64)
 814 #undef __i915_write