2 * Copyright (c) 1997 Semen Ustimenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_txreg.h,v 1.12.2.1 2002/10/29 01:43:50 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_txreg.h,v 1.3 2005/11/20 11:59:54 sephe Exp $
30 #define EPIC_MAX_MTU 1600 /* This is experiment-derived value */
32 /* EPIC's registers */
33 #define COMMAND 0x0000
34 #define INTSTAT 0x0004 /* Interrupt status. See below */
35 #define INTMASK 0x0008 /* Interrupt mask. See below */
38 #define EECTL 0x0014 /* EEPROM control **/
39 #define TEST1 0x001C /* XXXXX */
40 #define CRCCNT 0x0020 /* CRC error counter */
41 #define ALICNT 0x0024 /* FrameTooLang error counter */
42 #define MPCNT 0x0028 /* MissedFrames error counters */
44 #define MIIDATA 0x0034
47 #define LAN0 0x0040 /* MAC address */
48 #define LAN1 0x0044 /* MAC address */
49 #define LAN2 0x0048 /* MAC address */
51 #define MC0 0x0050 /* Multicast filter table */
52 #define MC1 0x0054 /* Multicast filter table */
53 #define MC2 0x0058 /* Multicast filter table */
54 #define MC3 0x005C /* Multicast filter table */
55 #define RXCON 0x0060 /* Rx control register */
56 #define TXCON 0x0070 /* Tx control register */
58 #define PRCDAR 0x0084 /* RxRing bus address */
60 #define PRCPTHR 0x00B0
61 #define PTCDAR 0x00C4 /* TxRing bus address */
64 #define COMMAND_STOP_RX 0x01
65 #define COMMAND_START_RX 0x02
66 #define COMMAND_TXQUEUED 0x04
67 #define COMMAND_RXQUEUED 0x08
68 #define COMMAND_NEXTFRAME 0x10
69 #define COMMAND_STOP_TDMA 0x20
70 #define COMMAND_STOP_RDMA 0x40
71 #define COMMAND_TXUGO 0x80
73 /* Interrupt register bits */
74 #define INTSTAT_RCC 0x00000001
75 #define INTSTAT_HCC 0x00000002
76 #define INTSTAT_RQE 0x00000004
77 #define INTSTAT_OVW 0x00000008
78 #define INTSTAT_RXE 0x00000010
79 #define INTSTAT_TXC 0x00000020
80 #define INTSTAT_TCC 0x00000040
81 #define INTSTAT_TQE 0x00000080
82 #define INTSTAT_TXU 0x00000100
83 #define INTSTAT_CNT 0x00000200
84 #define INTSTAT_PREI 0x00000400
85 #define INTSTAT_RCT 0x00000800
86 #define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */
87 #define INTSTAT_UNUSED1 0x00002000
88 #define INTSTAT_UNUSED2 0x00004000
89 #define INTSTAT_GP2 0x00008000 /* PHY Event */
90 #define INTSTAT_INT_ACTV 0x00010000
91 #define INTSTAT_RXIDLE 0x00020000
92 #define INTSTAT_TXIDLE 0x00040000
93 #define INTSTAT_RCIP 0x00080000
94 #define INTSTAT_TCIP 0x00100000
95 #define INTSTAT_RBE 0x00200000
96 #define INTSTAT_RCTS 0x00400000
97 #define INTSTAT_RSV 0x00800000
98 #define INTSTAT_DPE 0x01000000 /* PCI Fatal error */
99 #define INTSTAT_APE 0x02000000 /* PCI Fatal error */
100 #define INTSTAT_PMA 0x04000000 /* PCI Fatal error */
101 #define INTSTAT_PTA 0x08000000 /* PCI Fatal error */
103 #define GENCTL_SOFT_RESET 0x00000001
104 #define GENCTL_ENABLE_INTERRUPT 0x00000002
105 #define GENCTL_SOFTWARE_INTERRUPT 0x00000004
106 #define GENCTL_POWER_DOWN 0x00000008
107 #define GENCTL_ONECOPY 0x00000010
108 #define GENCTL_BIG_ENDIAN 0x00000020
109 #define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040
110 #define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080
111 #define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300
112 #define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200
113 #define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100
114 #define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000
115 #define GENCTL_MEMORY_READ_LINE 0x00000400
116 #define GENCTL_MEMORY_READ_MULTIPLE 0x00000800
117 #define GENCTL_SOFTWARE1 0x00001000
118 #define GENCTL_SOFTWARE2 0x00002000
119 #define GENCTL_RESET_PHY 0x00004000
121 #define NVCTL_ENABLE_MEMORY_MAP 0x00000001
122 #define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002
123 #define NVCTL_GP1_OUTPUT_ENABLE 0x00000004
124 #define NVCTL_GP2_OUTPUT_ENABLE 0x00000008
125 #define NVCTL_GP1 0x00000010
126 #define NVCTL_GP2 0x00000020
127 #define NVCTL_CARDBUS_MODE 0x00000040
128 #define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7)
130 #define RXCON_SAVE_ERRORED_PACKETS 0x00000001
131 #define RXCON_RECEIVE_RUNT_FRAMES 0x00000002
132 #define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004
133 #define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008
134 #define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010
135 #define RXCON_PROMISCUOUS_MODE 0x00000020
136 #define RXCON_MONITOR_MODE 0x00000040
137 #define RXCON_EARLY_RECEIVE_ENABLE 0x00000080
138 #define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000
139 #define RXCON_EXTERNAL_BUFFER_16K 0x00000100
140 #define RXCON_EXTERNAL_BUFFER_32K 0x00000200
141 #define RXCON_EXTERNAL_BUFFER_128K 0x00000300
143 #define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001
144 #define TXCON_LOOPBACK_DISABLE 0x00000000
145 #define TXCON_LOOPBACK_MODE_INT 0x00000002
146 #define TXCON_LOOPBACK_MODE_PHY 0x00000004
147 #define TXCON_LOOPBACK_MODE 0x00000006
148 #define TXCON_FULL_DUPLEX 0x00000006
149 #define TXCON_SLOT_TIME 0x00000078
151 #define MIICFG_SERIAL_ENABLE 0x00000001
152 #define MIICFG_694_ENABLE 0x00000002
153 #define MIICFG_694_STATUS 0x00000004
154 #define MIICFG_PHY_PRESENT 0x00000008
155 #define MIICFG_SMI_ENABLE 0x00000010
157 #define TEST1_CLOCK_TEST 0x00000008
160 * Some default values
162 #define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE)
163 #define TRANSMIT_THRESHOLD 0x300
164 #define TRANSMIT_THRESHOLD_MAX 0x600
166 #define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \
167 RXCON_RECEIVE_BROADCAST_FRAMES)
169 #define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \
170 RXCON_SAVE_ERRORED_PACKETS)
173 * SMC9432* eeprom is organized by words and only first 8 words
174 * have distinctive meaning (according to datasheet)
176 #define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */
177 #define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */
178 #define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */
179 #define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */
180 #define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */
181 #define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */
182 #define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */
183 #define EEPROM_SSID 0x0006 /* Subsystem Id */
186 * Hardware structures
189 /* EPIC's hardware descriptors, must be aligned on dword in memory */
190 /* NB: to make driver happy, this two structures MUST have thier sizes */
191 /* be divisor of PAGE_SIZE */
192 struct epic_tx_desc {
193 volatile u_int16_t status;
194 volatile u_int16_t txlength;
195 volatile u_int32_t bufaddr;
196 volatile u_int16_t buflength;
197 volatile u_int16_t control;
198 volatile u_int32_t next;
200 struct epic_rx_desc {
201 volatile u_int16_t status;
202 volatile u_int16_t rxlength;
203 volatile u_int32_t bufaddr;
204 volatile u_int32_t buflength;
205 volatile u_int32_t next;
208 /* This structure defines EPIC's fragment list, maximum number of frags */
209 /* is 63. Let use maximum, becouse size of struct MUST be divisor of */
210 /* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */
211 #define EPIC_MAX_FRAGS 63
212 struct epic_frag_list {
213 volatile u_int32_t numfrags;
215 volatile u_int32_t fragaddr;
216 volatile u_int32_t fraglen;
217 } frag[EPIC_MAX_FRAGS];
218 volatile u_int32_t pad; /* align on 256 bytes */
222 * NB: ALIGN OF ABOVE STRUCTURES
223 * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword
226 #define SMC9432DMT 0xA010
227 #define SMC9432TX 0xA011
228 #define SMC9032TXM 0xA012
229 #define SMC9032TX 0xA013
230 #define SMC9432TXPWR 0xA014
231 #define SMC9432BTX 0xA015
232 #define SMC9432FTX 0xA016
233 #define SMC9432FTX_SC 0xA017
234 #define SMC9432TX_XG_ADHOC 0xA020
235 #define SMC9434TX_XG_ADHOC 0xA021
236 #define SMC9432FTX_ADHOC 0xA022
237 #define SMC9432BTX1 0xA024