2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
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32 * $FreeBSD: src/sys/dev/rp/rpreg.h,v 1.4.2.1 2002/06/18 03:11:46 obrien Exp $
33 * $DragonFly: src/sys/dev/serial/rp/rpreg.h,v 1.3 2004/05/19 22:52:49 dillon Exp $
37 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
40 typedef unsigned char Byte_t;
41 typedef unsigned int ByteIO_t;
43 typedef unsigned int Word_t;
44 typedef unsigned int WordIO_t;
46 typedef unsigned long DWord_t;
47 typedef unsigned int DWordIO_t;
49 #define rp_readio(size, ctlp, rid, offset) \
50 (bus_space_read_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset))
51 #define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
52 (bus_space_read_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
53 #define rp_writeio(size, ctlp, rid, offset, data) \
54 (bus_space_write_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, data))
55 #define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
56 (bus_space_write_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
58 #define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset)
59 #define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset)
60 #define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset)
61 #define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data)
62 #define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data)
63 #define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data)
64 #define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count)
65 #define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count)
66 #define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count)
67 #define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count)
68 #define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count)
69 #define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count)
71 #define rp_readaiop1(ctlp, aiop, offset) \
72 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
73 #define rp_readaiop2(ctlp, aiop, offset) \
74 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
75 #define rp_readaiop4(ctlp, aiop, offset) \
76 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
77 #define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
78 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
79 #define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
80 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
81 #define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
82 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
83 #define rp_writeaiop1(ctlp, aiop, offset, data) \
84 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
85 #define rp_writeaiop2(ctlp, aiop, offset, data) \
86 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
87 #define rp_writeaiop4(ctlp, aiop, offset, data) \
88 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
89 #define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
90 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
91 #define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
92 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
93 #define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
94 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
96 #define rp_readch1(chp, offset) \
97 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
98 #define rp_readch2(chp, offset) \
99 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
100 #define rp_readch4(chp, offset) \
101 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
102 #define rp_readmultich1(chp, offset, addr, count) \
103 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
104 #define rp_readmultich2(chp, offset, addr, count) \
105 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
106 #define rp_readmultich4(chp, offset, addr, count) \
107 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
108 #define rp_writech1(chp, offset, data) \
109 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
110 #define rp_writech2(chp, offset, data) \
111 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
112 #define rp_writech4(chp, offset, data) \
113 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
114 #define rp_writemultich1(chp, offset, addr, count) \
115 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
116 #define rp_writemultich2(chp, offset, addr, count) \
117 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
118 #define rp_writemultich4(chp, offset, addr, count) \
119 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
122 * End of OS-specific defines
128 #define AIOP_CTL_SIZE 4
129 #define CHAN_AIOP_SIZE 8
130 #define MAX_PORTS_PER_AIOP 8
131 #define MAX_AIOPS_PER_BOARD 4
132 #define MAX_PORTS_PER_BOARD 32
134 /* Controller ID numbers */
135 #define CTLID_NULL -1 /* no controller exists */
136 #define CTLID_0001 0x0001 /* controller release 1 */
138 /* AIOP ID numbers, identifies AIOP type implementing channel */
139 #define AIOPID_NULL -1 /* no AIOP or channel exists */
140 #define AIOPID_0001 0x0001 /* AIOP release 1 */
142 #define NULLDEV -1 /* identifies non-existant device */
143 #define NULLCTL -1 /* identifies non-existant controller */
144 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
145 #define NULLAIOP -1 /* identifies non-existant AIOP */
146 #define NULLCHAN -1 /* identifies non-existant channel */
148 /************************************************************************
149 Global Register Offsets - Direct Access - Fixed values
150 ************************************************************************/
152 #define _CMD_REG 0x38 /* Command Register 8 Write */
153 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
154 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
155 #define _UNUSED 0x3B /* Unused 8 */
156 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
157 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
159 /************************************************************************
160 Channel Register Offsets for 1st channel in AIOP - Direct Access
161 ************************************************************************/
162 #define _TD0 0x00 /* Transmit Data 16 Write */
163 #define _RD0 0x00 /* Receive Data 16 Read */
164 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
165 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
166 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
168 /************************************************************************
169 Tx Control Register Offsets - Indexed - External - Fixed
170 ************************************************************************/
171 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
172 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
173 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
174 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
175 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
176 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
178 /************************************************************************
180 ************************************************************************/
181 #define RXFIFO_DATA 0x5f
182 #define RXFIFO_OUT 0x5c
183 #define RXFIFO_EN 0x08
184 #define RXFIFO_DIS 0xa7
186 /************************************************************************
187 Memory Controller Register Offsets - Indexed - External - Fixed
188 ************************************************************************/
189 #define _RX_FIFO 0x000 /* Rx FIFO */
190 #define _TX_FIFO 0x800 /* Tx FIFO */
191 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
192 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
193 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
194 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
195 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
196 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
198 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
199 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
200 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
202 /************************************************************************
203 Tx Priority Buffer - Indexed - External - Fixed
204 ************************************************************************/
205 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
206 #define TXP_SIZE 0x20 /* 32 bytes */
208 /************************************************************************
209 Channel Register Offsets - Indexed - Internal - Fixed
210 ************************************************************************/
212 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
213 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
214 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
215 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
217 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
243 #define STMBREAK 0x08 /* BREAK */
244 #define STMFRAME 0x04 /* framing error */
245 #define STMRCVROVR 0x02 /* receiver over run error */
246 #define STMPARITY 0x01 /* parity error */
247 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
248 #define STMBREAKH 0x800 /* BREAK */
249 #define STMFRAMEH 0x400 /* framing error */
250 #define STMRCVROVRH 0x200 /* receiver over run error */
251 #define STMPARITYH 0x100 /* parity error */
252 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
254 #define CTS_ACT 0x20 /* CTS input asserted */
255 #define DSR_ACT 0x10 /* DSR input asserted */
256 #define CD_ACT 0x08 /* CD input asserted */
257 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
258 #define TXSHRMT 0x02 /* Tx shift register is empty */
259 #define RDA 0x01 /* Rx data available */
260 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
262 #define STATMODE 0x8000 /* status mode enable bit */
263 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
264 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
265 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
266 #define RXBREAK 0x0400 /* received BREAK */
267 #define RXFRAME 0x0200 /* received framing error */
268 #define RXPARITY 0x0100 /* received parity error */
269 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
271 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
272 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
273 #define TXINT_EN 0x10 /* transmit interrupt enable */
274 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
275 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
276 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
277 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
279 #define SETBREAK 0x10 /* send break condition (must clear) */
280 #define LOCALLOOP 0x08 /* local loopback set for test */
281 #define SET_DTR 0x04 /* assert DTR */
282 #define SET_RTS 0x02 /* assert RTS */
283 #define TX_ENABLE 0x01 /* enable transmitter */
285 #define RTSFC_EN 0x40 /* RTS flow control enable */
286 #define RXPROC_EN 0x20 /* receive processor enable */
287 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
288 #define TRIG_1 0x08 /* trigger level 1 char */
289 #define TRIG_1_2 0x10 /* trigger level 1/2 */
290 #define TRIG_7_8 0x18 /* trigger level 7/8 */
291 #define TRIG_MASK 0x18 /* trigger level mask */
292 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
293 #define RXINT_EN 0x02 /* Rx interrupt enable */
294 #define MCINT_EN 0x01 /* modem change interrupt enable */
296 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
297 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
298 #define SRC_INT 0x08 /* special receive condition interrupt */
299 #define DELTA_CD 0x04 /* CD change interrupt */
300 #define DELTA_CTS 0x02 /* CTS change interrupt */
301 #define DELTA_DSR 0x01 /* DSR change interrupt */
303 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
304 #define IGN2_EN 0x08 /* ignore byte 2 enable */
305 #define IGN1_EN 0x04 /* ignore byte 1 enable */
306 #define COMP2_EN 0x02 /* compare byte 2 enable */
307 #define COMP1_EN 0x01 /* compare byte 1 enable */
309 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
310 #define TXOVERIDE 0x40 /* Transmit software off override */
311 #define RESETUART 0x20 /* reset channel's UART */
312 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
313 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
315 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
316 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
317 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
318 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
320 #define INTR_EN 0x08 /* allow interrupts to host */
321 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
323 #define CHAN3_EN 0x08 /* enable AIOP 3 */
324 #define CHAN2_EN 0x04 /* enable AIOP 2 */
325 #define CHAN1_EN 0x02 /* enable AIOP 1 */
326 #define CHAN0_EN 0x01 /* enable AIOP 0 */
327 #define FREQ_DIS 0x00
328 #define FREQ_274HZ 0x60
329 #define FREQ_137HZ 0x50
330 #define FREQ_69HZ 0x40
331 #define FREQ_34HZ 0x30
332 #define FREQ_17HZ 0x20
333 #define FREQ_9HZ 0x10
334 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
336 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
339 #define RREGDATASIZE 52
349 struct CONTROLLER_str;
352 /* The types of bus-specific methods */
353 typedef int rp_aiop2rid_t(int, int);
354 typedef int rp_aiop2off_t(int, int);
355 typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
357 /* Controller level information structure */
358 struct CONTROLLER_str
362 int AiopID[AIOP_CTL_SIZE];
363 int AiopNumChan[AIOP_CTL_SIZE];
365 /* Device and resource management */
366 device_t dev; /* device */
367 int io_num; /* Number of IO resources */
368 int *io_rid; /* IO resource IDs */
369 struct resource **io; /* IO resources */
371 struct rp_port *rp; /* port */
372 struct tty *tty; /* tty */
374 /* Bus-specific properties */
377 /* Bus-specific methods */
378 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */
379 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */
380 rp_ctlmask_t *ctlmask; /* Int status */
382 typedef struct CONTROLLER_str CONTROLLER_T;
383 typedef CONTROLLER_T CONTROLLER_t;
385 /* Channel level information structure */
401 Byte_t R[RREGDATASIZE];
408 Byte_t TxReplace1[4];
409 Byte_t TxReplace2[4];
412 typedef struct CHANNEL_str CHANNEL_T;
413 typedef CHANNEL_T CHANNEL_t;
414 typedef CHANNEL_T * CHANPTR_T;
416 #define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0)
417 #define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0)
418 #define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0)
419 #define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0)
421 /***************************************************************************
423 Purpose: Stop sending a transmit BREAK signal
425 CHANNEL_T *ChP; Ptr to channel structure
427 #define sClrBreak(ChP) \
429 (ChP)->TxControl[3] &= ~SETBREAK; \
430 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
433 /***************************************************************************
435 Purpose: Clr the DTR output
437 CHANNEL_T *ChP; Ptr to channel structure
439 #define sClrDTR(ChP) \
441 (ChP)->TxControl[3] &= ~SET_DTR; \
442 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
445 /***************************************************************************
447 Purpose: Clr the RTS output
449 CHANNEL_T *ChP; Ptr to channel structure
451 #define sClrRTS(ChP) \
453 (ChP)->TxControl[3] &= ~SET_RTS; \
454 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
457 /***************************************************************************
459 Purpose: Clear any existing transmit software flow control off condition
460 Call: sClrTxXOFF(ChP)
461 CHANNEL_T *ChP; Ptr to channel structure
463 #define sClrTxXOFF(ChP) \
465 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
466 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
469 /***************************************************************************
470 Function: sDisCTSFlowCtl
471 Purpose: Disable output flow control using CTS
472 Call: sDisCTSFlowCtl(ChP)
473 CHANNEL_T *ChP; Ptr to channel structure
475 #define sDisCTSFlowCtl(ChP) \
477 (ChP)->TxControl[2] &= ~CTSFC_EN; \
478 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
481 /***************************************************************************
483 Purpose: Disable parity
484 Call: sDisParity(ChP)
485 CHANNEL_T *ChP; Ptr to channel structure
486 Comments: Function sSetParity() can be used in place of functions sEnParity(),
487 sDisParity(), sSetOddParity(), and sSetEvenParity().
489 #define sDisParity(ChP) \
491 (ChP)->TxControl[2] &= ~PARITY_EN; \
492 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
495 /***************************************************************************
497 Purpose: Disable Rx FIFO
498 Call: sDisRxFIFO(ChP)
499 CHANNEL_T *ChP; Ptr to channel structure
501 #define sDisRxFIFO(ChP) \
503 (ChP)->R[0x32] = 0x0a; \
504 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
507 /***************************************************************************
508 Function: sDisRxStatusMode
509 Purpose: Disable the Rx status mode
510 Call: sDisRxStatusMode(ChP)
511 CHANNEL_T *ChP; Ptr to channel structure
512 Comments: This takes the channel out of the receive status mode. All
513 subsequent reads of receive data using sReadRxWord() will return
516 #define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
518 /***************************************************************************
519 Function: sDisTransmit
520 Purpose: Disable transmit
521 Call: sDisTransmit(ChP)
522 CHANNEL_T *ChP; Ptr to channel structure
523 This disables movement of Tx data from the Tx FIFO into the 1 byte
524 Tx buffer. Therefore there could be up to a 2 byte latency
525 between the time sDisTransmit() is called and the transmit buffer
526 and transmit shift register going completely empty.
528 #define sDisTransmit(ChP) \
530 (ChP)->TxControl[3] &= ~TX_ENABLE; \
531 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
534 /***************************************************************************
535 Function: sDisTxSoftFlowCtl
536 Purpose: Disable Tx Software Flow Control
537 Call: sDisTxSoftFlowCtl(ChP)
538 CHANNEL_T *ChP; Ptr to channel structure
540 #define sDisTxSoftFlowCtl(ChP) \
542 (ChP)->R[0x06] = 0x8a; \
543 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x04]); \
546 /***************************************************************************
547 Function: sEnCTSFlowCtl
548 Purpose: Enable output flow control using CTS
549 Call: sEnCTSFlowCtl(ChP)
550 CHANNEL_T *ChP; Ptr to channel structure
552 #define sEnCTSFlowCtl(ChP) \
554 (ChP)->TxControl[2] |= CTSFC_EN; \
555 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
558 /***************************************************************************
560 Purpose: Enable parity
562 CHANNEL_T *ChP; Ptr to channel structure
563 Comments: Function sSetParity() can be used in place of functions sEnParity(),
564 sDisParity(), sSetOddParity(), and sSetEvenParity().
566 Warnings: Before enabling parity odd or even parity should be chosen using
567 functions sSetOddParity() or sSetEvenParity().
569 #define sEnParity(ChP) \
571 (ChP)->TxControl[2] |= PARITY_EN; \
572 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
575 /***************************************************************************
576 Function: sEnRTSFlowCtl
579 #define sEnRTSFlowCtl(ChP) \
581 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
582 (ChP)->TxControl[3] &= ~SET_RTS; \
583 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
584 (ChP)->RxControl[2] |= RTSFC_EN; \
585 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
588 /***************************************************************************
589 Function: sDisRTSFlowCtl
592 #define sDisRTSFlowCtl(ChP) \
594 (ChP)->RxControl[2] &= ~RTSFC_EN; \
595 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
598 /***************************************************************************
600 Purpose: Enable Rx FIFO
602 CHANNEL_T *ChP; Ptr to channel structure
604 #define sEnRxFIFO(ChP) \
606 (ChP)->R[0x32] = 0x08; \
607 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
610 /***************************************************************************
611 Function: sEnRxProcessor
612 Purpose: Enable the receive processor
613 Call: sEnRxProcessor(ChP)
614 CHANNEL_T *ChP; Ptr to channel structure
615 Comments: This function is used to start the receive processor. When
616 the channel is in the reset state the receive processor is not
617 running. This is done to prevent the receive processor from
618 executing invalid microcode instructions prior to the
619 downloading of the microcode.
621 Warnings: This function must be called after valid microcode has been
622 downloaded to the AIOP, and it must not be called before the
623 microcode has been downloaded.
625 #define sEnRxProcessor(ChP) \
627 (ChP)->RxControl[2] |= RXPROC_EN; \
628 rp_writech2(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
631 /***************************************************************************
632 Function: sEnRxStatusMode
633 Purpose: Enable the Rx status mode
634 Call: sEnRxStatusMode(ChP)
635 CHANNEL_T *ChP; Ptr to channel structure
636 Comments: This places the channel in the receive status mode. All subsequent
637 reads of receive data using sReadRxWord() will return a data byte
638 in the low word and a status byte in the high word.
641 #define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
643 /***************************************************************************
644 Function: sEnTransmit
645 Purpose: Enable transmit
646 Call: sEnTransmit(ChP)
647 CHANNEL_T *ChP; Ptr to channel structure
649 #define sEnTransmit(ChP) \
651 (ChP)->TxControl[3] |= TX_ENABLE; \
652 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
655 /***************************************************************************
656 Function: sGetAiopIntStatus
657 Purpose: Get the AIOP interrupt status
658 Call: sGetAiopIntStatus(CtlP,AiopNum)
659 CONTROLLER_T *CtlP; Ptr to controller structure
660 int AiopNum; AIOP number
661 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
662 represent channels 0 through 7 respectively. If a
663 bit is set that channel is interrupting.
665 #define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
667 /***************************************************************************
668 Function: sGetAiopNumChan
669 Purpose: Get the number of channels supported by an AIOP
670 Call: sGetAiopNumChan(CtlP,AiopNum)
671 CONTROLLER_T *CtlP; Ptr to controller structure
672 int AiopNum; AIOP number
673 Return: int: The number of channels supported by the AIOP
675 #define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
677 /***************************************************************************
678 Function: sGetChanIntID
679 Purpose: Get a channel's interrupt identification byte
680 Call: sGetChanIntID(ChP)
681 CHANNEL_T *ChP; Ptr to channel structure
682 Return: Byte_t: The channel interrupt ID. Can be any
683 combination of the following flags:
684 RXF_TRIG: Rx FIFO trigger level interrupt
685 TXFIFO_MT: Tx FIFO empty interrupt
686 SRC_INT: Special receive condition interrupt
687 DELTA_CD: CD change interrupt
688 DELTA_CTS: CTS change interrupt
689 DELTA_DSR: DSR change interrupt
691 #define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
693 /***************************************************************************
694 Function: sGetChanNum
695 Purpose: Get the number of a channel within an AIOP
696 Call: sGetChanNum(ChP)
697 CHANNEL_T *ChP; Ptr to channel structure
698 Return: int: Channel number within AIOP, or NULLCHAN if channel does
701 #define sGetChanNum(ChP) (ChP)->ChanNum
703 /***************************************************************************
704 Function: sGetChanStatus
705 Purpose: Get the channel status
706 Call: sGetChanStatus(ChP)
707 CHANNEL_T *ChP; Ptr to channel structure
708 Return: Word_t: The channel status. Can be any combination of
711 CTS_ACT: CTS input asserted
712 DSR_ACT: DSR input asserted
713 CD_ACT: CD input asserted
714 TXFIFOMT: Tx FIFO is empty
715 TXSHRMT: Tx shift register is empty
716 RDA: Rx data available
719 STATMODE: status mode enable bit
720 RXFOVERFL: receive FIFO overflow
721 RX2MATCH: receive compare byte 2 match
722 RX1MATCH: receive compare byte 1 match
723 RXBREAK: received BREAK
724 RXFRAME: received framing error
725 RXPARITY: received parity error
726 Warnings: This function will clear the high byte flags in the Channel
729 #define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
731 /***************************************************************************
732 Function: sGetChanStatusLo
733 Purpose: Get the low byte only of the channel status
734 Call: sGetChanStatusLo(ChP)
735 CHANNEL_T *ChP; Ptr to channel structure
736 Return: Byte_t: The channel status low byte. Can be any combination
737 of the following flags:
738 CTS_ACT: CTS input asserted
739 DSR_ACT: DSR input asserted
740 CD_ACT: CD input asserted
741 TXFIFOMT: Tx FIFO is empty
742 TXSHRMT: Tx shift register is empty
743 RDA: Rx data available
745 #define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
747 /***************************************************************************
749 Purpose: Get the number of data bytes in the Rx FIFO
751 CHANNEL_T *ChP; Ptr to channel structure
752 Return: int: The number of data bytes in the Rx FIFO.
753 Comments: Byte read of count register is required to obtain Rx count.
756 #define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
758 /***************************************************************************
760 Purpose: Get the number of data bytes in the Tx FIFO
762 CHANNEL_T *ChP; Ptr to channel structure
763 Return: Byte_t: The number of data bytes in the Tx FIFO.
764 Comments: Byte read of count register is required to obtain Tx count.
767 #define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
769 /*****************************************************************************
770 Function: sGetTxRxDataIO
771 Purpose: Get the offset of a channel's TxRx Data register
772 Call: sGetTxRxDataIO(ChP)
773 CHANNEL_T *ChP; Ptr to channel structure
774 Return: WordIO_t: offset of a channel's TxRx Data register
776 #define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
778 /***************************************************************************
779 Function: sInitChanDefaults
780 Purpose: Initialize a channel structure to its default state.
781 Call: sInitChanDefaults(ChP)
782 CHANNEL_T *ChP; Ptr to the channel structure
783 Comments: This function must be called once for every channel structure
784 that exists before any other SSCI calls can be made.
787 #define sInitChanDefaults(ChP) \
789 (ChP)->CtlP = NULLCTLPTR; \
790 (ChP)->AiopNum = NULLAIOP; \
791 (ChP)->ChanID = AIOPID_NULL; \
792 (ChP)->ChanNum = NULLCHAN; \
795 /***************************************************************************
796 Function: sResetAiopByNum
797 Purpose: Reset the AIOP by number
798 Call: sResetAiopByNum(CTLP,AIOPNUM)
799 CONTROLLER_T CTLP; Ptr to controller structure
802 #define sResetAiopByNum(CTLP,AIOPNUM) \
804 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
805 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
808 /***************************************************************************
810 Purpose: Send a transmit BREAK signal
811 Call: sSendBreak(ChP)
812 CHANNEL_T *ChP; Ptr to channel structure
814 #define sSendBreak(ChP) \
816 (ChP)->TxControl[3] |= SETBREAK; \
817 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
820 /***************************************************************************
822 Purpose: Set baud rate
823 Call: sSetBaud(ChP,Divisor)
824 CHANNEL_T *ChP; Ptr to channel structure
825 Word_t Divisor; 16 bit baud rate divisor for channel
827 #define sSetBaud(ChP,DIVISOR) \
829 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
830 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
831 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->BaudDiv[0]); \
834 /***************************************************************************
836 Purpose: Set data bits to 7
838 CHANNEL_T *ChP; Ptr to channel structure
840 #define sSetData7(ChP) \
842 (ChP)->TxControl[2] &= ~DATA8BIT; \
843 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
846 /***************************************************************************
848 Purpose: Set data bits to 8
850 CHANNEL_T *ChP; Ptr to channel structure
852 #define sSetData8(ChP) \
854 (ChP)->TxControl[2] |= DATA8BIT; \
855 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
858 /***************************************************************************
860 Purpose: Set the DTR output
862 CHANNEL_T *ChP; Ptr to channel structure
864 #define sSetDTR(ChP) \
866 (ChP)->TxControl[3] |= SET_DTR; \
867 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
870 /***************************************************************************
871 Function: sSetEvenParity
872 Purpose: Set even parity
873 Call: sSetEvenParity(ChP)
874 CHANNEL_T *ChP; Ptr to channel structure
875 Comments: Function sSetParity() can be used in place of functions sEnParity(),
876 sDisParity(), sSetOddParity(), and sSetEvenParity().
878 Warnings: This function has no effect unless parity is enabled with function
881 #define sSetEvenParity(ChP) \
883 (ChP)->TxControl[2] |= EVEN_PAR; \
884 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
887 /***************************************************************************
888 Function: sSetOddParity
889 Purpose: Set odd parity
890 Call: sSetOddParity(ChP)
891 CHANNEL_T *ChP; Ptr to channel structure
892 Comments: Function sSetParity() can be used in place of functions sEnParity(),
893 sDisParity(), sSetOddParity(), and sSetEvenParity().
895 Warnings: This function has no effect unless parity is enabled with function
898 #define sSetOddParity(ChP) \
900 (ChP)->TxControl[2] &= ~EVEN_PAR; \
901 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
904 /***************************************************************************
906 Purpose: Set the RTS output
908 CHANNEL_T *ChP; Ptr to channel structure
910 #define sSetRTS(ChP) \
912 (ChP)->TxControl[3] |= SET_RTS; \
913 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
916 /***************************************************************************
917 Function: sSetRxTrigger
918 Purpose: Set the Rx FIFO trigger level
919 Call: sSetRxProcessor(ChP,Level)
920 CHANNEL_T *ChP; Ptr to channel structure
921 Byte_t Level; Number of characters in Rx FIFO at which the
922 interrupt will be generated. Can be any of the following flags:
925 TRIG_1: 1 character in FIFO
926 TRIG_1_2: FIFO 1/2 full
927 TRIG_7_8: FIFO 7/8 full
928 Comments: An interrupt will be generated when the trigger level is reached
929 only if function sEnInterrupt() has been called with flag
930 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
931 register will be set whenever the trigger level is reached
932 regardless of the setting of RXINT_EN.
935 #define sSetRxTrigger(ChP,LEVEL) \
937 (ChP)->RxControl[2] &= ~TRIG_MASK; \
938 (ChP)->RxControl[2] |= LEVEL; \
939 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
942 /***************************************************************************
944 Purpose: Set stop bits to 1
946 CHANNEL_T *ChP; Ptr to channel structure
948 #define sSetStop1(ChP) \
950 (ChP)->TxControl[2] &= ~STOP2; \
951 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
954 /***************************************************************************
956 Purpose: Set stop bits to 2
958 CHANNEL_T *ChP; Ptr to channel structure
960 #define sSetStop2(ChP) \
962 (ChP)->TxControl[2] |= STOP2; \
963 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
966 /***************************************************************************
967 Function: sStartRxProcessor
968 Purpose: Start a channel's receive processor
969 Call: sStartRxProcessor(ChP)
970 CHANNEL_T *ChP; Ptr to channel structure
971 Comments: This function is used to start a Rx processor after it was
972 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
973 will restart both the Rx processor and software input flow control.
976 #define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0])
978 /***************************************************************************
979 Function: sWriteTxByte
980 Purpose: Write a transmit data byte to a channel.
981 CHANNEL_T *ChP; Ptr to channel structure
982 ByteIO_t io: Channel transmit register I/O address. This can
983 be obtained with sGetTxRxDataIO().
984 Byte_t Data; The transmit data byte.
985 Warnings: This function writes the data byte without checking to see if
986 sMaxTxSize is exceeded in the Tx FIFO.
988 #define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
990 int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
991 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
992 int sInitChan( CONTROLLER_T *CtlP,
996 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
997 void sStopRxProcessor(CHANNEL_T *ChP);
998 void sStopSWInFlowCtl(CHANNEL_T *ChP);
999 void sFlushRxFIFO(CHANNEL_T *ChP);
1000 void sFlushTxFIFO(CHANNEL_T *ChP);
1001 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1002 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1003 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1004 int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
1005 void rp_releaseresource(CONTROLLER_t *ctlp);
1008 extern Byte_t R[RDATASIZE];
1009 extern CONTROLLER_T sController[CTL_SIZE];
1010 extern Byte_t sIRQMap[16];
1012 extern Byte_t rp_sBitMapClrTbl[8];
1013 extern Byte_t rp_sBitMapSetTbl[8];