1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_crtc_helper.h>
42 static struct drm_driver driver;
44 #define GEN_DEFAULT_PIPEOFFSETS \
45 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
46 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
47 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
48 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
49 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51 #define GEN_CHV_PIPEOFFSETS \
52 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
53 CHV_PIPE_C_OFFSET }, \
54 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
55 CHV_TRANSCODER_C_OFFSET, }, \
56 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
57 CHV_PALETTE_C_OFFSET }
59 #define CURSOR_OFFSETS \
60 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62 #define IVB_CURSOR_OFFSETS \
63 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
68 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
70 static const struct intel_device_info intel_i830_info = {
71 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
72 .has_overlay = 1, .overlay_needs_physical = 1,
73 .ring_mask = RENDER_RING,
74 GEN_DEFAULT_PIPEOFFSETS,
78 static const struct intel_device_info intel_845g_info = {
79 .gen = 2, .num_pipes = 1,
80 .has_overlay = 1, .overlay_needs_physical = 1,
81 .ring_mask = RENDER_RING,
82 GEN_DEFAULT_PIPEOFFSETS,
86 static const struct intel_device_info intel_i85x_info = {
87 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
88 .cursor_needs_physical = 1,
89 .has_overlay = 1, .overlay_needs_physical = 1,
91 .ring_mask = RENDER_RING,
92 GEN_DEFAULT_PIPEOFFSETS,
96 static const struct intel_device_info intel_i865g_info = {
97 .gen = 2, .num_pipes = 1,
98 .has_overlay = 1, .overlay_needs_physical = 1,
99 .ring_mask = RENDER_RING,
100 GEN_DEFAULT_PIPEOFFSETS,
104 static const struct intel_device_info intel_i915g_info = {
105 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
106 .has_overlay = 1, .overlay_needs_physical = 1,
107 .ring_mask = RENDER_RING,
108 GEN_DEFAULT_PIPEOFFSETS,
111 static const struct intel_device_info intel_i915gm_info = {
112 .gen = 3, .is_mobile = 1, .num_pipes = 2,
113 .cursor_needs_physical = 1,
114 .has_overlay = 1, .overlay_needs_physical = 1,
117 .ring_mask = RENDER_RING,
118 GEN_DEFAULT_PIPEOFFSETS,
121 static const struct intel_device_info intel_i945g_info = {
122 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
123 .has_overlay = 1, .overlay_needs_physical = 1,
124 .ring_mask = RENDER_RING,
125 GEN_DEFAULT_PIPEOFFSETS,
128 static const struct intel_device_info intel_i945gm_info = {
129 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
130 .has_hotplug = 1, .cursor_needs_physical = 1,
131 .has_overlay = 1, .overlay_needs_physical = 1,
134 .ring_mask = RENDER_RING,
135 GEN_DEFAULT_PIPEOFFSETS,
139 static const struct intel_device_info intel_i965g_info = {
140 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
143 .ring_mask = RENDER_RING,
144 GEN_DEFAULT_PIPEOFFSETS,
148 static const struct intel_device_info intel_i965gm_info = {
149 .gen = 4, .is_crestline = 1, .num_pipes = 2,
150 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
153 .ring_mask = RENDER_RING,
154 GEN_DEFAULT_PIPEOFFSETS,
158 static const struct intel_device_info intel_g33_info = {
159 .gen = 3, .is_g33 = 1, .num_pipes = 2,
160 .need_gfx_hws = 1, .has_hotplug = 1,
162 .ring_mask = RENDER_RING,
163 GEN_DEFAULT_PIPEOFFSETS,
167 static const struct intel_device_info intel_g45_info = {
168 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
169 .has_pipe_cxsr = 1, .has_hotplug = 1,
170 .ring_mask = RENDER_RING | BSD_RING,
171 GEN_DEFAULT_PIPEOFFSETS,
175 static const struct intel_device_info intel_gm45_info = {
176 .gen = 4, .is_g4x = 1, .num_pipes = 2,
177 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
178 .has_pipe_cxsr = 1, .has_hotplug = 1,
180 .ring_mask = RENDER_RING | BSD_RING,
181 GEN_DEFAULT_PIPEOFFSETS,
185 static const struct intel_device_info intel_pineview_info = {
186 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
187 .need_gfx_hws = 1, .has_hotplug = 1,
189 GEN_DEFAULT_PIPEOFFSETS,
193 static const struct intel_device_info intel_ironlake_d_info = {
194 .gen = 5, .num_pipes = 2,
195 .need_gfx_hws = 1, .has_hotplug = 1,
196 .ring_mask = RENDER_RING | BSD_RING,
197 GEN_DEFAULT_PIPEOFFSETS,
201 static const struct intel_device_info intel_ironlake_m_info = {
202 .gen = 5, .is_mobile = 1, .num_pipes = 2,
203 .need_gfx_hws = 1, .has_hotplug = 1,
205 .ring_mask = RENDER_RING | BSD_RING,
206 GEN_DEFAULT_PIPEOFFSETS,
210 static const struct intel_device_info intel_sandybridge_d_info = {
211 .gen = 6, .num_pipes = 2,
212 .need_gfx_hws = 1, .has_hotplug = 1,
214 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
216 GEN_DEFAULT_PIPEOFFSETS,
220 static const struct intel_device_info intel_sandybridge_m_info = {
221 .gen = 6, .is_mobile = 1, .num_pipes = 2,
222 .need_gfx_hws = 1, .has_hotplug = 1,
224 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
226 GEN_DEFAULT_PIPEOFFSETS,
230 #define GEN7_FEATURES \
231 .gen = 7, .num_pipes = 3, \
232 .need_gfx_hws = 1, .has_hotplug = 1, \
234 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
236 GEN_DEFAULT_PIPEOFFSETS, \
239 static const struct intel_device_info intel_ivybridge_d_info = {
244 static const struct intel_device_info intel_ivybridge_m_info = {
250 static const struct intel_device_info intel_ivybridge_q_info = {
253 .num_pipes = 0, /* legal, last one wins */
256 #define VLV_FEATURES \
257 .gen = 7, .num_pipes = 2, \
258 .need_gfx_hws = 1, .has_hotplug = 1, \
259 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
260 .display_mmio_offset = VLV_DISPLAY_BASE, \
261 GEN_DEFAULT_PIPEOFFSETS, \
264 static const struct intel_device_info intel_valleyview_m_info = {
270 static const struct intel_device_info intel_valleyview_d_info = {
275 #define HSW_FEATURES \
277 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
281 static const struct intel_device_info intel_haswell_d_info = {
286 static const struct intel_device_info intel_haswell_m_info = {
292 #define BDW_FEATURES \
296 static const struct intel_device_info intel_broadwell_d_info = {
301 static const struct intel_device_info intel_broadwell_m_info = {
303 .gen = 8, .is_mobile = 1,
306 static const struct intel_device_info intel_broadwell_gt3d_info = {
309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
312 static const struct intel_device_info intel_broadwell_gt3m_info = {
314 .gen = 8, .is_mobile = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
318 static const struct intel_device_info intel_cherryview_info = {
319 .gen = 8, .num_pipes = 3,
320 .need_gfx_hws = 1, .has_hotplug = 1,
321 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
323 .display_mmio_offset = VLV_DISPLAY_BASE,
329 static const struct intel_device_info intel_skylake_info = {
335 static const struct intel_device_info intel_skylake_gt3_info = {
339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
342 static const struct intel_device_info intel_broxton_info = {
346 .need_gfx_hws = 1, .has_hotplug = 1,
347 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 GEN_DEFAULT_PIPEOFFSETS,
357 static const struct intel_device_info intel_kabylake_info = {
363 static const struct intel_device_info intel_kabylake_gt3_info = {
367 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
370 static const struct intel_device_info intel_coffeelake_gt1_info = {
376 static const struct intel_device_info intel_coffeelake_gt2_info = {
382 static const struct intel_device_info intel_coffeelake_gt3_info = {
386 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
390 * Make sure any device matches here are from most specific to most
391 * general. For example, since the Quanta match is based on the subsystem
392 * and subvendor IDs, we need it to come before the more general IVB
393 * PCI ID matches, otherwise we'll use the wrong info struct above.
396 static const struct pci_device_id pciidlist[] = {
397 INTEL_I830_IDS(&intel_i830_info),
398 INTEL_I845G_IDS(&intel_845g_info),
399 INTEL_I85X_IDS(&intel_i85x_info),
400 INTEL_I865G_IDS(&intel_i865g_info),
401 INTEL_I915G_IDS(&intel_i915g_info),
402 INTEL_I915GM_IDS(&intel_i915gm_info),
403 INTEL_I945G_IDS(&intel_i945g_info),
404 INTEL_I945GM_IDS(&intel_i945gm_info),
405 INTEL_I965G_IDS(&intel_i965g_info),
406 INTEL_G33_IDS(&intel_g33_info),
407 INTEL_I965GM_IDS(&intel_i965gm_info),
408 INTEL_GM45_IDS(&intel_gm45_info),
409 INTEL_G45_IDS(&intel_g45_info),
410 INTEL_PINEVIEW_IDS(&intel_pineview_info),
411 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
412 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
413 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
414 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
415 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
416 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
417 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
418 INTEL_HSW_D_IDS(&intel_haswell_d_info),
419 INTEL_HSW_M_IDS(&intel_haswell_m_info),
420 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
421 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
422 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
423 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
424 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
425 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
426 INTEL_CHV_IDS(&intel_cherryview_info),
427 INTEL_SKL_GT1_IDS(&intel_skylake_info),
428 INTEL_SKL_GT2_IDS(&intel_skylake_info),
429 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
430 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
431 INTEL_BXT_IDS(&intel_broxton_info),
432 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
433 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
434 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
435 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
436 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
437 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
438 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
439 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
440 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
441 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
442 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
443 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
447 #define PCI_VENDOR_INTEL 0x8086
449 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
451 enum intel_pch ret = PCH_NOP;
454 * In a virtualized passthrough environment we can be in a
455 * setup where the ISA bridge is not able to be passed through.
456 * In this case, a south bridge can be emulated and we have to
457 * make an educated guess as to which PCH is really there.
462 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
463 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
465 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
466 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
468 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
469 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
471 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
477 void intel_detect_pch(struct drm_device *dev)
479 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct pci_devinfo *di;
483 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
484 * (which really amounts to a PCH but no South Display).
486 if (INTEL_INFO(dev)->num_pipes == 0) {
487 dev_priv->pch_type = PCH_NOP;
491 /* XXX The ISA bridge probe causes some old Core2 machines to hang */
492 if (INTEL_INFO(dev)->gen < 5)
496 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
497 * make graphics device passthrough work easy for VMM, that only
498 * need to expose ISA bridge to let driver know the real hardware
499 * underneath. This is a requirement from virtualization team.
501 * In some virtualized environments (e.g. XEN), there is irrelevant
502 * ISA bridge in the system. To work reliably, we should scan trhough
503 * all the ISA bridge devices and check for the first match, instead
504 * of only checking the first one.
508 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) {
509 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
510 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
511 dev_priv->pch_id = id;
513 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
514 dev_priv->pch_type = PCH_IBX;
515 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
516 WARN_ON(!IS_GEN5(dev));
517 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
518 dev_priv->pch_type = PCH_CPT;
519 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
520 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
521 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
522 /* PantherPoint is CPT compatible */
523 dev_priv->pch_type = PCH_CPT;
524 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
525 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
526 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
527 dev_priv->pch_type = PCH_LPT;
528 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
529 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
530 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
531 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
532 dev_priv->pch_type = PCH_LPT;
533 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
534 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
535 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
536 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
537 dev_priv->pch_type = PCH_SPT;
538 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
539 WARN_ON(!IS_SKYLAKE(dev) &&
541 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
542 dev_priv->pch_type = PCH_SPT;
543 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
544 WARN_ON(!IS_SKYLAKE(dev) &&
546 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
547 dev_priv->pch_type = PCH_KBP;
548 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
549 WARN_ON(!IS_KABYLAKE(dev));
550 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
551 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
552 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
554 dev_priv->pch_type = intel_virt_detect_pch(dev);
562 DRM_DEBUG_KMS("No PCH found.\n");
569 bool i915_semaphore_is_enabled(struct drm_device *dev)
571 if (INTEL_INFO(dev)->gen < 6)
574 if (i915.semaphores >= 0)
575 return i915.semaphores;
577 /* TODO: make semaphores and Execlists play nicely together */
578 if (i915.enable_execlists)
581 /* Until we get further testing... */
585 #ifdef CONFIG_INTEL_IOMMU
586 /* Enable semaphores on SNB when IO remapping is off */
587 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
595 #define IS_BUILTIN(blah) 0
598 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
600 struct drm_device *dev = dev_priv->dev;
601 struct intel_encoder *encoder;
603 drm_modeset_lock_all(dev);
604 for_each_intel_encoder(dev, encoder)
605 if (encoder->suspend)
606 encoder->suspend(encoder);
607 drm_modeset_unlock_all(dev);
610 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
612 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
614 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
616 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
617 if (acpi_target_system_state() < ACPI_STATE_S3)
623 static int i915_drm_suspend(struct drm_device *dev)
625 struct drm_i915_private *dev_priv = dev->dev_private;
626 pci_power_t opregion_target_state;
629 /* ignore lid events during suspend */
630 mutex_lock(&dev_priv->modeset_restore_lock);
631 dev_priv->modeset_restore = MODESET_SUSPENDED;
632 mutex_unlock(&dev_priv->modeset_restore_lock);
634 disable_rpm_wakeref_asserts(dev_priv);
636 /* We do a lot of poking in a lot of registers, make sure they work
638 intel_display_set_init_power(dev_priv, true);
640 drm_kms_helper_poll_disable(dev);
643 pci_save_state(dev->pdev);
646 error = i915_gem_suspend(dev);
649 "GEM idle failed, resume might fail\n");
653 intel_guc_suspend(dev);
655 intel_suspend_gt_powersave(dev);
657 intel_display_suspend(dev);
660 intel_dp_mst_suspend(dev);
663 intel_runtime_pm_disable_interrupts(dev_priv);
664 intel_hpd_cancel_work(dev_priv);
666 intel_suspend_encoders(dev_priv);
668 intel_suspend_hw(dev);
670 i915_gem_suspend_gtt_mappings(dev);
672 i915_save_state(dev);
674 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
675 intel_opregion_notify_adapter(dev, opregion_target_state);
677 intel_uncore_forcewake_reset(dev, false);
678 intel_opregion_fini(dev);
681 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
684 dev_priv->suspend_count++;
686 intel_display_set_init_power(dev_priv, false);
688 intel_csr_ucode_suspend(dev_priv);
691 enable_rpm_wakeref_asserts(dev_priv);
696 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
698 struct drm_i915_private *dev_priv = drm_dev->dev_private;
702 disable_rpm_wakeref_asserts(dev_priv);
704 fw_csr = !IS_BROXTON(dev_priv) &&
705 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
707 * In case of firmware assisted context save/restore don't manually
708 * deinit the power domains. This also means the CSR/DMC firmware will
709 * stay active, it will power down any HW resources as required and
710 * also enable deeper system power states that would be blocked if the
711 * firmware was inactive.
714 intel_power_domains_suspend(dev_priv);
717 if (IS_BROXTON(dev_priv))
718 bxt_enable_dc9(dev_priv);
719 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
720 hsw_enable_pc8(dev_priv);
721 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
722 ret = vlv_suspend_complete(dev_priv);
725 DRM_ERROR("Suspend complete failed: %d\n", ret);
727 intel_power_domains_init_hw(dev_priv, true);
733 pci_disable_device(drm_dev->pdev);
735 * During hibernation on some platforms the BIOS may try to access
736 * the device even though it's already in D3 and hang the machine. So
737 * leave the device in D0 on those platforms and hope the BIOS will
738 * power down the device properly. The issue was seen on multiple old
739 * GENs with different BIOS vendors, so having an explicit blacklist
740 * is inpractical; apply the workaround on everything pre GEN6. The
741 * platforms where the issue was seen:
742 * Lenovo Thinkpad X301, X61s, X60, T60, X41
746 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
747 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
750 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
753 enable_rpm_wakeref_asserts(dev_priv);
758 int i915_suspend_switcheroo(device_t kdev)
760 struct drm_device *dev = device_get_softc(kdev);
763 if (!dev || !dev->dev_private) {
764 DRM_ERROR("dev: %p\n", dev);
765 DRM_ERROR("DRM not initialized, aborting suspend.\n");
770 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
771 state.event != PM_EVENT_FREEZE))
775 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
778 error = i915_drm_suspend(dev);
782 return i915_drm_suspend_late(dev, false);
785 static int i915_drm_resume(struct drm_device *dev)
787 struct drm_i915_private *dev_priv = dev->dev_private;
790 disable_rpm_wakeref_asserts(dev_priv);
792 ret = i915_ggtt_enable_hw(dev);
794 DRM_ERROR("failed to re-enable GGTT\n");
796 intel_csr_ucode_resume(dev_priv);
798 mutex_lock(&dev->struct_mutex);
799 i915_gem_restore_gtt_mappings(dev);
800 mutex_unlock(&dev->struct_mutex);
802 i915_restore_state(dev);
803 intel_opregion_setup(dev);
805 intel_init_pch_refclk(dev);
806 drm_mode_config_reset(dev);
809 * Interrupts have to be enabled before any batches are run. If not the
810 * GPU will hang. i915_gem_init_hw() will initiate batches to
811 * update/restore the context.
813 * Modeset enabling in intel_modeset_init_hw() also needs working
816 intel_runtime_pm_enable_interrupts(dev_priv);
818 mutex_lock(&dev->struct_mutex);
819 if (i915_gem_init_hw(dev)) {
820 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
821 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
823 mutex_unlock(&dev->struct_mutex);
825 intel_guc_resume(dev);
827 intel_modeset_init_hw(dev);
829 spin_lock_irq(&dev_priv->irq_lock);
830 if (dev_priv->display.hpd_irq_setup)
831 dev_priv->display.hpd_irq_setup(dev);
832 spin_unlock_irq(&dev_priv->irq_lock);
834 intel_dp_mst_resume(dev);
836 intel_display_resume(dev);
839 * ... but also need to make sure that hotplug processing
840 * doesn't cause havoc. Like in the driver load code we don't
841 * bother with the tiny race here where we might loose hotplug
844 intel_hpd_init(dev_priv);
845 /* Config may have changed between suspend and resume */
846 drm_helper_hpd_irq_event(dev);
848 intel_opregion_init(dev);
850 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
852 mutex_lock(&dev_priv->modeset_restore_lock);
853 dev_priv->modeset_restore = MODESET_DONE;
854 mutex_unlock(&dev_priv->modeset_restore_lock);
857 intel_opregion_notify_adapter(dev, PCI_D0);
860 drm_kms_helper_poll_enable(dev);
862 enable_rpm_wakeref_asserts(dev_priv);
867 static int i915_drm_resume_early(struct drm_device *dev)
869 struct drm_i915_private *dev_priv = dev->dev_private;
873 * We have a resume ordering issue with the snd-hda driver also
874 * requiring our device to be power up. Due to the lack of a
875 * parent/child relationship we currently solve this with an early
878 * FIXME: This should be solved with a special hdmi sink device or
879 * similar so that power domains can be employed.
883 * Note that we need to set the power state explicitly, since we
884 * powered off the device during freeze and the PCI core won't power
885 * it back up for us during thaw. Powering off the device during
886 * freeze is not a hard requirement though, and during the
887 * suspend/resume phases the PCI core makes sure we get here with the
888 * device powered on. So in case we change our freeze logic and keep
889 * the device powered we can also remove the following set power state
893 ret = pci_set_power_state(dev->pdev, PCI_D0);
895 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
900 * Note that pci_enable_device() first enables any parent bridge
901 * device and only then sets the power state for this device. The
902 * bridge enabling is a nop though, since bridge devices are resumed
903 * first. The order of enabling power and enabling the device is
904 * imposed by the PCI core as described above, so here we preserve the
905 * same order for the freeze/thaw phases.
907 * TODO: eventually we should remove pci_disable_device() /
908 * pci_enable_enable_device() from suspend/resume. Due to how they
909 * depend on the device enable refcount we can't anyway depend on them
910 * disabling/enabling the device.
912 if (pci_enable_device(dev->pdev)) {
917 pci_set_master(dev->pdev);
920 disable_rpm_wakeref_asserts(dev_priv);
922 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
923 ret = vlv_resume_prepare(dev_priv, false);
925 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
928 intel_uncore_early_sanitize(dev, true);
930 if (IS_BROXTON(dev)) {
931 if (!dev_priv->suspended_to_idle)
932 gen9_sanitize_dc_state(dev_priv);
933 bxt_disable_dc9(dev_priv);
934 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
935 hsw_disable_pc8(dev_priv);
938 intel_uncore_sanitize(dev);
940 if (IS_BROXTON(dev_priv) ||
941 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
942 intel_power_domains_init_hw(dev_priv, true);
944 enable_rpm_wakeref_asserts(dev_priv);
949 dev_priv->suspended_to_idle = false;
954 int i915_resume_switcheroo(struct drm_device *dev)
958 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
961 ret = i915_drm_resume_early(dev);
965 return i915_drm_resume(dev);
968 /* XXX Hack for the old *BSD drm code base
969 * The device id field is set at probe time */
970 static drm_pci_id_list_t i915_attach_list[] = {
971 {0x8086, 0, 0, "Intel i915 GPU"},
975 struct intel_device_info *
976 i915_get_device_id(int device)
978 const struct pci_device_id *did;
980 for (did = &pciidlist[0]; did->device != 0; did++) {
981 if (did->device != device)
983 return (struct intel_device_info *)did->driver_data;
988 static int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
989 struct sysctl_oid *top)
991 return drm_add_busid_modesetting(dev, ctx, top);
994 extern devclass_t drm_devclass;
997 * i915_reset - reset chip after a hang
998 * @dev: drm device to reset
1000 * Reset the chip. Useful if a hang is detected. Returns zero on successful
1001 * reset or otherwise an error code.
1003 * Procedure is fairly simple:
1004 * - reset the chip using the reset reg
1005 * - re-init context state
1006 * - re-init hardware status page
1007 * - re-init ring buffer
1008 * - re-init interrupt state
1011 int i915_reset(struct drm_device *dev)
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 struct i915_gpu_error *error = &dev_priv->gpu_error;
1015 unsigned reset_counter;
1018 intel_reset_gt_powersave(dev);
1020 mutex_lock(&dev->struct_mutex);
1022 /* Clear any previous failed attempts at recovery. Time to try again. */
1023 atomic_andnot(I915_WEDGED, &error->reset_counter);
1025 /* Clear the reset-in-progress flag and increment the reset epoch. */
1026 reset_counter = atomic_inc_return(&error->reset_counter);
1027 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1032 i915_gem_reset(dev);
1034 ret = intel_gpu_reset(dev, ALL_ENGINES);
1036 /* Also reset the gpu hangman. */
1037 if (error->stop_rings != 0) {
1038 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
1039 error->stop_rings = 0;
1040 if (ret == -ENODEV) {
1041 DRM_INFO("Reset not implemented, but ignoring "
1042 "error for simulated gpu hangs\n");
1047 if (i915_stop_ring_allow_warn(dev_priv))
1048 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1052 DRM_ERROR("Failed to reset chip: %i\n", ret);
1054 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1058 intel_overlay_reset(dev_priv);
1060 /* Ok, now get things going again... */
1063 * Everything depends on having the GTT running, so we need to start
1064 * there. Fortunately we don't need to do this unless we reset the
1065 * chip at a PCI level.
1067 * Next we need to restore the context, but we don't use those
1070 * Ring buffer needs to be re-initialized in the KMS case, or if X
1071 * was running at the time of the reset (i.e. we weren't VT
1074 ret = i915_gem_init_hw(dev);
1076 DRM_ERROR("Failed hw init on reset %d\n", ret);
1080 mutex_unlock(&dev->struct_mutex);
1083 * rps/rc6 re-init is necessary to restore state lost after the
1084 * reset and the re-install of gt irqs. Skip for ironlake per
1085 * previous concerns that it doesn't respond well to some forms
1086 * of re-init after reset.
1088 if (INTEL_INFO(dev)->gen > 5)
1089 intel_enable_gt_powersave(dev);
1094 atomic_or(I915_WEDGED, &error->reset_counter);
1095 mutex_unlock(&dev->struct_mutex);
1099 static int i915_pci_probe(device_t kdev)
1103 if (pci_get_class(kdev) != PCIC_DISPLAY)
1106 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
1109 device = pci_get_device(kdev);
1111 for (i = 0; pciidlist[i].device != 0; i++) {
1112 if (pciidlist[i].device == device) {
1113 i915_attach_list[0].device = device;
1123 i915_pci_remove(struct pci_dev *pdev)
1125 struct drm_device *dev = pci_get_drvdata(pdev);
1130 static int i915_pm_suspend(struct device *dev)
1132 struct pci_dev *pdev = to_pci_dev(dev);
1133 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1135 if (!drm_dev || !drm_dev->dev_private) {
1136 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1140 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1143 return i915_drm_suspend(drm_dev);
1146 static int i915_pm_suspend_late(struct device *dev)
1148 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1151 * We have a suspend ordering issue with the snd-hda driver also
1152 * requiring our device to be power up. Due to the lack of a
1153 * parent/child relationship we currently solve this with an late
1156 * FIXME: This should be solved with a special hdmi sink device or
1157 * similar so that power domains can be employed.
1159 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1162 return i915_drm_suspend_late(drm_dev, false);
1165 static int i915_pm_poweroff_late(struct device *dev)
1167 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1169 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1172 return i915_drm_suspend_late(drm_dev, true);
1175 static int i915_pm_resume_early(struct device *dev)
1177 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1179 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1182 return i915_drm_resume_early(drm_dev);
1185 static int i915_pm_resume(struct device *dev)
1187 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1189 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1192 return i915_drm_resume(drm_dev);
1197 * Save all Gunit registers that may be lost after a D3 and a subsequent
1198 * S0i[R123] transition. The list of registers needing a save/restore is
1199 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1200 * registers in the following way:
1201 * - Driver: saved/restored by the driver
1202 * - Punit : saved/restored by the Punit firmware
1203 * - No, w/o marking: no need to save/restore, since the register is R/O or
1204 * used internally by the HW in a way that doesn't depend
1205 * keeping the content across a suspend/resume.
1206 * - Debug : used for debugging
1208 * We save/restore all registers marked with 'Driver', with the following
1210 * - Registers out of use, including also registers marked with 'Debug'.
1211 * These have no effect on the driver's operation, so we don't save/restore
1212 * them to reduce the overhead.
1213 * - Registers that are fully setup by an initialization function called from
1214 * the resume path. For example many clock gating and RPS/RC6 registers.
1215 * - Registers that provide the right functionality with their reset defaults.
1217 * TODO: Except for registers that based on the above 3 criteria can be safely
1218 * ignored, we save/restore all others, practically treating the HW context as
1219 * a black-box for the driver. Further investigation is needed to reduce the
1220 * saved/restored registers even further, by following the same 3 criteria.
1222 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1224 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1227 /* GAM 0x4000-0x4770 */
1228 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1229 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1230 s->arb_mode = I915_READ(ARB_MODE);
1231 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1232 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1234 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1235 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1237 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1238 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1240 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1241 s->ecochk = I915_READ(GAM_ECOCHK);
1242 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1243 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1245 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1247 /* MBC 0x9024-0x91D0, 0x8500 */
1248 s->g3dctl = I915_READ(VLV_G3DCTL);
1249 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1250 s->mbctl = I915_READ(GEN6_MBCTL);
1252 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1253 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1254 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1255 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1256 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1257 s->rstctl = I915_READ(GEN6_RSTCTL);
1258 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1260 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1261 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1262 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1263 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1264 s->ecobus = I915_READ(ECOBUS);
1265 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1266 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1267 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1268 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1269 s->rcedata = I915_READ(VLV_RCEDATA);
1270 s->spare2gh = I915_READ(VLV_SPAREG2H);
1272 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1273 s->gt_imr = I915_READ(GTIMR);
1274 s->gt_ier = I915_READ(GTIER);
1275 s->pm_imr = I915_READ(GEN6_PMIMR);
1276 s->pm_ier = I915_READ(GEN6_PMIER);
1278 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1279 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1281 /* GT SA CZ domain, 0x100000-0x138124 */
1282 s->tilectl = I915_READ(TILECTL);
1283 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1284 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1285 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1286 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1288 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1289 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1290 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1291 s->pcbr = I915_READ(VLV_PCBR);
1292 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1295 * Not saving any of:
1296 * DFT, 0x9800-0x9EC0
1297 * SARB, 0xB000-0xB1FC
1298 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1303 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1305 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1309 /* GAM 0x4000-0x4770 */
1310 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1311 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1312 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1313 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1314 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1316 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1317 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1319 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1320 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1322 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1323 I915_WRITE(GAM_ECOCHK, s->ecochk);
1324 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1325 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1327 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1329 /* MBC 0x9024-0x91D0, 0x8500 */
1330 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1331 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1332 I915_WRITE(GEN6_MBCTL, s->mbctl);
1334 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1335 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1336 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1337 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1338 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1339 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1340 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1342 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1343 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1344 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1345 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1346 I915_WRITE(ECOBUS, s->ecobus);
1347 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1348 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1349 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1350 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1351 I915_WRITE(VLV_RCEDATA, s->rcedata);
1352 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1354 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1355 I915_WRITE(GTIMR, s->gt_imr);
1356 I915_WRITE(GTIER, s->gt_ier);
1357 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1358 I915_WRITE(GEN6_PMIER, s->pm_ier);
1360 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1361 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1363 /* GT SA CZ domain, 0x100000-0x138124 */
1364 I915_WRITE(TILECTL, s->tilectl);
1365 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1367 * Preserve the GT allow wake and GFX force clock bit, they are not
1368 * be restored, as they are used to control the s0ix suspend/resume
1369 * sequence by the caller.
1371 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1372 val &= VLV_GTLC_ALLOWWAKEREQ;
1373 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1374 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1376 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1377 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1378 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1379 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1381 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1383 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1384 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1385 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1386 I915_WRITE(VLV_PCBR, s->pcbr);
1387 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1390 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1395 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1397 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1398 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1400 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1401 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1406 err = wait_for(COND, 20);
1408 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1409 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1415 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1420 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1421 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1423 val |= VLV_GTLC_ALLOWWAKEREQ;
1424 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1425 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1427 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1429 err = wait_for(COND, 1);
1431 DRM_ERROR("timeout disabling GT waking\n");
1436 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1443 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1444 val = wait_for_on ? mask : 0;
1445 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1449 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1451 I915_READ(VLV_GTLC_PW_STATUS));
1454 * RC6 transitioning can be delayed up to 2 msec (see
1455 * valleyview_enable_rps), use 3 msec for safety.
1457 err = wait_for(COND, 3);
1459 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1460 onoff(wait_for_on));
1466 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1468 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1471 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1472 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1475 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1481 * Bspec defines the following GT well on flags as debug only, so
1482 * don't treat them as hard failures.
1484 (void)vlv_wait_for_gt_wells(dev_priv, false);
1486 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1487 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1489 vlv_check_no_gt_access(dev_priv);
1491 err = vlv_force_gfx_clock(dev_priv, true);
1495 err = vlv_allow_gt_wake(dev_priv, false);
1499 if (!IS_CHERRYVIEW(dev_priv))
1500 vlv_save_gunit_s0ix_state(dev_priv);
1502 err = vlv_force_gfx_clock(dev_priv, false);
1509 /* For safety always re-enable waking and disable gfx clock forcing */
1510 vlv_allow_gt_wake(dev_priv, true);
1512 vlv_force_gfx_clock(dev_priv, false);
1517 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1520 struct drm_device *dev = dev_priv->dev;
1525 * If any of the steps fail just try to continue, that's the best we
1526 * can do at this point. Return the first error code (which will also
1527 * leave RPM permanently disabled).
1529 ret = vlv_force_gfx_clock(dev_priv, true);
1531 if (!IS_CHERRYVIEW(dev_priv))
1532 vlv_restore_gunit_s0ix_state(dev_priv);
1534 err = vlv_allow_gt_wake(dev_priv, true);
1538 err = vlv_force_gfx_clock(dev_priv, false);
1542 vlv_check_no_gt_access(dev_priv);
1545 intel_init_clock_gating(dev);
1546 i915_gem_restore_fences(dev);
1553 static int intel_runtime_suspend(struct device *device)
1555 struct pci_dev *pdev = to_pci_dev(device);
1556 struct drm_device *dev = pci_get_drvdata(pdev);
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1560 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1563 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1566 DRM_DEBUG_KMS("Suspending device\n");
1569 * We could deadlock here in case another thread holding struct_mutex
1570 * calls RPM suspend concurrently, since the RPM suspend will wait
1571 * first for this RPM suspend to finish. In this case the concurrent
1572 * RPM resume will be followed by its RPM suspend counterpart. Still
1573 * for consistency return -EAGAIN, which will reschedule this suspend.
1575 if (!mutex_trylock(&dev->struct_mutex)) {
1576 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1578 * Bump the expiration timestamp, otherwise the suspend won't
1581 pm_runtime_mark_last_busy(device);
1586 disable_rpm_wakeref_asserts(dev_priv);
1589 * We are safe here against re-faults, since the fault handler takes
1592 i915_gem_release_all_mmaps(dev_priv);
1593 mutex_unlock(&dev->struct_mutex);
1595 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1597 intel_guc_suspend(dev);
1599 intel_suspend_gt_powersave(dev);
1600 intel_runtime_pm_disable_interrupts(dev_priv);
1603 if (IS_BROXTON(dev_priv)) {
1604 bxt_display_core_uninit(dev_priv);
1605 bxt_enable_dc9(dev_priv);
1606 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1607 hsw_enable_pc8(dev_priv);
1608 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1609 ret = vlv_suspend_complete(dev_priv);
1613 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1614 intel_runtime_pm_enable_interrupts(dev_priv);
1616 enable_rpm_wakeref_asserts(dev_priv);
1621 intel_uncore_forcewake_reset(dev, false);
1623 enable_rpm_wakeref_asserts(dev_priv);
1624 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1626 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1627 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1629 dev_priv->pm.suspended = true;
1632 * FIXME: We really should find a document that references the arguments
1635 if (IS_BROADWELL(dev)) {
1637 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1638 * being detected, and the call we do at intel_runtime_resume()
1639 * won't be able to restore them. Since PCI_D3hot matches the
1640 * actual specification and appears to be working, use it.
1642 intel_opregion_notify_adapter(dev, PCI_D3hot);
1645 * current versions of firmware which depend on this opregion
1646 * notification have repurposed the D1 definition to mean
1647 * "runtime suspended" vs. what you would normally expect (D3)
1648 * to distinguish it from notifications that might be sent via
1651 intel_opregion_notify_adapter(dev, PCI_D1);
1654 assert_forcewakes_inactive(dev_priv);
1656 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
1657 intel_hpd_poll_init(dev_priv);
1659 DRM_DEBUG_KMS("Device suspended\n");
1663 static int intel_runtime_resume(struct device *device)
1665 struct pci_dev *pdev = to_pci_dev(device);
1666 struct drm_device *dev = pci_get_drvdata(pdev);
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1670 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1673 DRM_DEBUG_KMS("Resuming device\n");
1675 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1676 disable_rpm_wakeref_asserts(dev_priv);
1678 intel_opregion_notify_adapter(dev, PCI_D0);
1679 dev_priv->pm.suspended = false;
1680 if (intel_uncore_unclaimed_mmio(dev_priv))
1681 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1683 intel_guc_resume(dev);
1685 if (IS_GEN6(dev_priv))
1686 intel_init_pch_refclk(dev);
1688 if (IS_BROXTON(dev)) {
1689 bxt_disable_dc9(dev_priv);
1690 bxt_display_core_init(dev_priv, true);
1691 if (dev_priv->csr.dmc_payload &&
1692 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
1693 gen9_enable_dc5(dev_priv);
1694 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1695 hsw_disable_pc8(dev_priv);
1696 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1697 ret = vlv_resume_prepare(dev_priv, true);
1701 * No point of rolling back things in case of an error, as the best
1702 * we can do is to hope that things will still work (and disable RPM).
1704 i915_gem_init_swizzling(dev);
1705 gen6_update_ring_freq(dev);
1707 intel_runtime_pm_enable_interrupts(dev_priv);
1710 * On VLV/CHV display interrupts are part of the display
1711 * power well, so hpd is reinitialized from there. For
1712 * everyone else do it here.
1714 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1715 intel_hpd_init(dev_priv);
1717 intel_enable_gt_powersave(dev);
1719 enable_rpm_wakeref_asserts(dev_priv);
1722 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1724 DRM_DEBUG_KMS("Device resumed\n");
1729 static const struct dev_pm_ops i915_pm_ops = {
1731 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1734 .suspend = i915_pm_suspend,
1735 .suspend_late = i915_pm_suspend_late,
1736 .resume_early = i915_pm_resume_early,
1737 .resume = i915_pm_resume,
1741 * @freeze, @freeze_late : called (1) before creating the
1742 * hibernation image [PMSG_FREEZE] and
1743 * (2) after rebooting, before restoring
1744 * the image [PMSG_QUIESCE]
1745 * @thaw, @thaw_early : called (1) after creating the hibernation
1746 * image, before writing it [PMSG_THAW]
1747 * and (2) after failing to create or
1748 * restore the image [PMSG_RECOVER]
1749 * @poweroff, @poweroff_late: called after writing the hibernation
1750 * image, before rebooting [PMSG_HIBERNATE]
1751 * @restore, @restore_early : called after rebooting and restoring the
1752 * hibernation image [PMSG_RESTORE]
1754 .freeze = i915_pm_suspend,
1755 .freeze_late = i915_pm_suspend_late,
1756 .thaw_early = i915_pm_resume_early,
1757 .thaw = i915_pm_resume,
1758 .poweroff = i915_pm_suspend,
1759 .poweroff_late = i915_pm_poweroff_late,
1760 .restore_early = i915_pm_resume_early,
1761 .restore = i915_pm_resume,
1763 /* S0ix (via runtime suspend) event handlers */
1764 .runtime_suspend = intel_runtime_suspend,
1765 .runtime_resume = intel_runtime_resume,
1768 static const struct vm_operations_struct i915_gem_vm_ops = {
1769 .fault = i915_gem_fault,
1770 .open = drm_gem_vm_open,
1771 .close = drm_gem_vm_close,
1774 static const struct file_operations i915_driver_fops = {
1775 .owner = THIS_MODULE,
1777 .release = drm_release,
1778 .unlocked_ioctl = drm_ioctl,
1779 .mmap = drm_gem_mmap,
1782 #ifdef CONFIG_COMPAT
1783 .compat_ioctl = i915_compat_ioctl,
1785 .llseek = noop_llseek,
1789 static struct cdev_pager_ops i915_gem_vm_ops = {
1790 .cdev_pg_fault = i915_gem_fault,
1791 .cdev_pg_ctor = i915_gem_pager_ctor,
1792 .cdev_pg_dtor = i915_gem_pager_dtor
1795 static struct drm_driver driver = {
1796 /* Don't use MTRRs here; the Xserver or userspace app should
1797 * deal with them for Intel hardware.
1800 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
1801 DRIVER_RENDER | DRIVER_MODESET,
1802 .load = i915_driver_load,
1803 .unload = i915_driver_unload,
1804 .open = i915_driver_open,
1805 .lastclose = i915_driver_lastclose,
1806 .preclose = i915_driver_preclose,
1807 .postclose = i915_driver_postclose,
1809 #if defined(CONFIG_DEBUG_FS)
1810 .debugfs_init = i915_debugfs_init,
1811 .debugfs_cleanup = i915_debugfs_cleanup,
1813 .gem_free_object = i915_gem_free_object,
1814 .gem_vm_ops = &i915_gem_vm_ops,
1816 .dumb_create = i915_gem_dumb_create,
1817 .dumb_map_offset = i915_gem_mmap_gtt,
1818 .dumb_destroy = drm_gem_dumb_destroy,
1819 .ioctls = i915_ioctls,
1820 .sysctl_init = i915_sysctl_init,
1821 .name = DRIVER_NAME,
1822 .desc = DRIVER_DESC,
1823 .date = DRIVER_DATE,
1824 .major = DRIVER_MAJOR,
1825 .minor = DRIVER_MINOR,
1826 .patchlevel = DRIVER_PATCHLEVEL,
1829 static int __init i915_init(void);
1832 i915_attach(device_t kdev)
1834 struct drm_device *dev = device_get_softc(kdev);
1838 dev->driver = &driver;
1839 error = drm_attach(kdev, i915_attach_list);
1842 * XXX hack - give the kvm_console time to come up before X starts
1843 * messing with everything, avoiding at least one deadlock.
1845 tsleep(&dummy, 0, "i915_attach", hz*2);
1850 static device_method_t i915_methods[] = {
1851 /* Device interface */
1852 DEVMETHOD(device_probe, i915_pci_probe),
1853 DEVMETHOD(device_attach, i915_attach),
1854 DEVMETHOD(device_suspend, i915_suspend_switcheroo),
1855 DEVMETHOD(device_resume, i915_resume_switcheroo),
1856 DEVMETHOD(device_detach, drm_release),
1860 static driver_t i915_driver = {
1863 sizeof(struct drm_device)
1866 static int __init i915_init(void)
1868 driver.num_ioctls = i915_max_ioctl;
1871 * Enable KMS by default, unless explicitly overriden by
1872 * either the i915.modeset prarameter or by the
1873 * vga_text_mode_force boot option.
1876 if (i915.modeset == 0)
1877 driver.driver_features &= ~DRIVER_MODESET;
1879 if (vgacon_text_force() && i915.modeset == -1)
1880 driver.driver_features &= ~DRIVER_MODESET;
1882 if (!(driver.driver_features & DRIVER_MODESET)) {
1883 /* Silently fail loading to not upset userspace. */
1884 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1888 if (i915.nuclear_pageflip)
1889 driver.driver_features |= DRIVER_ATOMIC;
1892 return drm_pci_init(&driver, &i915_pci_driver);
1899 static void __exit i915_exit(void)
1901 if (!(driver.driver_features & DRIVER_MODESET))
1902 return; /* Never loaded a driver. */
1904 drm_pci_exit(&driver, &i915_pci_driver);
1908 module_init(i915_init);
1910 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY);
1911 MODULE_DEPEND(i915, drm, 1, 1, 1);
1913 MODULE_DEPEND(i915, acpi, 1, 1, 1);