- convert to critical sections
[dragonfly.git] / sys / dev / netif / gx / if_gx.c
1 /*-
2  * Copyright (c) 1999,2000,2001 Jonathan Lemon
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the author nor the names of any co-contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
30  * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.18 2005/06/14 16:47:38 joerg Exp $
31  */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/thread2.h>
41 #include <sys/queue.h>
42
43 #include <net/if.h>
44 #include <net/ifq_var.h>
45 #include <net/if_arp.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49
50 #include <net/bpf.h>
51 #include <net/if_types.h>
52 #include <net/vlan/if_vlan_var.h>
53
54 #include <netinet/in_systm.h>
55 #include <netinet/in.h>
56 #include <netinet/ip.h>
57 #include <netinet/tcp.h>
58 #include <netinet/udp.h>
59
60 #include <vm/vm.h>              /* for vtophys */
61 #include <vm/pmap.h>            /* for vtophys */
62 #include <machine/clock.h>      /* for DELAY */
63 #include <machine/bus_memio.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66 #include <sys/bus.h>
67 #include <sys/rman.h>
68
69 #include <bus/pci/pcireg.h>
70 #include <bus/pci/pcivar.h>
71
72 #include "../mii_layer/mii.h"
73 #include "../mii_layer/miivar.h"
74
75 #include "if_gxreg.h"
76 #include "if_gxvar.h"
77
78 #include "miibus_if.h"
79
80 #define TUNABLE_TX_INTR_DELAY   100
81 #define TUNABLE_RX_INTR_DELAY   100
82
83 #define GX_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
84
85 /*
86  * Various supported device vendors/types and their names.
87  */
88 struct gx_device {
89         u_int16_t       vendor;
90         u_int16_t       device;
91         int             version_flags;
92         u_int32_t       version_ipg;
93         char            *name;
94 };
95
96 static struct gx_device gx_devs[] = {
97         { INTEL_VENDORID, DEVICEID_WISEMAN,
98             GXF_FORCE_TBI | GXF_OLD_REGS,
99             10 | 2 << 10 | 10 << 20,
100             "Intel Gigabit Ethernet (82542)" },
101         { INTEL_VENDORID, DEVICEID_LIVINGOOD_FIBER,
102             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
103             6 | 8 << 10 | 6 << 20,
104             "Intel Gigabit Ethernet (82543GC-F)" },
105         { INTEL_VENDORID, DEVICEID_LIVINGOOD_COPPER,
106             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
107             8 | 8 << 10 | 6 << 20,
108             "Intel Gigabit Ethernet (82543GC-T)" },
109 #if 0
110 /* notyet.. */
111         { INTEL_VENDORID, DEVICEID_CORDOVA_FIBER,
112             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
113             6 | 8 << 10 | 6 << 20,
114             "Intel Gigabit Ethernet (82544EI-F)" },
115         { INTEL_VENDORID, DEVICEID_CORDOVA_COPPER,
116             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
117             8 | 8 << 10 | 6 << 20,
118             "Intel Gigabit Ethernet (82544EI-T)" },
119         { INTEL_VENDORID, DEVICEID_CORDOVA2_COPPER,
120             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
121             8 | 8 << 10 | 6 << 20,
122             "Intel Gigabit Ethernet (82544GC-T)" },
123 #endif
124         { 0, 0, 0, NULL }
125 };
126
127 static struct gx_regs new_regs = {
128         GX_RX_RING_BASE, GX_RX_RING_LEN,
129         GX_RX_RING_HEAD, GX_RX_RING_TAIL,
130         GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
131
132         GX_TX_RING_BASE, GX_TX_RING_LEN,
133         GX_TX_RING_HEAD, GX_TX_RING_TAIL,
134         GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
135 };
136 static struct gx_regs old_regs = {
137         GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
138         GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
139         GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
140
141         GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
142         GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
143         GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
144 };
145
146 static int      gx_probe(device_t dev);
147 static int      gx_attach(device_t dev);
148 static int      gx_detach(device_t dev);
149 static void     gx_shutdown(device_t dev);
150
151 static void     gx_intr(void *xsc);
152 static void     gx_init(void *xsc);
153
154 static struct   gx_device *gx_match(device_t dev);
155 static void     gx_eeprom_getword(struct gx_softc *gx, int addr,
156                     u_int16_t *dest);
157 static int      gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
158                     int cnt);
159 static int      gx_ifmedia_upd(struct ifnet *ifp);
160 static void     gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
161 static int      gx_miibus_readreg(device_t dev, int phy, int reg);
162 static void     gx_miibus_writereg(device_t dev, int phy, int reg, int value);
163 static void     gx_miibus_statchg(device_t dev);
164 static int      gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
165                     struct ucred *);
166 static void     gx_setmulti(struct gx_softc *gx);
167 static void     gx_reset(struct gx_softc *gx);
168 static void     gx_phy_reset(struct gx_softc *gx);
169 static void     gx_stop(struct gx_softc *gx);
170 static void     gx_watchdog(struct ifnet *ifp);
171 static void     gx_start(struct ifnet *ifp);
172
173 static int      gx_init_rx_ring(struct gx_softc *gx);
174 static void     gx_free_rx_ring(struct gx_softc *gx);
175 static int      gx_init_tx_ring(struct gx_softc *gx);
176 static void     gx_free_tx_ring(struct gx_softc *gx);
177
178 static device_method_t gx_methods[] = {
179         /* Device interface */
180         DEVMETHOD(device_probe,         gx_probe),
181         DEVMETHOD(device_attach,        gx_attach),
182         DEVMETHOD(device_detach,        gx_detach),
183         DEVMETHOD(device_shutdown,      gx_shutdown),
184
185         /* MII interface */
186         DEVMETHOD(miibus_readreg,       gx_miibus_readreg),
187         DEVMETHOD(miibus_writereg,      gx_miibus_writereg),
188         DEVMETHOD(miibus_statchg,       gx_miibus_statchg),
189
190         { 0, 0 }
191 };
192
193 static driver_t gx_driver = {
194         "gx",
195         gx_methods,
196         sizeof(struct gx_softc)
197 };
198
199 static devclass_t gx_devclass;
200
201 DECLARE_DUMMY_MODULE(if_gx);
202 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
203 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
204 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
205
206 static struct gx_device *
207 gx_match(device_t dev)
208 {
209         int i;
210
211         for (i = 0; gx_devs[i].name != NULL; i++) {
212                 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
213                     (pci_get_device(dev) == gx_devs[i].device))
214                         return (&gx_devs[i]);
215         }
216         return (NULL);
217 }
218
219 static int
220 gx_probe(device_t dev)
221 {
222         struct gx_device *gx_dev;
223
224         gx_dev = gx_match(dev);
225         if (gx_dev == NULL)
226                 return (ENXIO);
227
228         device_set_desc(dev, gx_dev->name);
229         return (0);
230 }
231
232 static int
233 gx_attach(device_t dev)
234 {
235         struct gx_softc *gx;
236         struct gx_device *gx_dev;
237         struct ifnet *ifp;
238         u_int32_t command;
239         int rid;
240         int error = 0;
241
242         gx = device_get_softc(dev);
243         gx->gx_dev = dev;
244
245         gx_dev = gx_match(dev);
246         gx->gx_vflags = gx_dev->version_flags;
247         gx->gx_ipg = gx_dev->version_ipg;
248
249         /*
250          * Map control/status registers.
251          */
252         command = pci_read_config(dev, PCIR_COMMAND, 4);
253         command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
254         if (gx->gx_vflags & GXF_ENABLE_MWI)
255                 command |= PCIM_CMD_MWIEN;
256         pci_write_config(dev, PCIR_COMMAND, command, 4);
257         command = pci_read_config(dev, PCIR_COMMAND, 4);
258
259 /* XXX check cache line size? */
260
261         if ((command & PCIM_CMD_MEMEN) == 0) {
262                 device_printf(dev, "failed to enable memory mapping!\n");
263                 error = ENXIO;
264                 goto fail;
265         }
266
267         rid = GX_PCI_LOMEM;
268         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
269             RF_ACTIVE);
270 #if 0
271 /* support PIO mode */
272         rid = PCI_LOIO;
273         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
274             RF_ACTIVE);
275 #endif
276
277         if (gx->gx_res == NULL) {
278                 device_printf(dev, "couldn't map memory\n");
279                 error = ENXIO;
280                 goto fail;
281         }
282
283         gx->gx_btag = rman_get_bustag(gx->gx_res);
284         gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
285
286         /* Allocate interrupt */
287         rid = 0;
288         gx->gx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
289             RF_SHAREABLE | RF_ACTIVE);
290
291         if (gx->gx_irq == NULL) {
292                 device_printf(dev, "couldn't map interrupt\n");
293                 error = ENXIO;
294                 goto fail;
295         }
296
297         /* compensate for different register mappings */
298         if (gx->gx_vflags & GXF_OLD_REGS)
299                 gx->gx_reg = old_regs;
300         else
301                 gx->gx_reg = new_regs;
302
303         if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
304             GX_EEMAP_MAC, 3)) {
305                 device_printf(dev, "failed to read station address\n");
306                 error = ENXIO;
307                 goto fail;
308         }
309
310         /* Allocate the ring buffers. */
311         gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
312             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
313
314         if (gx->gx_rdata == NULL) {
315                 device_printf(dev, "no memory for list buffers!\n");
316                 error = ENXIO;
317                 goto fail;
318         }
319         bzero(gx->gx_rdata, sizeof(struct gx_ring_data));
320
321         /* Set default tuneable values. */
322         gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
323         gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
324
325         /* Set up ifnet structure */
326         ifp = &gx->arpcom.ac_if;
327         ifp->if_softc = gx;
328         if_initname(ifp, "gx", device_get_unit(dev));
329         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
330         ifp->if_ioctl = gx_ioctl;
331         ifp->if_start = gx_start;
332         ifp->if_watchdog = gx_watchdog;
333         ifp->if_init = gx_init;
334         ifp->if_mtu = ETHERMTU;
335         ifq_set_maxlen(&ifp->if_snd, GX_TX_RING_CNT - 1);
336         ifq_set_ready(&ifp->if_snd);
337
338         /* see if we can enable hardware checksumming */
339         if (gx->gx_vflags & GXF_CSUM) {
340                 ifp->if_capabilities = IFCAP_HWCSUM;
341                 ifp->if_capenable = ifp->if_capabilities;
342         }
343
344         /* figure out transciever type */
345         if (gx->gx_vflags & GXF_FORCE_TBI ||
346             CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
347                 gx->gx_tbimode = 1;
348
349         if (gx->gx_tbimode) {
350                 /* SERDES transceiver */
351                 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
352                     gx_ifmedia_sts);
353                 ifmedia_add(&gx->gx_media,
354                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
355                 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
356                 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
357         } else {
358                 /* GMII/MII transceiver */
359                 gx_phy_reset(gx);
360                 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
361                     gx_ifmedia_sts)) {
362                         device_printf(dev, "GMII/MII, PHY not detected\n");
363                         error = ENXIO;
364                         goto fail;
365                 }
366         }
367
368         /*
369          * Call MI attach routines.
370          */
371         ether_ifattach(ifp, gx->arpcom.ac_enaddr);
372
373         error = bus_setup_intr(dev, gx->gx_irq, INTR_TYPE_NET,
374                                gx_intr, gx, &gx->gx_intrhand, NULL);
375         if (error) {
376                 device_printf(dev, "couldn't setup irq\n");
377                 goto fail;
378         }
379
380         return (0);
381
382 fail:
383         gx_detach(dev);
384         return (error);
385 }
386
387 static void
388 gx_init(void *xsc)
389 {
390         struct gx_softc *gx = (struct gx_softc *)xsc;
391         struct ifmedia *ifm;
392         struct ifnet *ifp = &gx->arpcom.ac_if;
393         u_int16_t *m;
394         u_int32_t ctrl;
395         int i, tmp;
396
397         crit_enter();
398
399         /* Disable host interrupts, halt chip. */
400         gx_reset(gx);
401
402         /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
403         gx_stop(gx);
404
405         /* Load our MAC address, invalidate other 15 RX addresses. */
406         m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
407         CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
408         CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
409         for (i = 1; i < 16; i++)
410                 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
411
412         /* Program multicast filter. */
413         gx_setmulti(gx);
414
415         /* Init RX ring. */
416         gx_init_rx_ring(gx);
417
418         /* Init TX ring. */
419         gx_init_tx_ring(gx);
420
421         if (gx->gx_vflags & GXF_DMA) {
422                 /* set up DMA control */        
423                 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
424                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
425         }
426
427         /* enable receiver */
428         ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
429         ctrl |= GX_RXC_BCAST_ACCEPT;
430
431         /* Enable or disable promiscuous mode as needed. */
432         if (ifp->if_flags & IFF_PROMISC)
433                 ctrl |= GX_RXC_UNI_PROMISC;
434
435         /* This is required if we want to accept jumbo frames */
436         if (ifp->if_mtu > ETHERMTU)
437                 ctrl |= GX_RXC_LONG_PKT_ENABLE;
438
439         /* setup receive checksum control */
440         if (ifp->if_capenable & IFCAP_RXCSUM)
441                 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
442                     GX_CSUM_TCP/* | GX_CSUM_IP*/);
443
444         /* setup transmit checksum control */
445         if (ifp->if_capenable & IFCAP_TXCSUM)
446                 ifp->if_hwassist = GX_CSUM_FEATURES;
447
448         ctrl |= GX_RXC_STRIP_ETHERCRC;          /* not on 82542? */
449         CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
450
451         /* enable transmitter */
452         ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
453
454         /* XXX we should support half-duplex here too... */
455         ctrl |= GX_TXC_COLL_TIME_FDX;
456
457         CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
458
459         /*
460          * set up recommended IPG times, which vary depending on chip type:
461          *      IPG transmit time:  80ns
462          *      IPG receive time 1: 20ns
463          *      IPG receive time 2: 80ns
464          */
465         CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
466
467         /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
468         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
469         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
470
471         /* set up 802.3x MAC flow control type -- 88:08 */
472         CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
473
474         /* Set up tuneables */
475         CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
476         CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
477
478         /*
479          * Configure chip for correct operation.
480          */
481         ctrl = GX_CTRL_DUPLEX;
482 #if BYTE_ORDER == BIG_ENDIAN
483         ctrl |= GX_CTRL_BIGENDIAN;
484 #endif
485         ctrl |= GX_CTRL_VLAN_ENABLE;
486
487         if (gx->gx_tbimode) {
488                 /*
489                  * It seems that TXCW must be initialized from the EEPROM
490                  * manually.
491                  *
492                  * XXX
493                  * should probably read the eeprom and re-insert the
494                  * values here.
495                  */
496 #define TXCONFIG_WORD   0x000001A0
497                 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
498
499                 /* turn on hardware autonegotiate */
500                 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
501         } else {
502                 /*
503                  * Auto-detect speed from PHY, instead of using direct
504                  * indication.  The SLU bit doesn't force the link, but
505                  * must be present for ASDE to work.
506                  */
507                 gx_phy_reset(gx);
508                 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
509         }
510
511         /*
512          * Take chip out of reset and start it running.
513          */
514         CSR_WRITE_4(gx, GX_CTRL, ctrl);
515
516         /* Turn interrupts on. */
517         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
518
519         ifp->if_flags |= IFF_RUNNING;
520         ifp->if_flags &= ~IFF_OACTIVE;
521
522         /*
523          * Set the current media.
524          */
525         if (gx->gx_miibus != NULL) {
526                 mii_mediachg(device_get_softc(gx->gx_miibus));
527         } else {
528                 ifm = &gx->gx_media;
529                 tmp = ifm->ifm_media;
530                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
531                 gx_ifmedia_upd(ifp);
532                 ifm->ifm_media = tmp;
533         }
534
535         /*
536          * XXX
537          * Have the LINK0 flag force the link in TBI mode.
538          */
539         if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
540                 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
541                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
542         }
543
544 #if 0
545 printf("66mhz: %s  64bit: %s\n",
546         CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
547         CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
548 #endif
549
550         crit_exit();
551 }
552
553 /*
554  * Stop all chip I/O so that the kernel's probe routines don't
555  * get confused by errant DMAs when rebooting.
556  */
557 static void
558 gx_shutdown(device_t dev)
559 {
560         struct gx_softc *gx;
561
562         gx = device_get_softc(dev);
563         gx_reset(gx);
564         gx_stop(gx);
565 }
566
567 static int
568 gx_detach(device_t dev)
569 {
570         struct gx_softc *gx = device_get_softc(dev);
571         struct ifnet *ifp = &gx->arpcom.ac_if;
572
573         if (device_is_attached(dev)) {
574                 ether_ifdetach(ifp);
575                 gx_reset(gx);
576                 gx_stop(gx);
577         }
578
579         if (gx->gx_miibus)
580                 device_delete_child(gx->gx_dev, gx->gx_miibus);
581         bus_generic_detach(gx->gx_dev);
582
583         if (gx->gx_intrhand)
584                 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
585
586         crit_exit();
587
588         if (gx->gx_irq)
589                 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
590         if (gx->gx_res)
591                 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
592                     GX_PCI_LOMEM, gx->gx_res);
593
594         if (gx->gx_rdata)
595                 contigfree(gx->gx_rdata, sizeof(struct gx_ring_data),
596                            M_DEVBUF);
597
598         if (gx->gx_tbimode)
599                 ifmedia_removeall(&gx->gx_media);
600
601         return (0);
602 }
603
604 static void
605 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
606 {
607         u_int16_t word = 0;
608         u_int32_t base, reg;
609         int x;
610
611         addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
612             (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
613
614         base = CSR_READ_4(gx, GX_EEPROM_CTRL);
615         base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
616         base |= GX_EE_SELECT;
617
618         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
619
620         for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
621                 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
622                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
623                 DELAY(10);
624                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
625                 DELAY(10);
626                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
627                 DELAY(10);
628         }
629
630         for (x = 1 << 15; x; x >>= 1) {
631                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
632                 DELAY(10);
633                 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
634                 if (reg & GX_EE_DATA_OUT)
635                         word |= x;
636                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
637                 DELAY(10);
638         }
639
640         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
641         DELAY(10);
642
643         *dest = word;
644 }
645         
646 static int
647 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
648 {
649         u_int16_t *word;
650         int i;
651
652         word = (u_int16_t *)dest;
653         for (i = 0; i < cnt; i ++) {
654                 gx_eeprom_getword(gx, off + i, word);
655                 word++;
656         }
657         return (0);
658 }
659
660 /*
661  * Set media options.
662  */
663 static int
664 gx_ifmedia_upd(struct ifnet *ifp)
665 {
666         struct gx_softc *gx;
667         struct ifmedia *ifm;
668         struct mii_data *mii;
669
670         gx = ifp->if_softc;
671
672         if (gx->gx_tbimode) {
673                 ifm = &gx->gx_media;
674                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
675                         return (EINVAL);
676                 switch (IFM_SUBTYPE(ifm->ifm_media)) {
677                 case IFM_AUTO:
678                         GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
679                         GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
680                         GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
681                         break;
682                 case IFM_1000_SX:
683                         device_printf(gx->gx_dev,
684                             "manual config not supported yet.\n");
685 #if 0
686                         GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
687                         config = /* bit symbols for 802.3z */0;
688                         ctrl |= GX_CTRL_SET_LINK_UP;
689                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
690                                 ctrl |= GX_CTRL_DUPLEX;
691 #endif
692                         break;
693                 default:
694                         return (EINVAL);
695                 }
696         } else {
697                 ifm = &gx->gx_media;
698
699                 /*
700                  * 1000TX half duplex does not work.
701                  */
702                 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
703                     IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T &&
704                     (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
705                         return (EINVAL);
706                 mii = device_get_softc(gx->gx_miibus);
707                 mii_mediachg(mii);
708         }
709         return (0);
710 }
711
712 /*
713  * Report current media status.
714  */
715 static void
716 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
717 {
718         struct gx_softc *gx;
719         struct mii_data *mii;
720         u_int32_t status;
721
722         gx = ifp->if_softc;
723
724         if (gx->gx_tbimode) {
725                 ifmr->ifm_status = IFM_AVALID;
726                 ifmr->ifm_active = IFM_ETHER;
727
728                 status = CSR_READ_4(gx, GX_STATUS);
729                 if ((status & GX_STAT_LINKUP) == 0)
730                         return;
731
732                 ifmr->ifm_status |= IFM_ACTIVE;
733                 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
734         } else {
735                 mii = device_get_softc(gx->gx_miibus);
736                 mii_pollstat(mii);
737                 if ((mii->mii_media_active & (IFM_1000_T | IFM_HDX)) ==
738                     (IFM_1000_T | IFM_HDX))
739                         mii->mii_media_active = IFM_ETHER | IFM_NONE;
740                 ifmr->ifm_active = mii->mii_media_active;
741                 ifmr->ifm_status = mii->mii_media_status;
742         }
743 }
744
745 static void 
746 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
747 {
748         u_int32_t reg, x;
749
750         /*
751          * Set up default GPIO direction + PHY data out.
752          */
753         reg = CSR_READ_4(gx, GX_CTRL);
754         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
755         reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
756
757         /*
758          * Shift in data to PHY.
759          */
760         for (x = 1 << (length - 1); x; x >>= 1) {
761                 if (data & x)
762                         reg |= GX_CTRL_PHY_IO;
763                 else
764                         reg &= ~GX_CTRL_PHY_IO;
765                 CSR_WRITE_4(gx, GX_CTRL, reg);
766                 DELAY(10);
767                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
768                 DELAY(10);
769                 CSR_WRITE_4(gx, GX_CTRL, reg);
770                 DELAY(10);
771         }
772 }
773
774 static u_int16_t 
775 gx_mii_shiftout(struct gx_softc *gx)
776 {
777         u_int32_t reg;
778         u_int16_t data;
779         int x;
780
781         /*
782          * Set up default GPIO direction + PHY data in.
783          */
784         reg = CSR_READ_4(gx, GX_CTRL);
785         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
786         reg |= GX_CTRL_GPIO_DIR;
787
788         CSR_WRITE_4(gx, GX_CTRL, reg);
789         DELAY(10);
790         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
791         DELAY(10);
792         CSR_WRITE_4(gx, GX_CTRL, reg);
793         DELAY(10);
794         /*
795          * Shift out data from PHY.
796          */
797         data = 0;
798         for (x = 1 << 15; x; x >>= 1) {
799                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
800                 DELAY(10);
801                 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
802                         data |= x;
803                 CSR_WRITE_4(gx, GX_CTRL, reg);
804                 DELAY(10);
805         }
806         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
807         DELAY(10);
808         CSR_WRITE_4(gx, GX_CTRL, reg);
809         DELAY(10);
810
811         return (data);
812 }
813
814 static int
815 gx_miibus_readreg(device_t dev, int phy, int reg)
816 {
817         struct gx_softc *gx;
818
819         gx = device_get_softc(dev);
820         if (gx->gx_tbimode)
821                 return (0);
822
823         /*
824          * XXX
825          * Note: Cordova has a MDIC register. livingood and < have mii bits
826          */ 
827
828         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
829         gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
830             (phy << 5) | reg, GX_PHY_READ_LEN);
831         return (gx_mii_shiftout(gx));
832 }
833
834 static void
835 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
836 {
837         struct gx_softc *gx;
838
839         gx = device_get_softc(dev);
840         if (gx->gx_tbimode)
841                 return;
842
843         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
844         gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
845             (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
846             (value & 0xffff), GX_PHY_WRITE_LEN);
847 }
848
849 static void
850 gx_miibus_statchg(device_t dev)
851 {
852         struct gx_softc *gx = device_get_softc(dev);
853         struct mii_data *mii;
854         int reg;
855
856         if (gx->gx_tbimode)
857                 return;
858
859         /*
860          * Set flow control behavior to mirror what PHY negotiated.
861          */
862         mii = device_get_softc(gx->gx_miibus);
863
864         crit_enter();
865
866         reg = CSR_READ_4(gx, GX_CTRL);
867         if (mii->mii_media_active & IFM_FLAG0)
868                 reg |= GX_CTRL_RX_FLOWCTRL;
869         else
870                 reg &= ~GX_CTRL_RX_FLOWCTRL;
871         if (mii->mii_media_active & IFM_FLAG1)
872                 reg |= GX_CTRL_TX_FLOWCTRL;
873         else
874                 reg &= ~GX_CTRL_TX_FLOWCTRL;
875         CSR_WRITE_4(gx, GX_CTRL, reg);
876
877         crit_exit();
878 }
879
880 static int
881 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
882 {
883         struct gx_softc *gx = ifp->if_softc;
884         struct ifreq *ifr = (struct ifreq *)data;
885         struct mii_data *mii;
886         int mask, error = 0;
887
888         crit_enter();
889
890         switch (command) {
891         case SIOCSIFMTU:
892                 if (ifr->ifr_mtu > GX_MAX_MTU) {
893                         error = EINVAL;
894                 } else {
895                         ifp->if_mtu = ifr->ifr_mtu;
896                         gx_init(gx);
897                 }
898                 break;
899         case SIOCSIFFLAGS:
900                 if ((ifp->if_flags & IFF_UP) == 0) {
901                         gx_stop(gx);
902                 } else if (ifp->if_flags & IFF_RUNNING &&
903                     ((ifp->if_flags & IFF_PROMISC) != 
904                     (gx->gx_if_flags & IFF_PROMISC))) {
905                         if (ifp->if_flags & IFF_PROMISC)
906                                 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
907                         else 
908                                 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
909                 } else {
910                         gx_init(gx);
911                 }
912                 gx->gx_if_flags = ifp->if_flags;
913                 break;
914         case SIOCADDMULTI:
915         case SIOCDELMULTI:
916                 if (ifp->if_flags & IFF_RUNNING)
917                         gx_setmulti(gx);
918                 break;
919         case SIOCSIFMEDIA:
920         case SIOCGIFMEDIA:
921                 if (gx->gx_miibus != NULL) {
922                         mii = device_get_softc(gx->gx_miibus);
923                         error = ifmedia_ioctl(ifp, ifr,
924                             &mii->mii_media, command);
925                 } else {
926                         error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
927                 }
928                 break;
929         case SIOCSIFCAP:
930                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
931                 if (mask & IFCAP_HWCSUM) {
932                         if (IFCAP_HWCSUM & ifp->if_capenable)
933                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
934                         else
935                                 ifp->if_capenable |= IFCAP_HWCSUM;
936                         if (ifp->if_flags & IFF_RUNNING)
937                                 gx_init(gx);
938                 }
939                 break;
940         default:
941                 error = ether_ioctl(ifp, command, data);
942                 break;
943         }
944
945         crit_exit();
946
947         return (error);
948 }
949
950 static void
951 gx_phy_reset(struct gx_softc *gx)
952 {
953         int reg;
954
955         GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
956
957         /*
958          * PHY reset is active low.
959          */
960         reg = CSR_READ_4(gx, GX_CTRL_EXT);
961         reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
962         reg |= GX_CTRLX_GPIO_DIR;
963
964         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
965         DELAY(10);
966         CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
967         DELAY(10);
968         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
969         DELAY(10);
970
971 #if 0
972         /* post-livingood (cordova) only */
973                 GX_SETBIT(gx, GX_CTRL, 0x80000000);
974                 DELAY(1000);
975                 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
976 #endif
977 }
978
979 static void
980 gx_reset(struct gx_softc *gx)
981 {
982
983         /* Disable host interrupts. */
984         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
985
986         /* reset chip (THWAP!) */
987         GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
988         DELAY(10);
989 }
990
991 static void
992 gx_stop(struct gx_softc *gx)
993 {
994         struct ifnet *ifp;
995
996         ifp = &gx->arpcom.ac_if;
997
998         /* reset and flush transmitter */
999         CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
1000
1001         /* reset and flush receiver */
1002         CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
1003
1004         /* reset link */
1005         if (gx->gx_tbimode)
1006                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
1007
1008         /* Free the RX lists. */
1009         gx_free_rx_ring(gx);
1010
1011         /* Free TX buffers. */
1012         gx_free_tx_ring(gx);
1013
1014         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1015 }
1016
1017 static void
1018 gx_watchdog(struct ifnet *ifp)
1019 {
1020         struct gx_softc *gx;
1021
1022         gx = ifp->if_softc;
1023
1024         device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1025         gx_reset(gx);
1026         gx_init(gx);
1027
1028         ifp->if_oerrors++;
1029 }
1030
1031 /*
1032  * Intialize a receive ring descriptor.
1033  */
1034 static int
1035 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1036 {
1037         struct mbuf *m_new = NULL;
1038         struct gx_rx_desc *r;
1039
1040         if (m == NULL) {
1041                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1042                 if (m_new == NULL) {
1043                         device_printf(gx->gx_dev, 
1044                             "mbuf allocation failed -- packet dropped\n");
1045                         return (ENOBUFS);
1046                 }
1047                 MCLGET(m_new, MB_DONTWAIT);
1048                 if ((m_new->m_flags & M_EXT) == 0) {
1049                         device_printf(gx->gx_dev, 
1050                             "cluster allocation failed -- packet dropped\n");
1051                         m_freem(m_new);
1052                         return (ENOBUFS);
1053                 }
1054                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1055         } else {
1056                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1057                 m->m_data = m->m_ext.ext_buf;
1058                 m->m_next = NULL;
1059                 m_new = m;
1060         }
1061
1062         /*
1063          * XXX
1064          * this will _NOT_ work for large MTU's; it will overwrite
1065          * the end of the buffer.  E.g.: take this out for jumbograms,
1066          * but then that breaks alignment.
1067          */
1068         if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1069                 m_adj(m_new, ETHER_ALIGN);
1070
1071         gx->gx_cdata.gx_rx_chain[idx] = m_new;
1072         r = &gx->gx_rdata->gx_rx_ring[idx];
1073         r->rx_addr = vtophys(mtod(m_new, caddr_t));
1074         r->rx_staterr = 0;
1075
1076         return (0);
1077 }
1078
1079 /*
1080  * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1081  * cluster, could add up to 128M of memory.  Due to alignment constraints,
1082  * the number of descriptors must be a multiple of 8.  For now, we
1083  * allocate 256 entries and hope that our CPU is fast enough to keep up
1084  * with the NIC.
1085  */
1086 static int
1087 gx_init_rx_ring(struct gx_softc *gx)
1088 {
1089         int i, error;
1090
1091         for (i = 0; i < GX_RX_RING_CNT; i++) {
1092                 error = gx_newbuf(gx, i, NULL);
1093                 if (error)
1094                         return (error);
1095         }
1096
1097         /* bring receiver out of reset state, leave disabled */
1098         CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1099
1100         /* set up ring registers */
1101         CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1102             (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1103
1104         CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1105             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1106         CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1107         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1108         gx->gx_rx_tail_idx = 0;
1109
1110         return (0);
1111 }
1112
1113 static void
1114 gx_free_rx_ring(struct gx_softc *gx)
1115 {
1116         struct mbuf **mp;
1117         int i;
1118
1119         mp = gx->gx_cdata.gx_rx_chain;
1120         for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1121                 if (*mp != NULL) {
1122                         m_freem(*mp);
1123                         *mp = NULL;
1124                 }
1125         }
1126         bzero((void *)gx->gx_rdata->gx_rx_ring,
1127             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1128
1129         /* release any partially-received packet chain */
1130         if (gx->gx_pkthdr != NULL) {
1131                 m_freem(gx->gx_pkthdr);
1132                 gx->gx_pkthdr = NULL;
1133         }
1134 }
1135
1136 static int
1137 gx_init_tx_ring(struct gx_softc *gx)
1138 {
1139
1140         /* bring transmitter out of reset state, leave disabled */
1141         CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1142
1143         /* set up ring registers */
1144         CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1145             (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1146         CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1147             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1148         CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1149         CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1150         gx->gx_tx_head_idx = 0;
1151         gx->gx_tx_tail_idx = 0;
1152         gx->gx_txcnt = 0;
1153
1154         /* set up initial TX context */
1155         gx->gx_txcontext = GX_TXCONTEXT_NONE;
1156
1157         return (0);
1158 }
1159
1160 static void
1161 gx_free_tx_ring(struct gx_softc *gx)
1162 {
1163         struct mbuf **mp;
1164         int i;
1165
1166         mp = gx->gx_cdata.gx_tx_chain;
1167         for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1168                 if (*mp != NULL) {
1169                         m_freem(*mp);
1170                         *mp = NULL;
1171                 }
1172         }
1173         bzero((void *)&gx->gx_rdata->gx_tx_ring,
1174             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1175 }
1176
1177 static void
1178 gx_setmulti(struct gx_softc *gx)
1179 {
1180         int i;
1181
1182         /* wipe out the multicast table */
1183         for (i = 1; i < 128; i++)
1184                 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1185 }
1186
1187 static void
1188 gx_rxeof(struct gx_softc *gx)
1189 {
1190         struct gx_rx_desc *rx;
1191         struct ifnet *ifp;
1192         int idx, staterr, len;
1193         struct mbuf *m;
1194
1195         gx->gx_rx_interrupts++;
1196
1197         ifp = &gx->arpcom.ac_if;
1198         idx = gx->gx_rx_tail_idx;
1199
1200         while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1201
1202                 rx = &gx->gx_rdata->gx_rx_ring[idx];
1203                 m = gx->gx_cdata.gx_rx_chain[idx];
1204                 /*
1205                  * gx_newbuf overwrites status and length bits, so we 
1206                  * make a copy of them here.
1207                  */
1208                 len = rx->rx_len;
1209                 staterr = rx->rx_staterr;
1210
1211                 if (staterr & GX_INPUT_ERROR)
1212                         goto ierror;
1213
1214                 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1215                         goto ierror;
1216
1217                 GX_INC(idx, GX_RX_RING_CNT);
1218
1219                 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1220                         /*
1221                          * multicast packet, must verify against
1222                          * multicast address.
1223                          */
1224                 }
1225
1226                 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1227                         if (gx->gx_pkthdr == NULL) {
1228                                 m->m_len = len;
1229                                 m->m_pkthdr.len = len;
1230                                 gx->gx_pkthdr = m;
1231                                 gx->gx_pktnextp = &m->m_next;
1232                         } else {
1233                                 m->m_len = len;
1234                                 gx->gx_pkthdr->m_pkthdr.len += len;
1235                                 *(gx->gx_pktnextp) = m;
1236                                 gx->gx_pktnextp = &m->m_next;
1237                         }
1238                         continue;
1239                 }
1240
1241                 if (gx->gx_pkthdr == NULL) {
1242                         m->m_len = len;
1243                         m->m_pkthdr.len = len;
1244                 } else {
1245                         m->m_len = len;
1246                         gx->gx_pkthdr->m_pkthdr.len += len;
1247                         *(gx->gx_pktnextp) = m;
1248                         m = gx->gx_pkthdr;
1249                         gx->gx_pkthdr = NULL;
1250                 }
1251
1252                 ifp->if_ipackets++;
1253                 m->m_pkthdr.rcvif = ifp;
1254
1255 #define IP_CSMASK       (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1256 #define TCP_CSMASK \
1257     (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1258                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1259 #if 0
1260                         /*
1261                          * Intel Erratum #23 indicates that the Receive IP
1262                          * Checksum offload feature has been completely
1263                          * disabled.
1264                          */
1265                         if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1266                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1267                                 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1268                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1269                         }
1270 #endif
1271                         if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1272                                 m->m_pkthdr.csum_flags |=
1273                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1274                                 m->m_pkthdr.csum_data = 0xffff;
1275                         }
1276                 }
1277                 /*
1278                  * If we received a packet with a vlan tag, pass it
1279                  * to vlan_input() instead of ether_input().
1280                  */
1281                 if (staterr & GX_RXSTAT_VLAN_PKT)
1282                         VLAN_INPUT_TAG(m, rx->rx_special);
1283                 else
1284                         (*ifp->if_input)(ifp, m);
1285                 continue;
1286
1287   ierror:
1288                 ifp->if_ierrors++;
1289                 gx_newbuf(gx, idx, m);
1290
1291                 /* 
1292                  * XXX
1293                  * this isn't quite right.  Suppose we have a packet that
1294                  * spans 5 descriptors (9K split into 2K buffers).  If
1295                  * the 3rd descriptor sets an error, we need to ignore
1296                  * the last two.  The way things stand now, the last two
1297                  * will be accepted as a single packet.
1298                  *
1299                  * we don't worry about this -- the chip may not set an
1300                  * error in this case, and the checksum of the upper layers
1301                  * will catch the error.
1302                  */
1303                 if (gx->gx_pkthdr != NULL) {
1304                         m_freem(gx->gx_pkthdr);
1305                         gx->gx_pkthdr = NULL;
1306                 }
1307                 GX_INC(idx, GX_RX_RING_CNT);
1308         }
1309
1310         gx->gx_rx_tail_idx = idx;
1311         if (--idx < 0)
1312                 idx = GX_RX_RING_CNT - 1;
1313         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1314 }
1315
1316 static void
1317 gx_txeof(struct gx_softc *gx)
1318 {
1319         struct ifnet *ifp;
1320         int idx, cnt;
1321
1322         gx->gx_tx_interrupts++;
1323
1324         ifp = &gx->arpcom.ac_if;
1325         idx = gx->gx_tx_head_idx;
1326         cnt = gx->gx_txcnt;
1327
1328         /*
1329          * If the system chipset performs I/O write buffering, it is 
1330          * possible for the PIO read of the head descriptor to bypass the
1331          * memory write of the descriptor, resulting in reading a descriptor
1332          * which has not been updated yet.
1333          */
1334         while (cnt) {
1335                 struct gx_tx_desc_old *tx;
1336
1337                 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1338                 cnt--;
1339
1340                 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1341                         GX_INC(idx, GX_TX_RING_CNT);
1342                         continue;
1343                 }
1344
1345                 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1346                         break;
1347
1348                 ifp->if_opackets++;
1349
1350                 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1351                 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1352                 gx->gx_txcnt = cnt;
1353                 ifp->if_timer = 0;
1354
1355                 GX_INC(idx, GX_TX_RING_CNT);
1356                 gx->gx_tx_head_idx = idx;
1357         }
1358
1359         if (gx->gx_txcnt == 0)
1360                 ifp->if_flags &= ~IFF_OACTIVE;
1361 }
1362
1363 static void
1364 gx_intr(void *xsc)
1365 {
1366         struct gx_softc *gx = xsc;
1367         struct ifnet *ifp = &gx->arpcom.ac_if;
1368         u_int32_t intr;
1369
1370         crit_enter();
1371
1372         gx->gx_interrupts++;
1373
1374         /* Disable host interrupts. */
1375         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1376
1377         /*
1378          * find out why we're being bothered.
1379          * reading this register automatically clears all bits.
1380          */
1381         intr = CSR_READ_4(gx, GX_INT_READ);
1382
1383         /* Check RX return ring producer/consumer */
1384         if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1385                 gx_rxeof(gx);
1386
1387         /* Check TX ring producer/consumer */
1388         if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1389                 gx_txeof(gx);
1390
1391         /*
1392          * handle other interrupts here.
1393          */
1394
1395         /*
1396          * Link change interrupts are not reliable; the interrupt may
1397          * not be generated if the link is lost.  However, the register
1398          * read is reliable, so check that.  Use SEQ errors to possibly
1399          * indicate that the link has changed.
1400          */
1401         if (intr & GX_INT_LINK_CHANGE) {
1402                 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1403                         device_printf(gx->gx_dev, "link down\n");
1404                 } else {
1405                         device_printf(gx->gx_dev, "link up\n");
1406                 }
1407         }
1408
1409         /* Turn interrupts on. */
1410         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1411
1412         if (ifp->if_flags & IFF_RUNNING && !ifq_is_empty(&ifp->if_snd))
1413                 gx_start(ifp);
1414
1415         crit_exit();
1416 }
1417
1418 /*
1419  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1420  * pointers to descriptors.
1421  */
1422 static int
1423 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1424 {
1425         struct gx_tx_desc_data *tx = NULL;
1426         struct gx_tx_desc_ctx *tctx;
1427         struct mbuf *m;
1428         int idx, cnt, csumopts, txcontext;
1429         struct ifvlan *ifv = NULL;
1430
1431         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1432             m_head->m_pkthdr.rcvif != NULL &&
1433             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1434                 ifv = m_head->m_pkthdr.rcvif->if_softc;
1435
1436         cnt = gx->gx_txcnt;
1437         idx = gx->gx_tx_tail_idx;
1438         txcontext = gx->gx_txcontext;
1439
1440         /*
1441          * Insure we have at least 4 descriptors pre-allocated.
1442          */
1443         if (cnt >= GX_TX_RING_CNT - 4)
1444                 return (ENOBUFS);
1445
1446         /*
1447          * Set up the appropriate offload context if necessary.
1448          */
1449         csumopts = 0;
1450         if (m_head->m_pkthdr.csum_flags) {
1451                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1452                         csumopts |= GX_TXTCP_OPT_IP_CSUM;
1453                 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1454                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1455                         txcontext = GX_TXCONTEXT_TCPIP;
1456                 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1457                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1458                         txcontext = GX_TXCONTEXT_UDPIP;
1459                 } else if (txcontext == GX_TXCONTEXT_NONE)
1460                         txcontext = GX_TXCONTEXT_TCPIP;
1461                 if (txcontext == gx->gx_txcontext)
1462                         goto context_done;
1463
1464                 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1465                 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1466                 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1467                 tctx->tx_ip_csum_offset = 
1468                     ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1469                 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1470                 tctx->tx_tcp_csum_end = 0;
1471                 if (txcontext == GX_TXCONTEXT_TCPIP)
1472                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1473                             sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1474                 else
1475                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1476                             sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1477                 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1478                 tctx->tx_type = 0;
1479                 tctx->tx_status = 0;
1480                 GX_INC(idx, GX_TX_RING_CNT);
1481                 cnt++;
1482         }
1483 context_done:
1484
1485         /*
1486          * Start packing the mbufs in this chain into the transmit
1487          * descriptors.  Stop when we run out of descriptors or hit
1488          * the end of the mbuf chain.
1489          */
1490         for (m = m_head; m != NULL; m = m->m_next) {
1491                 if (m->m_len == 0)
1492                         continue;
1493
1494                 if (cnt == GX_TX_RING_CNT) {
1495 printf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1496                         return (ENOBUFS);
1497 }
1498
1499                 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1500                 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1501                 tx->tx_status = 0;
1502                 tx->tx_len = m->m_len;
1503                 if (gx->arpcom.ac_if.if_hwassist) {
1504                         tx->tx_type = 1;
1505                         tx->tx_command = GX_TXTCP_EXTENSION;
1506                         tx->tx_options = csumopts;
1507                 } else {
1508                         /*
1509                          * This is really a struct gx_tx_desc_old.
1510                          */
1511                         tx->tx_command = 0;
1512                 }
1513                 GX_INC(idx, GX_TX_RING_CNT);
1514                 cnt++;
1515         }
1516
1517         if (tx != NULL) {
1518                 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1519                     GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1520                 if (ifv != NULL) {
1521                         tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1522                         tx->tx_vlan = ifv->ifv_tag;
1523                 }
1524                 gx->gx_txcnt = cnt;
1525                 gx->gx_tx_tail_idx = idx;
1526                 gx->gx_txcontext = txcontext;
1527                 idx = GX_PREV(idx, GX_TX_RING_CNT);
1528                 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1529
1530                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1531         }
1532         
1533         return (0);
1534 }
1535  
1536 /*
1537  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1538  * to the mbuf data regions directly in the transmit descriptors.
1539  */
1540 static void
1541 gx_start(struct ifnet *ifp)
1542 {
1543         struct gx_softc *gx = ifp->if_softc;
1544         struct mbuf *m_head;
1545
1546         crit_enter();
1547
1548         for (;;) {
1549                 m_head = ifq_poll(&ifp->if_snd);
1550                 if (m_head == NULL)
1551                         break;
1552
1553                 /*
1554                  * Pack the data into the transmit ring. If we
1555                  * don't have room, set the OACTIVE flag and wait
1556                  * for the NIC to drain the ring.
1557                  */
1558                 if (gx_encap(gx, m_head) != 0) {
1559                         ifp->if_flags |= IFF_OACTIVE;
1560                         break;
1561                 }
1562                 m_head = ifq_dequeue(&ifp->if_snd);
1563
1564                 BPF_MTAP(ifp, m_head);
1565
1566                 /*
1567                  * Set a timeout in case the chip goes out to lunch.
1568                  */
1569                 ifp->if_timer = 5;
1570         }
1571
1572         crit_exit();
1573 }