2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.38 2005/11/21 13:20:29 sephe Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include "opt_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/socket.h>
72 #include <sys/thread2.h>
75 #include <net/ifq_var.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
83 #include <vm/vm.h> /* for vtophys */
84 #include <vm/pmap.h> /* for vtophys */
85 #include <machine/bus_pio.h>
86 #include <machine/bus_memio.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include <dev/netif/mii_layer/mii.h>
93 #include <dev/netif/mii_layer/miivar.h>
95 #include <bus/pci/pcireg.h>
96 #include <bus/pci/pcivar.h>
100 #include <dev/netif/vr/if_vrreg.h>
102 /* "controller miibus0" required. See GENERIC if you get errors here. */
103 #include "miibus_if.h"
108 * Various supported device vendors/types and their names.
110 static struct vr_type vr_devs[] = {
111 { VIA_VENDORID, VIA_DEVICEID_RHINE,
112 "VIA VT3043 Rhine I 10/100BaseTX" },
113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
114 "VIA VT86C100A Rhine II 10/100BaseTX" },
115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
116 "VIA VT6102 Rhine II 10/100BaseTX" },
117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
118 "VIA VT6105 Rhine III 10/100BaseTX" },
119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
120 "VIA VT6105M Rhine III 10/100BaseTX" },
121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
122 "Delta Electronics Rhine II 10/100BaseTX" },
123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
124 "Addtron Technology Rhine II 10/100BaseTX" },
128 static int vr_probe(device_t);
129 static int vr_attach(device_t);
130 static int vr_detach(device_t);
132 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
134 static int vr_encap(struct vr_softc *, int, struct mbuf * );
136 static void vr_rxeof(struct vr_softc *);
137 static void vr_rxeoc(struct vr_softc *);
138 static void vr_txeof(struct vr_softc *);
139 static void vr_txeoc(struct vr_softc *);
140 static void vr_tick(void *);
141 static void vr_intr(void *);
142 static void vr_start(struct ifnet *);
143 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
144 static void vr_init(void *);
145 static void vr_stop(struct vr_softc *);
146 static void vr_watchdog(struct ifnet *);
147 static void vr_shutdown(device_t);
148 static int vr_ifmedia_upd(struct ifnet *);
149 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
152 static void vr_mii_sync(struct vr_softc *);
153 static void vr_mii_send(struct vr_softc *, uint32_t, int);
155 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
156 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
157 static int vr_miibus_readreg(device_t, int, int);
158 static int vr_miibus_writereg(device_t, int, int, int);
159 static void vr_miibus_statchg(device_t);
161 static void vr_setcfg(struct vr_softc *, int);
162 static void vr_setmulti(struct vr_softc *);
163 static void vr_reset(struct vr_softc *);
164 static int vr_list_rx_init(struct vr_softc *);
165 static int vr_list_tx_init(struct vr_softc *);
166 #ifdef DEVICE_POLLING
167 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
171 #define VR_RES SYS_RES_IOPORT
172 #define VR_RID VR_PCI_LOIO
174 #define VR_RES SYS_RES_MEMORY
175 #define VR_RID VR_PCI_LOMEM
178 static device_method_t vr_methods[] = {
179 /* Device interface */
180 DEVMETHOD(device_probe, vr_probe),
181 DEVMETHOD(device_attach, vr_attach),
182 DEVMETHOD(device_detach, vr_detach),
183 DEVMETHOD(device_shutdown, vr_shutdown),
186 DEVMETHOD(bus_print_child, bus_generic_print_child),
187 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
191 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
192 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
197 static driver_t vr_driver = {
200 sizeof(struct vr_softc)
203 static devclass_t vr_devclass;
205 DECLARE_DUMMY_MODULE(if_vr);
206 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
209 #define VR_SETBIT(sc, reg, x) \
210 CSR_WRITE_1(sc, reg, \
211 CSR_READ_1(sc, reg) | (x))
213 #define VR_CLRBIT(sc, reg, x) \
214 CSR_WRITE_1(sc, reg, \
215 CSR_READ_1(sc, reg) & ~(x))
217 #define VR_SETBIT16(sc, reg, x) \
218 CSR_WRITE_2(sc, reg, \
219 CSR_READ_2(sc, reg) | (x))
221 #define VR_CLRBIT16(sc, reg, x) \
222 CSR_WRITE_2(sc, reg, \
223 CSR_READ_2(sc, reg) & ~(x))
225 #define VR_SETBIT32(sc, reg, x) \
226 CSR_WRITE_4(sc, reg, \
227 CSR_READ_4(sc, reg) | (x))
229 #define VR_CLRBIT32(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, \
231 CSR_READ_4(sc, reg) & ~(x))
234 CSR_WRITE_1(sc, VR_MIICMD, \
235 CSR_READ_1(sc, VR_MIICMD) | (x))
238 CSR_WRITE_1(sc, VR_MIICMD, \
239 CSR_READ_1(sc, VR_MIICMD) & ~(x))
243 * Sync the PHYs by setting data bit and strobing the clock 32 times.
246 vr_mii_sync(struct vr_softc *sc)
250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
252 for (i = 0; i < 32; i++) {
253 SIO_SET(VR_MIICMD_CLK);
255 SIO_CLR(VR_MIICMD_CLK);
261 * Clock a series of bits through the MII.
264 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
268 SIO_CLR(VR_MIICMD_CLK);
270 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
272 SIO_SET(VR_MIICMD_DATAIN);
274 SIO_CLR(VR_MIICMD_DATAIN);
276 SIO_CLR(VR_MIICMD_CLK);
278 SIO_SET(VR_MIICMD_CLK);
284 * Read an PHY register through the MII.
287 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
294 /* Set up frame for RX. */
295 frame->mii_stdelim = VR_MII_STARTDELIM;
296 frame->mii_opcode = VR_MII_READOP;
297 frame->mii_turnaround = 0;
300 CSR_WRITE_1(sc, VR_MIICMD, 0);
301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
303 /* Turn on data xmit. */
304 SIO_SET(VR_MIICMD_DIR);
308 /* Send command/address info. */
309 vr_mii_send(sc, frame->mii_stdelim, 2);
310 vr_mii_send(sc, frame->mii_opcode, 2);
311 vr_mii_send(sc, frame->mii_phyaddr, 5);
312 vr_mii_send(sc, frame->mii_regaddr, 5);
315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
317 SIO_SET(VR_MIICMD_CLK);
321 SIO_CLR(VR_MIICMD_DIR);
324 SIO_CLR(VR_MIICMD_CLK);
326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
327 SIO_SET(VR_MIICMD_CLK);
331 * Now try reading data bits. If the ack failed, we still
332 * need to clock through 16 cycles to keep the PHY(s) in sync.
335 for(i = 0; i < 16; i++) {
336 SIO_CLR(VR_MIICMD_CLK);
338 SIO_SET(VR_MIICMD_CLK);
344 for (i = 0x8000; i; i >>= 1) {
345 SIO_CLR(VR_MIICMD_CLK);
348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
349 frame->mii_data |= i;
352 SIO_SET(VR_MIICMD_CLK);
357 SIO_CLR(VR_MIICMD_CLK);
359 SIO_SET(VR_MIICMD_CLK);
374 /* Set the PHY address. */
375 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
378 /* Set the register address. */
379 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
380 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
382 for (i = 0; i < 10000; i++) {
383 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
387 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
397 * Write to a PHY register through the MII.
400 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
406 CSR_WRITE_1(sc, VR_MIICMD, 0);
407 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
409 /* Set up frame for TX. */
410 frame->mii_stdelim = VR_MII_STARTDELIM;
411 frame->mii_opcode = VR_MII_WRITEOP;
412 frame->mii_turnaround = VR_MII_TURNAROUND;
414 /* Turn on data output. */
415 SIO_SET(VR_MIICMD_DIR);
419 vr_mii_send(sc, frame->mii_stdelim, 2);
420 vr_mii_send(sc, frame->mii_opcode, 2);
421 vr_mii_send(sc, frame->mii_phyaddr, 5);
422 vr_mii_send(sc, frame->mii_regaddr, 5);
423 vr_mii_send(sc, frame->mii_turnaround, 2);
424 vr_mii_send(sc, frame->mii_data, 16);
427 SIO_SET(VR_MIICMD_CLK);
429 SIO_CLR(VR_MIICMD_CLK);
433 SIO_CLR(VR_MIICMD_DIR);
445 /* Set the PHY-adress */
446 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
449 /* Set the register address and data to write. */
450 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
451 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
453 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
455 for (i = 0; i < 10000; i++) {
456 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
468 vr_miibus_readreg(device_t dev, int phy, int reg)
470 struct vr_mii_frame frame;
473 sc = device_get_softc(dev);
475 switch (sc->vr_revid) {
476 case REV_ID_VT6102_APOLLO:
484 bzero(&frame, sizeof(frame));
486 frame.mii_phyaddr = phy;
487 frame.mii_regaddr = reg;
488 vr_mii_readreg(sc, &frame);
490 return(frame.mii_data);
494 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
496 struct vr_mii_frame frame;
499 sc = device_get_softc(dev);
501 switch (sc->vr_revid) {
502 case REV_ID_VT6102_APOLLO:
510 bzero(&frame, sizeof(frame));
512 frame.mii_phyaddr = phy;
513 frame.mii_regaddr = reg;
514 frame.mii_data = data;
516 vr_mii_writereg(sc, &frame);
522 vr_miibus_statchg(device_t dev)
524 struct mii_data *mii;
527 sc = device_get_softc(dev);
528 mii = device_get_softc(sc->vr_miibus);
529 vr_setcfg(sc, mii->mii_media_active);
533 * Program the 64-bit multicast hash filter.
536 vr_setmulti(struct vr_softc *sc)
539 uint32_t hashes[2] = { 0, 0 };
540 struct ifmultiaddr *ifma;
544 ifp = &sc->arpcom.ac_if;
546 rxfilt = CSR_READ_1(sc, VR_RXCFG);
548 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
549 rxfilt |= VR_RXCFG_RX_MULTI;
550 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
551 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
552 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
556 /* First, zero out all the existing hash bits. */
557 CSR_WRITE_4(sc, VR_MAR0, 0);
558 CSR_WRITE_4(sc, VR_MAR1, 0);
560 /* Now program new ones. */
561 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
564 if (ifma->ifma_addr->sa_family != AF_LINK)
567 /* use the lower 6 bits */
569 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
570 ETHER_ADDR_LEN) >> 26) & 0x0000003F;
572 hashes[0] |= (1 << h);
574 hashes[1] |= (1 << (h - 32));
579 rxfilt |= VR_RXCFG_RX_MULTI;
581 rxfilt &= ~VR_RXCFG_RX_MULTI;
583 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
584 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
585 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
589 * In order to fiddle with the
590 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
591 * first have to put the transmit and/or receive logic in the idle state.
594 vr_setcfg(struct vr_softc *sc, int media)
598 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
600 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
603 if ((media & IFM_GMASK) == IFM_FDX)
604 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
606 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
609 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
613 vr_reset(struct vr_softc *sc)
617 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
619 for (i = 0; i < VR_TIMEOUT; i++) {
621 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
624 if (i == VR_TIMEOUT) {
625 struct ifnet *ifp = &sc->arpcom.ac_if;
627 if (sc->vr_revid < REV_ID_VT3065_A) {
628 if_printf(ifp, "reset never completed!\n");
630 /* Use newer force reset command */
631 if_printf(ifp, "Using force reset command.\n");
632 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
636 /* Wait a little while for the chip to get its brains in order. */
641 * Probe for a VIA Rhine chip. Check the PCI vendor and device
642 * IDs against our list and return a device name if we find a match.
645 vr_probe(device_t dev)
650 vid = pci_get_vendor(dev);
651 did = pci_get_device(dev);
653 for (t = vr_devs; t->vr_name != NULL; ++t) {
654 if (vid == t->vr_vid && did == t->vr_did) {
655 device_set_desc(dev, t->vr_name);
664 * Attach the interface. Allocate softc structures, do ifmedia
665 * setup and ethernet/BPF attach.
668 vr_attach(device_t dev)
671 uint8_t eaddr[ETHER_ADDR_LEN];
676 sc = device_get_softc(dev);
677 callout_init(&sc->vr_stat_timer);
680 * Handle power management nonsense.
682 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
683 uint32_t iobase, membase, irq;
685 /* Save important PCI config data. */
686 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
687 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
688 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
690 /* Reset the power state. */
691 device_printf(dev, "chip is in D%d power mode "
692 "-- setting to D0\n", pci_get_powerstate(dev));
693 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
695 /* Restore PCI config data. */
696 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
697 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
698 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
701 pci_enable_busmaster(dev);
703 sc->vr_revid = pci_get_revid(dev);
706 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
708 if (sc->vr_res == NULL) {
709 device_printf(dev, "couldn't map ports/memory\n");
713 sc->vr_btag = rman_get_bustag(sc->vr_res);
714 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
716 /* Allocate interrupt */
718 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
719 RF_SHAREABLE | RF_ACTIVE);
721 if (sc->vr_irq == NULL) {
722 device_printf(dev, "couldn't map interrupt\n");
728 * Windows may put the chip in suspend mode when it
729 * shuts down. Be sure to kick it in the head to wake it
732 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
734 ifp = &sc->arpcom.ac_if;
735 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
737 /* Reset the adapter. */
741 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
742 * initialization and disable AUTOPOLL.
744 pci_write_config(dev, VR_PCI_MODE,
745 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
746 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
749 * Get station address. The way the Rhine chips work,
750 * you're not allowed to directly access the EEPROM once
751 * they've been programmed a special way. Consequently,
752 * we need to read the node address from the PAR0 and PAR1
755 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
757 for (i = 0; i < ETHER_ADDR_LEN; i++)
758 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
760 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
761 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
763 if (sc->vr_ldata == NULL) {
764 device_printf(dev, "no memory for list buffers!\n");
769 /* Initialize TX buffer */
770 sc->vr_cdata.vr_tx_buf = contigmalloc(VR_TX_BUF_SIZE, M_DEVBUF,
771 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
772 if (sc->vr_cdata.vr_tx_buf == NULL) {
773 device_printf(dev, "can't allocate tx buffer!\n");
778 /* Set various TX indexes to invalid value */
779 sc->vr_cdata.vr_tx_free_idx = -1;
780 sc->vr_cdata.vr_tx_tail_idx = -1;
781 sc->vr_cdata.vr_tx_head_idx = -1;
785 ifp->if_mtu = ETHERMTU;
786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
787 ifp->if_ioctl = vr_ioctl;
788 ifp->if_start = vr_start;
789 #ifdef DEVICE_POLLING
790 ifp->if_poll = vr_poll;
792 ifp->if_watchdog = vr_watchdog;
793 ifp->if_init = vr_init;
794 ifp->if_baudrate = 10000000;
795 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
796 ifq_set_ready(&ifp->if_snd);
801 if (mii_phy_probe(dev, &sc->vr_miibus,
802 vr_ifmedia_upd, vr_ifmedia_sts)) {
803 if_printf(ifp, "MII without any phy!\n");
808 /* Call MI attach routine. */
809 ether_ifattach(ifp, eaddr);
811 error = bus_setup_intr(dev, sc->vr_irq, 0,
812 vr_intr, sc, &sc->vr_intrhand, NULL);
815 device_printf(dev, "couldn't set up irq\n");
827 vr_detach(device_t dev)
829 struct vr_softc *sc = device_get_softc(dev);
830 struct ifnet *ifp = &sc->arpcom.ac_if;
834 if (device_is_attached(dev)) {
838 if (sc->vr_miibus != NULL)
839 device_delete_child(dev, sc->vr_miibus);
840 bus_generic_detach(dev);
842 if (sc->vr_intrhand != NULL)
843 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
847 if (sc->vr_irq != NULL)
848 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
849 if (sc->vr_res != NULL)
850 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
851 if (sc->vr_ldata != NULL)
852 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
853 if (sc->vr_cdata.vr_tx_buf != NULL)
854 contigfree(sc->vr_cdata.vr_tx_buf, VR_TX_BUF_SIZE, M_DEVBUF);
860 * Initialize the transmit descriptors.
863 vr_list_tx_init(struct vr_softc *sc)
865 struct vr_chain_data *cd;
866 struct vr_list_data *ld;
867 struct vr_chain *tx_chain;
872 tx_chain = cd->vr_tx_chain;
874 for (i = 0; i < VR_TX_LIST_CNT; i++) {
875 tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
876 if (i == (VR_TX_LIST_CNT - 1))
877 tx_chain[i].vr_next_idx = 0;
879 tx_chain[i].vr_next_idx = i + 1;
882 for (i = 0; i < VR_TX_LIST_CNT; ++i) {
886 tx_buf = VR_TX_BUF(sc, i);
887 next_idx = tx_chain[i].vr_next_idx;
889 tx_chain[i].vr_next_desc_paddr =
890 vtophys(tx_chain[next_idx].vr_ptr);
891 tx_chain[i].vr_buf_paddr = vtophys(tx_buf);
894 cd->vr_tx_free_idx = 0;
895 cd->vr_tx_tail_idx = cd->vr_tx_head_idx = -1;
902 * Initialize the RX descriptors and allocate mbufs for them. Note that
903 * we arrange the descriptors in a closed ring, so that the last descriptor
904 * points back to the first.
907 vr_list_rx_init(struct vr_softc *sc)
909 struct vr_chain_data *cd;
910 struct vr_list_data *ld;
916 for (i = 0; i < VR_RX_LIST_CNT; i++) {
917 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
918 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
920 if (i == (VR_RX_LIST_CNT - 1))
924 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
925 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
928 cd->vr_rx_head = &cd->vr_rx_chain[0];
934 * Initialize an RX descriptor and attach an MBUF cluster.
935 * Note: the length fields are only 11 bits wide, which means the
936 * largest size we can specify is 2047. This is important because
937 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
938 * overflow the field and make a mess.
941 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
943 struct mbuf *m_new = NULL;
946 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
949 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
952 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
953 m_new->m_data = m_new->m_ext.ext_buf;
956 m_adj(m_new, sizeof(uint64_t));
959 c->vr_ptr->vr_status = VR_RXSTAT;
960 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
961 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
967 * A frame has been uploaded: pass the resulting mbuf chain up to
968 * the higher level protocols.
971 vr_rxeof(struct vr_softc *sc)
975 struct vr_chain_onefrag *cur_rx;
979 ifp = &sc->arpcom.ac_if;
981 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
983 struct mbuf *m0 = NULL;
985 cur_rx = sc->vr_cdata.vr_rx_head;
986 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
990 * If an error occurs, update stats, clear the
991 * status word and leave the mbuf cluster in place:
992 * it should simply get re-used next time this descriptor
993 * comes up in the ring.
995 if (rxstat & VR_RXSTAT_RXERR) {
997 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
998 if (rxstat & VR_RXSTAT_CRCERR)
999 printf(" crc error");
1000 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1001 printf(" frame alignment error\n");
1002 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1003 printf(" FIFO overflow");
1004 if (rxstat & VR_RXSTAT_GIANT)
1005 printf(" received giant packet");
1006 if (rxstat & VR_RXSTAT_RUNT)
1007 printf(" received runt packet");
1008 if (rxstat & VR_RXSTAT_BUSERR)
1009 printf(" system bus error");
1010 if (rxstat & VR_RXSTAT_BUFFERR)
1011 printf("rx buffer error");
1013 vr_newbuf(sc, cur_rx, m);
1017 /* No errors; receive the packet. */
1018 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1021 * XXX The VIA Rhine chip includes the CRC with every
1022 * received frame, and there's no way to turn this
1023 * behavior off (at least, I can't find anything in
1024 * the manual that explains how to do it) so we have
1025 * to trim off the CRC manually.
1027 total_len -= ETHER_CRC_LEN;
1029 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1030 total_len + ETHER_ALIGN, 0, ifp, NULL);
1031 vr_newbuf(sc, cur_rx, m);
1036 m_adj(m0, ETHER_ALIGN);
1040 (*ifp->if_input)(ifp, m);
1045 vr_rxeoc(struct vr_softc *sc)
1050 ifp = &sc->arpcom.ac_if;
1054 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1057 /* Wait for receiver to stop */
1059 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1061 ; /* Wait for receiver to stop */
1064 if_printf(ifp, "rx shutdown error!\n");
1065 sc->vr_flags |= VR_F_RESTART;
1071 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1072 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1073 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1077 * A frame was downloaded to the chip. It's safe for us to clean up
1081 vr_txeof(struct vr_softc *sc)
1083 struct vr_chain_data *cd;
1084 struct vr_chain *tx_chain;
1087 ifp = &sc->arpcom.ac_if;
1090 /* Reset the timeout timer; if_txeoc will clear it. */
1094 if (cd->vr_tx_head_idx == -1)
1097 tx_chain = cd->vr_tx_chain;
1100 * Go through our tx list and free mbufs for those
1101 * frames that have been transmitted.
1103 while(tx_chain[cd->vr_tx_head_idx].vr_buf != NULL) {
1104 struct vr_chain *cur_tx;
1108 cur_tx = &tx_chain[cd->vr_tx_head_idx];
1109 txstat = cur_tx->vr_ptr->vr_status;
1111 if ((txstat & VR_TXSTAT_ABRT) ||
1112 (txstat & VR_TXSTAT_UDF)) {
1114 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1116 ; /* Wait for chip to shutdown */
1118 if_printf(ifp, "tx shutdown timeout\n");
1119 sc->vr_flags |= VR_F_RESTART;
1122 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1123 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1127 if (txstat & VR_TXSTAT_OWN)
1130 if (txstat & VR_TXSTAT_ERRSUM) {
1132 if (txstat & VR_TXSTAT_DEFER)
1133 ifp->if_collisions++;
1134 if (txstat & VR_TXSTAT_LATECOLL)
1135 ifp->if_collisions++;
1138 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3;
1141 cur_tx->vr_buf = NULL;
1143 if (cd->vr_tx_head_idx == cd->vr_tx_tail_idx) {
1144 cd->vr_tx_head_idx = -1;
1145 cd->vr_tx_tail_idx = -1;
1149 cd->vr_tx_head_idx = cur_tx->vr_next_idx;
1154 * TX 'end of channel' interrupt handler.
1157 vr_txeoc(struct vr_softc *sc)
1161 ifp = &sc->arpcom.ac_if;
1163 if (sc->vr_cdata.vr_tx_head_idx == -1) {
1164 ifp->if_flags &= ~IFF_OACTIVE;
1165 sc->vr_cdata.vr_tx_tail_idx = -1;
1173 struct vr_softc *sc = xsc;
1174 struct mii_data *mii;
1178 if (sc->vr_flags & VR_F_RESTART) {
1179 if_printf(&sc->arpcom.ac_if, "restarting\n");
1183 sc->vr_flags &= ~VR_F_RESTART;
1186 mii = device_get_softc(sc->vr_miibus);
1189 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1197 struct vr_softc *sc;
1202 ifp = &sc->arpcom.ac_if;
1204 /* Supress unwanted interrupts. */
1205 if (!(ifp->if_flags & IFF_UP)) {
1210 /* Disable interrupts. */
1211 if ((ifp->if_flags & IFF_POLLING) == 0)
1212 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1215 status = CSR_READ_2(sc, VR_ISR);
1217 CSR_WRITE_2(sc, VR_ISR, status);
1219 if ((status & VR_INTRS) == 0)
1222 if (status & VR_ISR_RX_OK)
1225 if (status & VR_ISR_RX_DROPPED) {
1226 if_printf(ifp, "rx packet lost\n");
1230 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1231 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1232 if_printf(ifp, "receive error (%04x)", status);
1233 if (status & VR_ISR_RX_NOBUF)
1234 printf(" no buffers");
1235 if (status & VR_ISR_RX_OFLOW)
1236 printf(" overflow");
1237 if (status & VR_ISR_RX_DROPPED)
1238 printf(" packet lost");
1243 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1249 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1250 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1252 if ((status & VR_ISR_UDFI) ||
1253 (status & VR_ISR_TX_ABRT2) ||
1254 (status & VR_ISR_TX_ABRT)) {
1256 if (sc->vr_cdata.vr_tx_head_idx != -1) {
1257 VR_SETBIT16(sc, VR_COMMAND,
1259 VR_SETBIT16(sc, VR_COMMAND,
1269 /* Re-enable interrupts. */
1270 if ((ifp->if_flags & IFF_POLLING) == 0)
1271 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1273 if (!ifq_is_empty(&ifp->if_snd))
1278 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1279 * pointers to the fragment pointers.
1282 vr_encap(struct vr_softc *sc, int chain_idx, struct mbuf *m_head)
1289 KASSERT(chain_idx >= 0 && chain_idx < VR_TX_LIST_CNT,
1290 ("%s: chain idx(%d) out of range 0-%d",
1291 sc->arpcom.ac_if.if_xname, chain_idx, VR_TX_LIST_CNT));
1294 * The VIA Rhine wants packet buffers to be longword
1295 * aligned, but very often our mbufs aren't. Rather than
1296 * waste time trying to decide when to copy and when not
1297 * to copy, just do it all the time.
1299 tx_buf = VR_TX_BUF(sc, chain_idx);
1300 m_copydata(m_head, 0, m_head->m_pkthdr.len, tx_buf);
1301 len = m_head->m_pkthdr.len;
1304 * The Rhine chip doesn't auto-pad, so we have to make
1305 * sure to pad short frames out to the minimum frame length
1308 if (len < VR_MIN_FRAMELEN) {
1309 bzero(tx_buf + len, VR_MIN_FRAMELEN - len);
1310 len = VR_MIN_FRAMELEN;
1313 c = &sc->vr_cdata.vr_tx_chain[chain_idx];
1317 f->vr_data = c->vr_buf_paddr;
1319 f->vr_ctl |= (VR_TXCTL_TLINK | VR_TXCTL_FIRSTFRAG);
1320 f->vr_ctl |= (VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1322 f->vr_next = c->vr_next_desc_paddr;
1328 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1329 * to the mbuf data regions directly in the transmit lists. We also save a
1330 * copy of the pointers since the transmit list fragment pointers are
1331 * physical addresses.
1334 vr_start(struct ifnet *ifp)
1336 struct vr_softc *sc;
1337 struct vr_chain_data *cd;
1338 struct vr_chain *tx_chain;
1339 int cur_tx_idx, start_tx_idx, prev_tx_idx;
1341 if (ifp->if_flags & IFF_OACTIVE)
1346 tx_chain = cd->vr_tx_chain;
1348 start_tx_idx = cd->vr_tx_free_idx;
1349 cur_tx_idx = prev_tx_idx = -1;
1351 /* Check for an available queue slot. If there are none, punt. */
1352 if (tx_chain[start_tx_idx].vr_buf != NULL) {
1353 ifp->if_flags |= IFF_OACTIVE;
1357 while(tx_chain[cd->vr_tx_free_idx].vr_buf == NULL) {
1358 struct mbuf *m_head;
1359 struct vr_chain *cur_tx;
1361 m_head = ifq_poll(&ifp->if_snd);
1365 /* Pick a descriptor off the free list. */
1366 cur_tx_idx = cd->vr_tx_free_idx;
1367 cur_tx = &tx_chain[cur_tx_idx];
1369 /* Pack the data into the descriptor. */
1370 if (vr_encap(sc, cur_tx_idx, m_head)) {
1371 ifp->if_flags |= IFF_OACTIVE;
1372 cur_tx_idx = prev_tx_idx;
1376 m_head = ifq_dequeue(&ifp->if_snd);
1379 if (cur_tx_idx != start_tx_idx)
1380 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1382 BPF_MTAP(ifp, m_head);
1385 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1386 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1388 /* Iff everything went OK, we bump up free index. */
1389 prev_tx_idx = cur_tx_idx;
1390 cd->vr_tx_free_idx = cur_tx->vr_next_idx;
1393 /* If there are no frames queued, bail. */
1394 if (cur_tx_idx == -1)
1397 sc->vr_cdata.vr_tx_tail_idx = cur_tx_idx;
1399 if (sc->vr_cdata.vr_tx_head_idx == -1)
1400 sc->vr_cdata.vr_tx_head_idx = start_tx_idx;
1403 * Set a timeout in case the chip goes out to lunch.
1411 struct vr_softc *sc = xsc;
1412 struct ifnet *ifp = &sc->arpcom.ac_if;
1413 struct mii_data *mii;
1416 mii = device_get_softc(sc->vr_miibus);
1420 /* Cancel pending I/O and free all RX/TX buffers. */
1424 /* Set our station address. */
1425 for (i = 0; i < ETHER_ADDR_LEN; i++)
1426 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1429 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1430 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1433 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1434 * so we must set both.
1436 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1437 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1439 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1440 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1442 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1443 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1445 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1446 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1448 /* Init circular RX list. */
1449 if (vr_list_rx_init(sc) == ENOBUFS) {
1452 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1456 /* Init tx descriptors. */
1457 vr_list_tx_init(sc);
1459 /* If we want promiscuous mode, set the allframes bit. */
1460 if (ifp->if_flags & IFF_PROMISC)
1461 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1463 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1465 /* Set capture broadcast bit to capture broadcast frames. */
1466 if (ifp->if_flags & IFF_BROADCAST)
1467 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1469 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1472 * Program the multicast filter, if necessary.
1477 * Load the address of the RX list.
1479 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1481 /* Enable receiver and transmitter. */
1482 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1483 VR_CMD_TX_ON|VR_CMD_RX_ON|
1486 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1489 * Enable interrupts, unless we are polling.
1491 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1492 if ((ifp->if_flags & IFF_POLLING) == 0)
1493 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1497 ifp->if_flags |= IFF_RUNNING;
1498 ifp->if_flags &= ~IFF_OACTIVE;
1502 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1506 * Set media options.
1509 vr_ifmedia_upd(struct ifnet *ifp)
1511 struct vr_softc *sc;
1515 if (ifp->if_flags & IFF_UP)
1522 * Report current media status.
1525 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1527 struct vr_softc *sc;
1528 struct mii_data *mii;
1531 mii = device_get_softc(sc->vr_miibus);
1533 ifmr->ifm_active = mii->mii_media_active;
1534 ifmr->ifm_status = mii->mii_media_status;
1538 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1540 struct vr_softc *sc = ifp->if_softc;
1541 struct ifreq *ifr = (struct ifreq *) data;
1542 struct mii_data *mii;
1549 if (ifp->if_flags & IFF_UP) {
1552 if (ifp->if_flags & IFF_RUNNING)
1564 mii = device_get_softc(sc->vr_miibus);
1565 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1568 error = ether_ioctl(ifp, command, data);
1577 #ifdef DEVICE_POLLING
1580 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1582 struct vr_softc *sc = ifp->if_softc;
1586 /* disable interrupts */
1587 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1589 case POLL_DEREGISTER:
1590 /* enable interrupts */
1591 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1601 vr_watchdog(struct ifnet *ifp)
1603 struct vr_softc *sc;
1608 if_printf(ifp, "watchdog timeout\n");
1610 #ifdef DEVICE_POLLING
1611 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1612 if_printf(ifp, "ints don't seem to be working, "
1613 "emergency switch to polling\n");
1614 emergency_poll_enable("if_vr");
1615 ether_poll_register(ifp); /* XXX illegal */
1624 if (!ifq_is_empty(&ifp->if_snd))
1629 * Stop the adapter and free any mbufs allocated to the
1633 vr_stop(struct vr_softc *sc)
1638 ifp = &sc->arpcom.ac_if;
1641 callout_stop(&sc->vr_stat_timer);
1643 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1644 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1645 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1646 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1647 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1650 * Free data in the RX lists.
1652 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1653 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1654 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1655 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1658 bzero(&sc->vr_ldata->vr_rx_list, sizeof(sc->vr_ldata->vr_rx_list));
1661 * Reset the TX list buffer pointers.
1663 for (i = 0; i < VR_TX_LIST_CNT; i++)
1664 sc->vr_cdata.vr_tx_chain[i].vr_buf = NULL;
1666 bzero(&sc->vr_ldata->vr_tx_list, sizeof(sc->vr_ldata->vr_tx_list));
1668 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1672 * Stop all chip I/O so that the kernel's probe routines don't
1673 * get confused by errant DMAs when rebooting.
1676 vr_shutdown(device_t dev)
1678 struct vr_softc *sc;
1680 sc = device_get_softc(dev);