sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* DragonFly device entry points.                                           */
 317 /****************************************************************************/
 318 static int      bce_probe(device_t);
 319 static int      bce_attach(device_t);
 320 static int      bce_detach(device_t);
 321 static void     bce_shutdown(device_t);
 322
 323 /****************************************************************************/
 324 /* BCE Debug Data Structure Dump Routines                                   */
 325 /****************************************************************************/
 326 #ifdef BCE_DEBUG
 327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 333                                 struct l2_fhdr *) __unused;
 334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_status_block(struct bce_softc *);
 337 static void     bce_dump_driver_state(struct bce_softc *);
 338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 339 static void     bce_dump_hw_state(struct bce_softc *);
 340 static void     bce_dump_txp_state(struct bce_softc *);
 341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 343 static void     bce_freeze_controller(struct bce_softc *) __unused;
 344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 345 static void     bce_breakpoint(struct bce_softc *);
 346 #endif  /* BCE_DEBUG */
 347
 348
 349 /****************************************************************************/
 350 /* BCE Register/Memory Access Routines                                      */
 351 /****************************************************************************/
 352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 357 static int      bce_miibus_read_reg(device_t, int, int);
 358 static int      bce_miibus_write_reg(device_t, int, int, int);
 359 static void     bce_miibus_statchg(device_t);
 360
 361
 362 /****************************************************************************/
 363 /* BCE NVRAM Access Routines                                                */
 364 /****************************************************************************/
 365 static int      bce_acquire_nvram_lock(struct bce_softc *);
 366 static int      bce_release_nvram_lock(struct bce_softc *);
 367 static void     bce_enable_nvram_access(struct bce_softc *);
 368 static void     bce_disable_nvram_access(struct bce_softc *);
 369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 370                                      uint32_t);
 371 static int      bce_init_nvram(struct bce_softc *);
 372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 373 static int      bce_nvram_test(struct bce_softc *);
 374
 375 /****************************************************************************/
 376 /* BCE DMA Allocate/Free Routines                                           */
 377 /****************************************************************************/
 378 static int      bce_dma_alloc(struct bce_softc *);
 379 static void     bce_dma_free(struct bce_softc *);
 380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 381
 382 /****************************************************************************/
 383 /* BCE Firmware Synchronization and Load                                    */
 384 /****************************************************************************/
 385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 387                                  uint32_t, uint32_t);
 388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 389                                 struct fw_info *);
 390 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 391 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 392 static void     bce_start_rxp_cpu(struct bce_softc *);
 393 static void     bce_init_rxp_cpu(struct bce_softc *);
 394 static void     bce_init_txp_cpu(struct bce_softc *);
 395 static void     bce_init_tpat_cpu(struct bce_softc *);
 396 static void     bce_init_cp_cpu(struct bce_softc *);
 397 static void     bce_init_com_cpu(struct bce_softc *);
 398 static void     bce_init_cpus(struct bce_softc *);
 399
 400 static void     bce_stop(struct bce_softc *);
 401 static int      bce_reset(struct bce_softc *, uint32_t);
 402 static int      bce_chipinit(struct bce_softc *);
 403 static int      bce_blockinit(struct bce_softc *);
 404 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 405                                uint32_t *, int);
 406 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 407 static void     bce_probe_pci_caps(struct bce_softc *);
 408 static void     bce_print_adapter_info(struct bce_softc *);
 409 static void     bce_get_media(struct bce_softc *);
 410
 411 static void     bce_init_tx_context(struct bce_softc *);
 412 static int      bce_init_tx_chain(struct bce_softc *);
 413 static void     bce_init_rx_context(struct bce_softc *);
 414 static int      bce_init_rx_chain(struct bce_softc *);
 415 static void     bce_free_rx_chain(struct bce_softc *);
 416 static void     bce_free_tx_chain(struct bce_softc *);
 417
 418 static int      bce_encap(struct bce_softc *, struct mbuf **);
 419 static void     bce_start(struct ifnet *);
 420 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 421 static void     bce_watchdog(struct ifnet *);
 422 static int      bce_ifmedia_upd(struct ifnet *);
 423 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 424 static void     bce_init(void *);
 425 static void     bce_mgmt_init(struct bce_softc *);
 426
 427 static int      bce_init_ctx(struct bce_softc *);
 428 static void     bce_get_mac_addr(struct bce_softc *);
 429 static void     bce_set_mac_addr(struct bce_softc *);
 430 static void     bce_phy_intr(struct bce_softc *);
 431 static void     bce_rx_intr(struct bce_softc *, int);
 432 static void     bce_tx_intr(struct bce_softc *);
 433 static void     bce_disable_intr(struct bce_softc *);
 434 static void     bce_enable_intr(struct bce_softc *, int);
 435
 436 #ifdef DEVICE_POLLING
 437 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 438 #endif
 439 static void     bce_intr(struct bce_softc *);
 440 static void     bce_intr_legacy(void *);
 441 static void     bce_intr_msi(void *);
 442 static void     bce_intr_msi_oneshot(void *);
 443 static void     bce_set_rx_mode(struct bce_softc *);
 444 static void     bce_stats_update(struct bce_softc *);
 445 static void     bce_tick(void *);
 446 static void     bce_tick_serialized(struct bce_softc *);
 447 static void     bce_pulse(void *);
 448 static void     bce_add_sysctls(struct bce_softc *);
 449
 450 static void     bce_coal_change(struct bce_softc *);
 451 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 452 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 453 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 454 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 457 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 458 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 459 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 460                                        uint32_t *, uint32_t);
 461
 462 /*
 463  * NOTE:
 464  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 465  * takes 1023 as the TX ticks limit.  However, using 1023 will
 466  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 467  * there is _no_ network activity on the NIC.
 468  */
 469 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 470 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 471 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 472 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 473 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 474 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 475 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 476 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 477
 478 static int      bce_msi_enable = 1;
 479
 480 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 481 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 482 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 483 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 484 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 485 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 486 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 487 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 488 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 489
 490 /****************************************************************************/
 491 /* DragonFly device dispatch table.                                         */
 492 /****************************************************************************/
 493 static device_method_t bce_methods[] = {
 494         /* Device interface */
 495         DEVMETHOD(device_probe,         bce_probe),
 496         DEVMETHOD(device_attach,        bce_attach),
 497         DEVMETHOD(device_detach,        bce_detach),
 498         DEVMETHOD(device_shutdown,      bce_shutdown),
 499
 500         /* bus interface */
 501         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 502         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 503
 504         /* MII interface */
 505         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 506         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 507         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 508
 509         { 0, 0 }
 510 };
 511
 512 static driver_t bce_driver = {
 513         "bce",
 514         bce_methods,
 515         sizeof(struct bce_softc)
 516 };
 517
 518 static devclass_t bce_devclass;
 519
 520
 521 DECLARE_DUMMY_MODULE(if_bce);
 522 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 523 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 524 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 525
 526
 527 /****************************************************************************/
 528 /* Device probe function.                                                   */
 529 /*                                                                          */
 530 /* Compares the device to the driver's list of supported devices and        */
 531 /* reports back to the OS whether this is the right driver for the device.  */
 532 /*                                                                          */
 533 /* Returns:                                                                 */
 534 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 535 /****************************************************************************/
 536 static int
 537 bce_probe(device_t dev)
 538 {
 539         struct bce_type *t;
 540         uint16_t vid, did, svid, sdid;
 541
 542         /* Get the data for the device to be probed. */
 543         vid  = pci_get_vendor(dev);
 544         did  = pci_get_device(dev);
 545         svid = pci_get_subvendor(dev);
 546         sdid = pci_get_subdevice(dev);
 547
 548         /* Look through the list of known devices for a match. */
 549         for (t = bce_devs; t->bce_name != NULL; ++t) {
 550                 if (vid == t->bce_vid && did == t->bce_did &&
 551                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 552                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 553                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 554                         char *descbuf;
 555
 556                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 557
 558                         /* Print out the device identity. */
 559                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 560                                   t->bce_name,
 561                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 562
 563                         device_set_desc_copy(dev, descbuf);
 564                         kfree(descbuf, M_TEMP);
 565                         return 0;
 566                 }
 567         }
 568         return ENXIO;
 569 }
 570
 571
 572 /****************************************************************************/
 573 /* PCI Capabilities Probe Function.                                         */
 574 /*                                                                          */
 575 /* Walks the PCI capabiites list for the device to find what features are   */
 576 /* supported.                                                               */
 577 /*                                                                          */
 578 /* Returns:                                                                 */
 579 /*   None.                                                                  */
 580 /****************************************************************************/
 581 static void
 582 bce_print_adapter_info(struct bce_softc *sc)
 583 {
 584         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 585
 586         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 587                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 588
 589         /* Bus info. */
 590         if (sc->bce_flags & BCE_PCIE_FLAG) {
 591                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 592                 switch (sc->link_speed) {
 593                 case 1:
 594                         kprintf("2.5Gbps); ");
 595                         break;
 596                 case 2:
 597                         kprintf("5Gbps); ");
 598                         break;
 599                 default:
 600                         kprintf("Unknown link speed); ");
 601                         break;
 602                 }
 603         } else {
 604                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 605                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 606                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 607                     sc->bus_speed_mhz);
 608         }
 609
 610         /* Firmware version and device features. */
 611         kprintf("B/C (%s)", sc->bce_bc_ver);
 612
 613         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 614             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 615                 kprintf("; Flags(");
 616                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 617                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 618                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 619                         kprintf(" 2.5G");
 620                 kprintf(")");
 621         }
 622         kprintf("\n");
 623 }
 624
 625
 626 /****************************************************************************/
 627 /* PCI Capabilities Probe Function.                                         */
 628 /*                                                                          */
 629 /* Walks the PCI capabiites list for the device to find what features are   */
 630 /* supported.                                                               */
 631 /*                                                                          */
 632 /* Returns:                                                                 */
 633 /*   None.                                                                  */
 634 /****************************************************************************/
 635 static void
 636 bce_probe_pci_caps(struct bce_softc *sc)
 637 {
 638         device_t dev = sc->bce_dev;
 639         uint8_t ptr;
 640
 641         if (pci_is_pcix(dev))
 642                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 643
 644         ptr = pci_get_pciecap_ptr(dev);
 645         if (ptr) {
 646                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 647
 648                 sc->link_speed = link_status & 0xf;
 649                 sc->link_width = (link_status >> 4) & 0x3f;
 650                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 651                 sc->bce_flags |= BCE_PCIE_FLAG;
 652         }
 653 }
 654
 655
 656 /****************************************************************************/
 657 /* Device attach function.                                                  */
 658 /*                                                                          */
 659 /* Allocates device resources, performs secondary chip identification,      */
 660 /* resets and initializes the hardware, and initializes driver instance     */
 661 /* variables.                                                               */
 662 /*                                                                          */
 663 /* Returns:                                                                 */
 664 /*   0 on success, positive value on failure.                               */
 665 /****************************************************************************/
 666 static int
 667 bce_attach(device_t dev)
 668 {
 669         struct bce_softc *sc = device_get_softc(dev);
 670         struct ifnet *ifp = &sc->arpcom.ac_if;
 671         uint32_t val;
 672         u_int irq_flags;
 673         void (*irq_handle)(void *);
 674         int rid, rc = 0;
 675         int i, j;
 676
 677         sc->bce_dev = dev;
 678         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 679
 680         pci_enable_busmaster(dev);
 681
 682         bce_probe_pci_caps(sc);
 683
 684         /* Allocate PCI memory resources. */
 685         rid = PCIR_BAR(0);
 686         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 687                                                  RF_ACTIVE | PCI_RF_DENSE);
 688         if (sc->bce_res_mem == NULL) {
 689                 device_printf(dev, "PCI memory allocation failed\n");
 690                 return ENXIO;
 691         }
 692         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 693         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 694
 695         /* Allocate PCI IRQ resources. */
 696         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 697             &sc->bce_irq_rid, &irq_flags);
 698
 699         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 700             &sc->bce_irq_rid, irq_flags);
 701         if (sc->bce_res_irq == NULL) {
 702                 device_printf(dev, "PCI map interrupt failed\n");
 703                 rc = ENXIO;
 704                 goto fail;
 705         }
 706
 707         /*
 708          * Configure byte swap and enable indirect register access.
 709          * Rely on CPU to do target byte swapping on big endian systems.
 710          * Access to registers outside of PCI configurtion space are not
 711          * valid until this is done.
 712          */
 713         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 714                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 715                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 716
 717         /* Save ASIC revsion info. */
 718         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 719
 720         /* Weed out any non-production controller revisions. */
 721         switch (BCE_CHIP_ID(sc)) {
 722         case BCE_CHIP_ID_5706_A0:
 723         case BCE_CHIP_ID_5706_A1:
 724         case BCE_CHIP_ID_5708_A0:
 725         case BCE_CHIP_ID_5708_B0:
 726         case BCE_CHIP_ID_5709_A0:
 727         case BCE_CHIP_ID_5709_B0:
 728         case BCE_CHIP_ID_5709_B1:
 729 #ifdef foo
 730         /* 5709C B2 seems to work fine */
 731         case BCE_CHIP_ID_5709_B2:
 732 #endif
 733                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 734                               BCE_CHIP_ID(sc));
 735                 rc = ENODEV;
 736                 goto fail;
 737         }
 738
 739         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
 740                 irq_handle = bce_intr_legacy;
 741         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
 742                 irq_handle = bce_intr_msi;
 743                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 744                         irq_handle = bce_intr_msi_oneshot;
 745                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
 746                 }
 747         } else {
 748                 panic("%s: unsupported intr type %d\n",
 749                     device_get_nameunit(dev), sc->bce_irq_type);
 750         }
 751
 752         /*
 753          * Find the base address for shared memory access.
 754          * Newer versions of bootcode use a signature and offset
 755          * while older versions use a fixed address.
 756          */
 757         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 758         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 759             BCE_SHM_HDR_SIGNATURE_SIG) {
 760                 /* Multi-port devices use different offsets in shared memory. */
 761                 sc->bce_shmem_base = REG_RD_IND(sc,
 762                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 763         } else {
 764                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 765         }
 766         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 767
 768         /* Fetch the bootcode revision. */
 769         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 770         for (i = 0, j = 0; i < 3; i++) {
 771                 uint8_t num;
 772                 int k, skip0;
 773
 774                 num = (uint8_t)(val >> (24 - (i * 8)));
 775                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 776                         if (num >= k || !skip0 || k == 1) {
 777                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 778                                 skip0 = 0;
 779                         }
 780                 }
 781                 if (i != 2)
 782                         sc->bce_bc_ver[j++] = '.';
 783         }
 784
 785         /* Check if any management firwmare is running. */
 786         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 787         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 788                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 789
 790                 /* Allow time for firmware to enter the running state. */
 791                 for (i = 0; i < 30; i++) {
 792                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 793                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 794                                 break;
 795                         DELAY(10000);
 796                 }
 797         }
 798
 799         /* Check the current bootcode state. */
 800         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 801             BCE_CONDITION_MFW_RUN_MASK;
 802         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 803             val != BCE_CONDITION_MFW_RUN_NONE) {
 804                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 805
 806                 for (i = 0, j = 0; j < 3; j++) {
 807                         val = bce_reg_rd_ind(sc, addr + j * 4);
 808                         val = bswap32(val);
 809                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 810                         i += 4;
 811                 }
 812         }
 813
 814         /* Get PCI bus information (speed and type). */
 815         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 816         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 817                 uint32_t clkreg;
 818
 819                 sc->bce_flags |= BCE_PCIX_FLAG;
 820
 821                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 822                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 823                 switch (clkreg) {
 824                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 825                         sc->bus_speed_mhz = 133;
 826                         break;
 827
 828                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 829                         sc->bus_speed_mhz = 100;
 830                         break;
 831
 832                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 833                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 834                         sc->bus_speed_mhz = 66;
 835                         break;
 836
 837                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 838                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 839                         sc->bus_speed_mhz = 50;
 840                         break;
 841
 842                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 844                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 845                         sc->bus_speed_mhz = 33;
 846                         break;
 847                 }
 848         } else {
 849                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 850                         sc->bus_speed_mhz = 66;
 851                 else
 852                         sc->bus_speed_mhz = 33;
 853         }
 854
 855         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 856                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 857
 858         /* Reset the controller. */
 859         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 860         if (rc != 0)
 861                 goto fail;
 862
 863         /* Initialize the controller. */
 864         rc = bce_chipinit(sc);
 865         if (rc != 0) {
 866                 device_printf(dev, "Controller initialization failed!\n");
 867                 goto fail;
 868         }
 869
 870         /* Perform NVRAM test. */
 871         rc = bce_nvram_test(sc);
 872         if (rc != 0) {
 873                 device_printf(dev, "NVRAM test failed!\n");
 874                 goto fail;
 875         }
 876
 877         /* Fetch the permanent Ethernet MAC address. */
 878         bce_get_mac_addr(sc);
 879
 880         /*
 881          * Trip points control how many BDs
 882          * should be ready before generating an
 883          * interrupt while ticks control how long
 884          * a BD can sit in the chain before
 885          * generating an interrupt.  Set the default
 886          * values for the RX and TX rings.
 887          */
 888
 889 #ifdef BCE_DRBUG
 890         /* Force more frequent interrupts. */
 891         sc->bce_tx_quick_cons_trip_int = 1;
 892         sc->bce_tx_quick_cons_trip     = 1;
 893         sc->bce_tx_ticks_int           = 0;
 894         sc->bce_tx_ticks               = 0;
 895
 896         sc->bce_rx_quick_cons_trip_int = 1;
 897         sc->bce_rx_quick_cons_trip     = 1;
 898         sc->bce_rx_ticks_int           = 0;
 899         sc->bce_rx_ticks               = 0;
 900 #else
 901         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 902         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 903         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 904         sc->bce_tx_ticks               = bce_tx_ticks;
 905
 906         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 907         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 908         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 909         sc->bce_rx_ticks               = bce_rx_ticks;
 910 #endif
 911
 912         /* Update statistics once every second. */
 913         sc->bce_stats_ticks = 1000000 & 0xffff00;
 914
 915         /* Find the media type for the adapter. */
 916         bce_get_media(sc);
 917
 918         /* Allocate DMA memory resources. */
 919         rc = bce_dma_alloc(sc);
 920         if (rc != 0) {
 921                 device_printf(dev, "DMA resource allocation failed!\n");
 922                 goto fail;
 923         }
 924
 925         /* Initialize the ifnet interface. */
 926         ifp->if_softc = sc;
 927         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 928         ifp->if_ioctl = bce_ioctl;
 929         ifp->if_start = bce_start;
 930         ifp->if_init = bce_init;
 931         ifp->if_watchdog = bce_watchdog;
 932 #ifdef DEVICE_POLLING
 933         ifp->if_poll = bce_poll;
 934 #endif
 935         ifp->if_mtu = ETHERMTU;
 936         ifp->if_hwassist = BCE_IF_HWASSIST;
 937         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 938         ifp->if_capenable = ifp->if_capabilities;
 939         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 940         ifq_set_ready(&ifp->if_snd);
 941
 942         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 943                 ifp->if_baudrate = IF_Gbps(2.5);
 944         else
 945                 ifp->if_baudrate = IF_Gbps(1);
 946
 947         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 948         sc->mbuf_alloc_size  = MCLBYTES;
 949
 950         /* Look for our PHY. */
 951         rc = mii_phy_probe(dev, &sc->bce_miibus,
 952                            bce_ifmedia_upd, bce_ifmedia_sts);
 953         if (rc != 0) {
 954                 device_printf(dev, "PHY probe failed!\n");
 955                 goto fail;
 956         }
 957
 958         /* Attach to the Ethernet interface list. */
 959         ether_ifattach(ifp, sc->eaddr, NULL);
 960
 961         callout_init_mp(&sc->bce_tick_callout);
 962         callout_init_mp(&sc->bce_pulse_callout);
 963
 964         /* Hookup IRQ last. */
 965         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
 966                             &sc->bce_intrhand, ifp->if_serializer);
 967         if (rc != 0) {
 968                 device_printf(dev, "Failed to setup IRQ!\n");
 969                 ether_ifdetach(ifp);
 970                 goto fail;
 971         }
 972
 973         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 974         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 975
 976         /* Print some important debugging info. */
 977         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 978
 979         /* Add the supported sysctls to the kernel. */
 980         bce_add_sysctls(sc);
 981
 982         /*
 983          * The chip reset earlier notified the bootcode that
 984          * a driver is present.  We now need to start our pulse
 985          * routine so that the bootcode is reminded that we're
 986          * still running.
 987          */
 988         bce_pulse(sc);
 989
 990         /* Get the firmware running so IPMI still works */
 991         bce_mgmt_init(sc);
 992
 993         if (bootverbose)
 994                 bce_print_adapter_info(sc);
 995
 996         return 0;
 997 fail:
 998         bce_detach(dev);
 999         return(rc);
1000 }
1001
1002
1003 /****************************************************************************/
1004 /* Device detach function.                                                  */
1005 /*                                                                          */
1006 /* Stops the controller, resets the controller, and releases resources.     */
1007 /*                                                                          */
1008 /* Returns:                                                                 */
1009 /*   0 on success, positive value on failure.                               */
1010 /****************************************************************************/
1011 static int
1012 bce_detach(device_t dev)
1013 {
1014         struct bce_softc *sc = device_get_softc(dev);
1015
1016         if (device_is_attached(dev)) {
1017                 struct ifnet *ifp = &sc->arpcom.ac_if;
1018                 uint32_t msg;
1019
1020                 /* Stop and reset the controller. */
1021                 lwkt_serialize_enter(ifp->if_serializer);
1022                 callout_stop(&sc->bce_pulse_callout);
1023                 bce_stop(sc);
1024                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1025                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1026                 else
1027                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1028                 bce_reset(sc, msg);
1029                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1030                 lwkt_serialize_exit(ifp->if_serializer);
1031
1032                 ether_ifdetach(ifp);
1033         }
1034
1035         /* If we have a child device on the MII bus remove it too. */
1036         if (sc->bce_miibus)
1037                 device_delete_child(dev, sc->bce_miibus);
1038         bus_generic_detach(dev);
1039
1040         if (sc->bce_res_irq != NULL) {
1041                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1042                     sc->bce_res_irq);
1043         }
1044
1045         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1046                 pci_release_msi(dev);
1047
1048         if (sc->bce_res_mem != NULL) {
1049                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1050                                      sc->bce_res_mem);
1051         }
1052
1053         bce_dma_free(sc);
1054
1055         if (sc->bce_sysctl_tree != NULL)
1056                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1057
1058         return 0;
1059 }
1060
1061
1062 /****************************************************************************/
1063 /* Device shutdown function.                                                */
1064 /*                                                                          */
1065 /* Stops and resets the controller.                                         */
1066 /*                                                                          */
1067 /* Returns:                                                                 */
1068 /*   Nothing                                                                */
1069 /****************************************************************************/
1070 static void
1071 bce_shutdown(device_t dev)
1072 {
1073         struct bce_softc *sc = device_get_softc(dev);
1074         struct ifnet *ifp = &sc->arpcom.ac_if;
1075         uint32_t msg;
1076
1077         lwkt_serialize_enter(ifp->if_serializer);
1078         bce_stop(sc);
1079         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1080                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1081         else
1082                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1083         bce_reset(sc, msg);
1084         lwkt_serialize_exit(ifp->if_serializer);
1085 }
1086
1087
1088 /****************************************************************************/
1089 /* Indirect register read.                                                  */
1090 /*                                                                          */
1091 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1092 /* configuration space.  Using this mechanism avoids issues with posted     */
1093 /* reads but is much slower than memory-mapped I/O.                         */
1094 /*                                                                          */
1095 /* Returns:                                                                 */
1096 /*   The value of the register.                                             */
1097 /****************************************************************************/
1098 static uint32_t
1099 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1100 {
1101         device_t dev = sc->bce_dev;
1102
1103         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1104 #ifdef BCE_DEBUG
1105         {
1106                 uint32_t val;
1107                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1108                 DBPRINT(sc, BCE_EXCESSIVE,
1109                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1110                         __func__, offset, val);
1111                 return val;
1112         }
1113 #else
1114         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1115 #endif
1116 }
1117
1118
1119 /****************************************************************************/
1120 /* Indirect register write.                                                 */
1121 /*                                                                          */
1122 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1123 /* configuration space.  Using this mechanism avoids issues with posted     */
1124 /* writes but is muchh slower than memory-mapped I/O.                       */
1125 /*                                                                          */
1126 /* Returns:                                                                 */
1127 /*   Nothing.                                                               */
1128 /****************************************************************************/
1129 static void
1130 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1131 {
1132         device_t dev = sc->bce_dev;
1133
1134         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1135                 __func__, offset, val);
1136
1137         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1138         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1139 }
1140
1141
1142 /****************************************************************************/
1143 /* Shared memory write.                                                     */
1144 /*                                                                          */
1145 /* Writes NetXtreme II shared memory region.                                */
1146 /*                                                                          */
1147 /* Returns:                                                                 */
1148 /*   Nothing.                                                               */
1149 /****************************************************************************/
1150 static void
1151 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1152 {
1153         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1154 }
1155
1156
1157 /****************************************************************************/
1158 /* Shared memory read.                                                      */
1159 /*                                                                          */
1160 /* Reads NetXtreme II shared memory region.                                 */
1161 /*                                                                          */
1162 /* Returns:                                                                 */
1163 /*   The 32 bit value read.                                                 */
1164 /****************************************************************************/
1165 static u32
1166 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1167 {
1168         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1169 }
1170
1171
1172 /****************************************************************************/
1173 /* Context memory write.                                                    */
1174 /*                                                                          */
1175 /* The NetXtreme II controller uses context memory to track connection      */
1176 /* information for L2 and higher network protocols.                         */
1177 /*                                                                          */
1178 /* Returns:                                                                 */
1179 /*   Nothing.                                                               */
1180 /****************************************************************************/
1181 static void
1182 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1183     uint32_t ctx_val)
1184 {
1185         uint32_t idx, offset = ctx_offset + cid_addr;
1186         uint32_t val, retry_cnt = 5;
1187
1188         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1189             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1190                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1191                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1192
1193                 for (idx = 0; idx < retry_cnt; idx++) {
1194                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1195                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1196                                 break;
1197                         DELAY(5);
1198                 }
1199
1200                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1201                         device_printf(sc->bce_dev,
1202                             "Unable to write CTX memory: "
1203                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1204                             cid_addr, ctx_offset);
1205                 }
1206         } else {
1207                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1208                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1209         }
1210 }
1211
1212
1213 /****************************************************************************/
1214 /* PHY register read.                                                       */
1215 /*                                                                          */
1216 /* Implements register reads on the MII bus.                                */
1217 /*                                                                          */
1218 /* Returns:                                                                 */
1219 /*   The value of the register.                                             */
1220 /****************************************************************************/
1221 static int
1222 bce_miibus_read_reg(device_t dev, int phy, int reg)
1223 {
1224         struct bce_softc *sc = device_get_softc(dev);
1225         uint32_t val;
1226         int i;
1227
1228         /* Make sure we are accessing the correct PHY address. */
1229         if (phy != sc->bce_phy_addr) {
1230                 DBPRINT(sc, BCE_VERBOSE,
1231                         "Invalid PHY address %d for PHY read!\n", phy);
1232                 return 0;
1233         }
1234
1235         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1236                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1237                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1238
1239                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1240                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1241
1242                 DELAY(40);
1243         }
1244
1245         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1246               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1247               BCE_EMAC_MDIO_COMM_START_BUSY;
1248         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1249
1250         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1251                 DELAY(10);
1252
1253                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1254                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1255                         DELAY(5);
1256
1257                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1258                         val &= BCE_EMAC_MDIO_COMM_DATA;
1259                         break;
1260                 }
1261         }
1262
1263         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1264                 if_printf(&sc->arpcom.ac_if,
1265                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1266                           phy, reg);
1267                 val = 0x0;
1268         } else {
1269                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1270         }
1271
1272         DBPRINT(sc, BCE_EXCESSIVE,
1273                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1274                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1275
1276         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1277                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1278                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1279
1280                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1281                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1282
1283                 DELAY(40);
1284         }
1285         return (val & 0xffff);
1286 }
1287
1288
1289 /****************************************************************************/
1290 /* PHY register write.                                                      */
1291 /*                                                                          */
1292 /* Implements register writes on the MII bus.                               */
1293 /*                                                                          */
1294 /* Returns:                                                                 */
1295 /*   The value of the register.                                             */
1296 /****************************************************************************/
1297 static int
1298 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1299 {
1300         struct bce_softc *sc = device_get_softc(dev);
1301         uint32_t val1;
1302         int i;
1303
1304         /* Make sure we are accessing the correct PHY address. */
1305         if (phy != sc->bce_phy_addr) {
1306                 DBPRINT(sc, BCE_WARN,
1307                         "Invalid PHY address %d for PHY write!\n", phy);
1308                 return(0);
1309         }
1310
1311         DBPRINT(sc, BCE_EXCESSIVE,
1312                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1313                 __func__, phy, (uint16_t)(reg & 0xffff),
1314                 (uint16_t)(val & 0xffff));
1315
1316         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1317                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1318                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1319
1320                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1321                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1322
1323                 DELAY(40);
1324         }
1325
1326         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1327                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1328                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1329         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1330
1331         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1332                 DELAY(10);
1333
1334                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1335                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1336                         DELAY(5);
1337                         break;
1338                 }
1339         }
1340
1341         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1342                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1343
1344         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1345                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1346                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1347
1348                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1349                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1350
1351                 DELAY(40);
1352         }
1353         return 0;
1354 }
1355
1356
1357 /****************************************************************************/
1358 /* MII bus status change.                                                   */
1359 /*                                                                          */
1360 /* Called by the MII bus driver when the PHY establishes link to set the    */
1361 /* MAC interface registers.                                                 */
1362 /*                                                                          */
1363 /* Returns:                                                                 */
1364 /*   Nothing.                                                               */
1365 /****************************************************************************/
1366 static void
1367 bce_miibus_statchg(device_t dev)
1368 {
1369         struct bce_softc *sc = device_get_softc(dev);
1370         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1371
1372         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1373                 mii->mii_media_active);
1374
1375 #ifdef BCE_DEBUG
1376         /* Decode the interface media flags. */
1377         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1378         switch(IFM_TYPE(mii->mii_media_active)) {
1379         case IFM_ETHER:
1380                 kprintf("Ethernet )");
1381                 break;
1382         default:
1383                 kprintf("Unknown )");
1384                 break;
1385         }
1386
1387         kprintf(" Media Options: ( ");
1388         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1389         case IFM_AUTO:
1390                 kprintf("Autoselect )");
1391                 break;
1392         case IFM_MANUAL:
1393                 kprintf("Manual )");
1394                 break;
1395         case IFM_NONE:
1396                 kprintf("None )");
1397                 break;
1398         case IFM_10_T:
1399                 kprintf("10Base-T )");
1400                 break;
1401         case IFM_100_TX:
1402                 kprintf("100Base-TX )");
1403                 break;
1404         case IFM_1000_SX:
1405                 kprintf("1000Base-SX )");
1406                 break;
1407         case IFM_1000_T:
1408                 kprintf("1000Base-T )");
1409                 break;
1410         default:
1411                 kprintf("Other )");
1412                 break;
1413         }
1414
1415         kprintf(" Global Options: (");
1416         if (mii->mii_media_active & IFM_FDX)
1417                 kprintf(" FullDuplex");
1418         if (mii->mii_media_active & IFM_HDX)
1419                 kprintf(" HalfDuplex");
1420         if (mii->mii_media_active & IFM_LOOP)
1421                 kprintf(" Loopback");
1422         if (mii->mii_media_active & IFM_FLAG0)
1423                 kprintf(" Flag0");
1424         if (mii->mii_media_active & IFM_FLAG1)
1425                 kprintf(" Flag1");
1426         if (mii->mii_media_active & IFM_FLAG2)
1427                 kprintf(" Flag2");
1428         kprintf(" )\n");
1429 #endif
1430
1431         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1432
1433         /*
1434          * Set MII or GMII interface based on the speed negotiated
1435          * by the PHY.
1436          */
1437         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1438             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1439                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1440                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1441         } else {
1442                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1443                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1444         }
1445
1446         /*
1447          * Set half or full duplex based on the duplicity negotiated
1448          * by the PHY.
1449          */
1450         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1451                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1452                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1453         } else {
1454                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1455                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1456         }
1457 }
1458
1459
1460 /****************************************************************************/
1461 /* Acquire NVRAM lock.                                                      */
1462 /*                                                                          */
1463 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1464 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1465 /* for use by the driver.                                                   */
1466 /*                                                                          */
1467 /* Returns:                                                                 */
1468 /*   0 on success, positive value on failure.                               */
1469 /****************************************************************************/
1470 static int
1471 bce_acquire_nvram_lock(struct bce_softc *sc)
1472 {
1473         uint32_t val;
1474         int j;
1475
1476         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1477
1478         /* Request access to the flash interface. */
1479         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1480         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1481                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1482                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1483                         break;
1484
1485                 DELAY(5);
1486         }
1487
1488         if (j >= NVRAM_TIMEOUT_COUNT) {
1489                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1490                 return EBUSY;
1491         }
1492         return 0;
1493 }
1494
1495
1496 /****************************************************************************/
1497 /* Release NVRAM lock.                                                      */
1498 /*                                                                          */
1499 /* When the caller is finished accessing NVRAM the lock must be released.   */
1500 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1501 /* for use by the driver.                                                   */
1502 /*                                                                          */
1503 /* Returns:                                                                 */
1504 /*   0 on success, positive value on failure.                               */
1505 /****************************************************************************/
1506 static int
1507 bce_release_nvram_lock(struct bce_softc *sc)
1508 {
1509         int j;
1510         uint32_t val;
1511
1512         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1513
1514         /*
1515          * Relinquish nvram interface.
1516          */
1517         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1518
1519         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1520                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1521                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1522                         break;
1523
1524                 DELAY(5);
1525         }
1526
1527         if (j >= NVRAM_TIMEOUT_COUNT) {
1528                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1529                 return EBUSY;
1530         }
1531         return 0;
1532 }
1533
1534
1535 /****************************************************************************/
1536 /* Enable NVRAM access.                                                     */
1537 /*                                                                          */
1538 /* Before accessing NVRAM for read or write operations the caller must      */
1539 /* enabled NVRAM access.                                                    */
1540 /*                                                                          */
1541 /* Returns:                                                                 */
1542 /*   Nothing.                                                               */
1543 /****************************************************************************/
1544 static void
1545 bce_enable_nvram_access(struct bce_softc *sc)
1546 {
1547         uint32_t val;
1548
1549         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1550
1551         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1552         /* Enable both bits, even on read. */
1553         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1554                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1555 }
1556
1557
1558 /****************************************************************************/
1559 /* Disable NVRAM access.                                                    */
1560 /*                                                                          */
1561 /* When the caller is finished accessing NVRAM access must be disabled.     */
1562 /*                                                                          */
1563 /* Returns:                                                                 */
1564 /*   Nothing.                                                               */
1565 /****************************************************************************/
1566 static void
1567 bce_disable_nvram_access(struct bce_softc *sc)
1568 {
1569         uint32_t val;
1570
1571         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1572
1573         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1574
1575         /* Disable both bits, even after read. */
1576         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1577                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1578 }
1579
1580
1581 /****************************************************************************/
1582 /* Read a dword (32 bits) from NVRAM.                                       */
1583 /*                                                                          */
1584 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1585 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1586 /*                                                                          */
1587 /* Returns:                                                                 */
1588 /*   0 on success and the 32 bit value read, positive value on failure.     */
1589 /****************************************************************************/
1590 static int
1591 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1592                      uint32_t cmd_flags)
1593 {
1594         uint32_t cmd;
1595         int i, rc = 0;
1596
1597         /* Build the command word. */
1598         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1599
1600         /* Calculate the offset for buffered flash. */
1601         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1602                 offset = ((offset / sc->bce_flash_info->page_size) <<
1603                           sc->bce_flash_info->page_bits) +
1604                          (offset % sc->bce_flash_info->page_size);
1605         }
1606
1607         /*
1608          * Clear the DONE bit separately, set the address to read,
1609          * and issue the read.
1610          */
1611         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1612         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1613         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1614
1615         /* Wait for completion. */
1616         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1617                 uint32_t val;
1618
1619                 DELAY(5);
1620
1621                 val = REG_RD(sc, BCE_NVM_COMMAND);
1622                 if (val & BCE_NVM_COMMAND_DONE) {
1623                         val = REG_RD(sc, BCE_NVM_READ);
1624
1625                         val = be32toh(val);
1626                         memcpy(ret_val, &val, 4);
1627                         break;
1628                 }
1629         }
1630
1631         /* Check for errors. */
1632         if (i >= NVRAM_TIMEOUT_COUNT) {
1633                 if_printf(&sc->arpcom.ac_if,
1634                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1635                           offset);
1636                 rc = EBUSY;
1637         }
1638         return rc;
1639 }
1640
1641
1642 /****************************************************************************/
1643 /* Initialize NVRAM access.                                                 */
1644 /*                                                                          */
1645 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1646 /* access that device.                                                      */
1647 /*                                                                          */
1648 /* Returns:                                                                 */
1649 /*   0 on success, positive value on failure.                               */
1650 /****************************************************************************/
1651 static int
1652 bce_init_nvram(struct bce_softc *sc)
1653 {
1654         uint32_t val;
1655         int j, entry_count, rc = 0;
1656         const struct flash_spec *flash;
1657
1658         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1659
1660         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1661             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1662                 sc->bce_flash_info = &flash_5709;
1663                 goto bce_init_nvram_get_flash_size;
1664         }
1665
1666         /* Determine the selected interface. */
1667         val = REG_RD(sc, BCE_NVM_CFG1);
1668
1669         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1670
1671         /*
1672          * Flash reconfiguration is required to support additional
1673          * NVRAM devices not directly supported in hardware.
1674          * Check if the flash interface was reconfigured
1675          * by the bootcode.
1676          */
1677
1678         if (val & 0x40000000) {
1679                 /* Flash interface reconfigured by bootcode. */
1680
1681                 DBPRINT(sc, BCE_INFO_LOAD,
1682                         "%s(): Flash WAS reconfigured.\n", __func__);
1683
1684                 for (j = 0, flash = flash_table; j < entry_count;
1685                      j++, flash++) {
1686                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1687                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1688                                 sc->bce_flash_info = flash;
1689                                 break;
1690                         }
1691                 }
1692         } else {
1693                 /* Flash interface not yet reconfigured. */
1694                 uint32_t mask;
1695
1696                 DBPRINT(sc, BCE_INFO_LOAD,
1697                         "%s(): Flash was NOT reconfigured.\n", __func__);
1698
1699                 if (val & (1 << 23))
1700                         mask = FLASH_BACKUP_STRAP_MASK;
1701                 else
1702                         mask = FLASH_STRAP_MASK;
1703
1704                 /* Look for the matching NVRAM device configuration data. */
1705                 for (j = 0, flash = flash_table; j < entry_count;
1706                      j++, flash++) {
1707                         /* Check if the device matches any of the known devices. */
1708                         if ((val & mask) == (flash->strapping & mask)) {
1709                                 /* Found a device match. */
1710                                 sc->bce_flash_info = flash;
1711
1712                                 /* Request access to the flash interface. */
1713                                 rc = bce_acquire_nvram_lock(sc);
1714                                 if (rc != 0)
1715                                         return rc;
1716
1717                                 /* Reconfigure the flash interface. */
1718                                 bce_enable_nvram_access(sc);
1719                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1720                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1721                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1722                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1723                                 bce_disable_nvram_access(sc);
1724                                 bce_release_nvram_lock(sc);
1725                                 break;
1726                         }
1727                 }
1728         }
1729
1730         /* Check if a matching device was found. */
1731         if (j == entry_count) {
1732                 sc->bce_flash_info = NULL;
1733                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1734                 return ENODEV;
1735         }
1736
1737 bce_init_nvram_get_flash_size:
1738         /* Write the flash config data to the shared memory interface. */
1739         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1740             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1741         if (val)
1742                 sc->bce_flash_size = val;
1743         else
1744                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1745
1746         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1747                 __func__, sc->bce_flash_info->total_size);
1748
1749         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1750
1751         return rc;
1752 }
1753
1754
1755 /****************************************************************************/
1756 /* Read an arbitrary range of data from NVRAM.                              */
1757 /*                                                                          */
1758 /* Prepares the NVRAM interface for access and reads the requested data     */
1759 /* into the supplied buffer.                                                */
1760 /*                                                                          */
1761 /* Returns:                                                                 */
1762 /*   0 on success and the data read, positive value on failure.             */
1763 /****************************************************************************/
1764 static int
1765 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1766                int buf_size)
1767 {
1768         uint32_t cmd_flags, offset32, len32, extra;
1769         int rc = 0;
1770
1771         if (buf_size == 0)
1772                 return 0;
1773
1774         /* Request access to the flash interface. */
1775         rc = bce_acquire_nvram_lock(sc);
1776         if (rc != 0)
1777                 return rc;
1778
1779         /* Enable access to flash interface */
1780         bce_enable_nvram_access(sc);
1781
1782         len32 = buf_size;
1783         offset32 = offset;
1784         extra = 0;
1785
1786         cmd_flags = 0;
1787
1788         /* XXX should we release nvram lock if read_dword() fails? */
1789         if (offset32 & 3) {
1790                 uint8_t buf[4];
1791                 uint32_t pre_len;
1792
1793                 offset32 &= ~3;
1794                 pre_len = 4 - (offset & 3);
1795
1796                 if (pre_len >= len32) {
1797                         pre_len = len32;
1798                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1799                 } else {
1800                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1801                 }
1802
1803                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1804                 if (rc)
1805                         return rc;
1806
1807                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1808
1809                 offset32 += 4;
1810                 ret_buf += pre_len;
1811                 len32 -= pre_len;
1812         }
1813
1814         if (len32 & 3) {
1815                 extra = 4 - (len32 & 3);
1816                 len32 = (len32 + 4) & ~3;
1817         }
1818
1819         if (len32 == 4) {
1820                 uint8_t buf[4];
1821
1822                 if (cmd_flags)
1823                         cmd_flags = BCE_NVM_COMMAND_LAST;
1824                 else
1825                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1826                                     BCE_NVM_COMMAND_LAST;
1827
1828                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1829
1830                 memcpy(ret_buf, buf, 4 - extra);
1831         } else if (len32 > 0) {
1832                 uint8_t buf[4];
1833
1834                 /* Read the first word. */
1835                 if (cmd_flags)
1836                         cmd_flags = 0;
1837                 else
1838                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1839
1840                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1841
1842                 /* Advance to the next dword. */
1843                 offset32 += 4;
1844                 ret_buf += 4;
1845                 len32 -= 4;
1846
1847                 while (len32 > 4 && rc == 0) {
1848                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1849
1850                         /* Advance to the next dword. */
1851                         offset32 += 4;
1852                         ret_buf += 4;
1853                         len32 -= 4;
1854                 }
1855
1856                 if (rc)
1857                         goto bce_nvram_read_locked_exit;
1858
1859                 cmd_flags = BCE_NVM_COMMAND_LAST;
1860                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1861
1862                 memcpy(ret_buf, buf, 4 - extra);
1863         }
1864
1865 bce_nvram_read_locked_exit:
1866         /* Disable access to flash interface and release the lock. */
1867         bce_disable_nvram_access(sc);
1868         bce_release_nvram_lock(sc);
1869
1870         return rc;
1871 }
1872
1873
1874 /****************************************************************************/
1875 /* Verifies that NVRAM is accessible and contains valid data.               */
1876 /*                                                                          */
1877 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1878 /* correct.                                                                 */
1879 /*                                                                          */
1880 /* Returns:                                                                 */
1881 /*   0 on success, positive value on failure.                               */
1882 /****************************************************************************/
1883 static int
1884 bce_nvram_test(struct bce_softc *sc)
1885 {
1886         uint32_t buf[BCE_NVRAM_SIZE / 4];
1887         uint32_t magic, csum;
1888         uint8_t *data = (uint8_t *)buf;
1889         int rc = 0;
1890
1891         /*
1892          * Check that the device NVRAM is valid by reading
1893          * the magic value at offset 0.
1894          */
1895         rc = bce_nvram_read(sc, 0, data, 4);
1896         if (rc != 0)
1897                 return rc;
1898
1899         magic = be32toh(buf[0]);
1900         if (magic != BCE_NVRAM_MAGIC) {
1901                 if_printf(&sc->arpcom.ac_if,
1902                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1903                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1904                 return ENODEV;
1905         }
1906
1907         /*
1908          * Verify that the device NVRAM includes valid
1909          * configuration data.
1910          */
1911         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1912         if (rc != 0)
1913                 return rc;
1914
1915         csum = ether_crc32_le(data, 0x100);
1916         if (csum != BCE_CRC32_RESIDUAL) {
1917                 if_printf(&sc->arpcom.ac_if,
1918                           "Invalid Manufacturing Information NVRAM CRC! "
1919                           "Expected: 0x%08X, Found: 0x%08X\n",
1920                           BCE_CRC32_RESIDUAL, csum);
1921                 return ENODEV;
1922         }
1923
1924         csum = ether_crc32_le(data + 0x100, 0x100);
1925         if (csum != BCE_CRC32_RESIDUAL) {
1926                 if_printf(&sc->arpcom.ac_if,
1927                           "Invalid Feature Configuration Information "
1928                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1929                           BCE_CRC32_RESIDUAL, csum);
1930                 rc = ENODEV;
1931         }
1932         return rc;
1933 }
1934
1935
1936 /****************************************************************************/
1937 /* Identifies the current media type of the controller and sets the PHY     */
1938 /* address.                                                                 */
1939 /*                                                                          */
1940 /* Returns:                                                                 */
1941 /*   Nothing.                                                               */
1942 /****************************************************************************/
1943 static void
1944 bce_get_media(struct bce_softc *sc)
1945 {
1946         uint32_t val;
1947
1948         sc->bce_phy_addr = 1;
1949
1950         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1951             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1952                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1953                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1954                 uint32_t strap;
1955
1956                 /*
1957                  * The BCM5709S is software configurable
1958                  * for Copper or SerDes operation.
1959                  */
1960                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1961                         return;
1962                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1963                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1964                         return;
1965                 }
1966
1967                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1968                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1969                 } else {
1970                         strap =
1971                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1972                 }
1973
1974                 if (pci_get_function(sc->bce_dev) == 0) {
1975                         switch (strap) {
1976                         case 0x4:
1977                         case 0x5:
1978                         case 0x6:
1979                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1980                                 break;
1981                         }
1982                 } else {
1983                         switch (strap) {
1984                         case 0x1:
1985                         case 0x2:
1986                         case 0x4:
1987                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1988                                 break;
1989                         }
1990                 }
1991         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1992                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1993         }
1994
1995         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1996                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1997                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1998                         sc->bce_phy_addr = 2;
1999                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2000                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2001                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2002                 }
2003         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2004             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2005                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2006         }
2007 }
2008
2009
2010 /****************************************************************************/
2011 /* Free any DMA memory owned by the driver.                                 */
2012 /*                                                                          */
2013 /* Scans through each data structre that requires DMA memory and frees      */
2014 /* the memory if allocated.                                                 */
2015 /*                                                                          */
2016 /* Returns:                                                                 */
2017 /*   Nothing.                                                               */
2018 /****************************************************************************/
2019 static void
2020 bce_dma_free(struct bce_softc *sc)
2021 {
2022         int i;
2023
2024         /* Destroy the status block. */
2025         if (sc->status_tag != NULL) {
2026                 if (sc->status_block != NULL) {
2027                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2028                         bus_dmamem_free(sc->status_tag, sc->status_block,
2029                                         sc->status_map);
2030                 }
2031                 bus_dma_tag_destroy(sc->status_tag);
2032         }
2033
2034
2035         /* Destroy the statistics block. */
2036         if (sc->stats_tag != NULL) {
2037                 if (sc->stats_block != NULL) {
2038                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2039                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2040                                         sc->stats_map);
2041                 }
2042                 bus_dma_tag_destroy(sc->stats_tag);
2043         }
2044
2045         /* Destroy the CTX DMA stuffs. */
2046         if (sc->ctx_tag != NULL) {
2047                 for (i = 0; i < sc->ctx_pages; i++) {
2048                         if (sc->ctx_block[i] != NULL) {
2049                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2050                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2051                                                 sc->ctx_map[i]);
2052                         }
2053                 }
2054                 bus_dma_tag_destroy(sc->ctx_tag);
2055         }
2056
2057         /* Destroy the TX buffer descriptor DMA stuffs. */
2058         if (sc->tx_bd_chain_tag != NULL) {
2059                 for (i = 0; i < TX_PAGES; i++) {
2060                         if (sc->tx_bd_chain[i] != NULL) {
2061                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2062                                                   sc->tx_bd_chain_map[i]);
2063                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2064                                                 sc->tx_bd_chain[i],
2065                                                 sc->tx_bd_chain_map[i]);
2066                         }
2067                 }
2068                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2069         }
2070
2071         /* Destroy the RX buffer descriptor DMA stuffs. */
2072         if (sc->rx_bd_chain_tag != NULL) {
2073                 for (i = 0; i < RX_PAGES; i++) {
2074                         if (sc->rx_bd_chain[i] != NULL) {
2075                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2076                                                   sc->rx_bd_chain_map[i]);
2077                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2078                                                 sc->rx_bd_chain[i],
2079                                                 sc->rx_bd_chain_map[i]);
2080                         }
2081                 }
2082                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2083         }
2084
2085         /* Destroy the TX mbuf DMA stuffs. */
2086         if (sc->tx_mbuf_tag != NULL) {
2087                 for (i = 0; i < TOTAL_TX_BD; i++) {
2088                         /* Must have been unloaded in bce_stop() */
2089                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2090                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2091                                            sc->tx_mbuf_map[i]);
2092                 }
2093                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2094         }
2095
2096         /* Destroy the RX mbuf DMA stuffs. */
2097         if (sc->rx_mbuf_tag != NULL) {
2098                 for (i = 0; i < TOTAL_RX_BD; i++) {
2099                         /* Must have been unloaded in bce_stop() */
2100                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2101                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2102                                            sc->rx_mbuf_map[i]);
2103                 }
2104                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2105                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2106         }
2107
2108         /* Destroy the parent tag */
2109         if (sc->parent_tag != NULL)
2110                 bus_dma_tag_destroy(sc->parent_tag);
2111 }
2112
2113
2114 /****************************************************************************/
2115 /* Get DMA memory from the OS.                                              */
2116 /*                                                                          */
2117 /* Validates that the OS has provided DMA buffers in response to a          */
2118 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2119 /* When the callback is used the OS will return 0 for the mapping function  */
2120 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2121 /* failures back to the caller.                                             */
2122 /*                                                                          */
2123 /* Returns:                                                                 */
2124 /*   Nothing.                                                               */
2125 /****************************************************************************/
2126 static void
2127 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2128 {
2129         bus_addr_t *busaddr = arg;
2130
2131         /*
2132          * Simulate a mapping failure.
2133          * XXX not correct.
2134          */
2135         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2136                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2137                         __FILE__, __LINE__);
2138                 error = ENOMEM);
2139
2140         /* Check for an error and signal the caller that an error occurred. */
2141         if (error)
2142                 return;
2143
2144         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2145         *busaddr = segs->ds_addr;
2146 }
2147
2148
2149 /****************************************************************************/
2150 /* Allocate any DMA memory needed by the driver.                            */
2151 /*                                                                          */
2152 /* Allocates DMA memory needed for the various global structures needed by  */
2153 /* hardware.                                                                */
2154 /*                                                                          */
2155 /* Memory alignment requirements:                                           */
2156 /* -----------------+----------+----------+----------+----------+           */
2157 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2158 /* -----------------+----------+----------+----------+----------+           */
2159 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2160 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2161 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2162 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2163 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2164 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2165 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2166 /* -----------------+----------+----------+----------+----------+           */
2167 /*                                                                          */
2168 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2169 /*                                                                          */
2170 /* Returns:                                                                 */
2171 /*   0 for success, positive value for failure.                             */
2172 /****************************************************************************/
2173 static int
2174 bce_dma_alloc(struct bce_softc *sc)
2175 {
2176         struct ifnet *ifp = &sc->arpcom.ac_if;
2177         int i, j, rc = 0;
2178         bus_addr_t busaddr, max_busaddr;
2179         bus_size_t status_align, stats_align;
2180
2181         /*
2182          * The embedded PCIe to PCI-X bridge (EPB)
2183          * in the 5708 cannot address memory above
2184          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2185          */
2186         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2187                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2188         else
2189                 max_busaddr = BUS_SPACE_MAXADDR;
2190
2191         /*
2192          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2193          */
2194         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2195             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2196                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2197                 if (sc->ctx_pages == 0)
2198                         sc->ctx_pages = 1;
2199                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2200                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2201                             sc->ctx_pages);
2202                         return ENOMEM;
2203                 }
2204                 status_align = 16;
2205                 stats_align = 16;
2206         } else {
2207                 status_align = 8;
2208                 stats_align = 8;
2209         }
2210
2211         /*
2212          * Allocate the parent bus DMA tag appropriate for PCI.
2213          */
2214         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2215                                 max_busaddr, BUS_SPACE_MAXADDR,
2216                                 NULL, NULL,
2217                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2218                                 BUS_SPACE_MAXSIZE_32BIT,
2219                                 0, &sc->parent_tag);
2220         if (rc != 0) {
2221                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2222                 return rc;
2223         }
2224
2225         /*
2226          * Allocate status block.
2227          */
2228         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2229                                 status_align, BCE_STATUS_BLK_SZ,
2230                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2231                                 &sc->status_tag, &sc->status_map,
2232                                 &sc->status_block_paddr);
2233         if (sc->status_block == NULL) {
2234                 if_printf(ifp, "Could not allocate status block!\n");
2235                 return ENOMEM;
2236         }
2237
2238         /*
2239          * Allocate statistics block.
2240          */
2241         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2242                                 stats_align, BCE_STATS_BLK_SZ,
2243                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2244                                 &sc->stats_tag, &sc->stats_map,
2245                                 &sc->stats_block_paddr);
2246         if (sc->stats_block == NULL) {
2247                 if_printf(ifp, "Could not allocate statistics block!\n");
2248                 return ENOMEM;
2249         }
2250
2251         /*
2252          * Allocate context block, if needed
2253          */
2254         if (sc->ctx_pages != 0) {
2255                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2256                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2257                                         NULL, NULL,
2258                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2259                                         0, &sc->ctx_tag);
2260                 if (rc != 0) {
2261                         if_printf(ifp, "Could not allocate "
2262                                   "context block DMA tag!\n");
2263                         return rc;
2264                 }
2265
2266                 for (i = 0; i < sc->ctx_pages; i++) {
2267                         rc = bus_dmamem_alloc(sc->ctx_tag,
2268                                               (void **)&sc->ctx_block[i],
2269                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2270                                               BUS_DMA_COHERENT,
2271                                               &sc->ctx_map[i]);
2272                         if (rc != 0) {
2273                                 if_printf(ifp, "Could not allocate %dth context "
2274                                           "DMA memory!\n", i);
2275                                 return rc;
2276                         }
2277
2278                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2279                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2280                                              bce_dma_map_addr, &busaddr,
2281                                              BUS_DMA_WAITOK);
2282                         if (rc != 0) {
2283                                 if (rc == EINPROGRESS) {
2284                                         panic("%s coherent memory loading "
2285                                               "is still in progress!", ifp->if_xname);
2286                                 }
2287                                 if_printf(ifp, "Could not map %dth context "
2288                                           "DMA memory!\n", i);
2289                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2290                                                 sc->ctx_map[i]);
2291                                 sc->ctx_block[i] = NULL;
2292                                 return rc;
2293                         }
2294                         sc->ctx_paddr[i] = busaddr;
2295                 }
2296         }
2297
2298         /*
2299          * Create a DMA tag for the TX buffer descriptor chain,
2300          * allocate and clear the  memory, and fetch the
2301          * physical address of the block.
2302          */
2303         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2304                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2305                                 NULL, NULL,
2306                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2307                                 0, &sc->tx_bd_chain_tag);
2308         if (rc != 0) {
2309                 if_printf(ifp, "Could not allocate "
2310                           "TX descriptor chain DMA tag!\n");
2311                 return rc;
2312         }
2313
2314         for (i = 0; i < TX_PAGES; i++) {
2315                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2316                                       (void **)&sc->tx_bd_chain[i],
2317                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2318                                       BUS_DMA_COHERENT,
2319                                       &sc->tx_bd_chain_map[i]);
2320                 if (rc != 0) {
2321                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2322                                   "chain DMA memory!\n", i);
2323                         return rc;
2324                 }
2325
2326                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2327                                      sc->tx_bd_chain_map[i],
2328                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2329                                      bce_dma_map_addr, &busaddr,
2330                                      BUS_DMA_WAITOK);
2331                 if (rc != 0) {
2332                         if (rc == EINPROGRESS) {
2333                                 panic("%s coherent memory loading "
2334                                       "is still in progress!", ifp->if_xname);
2335                         }
2336                         if_printf(ifp, "Could not map %dth TX descriptor "
2337                                   "chain DMA memory!\n", i);
2338                         bus_dmamem_free(sc->tx_bd_chain_tag,
2339                                         sc->tx_bd_chain[i],
2340                                         sc->tx_bd_chain_map[i]);
2341                         sc->tx_bd_chain[i] = NULL;
2342                         return rc;
2343                 }
2344
2345                 sc->tx_bd_chain_paddr[i] = busaddr;
2346                 /* DRC - Fix for 64 bit systems. */
2347                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2348                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2349         }
2350
2351         /* Create a DMA tag for TX mbufs. */
2352         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2353                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2354                                 NULL, NULL,
2355                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2356                                 BCE_MAX_SEGMENTS, MCLBYTES,
2357                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2358                                 BUS_DMA_ONEBPAGE,
2359                                 &sc->tx_mbuf_tag);
2360         if (rc != 0) {
2361                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2362                 return rc;
2363         }
2364
2365         /* Create DMA maps for the TX mbufs clusters. */
2366         for (i = 0; i < TOTAL_TX_BD; i++) {
2367                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2368                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2369                                        &sc->tx_mbuf_map[i]);
2370                 if (rc != 0) {
2371                         for (j = 0; j < i; ++j) {
2372                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2373                                                    sc->tx_mbuf_map[i]);
2374                         }
2375                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2376                         sc->tx_mbuf_tag = NULL;
2377
2378                         if_printf(ifp, "Unable to create "
2379                                   "%dth TX mbuf DMA map!\n", i);
2380                         return rc;
2381                 }
2382         }
2383
2384         /*
2385          * Create a DMA tag for the RX buffer descriptor chain,
2386          * allocate and clear the  memory, and fetch the physical
2387          * address of the blocks.
2388          */
2389         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2390                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2391                                 NULL, NULL,
2392                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2393                                 0, &sc->rx_bd_chain_tag);
2394         if (rc != 0) {
2395                 if_printf(ifp, "Could not allocate "
2396                           "RX descriptor chain DMA tag!\n");
2397                 return rc;
2398         }
2399
2400         for (i = 0; i < RX_PAGES; i++) {
2401                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2402                                       (void **)&sc->rx_bd_chain[i],
2403                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2404                                       BUS_DMA_COHERENT,
2405                                       &sc->rx_bd_chain_map[i]);
2406                 if (rc != 0) {
2407                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2408                                   "chain DMA memory!\n", i);
2409                         return rc;
2410                 }
2411
2412                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2413                                      sc->rx_bd_chain_map[i],
2414                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2415                                      bce_dma_map_addr, &busaddr,
2416                                      BUS_DMA_WAITOK);
2417                 if (rc != 0) {
2418                         if (rc == EINPROGRESS) {
2419                                 panic("%s coherent memory loading "
2420                                       "is still in progress!", ifp->if_xname);
2421                         }
2422                         if_printf(ifp, "Could not map %dth RX descriptor "
2423                                   "chain DMA memory!\n", i);
2424                         bus_dmamem_free(sc->rx_bd_chain_tag,
2425                                         sc->rx_bd_chain[i],
2426                                         sc->rx_bd_chain_map[i]);
2427                         sc->rx_bd_chain[i] = NULL;
2428                         return rc;
2429                 }
2430
2431                 sc->rx_bd_chain_paddr[i] = busaddr;
2432                 /* DRC - Fix for 64 bit systems. */
2433                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2434                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2435         }
2436
2437         /* Create a DMA tag for RX mbufs. */
2438         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2439                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2440                                 NULL, NULL,
2441                                 MCLBYTES, 1, MCLBYTES,
2442                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2443                                 BUS_DMA_WAITOK,
2444                                 &sc->rx_mbuf_tag);
2445         if (rc != 0) {
2446                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2447                 return rc;
2448         }
2449
2450         /* Create tmp DMA map for RX mbuf clusters. */
2451         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2452                                &sc->rx_mbuf_tmpmap);
2453         if (rc != 0) {
2454                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2455                 sc->rx_mbuf_tag = NULL;
2456
2457                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2458                 return rc;
2459         }
2460
2461         /* Create DMA maps for the RX mbuf clusters. */
2462         for (i = 0; i < TOTAL_RX_BD; i++) {
2463                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2464                                        &sc->rx_mbuf_map[i]);
2465                 if (rc != 0) {
2466                         for (j = 0; j < i; ++j) {
2467                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2468                                                    sc->rx_mbuf_map[j]);
2469                         }
2470                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2471                         sc->rx_mbuf_tag = NULL;
2472
2473                         if_printf(ifp, "Unable to create "
2474                                   "%dth RX mbuf DMA map!\n", i);
2475                         return rc;
2476                 }
2477         }
2478         return 0;
2479 }
2480
2481
2482 /****************************************************************************/
2483 /* Firmware synchronization.                                                */
2484 /*                                                                          */
2485 /* Before performing certain events such as a chip reset, synchronize with  */
2486 /* the firmware first.                                                      */
2487 /*                                                                          */
2488 /* Returns:                                                                 */
2489 /*   0 for success, positive value for failure.                             */
2490 /****************************************************************************/
2491 static int
2492 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2493 {
2494         int i, rc = 0;
2495         uint32_t val;
2496
2497         /* Don't waste any time if we've timed out before. */
2498         if (sc->bce_fw_timed_out)
2499                 return EBUSY;
2500
2501         /* Increment the message sequence number. */
2502         sc->bce_fw_wr_seq++;
2503         msg_data |= sc->bce_fw_wr_seq;
2504
2505         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2506
2507         /* Send the message to the bootcode driver mailbox. */
2508         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2509
2510         /* Wait for the bootcode to acknowledge the message. */
2511         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2512                 /* Check for a response in the bootcode firmware mailbox. */
2513                 val = bce_shmem_rd(sc, BCE_FW_MB);
2514                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2515                         break;
2516                 DELAY(1000);
2517         }
2518
2519         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2520         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2521             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2522                 if_printf(&sc->arpcom.ac_if,
2523                           "Firmware synchronization timeout! "
2524                           "msg_data = 0x%08X\n", msg_data);
2525
2526                 msg_data &= ~BCE_DRV_MSG_CODE;
2527                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2528
2529                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2530
2531                 sc->bce_fw_timed_out = 1;
2532                 rc = EBUSY;
2533         }
2534         return rc;
2535 }
2536
2537
2538 /****************************************************************************/
2539 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2540 /*                                                                          */
2541 /* Returns:                                                                 */
2542 /*   Nothing.                                                               */
2543 /****************************************************************************/
2544 static void
2545 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2546                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2547 {
2548         int i;
2549         uint32_t val;
2550
2551         for (i = 0; i < rv2p_code_len; i += 8) {
2552                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2553                 rv2p_code++;
2554                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2555                 rv2p_code++;
2556
2557                 if (rv2p_proc == RV2P_PROC1) {
2558                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2559                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2560                 } else {
2561                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2562                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2563                 }
2564         }
2565
2566         /* Reset the processor, un-stall is done later. */
2567         if (rv2p_proc == RV2P_PROC1)
2568                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2569         else
2570                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2571 }
2572
2573
2574 /****************************************************************************/
2575 /* Load RISC processor firmware.                                            */
2576 /*                                                                          */
2577 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2578 /* associated with a particular processor.                                  */
2579 /*                                                                          */
2580 /* Returns:                                                                 */
2581 /*   Nothing.                                                               */
2582 /****************************************************************************/
2583 static void
2584 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2585                 struct fw_info *fw)
2586 {
2587         uint32_t offset;
2588         int j;
2589
2590         bce_halt_cpu(sc, cpu_reg);
2591
2592         /* Load the Text area. */
2593         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2594         if (fw->text) {
2595                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2596                         REG_WR_IND(sc, offset, fw->text[j]);
2597         }
2598
2599         /* Load the Data area. */
2600         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2601         if (fw->data) {
2602                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2603                         REG_WR_IND(sc, offset, fw->data[j]);
2604         }
2605
2606         /* Load the SBSS area. */
2607         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2608         if (fw->sbss) {
2609                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2610                         REG_WR_IND(sc, offset, fw->sbss[j]);
2611         }
2612
2613         /* Load the BSS area. */
2614         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2615         if (fw->bss) {
2616                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2617                         REG_WR_IND(sc, offset, fw->bss[j]);
2618         }
2619
2620         /* Load the Read-Only area. */
2621         offset = cpu_reg->spad_base +
2622                 (fw->rodata_addr - cpu_reg->mips_view_base);
2623         if (fw->rodata) {
2624                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2625                         REG_WR_IND(sc, offset, fw->rodata[j]);
2626         }
2627
2628         /* Clear the pre-fetch instruction and set the FW start address. */
2629         REG_WR_IND(sc, cpu_reg->inst, 0);
2630         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2631 }
2632
2633
2634 /****************************************************************************/
2635 /* Starts the RISC processor.                                               */
2636 /*                                                                          */
2637 /* Assumes the CPU starting address has already been set.                   */
2638 /*                                                                          */
2639 /* Returns:                                                                 */
2640 /*   Nothing.                                                               */
2641 /****************************************************************************/
2642 static void
2643 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2644 {
2645         uint32_t val;
2646
2647         /* Start the CPU. */
2648         val = REG_RD_IND(sc, cpu_reg->mode);
2649         val &= ~cpu_reg->mode_value_halt;
2650         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2651         REG_WR_IND(sc, cpu_reg->mode, val);
2652 }
2653
2654
2655 /****************************************************************************/
2656 /* Halts the RISC processor.                                                */
2657 /*                                                                          */
2658 /* Returns:                                                                 */
2659 /*   Nothing.                                                               */
2660 /****************************************************************************/
2661 static void
2662 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2663 {
2664         uint32_t val;
2665
2666         /* Halt the CPU. */
2667         val = REG_RD_IND(sc, cpu_reg->mode);
2668         val |= cpu_reg->mode_value_halt;
2669         REG_WR_IND(sc, cpu_reg->mode, val);
2670         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2671 }
2672
2673
2674 /****************************************************************************/
2675 /* Start the RX CPU.                                                        */
2676 /*                                                                          */
2677 /* Returns:                                                                 */
2678 /*   Nothing.                                                               */
2679 /****************************************************************************/
2680 static void
2681 bce_start_rxp_cpu(struct bce_softc *sc)
2682 {
2683         struct cpu_reg cpu_reg;
2684
2685         cpu_reg.mode = BCE_RXP_CPU_MODE;
2686         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2687         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2688         cpu_reg.state = BCE_RXP_CPU_STATE;
2689         cpu_reg.state_value_clear = 0xffffff;
2690         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2691         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2692         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2693         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2694         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2695         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2696         cpu_reg.mips_view_base = 0x8000000;
2697
2698         bce_start_cpu(sc, &cpu_reg);
2699 }
2700
2701
2702 /****************************************************************************/
2703 /* Initialize the RX CPU.                                                   */
2704 /*                                                                          */
2705 /* Returns:                                                                 */
2706 /*   Nothing.                                                               */
2707 /****************************************************************************/
2708 static void
2709 bce_init_rxp_cpu(struct bce_softc *sc)
2710 {
2711         struct cpu_reg cpu_reg;
2712         struct fw_info fw;
2713
2714         cpu_reg.mode = BCE_RXP_CPU_MODE;
2715         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2716         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2717         cpu_reg.state = BCE_RXP_CPU_STATE;
2718         cpu_reg.state_value_clear = 0xffffff;
2719         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2720         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2721         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2722         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2723         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2724         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2725         cpu_reg.mips_view_base = 0x8000000;
2726
2727         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2728             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2729                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2730                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2731                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2732                 fw.start_addr = bce_RXP_b09FwStartAddr;
2733
2734                 fw.text_addr = bce_RXP_b09FwTextAddr;
2735                 fw.text_len = bce_RXP_b09FwTextLen;
2736                 fw.text_index = 0;
2737                 fw.text = bce_RXP_b09FwText;
2738
2739                 fw.data_addr = bce_RXP_b09FwDataAddr;
2740                 fw.data_len = bce_RXP_b09FwDataLen;
2741                 fw.data_index = 0;
2742                 fw.data = bce_RXP_b09FwData;
2743
2744                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2745                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2746                 fw.sbss_index = 0;
2747                 fw.sbss = bce_RXP_b09FwSbss;
2748
2749                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2750                 fw.bss_len = bce_RXP_b09FwBssLen;
2751                 fw.bss_index = 0;
2752                 fw.bss = bce_RXP_b09FwBss;
2753
2754                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2755                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2756                 fw.rodata_index = 0;
2757                 fw.rodata = bce_RXP_b09FwRodata;
2758         } else {
2759                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2760                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2761                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2762                 fw.start_addr = bce_RXP_b06FwStartAddr;
2763
2764                 fw.text_addr = bce_RXP_b06FwTextAddr;
2765                 fw.text_len = bce_RXP_b06FwTextLen;
2766                 fw.text_index = 0;
2767                 fw.text = bce_RXP_b06FwText;
2768
2769                 fw.data_addr = bce_RXP_b06FwDataAddr;
2770                 fw.data_len = bce_RXP_b06FwDataLen;
2771                 fw.data_index = 0;
2772                 fw.data = bce_RXP_b06FwData;
2773
2774                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2775                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2776                 fw.sbss_index = 0;
2777                 fw.sbss = bce_RXP_b06FwSbss;
2778
2779                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2780                 fw.bss_len = bce_RXP_b06FwBssLen;
2781                 fw.bss_index = 0;
2782                 fw.bss = bce_RXP_b06FwBss;
2783
2784                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2785                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2786                 fw.rodata_index = 0;
2787                 fw.rodata = bce_RXP_b06FwRodata;
2788         }
2789
2790         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2791         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2792         /* Delay RXP start until initialization is complete. */
2793 }
2794
2795
2796 /****************************************************************************/
2797 /* Initialize the TX CPU.                                                   */
2798 /*                                                                          */
2799 /* Returns:                                                                 */
2800 /*   Nothing.                                                               */
2801 /****************************************************************************/
2802 static void
2803 bce_init_txp_cpu(struct bce_softc *sc)
2804 {
2805         struct cpu_reg cpu_reg;
2806         struct fw_info fw;
2807
2808         cpu_reg.mode = BCE_TXP_CPU_MODE;
2809         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2810         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2811         cpu_reg.state = BCE_TXP_CPU_STATE;
2812         cpu_reg.state_value_clear = 0xffffff;
2813         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2814         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2815         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2816         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2817         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2818         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2819         cpu_reg.mips_view_base = 0x8000000;
2820
2821         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2822             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2823                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2824                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2825                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2826                 fw.start_addr = bce_TXP_b09FwStartAddr;
2827
2828                 fw.text_addr = bce_TXP_b09FwTextAddr;
2829                 fw.text_len = bce_TXP_b09FwTextLen;
2830                 fw.text_index = 0;
2831                 fw.text = bce_TXP_b09FwText;
2832
2833                 fw.data_addr = bce_TXP_b09FwDataAddr;
2834                 fw.data_len = bce_TXP_b09FwDataLen;
2835                 fw.data_index = 0;
2836                 fw.data = bce_TXP_b09FwData;
2837
2838                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2839                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2840                 fw.sbss_index = 0;
2841                 fw.sbss = bce_TXP_b09FwSbss;
2842
2843                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2844                 fw.bss_len = bce_TXP_b09FwBssLen;
2845                 fw.bss_index = 0;
2846                 fw.bss = bce_TXP_b09FwBss;
2847
2848                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2849                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2850                 fw.rodata_index = 0;
2851                 fw.rodata = bce_TXP_b09FwRodata;
2852         } else {
2853                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2854                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2855                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2856                 fw.start_addr = bce_TXP_b06FwStartAddr;
2857
2858                 fw.text_addr = bce_TXP_b06FwTextAddr;
2859                 fw.text_len = bce_TXP_b06FwTextLen;
2860                 fw.text_index = 0;
2861                 fw.text = bce_TXP_b06FwText;
2862
2863                 fw.data_addr = bce_TXP_b06FwDataAddr;
2864                 fw.data_len = bce_TXP_b06FwDataLen;
2865                 fw.data_index = 0;
2866                 fw.data = bce_TXP_b06FwData;
2867
2868                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2869                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2870                 fw.sbss_index = 0;
2871                 fw.sbss = bce_TXP_b06FwSbss;
2872
2873                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2874                 fw.bss_len = bce_TXP_b06FwBssLen;
2875                 fw.bss_index = 0;
2876                 fw.bss = bce_TXP_b06FwBss;
2877
2878                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2879                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2880                 fw.rodata_index = 0;
2881                 fw.rodata = bce_TXP_b06FwRodata;
2882         }
2883
2884         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2885         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2886         bce_start_cpu(sc, &cpu_reg);
2887 }
2888
2889
2890 /****************************************************************************/
2891 /* Initialize the TPAT CPU.                                                 */
2892 /*                                                                          */
2893 /* Returns:                                                                 */
2894 /*   Nothing.                                                               */
2895 /****************************************************************************/
2896 static void
2897 bce_init_tpat_cpu(struct bce_softc *sc)
2898 {
2899         struct cpu_reg cpu_reg;
2900         struct fw_info fw;
2901
2902         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2903         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2904         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2905         cpu_reg.state = BCE_TPAT_CPU_STATE;
2906         cpu_reg.state_value_clear = 0xffffff;
2907         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2908         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2909         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2910         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2911         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2912         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2913         cpu_reg.mips_view_base = 0x8000000;
2914
2915         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2916             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2917                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2918                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2919                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2920                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2921
2922                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2923                 fw.text_len = bce_TPAT_b09FwTextLen;
2924                 fw.text_index = 0;
2925                 fw.text = bce_TPAT_b09FwText;
2926
2927                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2928                 fw.data_len = bce_TPAT_b09FwDataLen;
2929                 fw.data_index = 0;
2930                 fw.data = bce_TPAT_b09FwData;
2931
2932                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2933                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2934                 fw.sbss_index = 0;
2935                 fw.sbss = bce_TPAT_b09FwSbss;
2936
2937                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2938                 fw.bss_len = bce_TPAT_b09FwBssLen;
2939                 fw.bss_index = 0;
2940                 fw.bss = bce_TPAT_b09FwBss;
2941
2942                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2943                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2944                 fw.rodata_index = 0;
2945                 fw.rodata = bce_TPAT_b09FwRodata;
2946         } else {
2947                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2948                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2949                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2950                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2951
2952                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2953                 fw.text_len = bce_TPAT_b06FwTextLen;
2954                 fw.text_index = 0;
2955                 fw.text = bce_TPAT_b06FwText;
2956
2957                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2958                 fw.data_len = bce_TPAT_b06FwDataLen;
2959                 fw.data_index = 0;
2960                 fw.data = bce_TPAT_b06FwData;
2961
2962                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2963                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2964                 fw.sbss_index = 0;
2965                 fw.sbss = bce_TPAT_b06FwSbss;
2966
2967                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2968                 fw.bss_len = bce_TPAT_b06FwBssLen;
2969                 fw.bss_index = 0;
2970                 fw.bss = bce_TPAT_b06FwBss;
2971
2972                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2973                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2974                 fw.rodata_index = 0;
2975                 fw.rodata = bce_TPAT_b06FwRodata;
2976         }
2977
2978         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2979         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2980         bce_start_cpu(sc, &cpu_reg);
2981 }
2982
2983
2984 /****************************************************************************/
2985 /* Initialize the CP CPU.                                                   */
2986 /*                                                                          */
2987 /* Returns:                                                                 */
2988 /*   Nothing.                                                               */
2989 /****************************************************************************/
2990 static void
2991 bce_init_cp_cpu(struct bce_softc *sc)
2992 {
2993         struct cpu_reg cpu_reg;
2994         struct fw_info fw;
2995
2996         cpu_reg.mode = BCE_CP_CPU_MODE;
2997         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2998         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2999         cpu_reg.state = BCE_CP_CPU_STATE;
3000         cpu_reg.state_value_clear = 0xffffff;
3001         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3002         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3003         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3004         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3005         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3006         cpu_reg.spad_base = BCE_CP_SCRATCH;
3007         cpu_reg.mips_view_base = 0x8000000;
3008
3009         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3010             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3011                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3012                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3013                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3014                 fw.start_addr = bce_CP_b09FwStartAddr;
3015
3016                 fw.text_addr = bce_CP_b09FwTextAddr;
3017                 fw.text_len = bce_CP_b09FwTextLen;
3018                 fw.text_index = 0;
3019                 fw.text = bce_CP_b09FwText;
3020
3021                 fw.data_addr = bce_CP_b09FwDataAddr;
3022                 fw.data_len = bce_CP_b09FwDataLen;
3023                 fw.data_index = 0;
3024                 fw.data = bce_CP_b09FwData;
3025
3026                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3027                 fw.sbss_len = bce_CP_b09FwSbssLen;
3028                 fw.sbss_index = 0;
3029                 fw.sbss = bce_CP_b09FwSbss;
3030
3031                 fw.bss_addr = bce_CP_b09FwBssAddr;
3032                 fw.bss_len = bce_CP_b09FwBssLen;
3033                 fw.bss_index = 0;
3034                 fw.bss = bce_CP_b09FwBss;
3035
3036                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3037                 fw.rodata_len = bce_CP_b09FwRodataLen;
3038                 fw.rodata_index = 0;
3039                 fw.rodata = bce_CP_b09FwRodata;
3040         } else {
3041                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3042                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3043                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3044                 fw.start_addr = bce_CP_b06FwStartAddr;
3045
3046                 fw.text_addr = bce_CP_b06FwTextAddr;
3047                 fw.text_len = bce_CP_b06FwTextLen;
3048                 fw.text_index = 0;
3049                 fw.text = bce_CP_b06FwText;
3050
3051                 fw.data_addr = bce_CP_b06FwDataAddr;
3052                 fw.data_len = bce_CP_b06FwDataLen;
3053                 fw.data_index = 0;
3054                 fw.data = bce_CP_b06FwData;
3055
3056                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3057                 fw.sbss_len = bce_CP_b06FwSbssLen;
3058                 fw.sbss_index = 0;
3059                 fw.sbss = bce_CP_b06FwSbss;
3060
3061                 fw.bss_addr = bce_CP_b06FwBssAddr;
3062                 fw.bss_len = bce_CP_b06FwBssLen;
3063                 fw.bss_index = 0;
3064                 fw.bss = bce_CP_b06FwBss;
3065
3066                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3067                 fw.rodata_len = bce_CP_b06FwRodataLen;
3068                 fw.rodata_index = 0;
3069                 fw.rodata = bce_CP_b06FwRodata;
3070         }
3071
3072         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3073         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3074         bce_start_cpu(sc, &cpu_reg);
3075 }
3076
3077
3078 /****************************************************************************/
3079 /* Initialize the COM CPU.                                                 */
3080 /*                                                                          */
3081 /* Returns:                                                                 */
3082 /*   Nothing.                                                               */
3083 /****************************************************************************/
3084 static void
3085 bce_init_com_cpu(struct bce_softc *sc)
3086 {
3087         struct cpu_reg cpu_reg;
3088         struct fw_info fw;
3089
3090         cpu_reg.mode = BCE_COM_CPU_MODE;
3091         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3092         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3093         cpu_reg.state = BCE_COM_CPU_STATE;
3094         cpu_reg.state_value_clear = 0xffffff;
3095         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3096         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3097         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3098         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3099         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3100         cpu_reg.spad_base = BCE_COM_SCRATCH;
3101         cpu_reg.mips_view_base = 0x8000000;
3102
3103         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3104             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3105                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3106                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3107                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3108                 fw.start_addr = bce_COM_b09FwStartAddr;
3109
3110                 fw.text_addr = bce_COM_b09FwTextAddr;
3111                 fw.text_len = bce_COM_b09FwTextLen;
3112                 fw.text_index = 0;
3113                 fw.text = bce_COM_b09FwText;
3114
3115                 fw.data_addr = bce_COM_b09FwDataAddr;
3116                 fw.data_len = bce_COM_b09FwDataLen;
3117                 fw.data_index = 0;
3118                 fw.data = bce_COM_b09FwData;
3119
3120                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3121                 fw.sbss_len = bce_COM_b09FwSbssLen;
3122                 fw.sbss_index = 0;
3123                 fw.sbss = bce_COM_b09FwSbss;
3124
3125                 fw.bss_addr = bce_COM_b09FwBssAddr;
3126                 fw.bss_len = bce_COM_b09FwBssLen;
3127                 fw.bss_index = 0;
3128                 fw.bss = bce_COM_b09FwBss;
3129
3130                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3131                 fw.rodata_len = bce_COM_b09FwRodataLen;
3132                 fw.rodata_index = 0;
3133                 fw.rodata = bce_COM_b09FwRodata;
3134         } else {
3135                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3136                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3137                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3138                 fw.start_addr = bce_COM_b06FwStartAddr;
3139
3140                 fw.text_addr = bce_COM_b06FwTextAddr;
3141                 fw.text_len = bce_COM_b06FwTextLen;
3142                 fw.text_index = 0;
3143                 fw.text = bce_COM_b06FwText;
3144
3145                 fw.data_addr = bce_COM_b06FwDataAddr;
3146                 fw.data_len = bce_COM_b06FwDataLen;
3147                 fw.data_index = 0;
3148                 fw.data = bce_COM_b06FwData;
3149
3150                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3151                 fw.sbss_len = bce_COM_b06FwSbssLen;
3152                 fw.sbss_index = 0;
3153                 fw.sbss = bce_COM_b06FwSbss;
3154
3155                 fw.bss_addr = bce_COM_b06FwBssAddr;
3156                 fw.bss_len = bce_COM_b06FwBssLen;
3157                 fw.bss_index = 0;
3158                 fw.bss = bce_COM_b06FwBss;
3159
3160                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3161                 fw.rodata_len = bce_COM_b06FwRodataLen;
3162                 fw.rodata_index = 0;
3163                 fw.rodata = bce_COM_b06FwRodata;
3164         }
3165
3166         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3167         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3168         bce_start_cpu(sc, &cpu_reg);
3169 }
3170
3171
3172 /****************************************************************************/
3173 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3174 /*                                                                          */
3175 /* Loads the firmware for each CPU and starts the CPU.                      */
3176 /*                                                                          */
3177 /* Returns:                                                                 */
3178 /*   Nothing.                                                               */
3179 /****************************************************************************/
3180 static void
3181 bce_init_cpus(struct bce_softc *sc)
3182 {
3183         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3184             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3185                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3186                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3187                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3188                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3189                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3190                 } else {
3191                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3192                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3193                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3194                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3195                 }
3196         } else {
3197                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3198                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3199                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3200                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3201         }
3202
3203         bce_init_rxp_cpu(sc);
3204         bce_init_txp_cpu(sc);
3205         bce_init_tpat_cpu(sc);
3206         bce_init_com_cpu(sc);
3207         bce_init_cp_cpu(sc);
3208 }
3209
3210
3211 /****************************************************************************/
3212 /* Initialize context memory.                                               */
3213 /*                                                                          */
3214 /* Clears the memory associated with each Context ID (CID).                 */
3215 /*                                                                          */
3216 /* Returns:                                                                 */
3217 /*   Nothing.                                                               */
3218 /****************************************************************************/
3219 static int
3220 bce_init_ctx(struct bce_softc *sc)
3221 {
3222         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3223             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3224                 /* DRC: Replace this constant value with a #define. */
3225                 int i, retry_cnt = 10;
3226                 uint32_t val;
3227
3228                 /*
3229                  * BCM5709 context memory may be cached
3230                  * in host memory so prepare the host memory
3231                  * for access.
3232                  */
3233                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3234                     (1 << 12);
3235                 val |= (BCM_PAGE_BITS - 8) << 16;
3236                 REG_WR(sc, BCE_CTX_COMMAND, val);
3237
3238                 /* Wait for mem init command to complete. */
3239                 for (i = 0; i < retry_cnt; i++) {
3240                         val = REG_RD(sc, BCE_CTX_COMMAND);
3241                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3242                                 break;
3243                         DELAY(2);
3244                 }
3245                 if (i == retry_cnt) {
3246                         device_printf(sc->bce_dev,
3247                             "Context memory initialization failed!\n");
3248                         return ETIMEDOUT;
3249                 }
3250
3251                 for (i = 0; i < sc->ctx_pages; i++) {
3252                         int j;
3253
3254                         /*
3255                          * Set the physical address of the context
3256                          * memory cache.
3257                          */
3258                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3259                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3260                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3261                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3262                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3263                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3264                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3265
3266                         /*
3267                          * Verify that the context memory write was successful.
3268                          */
3269                         for (j = 0; j < retry_cnt; j++) {
3270                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3271                                 if ((val &
3272                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3273                                         break;
3274                                 DELAY(5);
3275                         }
3276                         if (j == retry_cnt) {
3277                                 device_printf(sc->bce_dev,
3278                                     "Failed to initialize context page!\n");
3279                                 return ETIMEDOUT;
3280                         }
3281                 }
3282         } else {
3283                 uint32_t vcid_addr, offset;
3284
3285                 /*
3286                  * For the 5706/5708, context memory is local to
3287                  * the controller, so initialize the controller
3288                  * context memory.
3289                  */
3290
3291                 vcid_addr = GET_CID_ADDR(96);
3292                 while (vcid_addr) {
3293                         vcid_addr -= PHY_CTX_SIZE;
3294
3295                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3296                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3297
3298                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3299                                 CTX_WR(sc, 0x00, offset, 0);
3300
3301                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3302                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3303                 }
3304         }
3305         return 0;
3306 }
3307
3308
3309 /****************************************************************************/
3310 /* Fetch the permanent MAC address of the controller.                       */
3311 /*                                                                          */
3312 /* Returns:                                                                 */
3313 /*   Nothing.                                                               */
3314 /****************************************************************************/
3315 static void
3316 bce_get_mac_addr(struct bce_softc *sc)
3317 {
3318         uint32_t mac_lo = 0, mac_hi = 0;
3319
3320         /*
3321          * The NetXtreme II bootcode populates various NIC
3322          * power-on and runtime configuration items in a
3323          * shared memory area.  The factory configured MAC
3324          * address is available from both NVRAM and the
3325          * shared memory area so we'll read the value from
3326          * shared memory for speed.
3327          */
3328
3329         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3330         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3331
3332         if (mac_lo == 0 && mac_hi == 0) {
3333                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3334         } else {
3335                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3336                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3337                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3338                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3339                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3340                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3341         }
3342
3343         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3344 }
3345
3346
3347 /****************************************************************************/
3348 /* Program the MAC address.                                                 */
3349 /*                                                                          */
3350 /* Returns:                                                                 */
3351 /*   Nothing.                                                               */
3352 /****************************************************************************/
3353 static void
3354 bce_set_mac_addr(struct bce_softc *sc)
3355 {
3356         const uint8_t *mac_addr = sc->eaddr;
3357         uint32_t val;
3358
3359         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3360                 sc->eaddr, ":");
3361
3362         val = (mac_addr[0] << 8) | mac_addr[1];
3363         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3364
3365         val = (mac_addr[2] << 24) |
3366               (mac_addr[3] << 16) |
3367               (mac_addr[4] << 8) |
3368               mac_addr[5];
3369         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3370 }
3371
3372
3373 /****************************************************************************/
3374 /* Stop the controller.                                                     */
3375 /*                                                                          */
3376 /* Returns:                                                                 */
3377 /*   Nothing.                                                               */
3378 /****************************************************************************/
3379 static void
3380 bce_stop(struct bce_softc *sc)
3381 {
3382         struct ifnet *ifp = &sc->arpcom.ac_if;
3383
3384         ASSERT_SERIALIZED(ifp->if_serializer);
3385
3386         callout_stop(&sc->bce_tick_callout);
3387
3388         /* Disable the transmit/receive blocks. */
3389         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3390         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3391         DELAY(20);
3392
3393         bce_disable_intr(sc);
3394
3395         /* Free the RX lists. */
3396         bce_free_rx_chain(sc);
3397
3398         /* Free TX buffers. */
3399         bce_free_tx_chain(sc);
3400
3401         sc->bce_link = 0;
3402         sc->bce_coalchg_mask = 0;
3403
3404         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3405         ifp->if_timer = 0;
3406 }
3407
3408
3409 static int
3410 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3411 {
3412         uint32_t val;
3413         int i, rc = 0;
3414
3415         /* Wait for pending PCI transactions to complete. */
3416         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3417                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3418                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3419                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3420                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3421         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3422         DELAY(5);
3423
3424         /* Disable DMA */
3425         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3426             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3427                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3428                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3429                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3430         }
3431
3432         /* Assume bootcode is running. */
3433         sc->bce_fw_timed_out = 0;
3434         sc->bce_drv_cardiac_arrest = 0;
3435
3436         /* Give the firmware a chance to prepare for the reset. */
3437         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3438         if (rc) {
3439                 if_printf(&sc->arpcom.ac_if,
3440                           "Firmware is not ready for reset\n");
3441                 return rc;
3442         }
3443
3444         /* Set a firmware reminder that this is a soft reset. */
3445         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3446             BCE_DRV_RESET_SIGNATURE_MAGIC);
3447
3448         /* Dummy read to force the chip to complete all current transactions. */
3449         val = REG_RD(sc, BCE_MISC_ID);
3450
3451         /* Chip reset. */
3452         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3453             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3454                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3455                 REG_RD(sc, BCE_MISC_COMMAND);
3456                 DELAY(5);
3457
3458                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3459                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3460
3461                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3462         } else {
3463                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3464                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3465                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3466                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3467
3468                 /* Allow up to 30us for reset to complete. */
3469                 for (i = 0; i < 10; i++) {
3470                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3471                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3472                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3473                                 break;
3474                         DELAY(10);
3475                 }
3476
3477                 /* Check that reset completed successfully. */
3478                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3479                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3480                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3481                         return EBUSY;
3482                 }
3483         }
3484
3485         /* Make sure byte swapping is properly configured. */
3486         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3487         if (val != 0x01020304) {
3488                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3489                 return ENODEV;
3490         }
3491
3492         /* Just completed a reset, assume that firmware is running again. */
3493         sc->bce_fw_timed_out = 0;
3494         sc->bce_drv_cardiac_arrest = 0;
3495
3496         /* Wait for the firmware to finish its initialization. */
3497         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3498         if (rc) {
3499                 if_printf(&sc->arpcom.ac_if,
3500                           "Firmware did not complete initialization!\n");
3501         }
3502         return rc;
3503 }
3504
3505
3506 static int
3507 bce_chipinit(struct bce_softc *sc)
3508 {
3509         uint32_t val;
3510         int rc = 0;
3511
3512         /* Make sure the interrupt is not active. */
3513         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3514         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3515
3516         /*
3517          * Initialize DMA byte/word swapping, configure the number of DMA
3518          * channels and PCI clock compensation delay.
3519          */
3520         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3521               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3522 #if BYTE_ORDER == BIG_ENDIAN
3523               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3524 #endif
3525               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3526               DMA_READ_CHANS << 12 |
3527               DMA_WRITE_CHANS << 16;
3528
3529         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3530
3531         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3532                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3533
3534         /*
3535          * This setting resolves a problem observed on certain Intel PCI
3536          * chipsets that cannot handle multiple outstanding DMA operations.
3537          * See errata E9_5706A1_65.
3538          */
3539         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3540             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3541             !(sc->bce_flags & BCE_PCIX_FLAG))
3542                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3543
3544         REG_WR(sc, BCE_DMA_CONFIG, val);
3545
3546         /* Enable the RX_V2P and Context state machines before access. */
3547         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3548                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3549                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3550                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3551
3552         /* Initialize context mapping and zero out the quick contexts. */
3553         rc = bce_init_ctx(sc);
3554         if (rc != 0)
3555                 return rc;
3556
3557         /* Initialize the on-boards CPUs */
3558         bce_init_cpus(sc);
3559
3560         /* Enable management frames (NC-SI) to flow to the MCP. */
3561         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3562                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3563                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3564                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3565         }
3566
3567         /* Prepare NVRAM for access. */
3568         rc = bce_init_nvram(sc);
3569         if (rc != 0)
3570                 return rc;
3571
3572         /* Set the kernel bypass block size */
3573         val = REG_RD(sc, BCE_MQ_CONFIG);
3574         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3575         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3576
3577         /* Enable bins used on the 5709/5716. */
3578         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3579             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3580                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3581                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3582                         val |= BCE_MQ_CONFIG_HALT_DIS;
3583         }
3584
3585         REG_WR(sc, BCE_MQ_CONFIG, val);
3586
3587         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3588         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3589         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3590
3591         /* Set the page size and clear the RV2P processor stall bits. */
3592         val = (BCM_PAGE_BITS - 8) << 24;
3593         REG_WR(sc, BCE_RV2P_CONFIG, val);
3594
3595         /* Configure page size. */
3596         val = REG_RD(sc, BCE_TBDR_CONFIG);
3597         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3598         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3599         REG_WR(sc, BCE_TBDR_CONFIG, val);
3600
3601         /* Set the perfect match control register to default. */
3602         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3603
3604         return 0;
3605 }
3606
3607
3608 /****************************************************************************/
3609 /* Initialize the controller in preparation to send/receive traffic.        */
3610 /*                                                                          */
3611 /* Returns:                                                                 */
3612 /*   0 for success, positive value for failure.                             */
3613 /****************************************************************************/
3614 static int
3615 bce_blockinit(struct bce_softc *sc)
3616 {
3617         uint32_t reg, val;
3618         int rc = 0;
3619
3620         /* Load the hardware default MAC address. */
3621         bce_set_mac_addr(sc);
3622
3623         /* Set the Ethernet backoff seed value */
3624         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3625               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3626         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3627
3628         sc->last_status_idx = 0;
3629         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3630
3631         /* Set up link change interrupt generation. */
3632         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3633
3634         /* Program the physical address of the status block. */
3635         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3636         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3637
3638         /* Program the physical address of the statistics block. */
3639         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3640                BCE_ADDR_LO(sc->stats_block_paddr));
3641         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3642                BCE_ADDR_HI(sc->stats_block_paddr));
3643
3644         /* Program various host coalescing parameters. */
3645         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3646                (sc->bce_tx_quick_cons_trip_int << 16) |
3647                sc->bce_tx_quick_cons_trip);
3648         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3649                (sc->bce_rx_quick_cons_trip_int << 16) |
3650                sc->bce_rx_quick_cons_trip);
3651         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3652                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3653         REG_WR(sc, BCE_HC_TX_TICKS,
3654                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3655         REG_WR(sc, BCE_HC_RX_TICKS,
3656                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3657         REG_WR(sc, BCE_HC_COM_TICKS,
3658                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3659         REG_WR(sc, BCE_HC_CMD_TICKS,
3660                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3661         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3662         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3663
3664         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3665         if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3666                 if (bootverbose)
3667                         if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3668                 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3669         }
3670         REG_WR(sc, BCE_HC_CONFIG, val);
3671
3672         /* Clear the internal statistics counters. */
3673         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3674
3675         /* Verify that bootcode is running. */
3676         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3677
3678         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3679                 if_printf(&sc->arpcom.ac_if,
3680                           "%s(%d): Simulating bootcode failure.\n",
3681                           __FILE__, __LINE__);
3682                 reg = 0);
3683
3684         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3685             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3686                 if_printf(&sc->arpcom.ac_if,
3687                           "Bootcode not running! Found: 0x%08X, "
3688                           "Expected: 08%08X\n",
3689                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3690                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3691                 return ENODEV;
3692         }
3693
3694         /* Enable DMA */
3695         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3696             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3697                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3698                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3699                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3700         }
3701
3702         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3703         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3704
3705         /* Enable link state change interrupt generation. */
3706         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3707
3708         /* Enable the RXP. */
3709         bce_start_rxp_cpu(sc);
3710
3711         /* Disable management frames (NC-SI) from flowing to the MCP. */
3712         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3713                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3714                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3715                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3716         }
3717
3718         /* Enable all remaining blocks in the MAC. */
3719         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3720             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3721                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3722                     BCE_MISC_ENABLE_DEFAULT_XI);
3723         } else {
3724                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3725         }
3726         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3727         DELAY(20);
3728
3729         /* Save the current host coalescing block settings. */
3730         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3731
3732         return 0;
3733 }
3734
3735
3736 /****************************************************************************/
3737 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3738 /*                                                                          */
3739 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3740 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3741 /* necessary.                                                               */
3742 /*                                                                          */
3743 /* Returns:                                                                 */
3744 /*   0 for success, positive value for failure.                             */
3745 /****************************************************************************/
3746 static int
3747 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3748                uint32_t *prod_bseq, int init)
3749 {
3750         bus_dmamap_t map;
3751         bus_dma_segment_t seg;
3752         struct mbuf *m_new;
3753         int error, nseg;
3754 #ifdef BCE_DEBUG
3755         uint16_t debug_chain_prod = *chain_prod;
3756 #endif
3757
3758         /* Make sure the inputs are valid. */
3759         DBRUNIF((*chain_prod > MAX_RX_BD),
3760                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3761                           "RX producer out of range: 0x%04X > 0x%04X\n",
3762                           __FILE__, __LINE__,
3763                           *chain_prod, (uint16_t)MAX_RX_BD));
3764
3765         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3766                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3767
3768         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3769                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3770                           "Simulating mbuf allocation failure.\n",
3771                           __FILE__, __LINE__);
3772                 sc->mbuf_alloc_failed++;
3773                 return ENOBUFS);
3774
3775         /* This is a new mbuf allocation. */
3776         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3777         if (m_new == NULL)
3778                 return ENOBUFS;
3779         DBRUNIF(1, sc->rx_mbuf_alloc++);
3780
3781         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3782
3783         /* Map the mbuf cluster into device memory. */
3784         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3785                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3786                         BUS_DMA_NOWAIT);
3787         if (error) {
3788                 m_freem(m_new);
3789                 if (init) {
3790                         if_printf(&sc->arpcom.ac_if,
3791                                   "Error mapping mbuf into RX chain!\n");
3792                 }
3793                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3794                 return error;
3795         }
3796
3797         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3798                 bus_dmamap_unload(sc->rx_mbuf_tag,
3799                                   sc->rx_mbuf_map[*chain_prod]);
3800         }
3801
3802         map = sc->rx_mbuf_map[*chain_prod];
3803         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3804         sc->rx_mbuf_tmpmap = map;
3805
3806         /* Watch for overflow. */
3807         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3808                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3809                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3810                           __FILE__, __LINE__, sc->free_rx_bd,
3811                           (uint16_t)USABLE_RX_BD));
3812
3813         /* Update some debug statistic counters */
3814         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3815                 sc->rx_low_watermark = sc->free_rx_bd);
3816         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3817
3818         /* Save the mbuf and update our counter. */
3819         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3820         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3821         sc->free_rx_bd--;
3822
3823         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3824
3825         DBRUN(BCE_VERBOSE_RECV,
3826               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3827
3828         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3829                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3830
3831         return 0;
3832 }
3833
3834
3835 static void
3836 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3837 {
3838         struct rx_bd *rxbd;
3839         bus_addr_t paddr;
3840         int len;
3841
3842         paddr = sc->rx_mbuf_paddr[chain_prod];
3843         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3844
3845         /* Setup the rx_bd for the first segment. */
3846         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3847
3848         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3849         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3850         rxbd->rx_bd_len = htole32(len);
3851         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3852         *prod_bseq += len;
3853
3854         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3855 }
3856
3857
3858 /****************************************************************************/
3859 /* Initialize the TX context memory.                                        */
3860 /*                                                                          */
3861 /* Returns:                                                                 */
3862 /*   Nothing                                                                */
3863 /****************************************************************************/
3864 static void
3865 bce_init_tx_context(struct bce_softc *sc)
3866 {
3867         uint32_t val;
3868
3869         /* Initialize the context ID for an L2 TX chain. */
3870         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3871             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3872                 /* Set the CID type to support an L2 connection. */
3873                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3874                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3875                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3876                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3877
3878                 /* Point the hardware to the first page in the chain. */
3879                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3880                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3881                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3882                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3883                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3884                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3885         } else {
3886                 /* Set the CID type to support an L2 connection. */
3887                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3888                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3889                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3890                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3891
3892                 /* Point the hardware to the first page in the chain. */
3893                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3894                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3895                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3896                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3897                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3898                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3899         }
3900 }
3901
3902
3903 /****************************************************************************/
3904 /* Allocate memory and initialize the TX data structures.                   */
3905 /*                                                                          */
3906 /* Returns:                                                                 */
3907 /*   0 for success, positive value for failure.                             */
3908 /****************************************************************************/
3909 static int
3910 bce_init_tx_chain(struct bce_softc *sc)
3911 {
3912         struct tx_bd *txbd;
3913         int i, rc = 0;
3914
3915         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3916
3917         /* Set the initial TX producer/consumer indices. */
3918         sc->tx_prod = 0;
3919         sc->tx_cons = 0;
3920         sc->tx_prod_bseq   = 0;
3921         sc->used_tx_bd = 0;
3922         sc->max_tx_bd = USABLE_TX_BD;
3923         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3924         DBRUNIF(1, sc->tx_full_count = 0);
3925
3926         /*
3927          * The NetXtreme II supports a linked-list structre called
3928          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3929          * consists of a series of 1 or more chain pages, each of which
3930          * consists of a fixed number of BD entries.
3931          * The last BD entry on each page is a pointer to the next page
3932          * in the chain, and the last pointer in the BD chain
3933          * points back to the beginning of the chain.
3934          */
3935
3936         /* Set the TX next pointer chain entries. */
3937         for (i = 0; i < TX_PAGES; i++) {
3938                 int j;
3939
3940                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3941
3942                 /* Check if we've reached the last page. */
3943                 if (i == (TX_PAGES - 1))
3944                         j = 0;
3945                 else
3946                         j = i + 1;
3947
3948                 txbd->tx_bd_haddr_hi =
3949                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3950                 txbd->tx_bd_haddr_lo =
3951                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3952         }
3953         bce_init_tx_context(sc);
3954
3955         return(rc);
3956 }
3957
3958
3959 /****************************************************************************/
3960 /* Free memory and clear the TX data structures.                            */
3961 /*                                                                          */
3962 /* Returns:                                                                 */
3963 /*   Nothing.                                                               */
3964 /****************************************************************************/
3965 static void
3966 bce_free_tx_chain(struct bce_softc *sc)
3967 {
3968         int i;
3969
3970         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3971
3972         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3973         for (i = 0; i < TOTAL_TX_BD; i++) {
3974                 if (sc->tx_mbuf_ptr[i] != NULL) {
3975                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3976                         m_freem(sc->tx_mbuf_ptr[i]);
3977                         sc->tx_mbuf_ptr[i] = NULL;
3978                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3979                 }
3980         }
3981
3982         /* Clear each TX chain page. */
3983         for (i = 0; i < TX_PAGES; i++)
3984                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3985         sc->used_tx_bd = 0;
3986
3987         /* Check if we lost any mbufs in the process. */
3988         DBRUNIF((sc->tx_mbuf_alloc),
3989                 if_printf(&sc->arpcom.ac_if,
3990                           "%s(%d): Memory leak! "
3991                           "Lost %d mbufs from tx chain!\n",
3992                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3993
3994         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3995 }
3996
3997
3998 /****************************************************************************/
3999 /* Initialize the RX context memory.                                        */
4000 /*                                                                          */
4001 /* Returns:                                                                 */
4002 /*   Nothing                                                                */
4003 /****************************************************************************/
4004 static void
4005 bce_init_rx_context(struct bce_softc *sc)
4006 {
4007         uint32_t val;
4008
4009         /* Initialize the context ID for an L2 RX chain. */
4010         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4011             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4012
4013         /*
4014          * Set the level for generating pause frames
4015          * when the number of available rx_bd's gets
4016          * too low (the low watermark) and the level
4017          * when pause frames can be stopped (the high
4018          * watermark).
4019          */
4020         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4021             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4022                 uint32_t lo_water, hi_water;
4023
4024                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4025                 hi_water = USABLE_RX_BD / 4;
4026
4027                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4028                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4029
4030                 if (hi_water > 0xf)
4031                         hi_water = 0xf;
4032                 else if (hi_water == 0)
4033                         lo_water = 0;
4034                 val |= lo_water |
4035                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4036         }
4037
4038         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4039
4040         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4041         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4042             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4043                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4044                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4045         }
4046
4047         /* Point the hardware to the first page in the chain. */
4048         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4049         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4050         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4051         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4052 }
4053
4054
4055 /****************************************************************************/
4056 /* Allocate memory and initialize the RX data structures.                   */
4057 /*                                                                          */
4058 /* Returns:                                                                 */
4059 /*   0 for success, positive value for failure.                             */
4060 /****************************************************************************/
4061 static int
4062 bce_init_rx_chain(struct bce_softc *sc)
4063 {
4064         struct rx_bd *rxbd;
4065         int i, rc = 0;
4066         uint16_t prod, chain_prod;
4067         uint32_t prod_bseq;
4068
4069         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4070
4071         /* Initialize the RX producer and consumer indices. */
4072         sc->rx_prod = 0;
4073         sc->rx_cons = 0;
4074         sc->rx_prod_bseq = 0;
4075         sc->free_rx_bd = USABLE_RX_BD;
4076         sc->max_rx_bd = USABLE_RX_BD;
4077         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
4078         DBRUNIF(1, sc->rx_empty_count = 0);
4079
4080         /* Initialize the RX next pointer chain entries. */
4081         for (i = 0; i < RX_PAGES; i++) {
4082                 int j;
4083
4084                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4085
4086                 /* Check if we've reached the last page. */
4087                 if (i == (RX_PAGES - 1))
4088                         j = 0;
4089                 else
4090                         j = i + 1;
4091
4092                 /* Setup the chain page pointers. */
4093                 rxbd->rx_bd_haddr_hi =
4094                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4095                 rxbd->rx_bd_haddr_lo =
4096                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4097         }
4098
4099         /* Allocate mbuf clusters for the rx_bd chain. */
4100         prod = prod_bseq = 0;
4101         while (prod < TOTAL_RX_BD) {
4102                 chain_prod = RX_CHAIN_IDX(prod);
4103                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4104                         if_printf(&sc->arpcom.ac_if,
4105                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4106                                   chain_prod);
4107                         rc = ENOBUFS;
4108                         break;
4109                 }
4110                 prod = NEXT_RX_BD(prod);
4111         }
4112
4113         /* Save the RX chain producer index. */
4114         sc->rx_prod = prod;
4115         sc->rx_prod_bseq = prod_bseq;
4116
4117         /* Tell the chip about the waiting rx_bd's. */
4118         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4119             sc->rx_prod);
4120         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4121             sc->rx_prod_bseq);
4122
4123         bce_init_rx_context(sc);
4124
4125         return(rc);
4126 }
4127
4128
4129 /****************************************************************************/
4130 /* Free memory and clear the RX data structures.                            */
4131 /*                                                                          */
4132 /* Returns:                                                                 */
4133 /*   Nothing.                                                               */
4134 /****************************************************************************/
4135 static void
4136 bce_free_rx_chain(struct bce_softc *sc)
4137 {
4138         int i;
4139
4140         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4141
4142         /* Free any mbufs still in the RX mbuf chain. */
4143         for (i = 0; i < TOTAL_RX_BD; i++) {
4144                 if (sc->rx_mbuf_ptr[i] != NULL) {
4145                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4146                         m_freem(sc->rx_mbuf_ptr[i]);
4147                         sc->rx_mbuf_ptr[i] = NULL;
4148                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4149                 }
4150         }
4151
4152         /* Clear each RX chain page. */
4153         for (i = 0; i < RX_PAGES; i++)
4154                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4155
4156         /* Check if we lost any mbufs in the process. */
4157         DBRUNIF((sc->rx_mbuf_alloc),
4158                 if_printf(&sc->arpcom.ac_if,
4159                           "%s(%d): Memory leak! "
4160                           "Lost %d mbufs from rx chain!\n",
4161                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4162
4163         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4164 }
4165
4166
4167 /****************************************************************************/
4168 /* Set media options.                                                       */
4169 /*                                                                          */
4170 /* Returns:                                                                 */
4171 /*   0 for success, positive value for failure.                             */
4172 /****************************************************************************/
4173 static int
4174 bce_ifmedia_upd(struct ifnet *ifp)
4175 {
4176         struct bce_softc *sc = ifp->if_softc;
4177         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4178         int error = 0;
4179
4180         /*
4181          * 'mii' will be NULL, when this function is called on following
4182          * code path: bce_attach() -> bce_mgmt_init()
4183          */
4184         if (mii != NULL) {
4185                 /* Make sure the MII bus has been enumerated. */
4186                 sc->bce_link = 0;
4187                 if (mii->mii_instance) {
4188                         struct mii_softc *miisc;
4189
4190                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4191                                 mii_phy_reset(miisc);
4192                 }
4193                 error = mii_mediachg(mii);
4194         }
4195         return error;
4196 }
4197
4198
4199 /****************************************************************************/
4200 /* Reports current media status.                                            */
4201 /*                                                                          */
4202 /* Returns:                                                                 */
4203 /*   Nothing.                                                               */
4204 /****************************************************************************/
4205 static void
4206 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4207 {
4208         struct bce_softc *sc = ifp->if_softc;
4209         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4210
4211         mii_pollstat(mii);
4212         ifmr->ifm_active = mii->mii_media_active;
4213         ifmr->ifm_status = mii->mii_media_status;
4214 }
4215
4216
4217 /****************************************************************************/
4218 /* Handles PHY generated interrupt events.                                  */
4219 /*                                                                          */
4220 /* Returns:                                                                 */
4221 /*   Nothing.                                                               */
4222 /****************************************************************************/
4223 static void
4224 bce_phy_intr(struct bce_softc *sc)
4225 {
4226         uint32_t new_link_state, old_link_state;
4227         struct ifnet *ifp = &sc->arpcom.ac_if;
4228
4229         ASSERT_SERIALIZED(ifp->if_serializer);
4230
4231         new_link_state = sc->status_block->status_attn_bits &
4232                          STATUS_ATTN_BITS_LINK_STATE;
4233         old_link_state = sc->status_block->status_attn_bits_ack &
4234                          STATUS_ATTN_BITS_LINK_STATE;
4235
4236         /* Handle any changes if the link state has changed. */
4237         if (new_link_state != old_link_state) { /* XXX redundant? */
4238                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4239
4240                 /* Update the status_attn_bits_ack field in the status block. */
4241                 if (new_link_state) {
4242                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4243                                STATUS_ATTN_BITS_LINK_STATE);
4244                         if (bootverbose)
4245                                 if_printf(ifp, "Link is now UP.\n");
4246                 } else {
4247                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4248                                STATUS_ATTN_BITS_LINK_STATE);
4249                         if (bootverbose)
4250                                 if_printf(ifp, "Link is now DOWN.\n");
4251                 }
4252
4253                 /*
4254                  * Assume link is down and allow tick routine to
4255                  * update the state based on the actual media state.
4256                  */
4257                 sc->bce_link = 0;
4258                 callout_stop(&sc->bce_tick_callout);
4259                 bce_tick_serialized(sc);
4260         }
4261
4262         /* Acknowledge the link change interrupt. */
4263         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4264 }
4265
4266
4267 /****************************************************************************/
4268 /* Reads the receive consumer value from the status block (skipping over    */
4269 /* chain page pointer if necessary).                                        */
4270 /*                                                                          */
4271 /* Returns:                                                                 */
4272 /*   hw_cons                                                                */
4273 /****************************************************************************/
4274 static __inline uint16_t
4275 bce_get_hw_rx_cons(struct bce_softc *sc)
4276 {
4277         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4278
4279         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4280                 hw_cons++;
4281         return hw_cons;
4282 }
4283
4284
4285 /****************************************************************************/
4286 /* Handles received frame interrupt events.                                 */
4287 /*                                                                          */
4288 /* Returns:                                                                 */
4289 /*   Nothing.                                                               */
4290 /****************************************************************************/
4291 static void
4292 bce_rx_intr(struct bce_softc *sc, int count)
4293 {
4294         struct ifnet *ifp = &sc->arpcom.ac_if;
4295         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4296         uint32_t sw_prod_bseq;
4297         struct mbuf_chain chain[MAXCPU];
4298
4299         ASSERT_SERIALIZED(ifp->if_serializer);
4300
4301         ether_input_chain_init(chain);
4302
4303         DBRUNIF(1, sc->rx_interrupts++);
4304
4305         /* Get the hardware's view of the RX consumer index. */
4306         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4307
4308         /* Get working copies of the driver's view of the RX indices. */
4309         sw_cons = sc->rx_cons;
4310         sw_prod = sc->rx_prod;
4311         sw_prod_bseq = sc->rx_prod_bseq;
4312
4313         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4314                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4315                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4316
4317         /* Prevent speculative reads from getting ahead of the status block. */
4318         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4319                           BUS_SPACE_BARRIER_READ);
4320
4321         /* Update some debug statistics counters */
4322         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4323                 sc->rx_low_watermark = sc->free_rx_bd);
4324         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4325
4326         /* Scan through the receive chain as long as there is work to do. */
4327         while (sw_cons != hw_cons) {
4328                 struct mbuf *m = NULL;
4329                 struct l2_fhdr *l2fhdr = NULL;
4330                 struct rx_bd *rxbd;
4331                 unsigned int len;
4332                 uint32_t status = 0;
4333
4334 #ifdef DEVICE_POLLING
4335                 if (count >= 0 && count-- == 0) {
4336                         sc->hw_rx_cons = sw_cons;
4337                         break;
4338                 }
4339 #endif
4340
4341                 /*
4342                  * Convert the producer/consumer indices
4343                  * to an actual rx_bd index.
4344                  */
4345                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4346                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4347
4348                 /* Get the used rx_bd. */
4349                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4350                                        [RX_IDX(sw_chain_cons)];
4351                 sc->free_rx_bd++;
4352
4353                 DBRUN(BCE_VERBOSE_RECV,
4354                       if_printf(ifp, "%s(): ", __func__);
4355                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4356
4357                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4358                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4359                         /* Validate that this is the last rx_bd. */
4360                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4361                                 if_printf(ifp, "%s(%d): "
4362                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4363                                 __FILE__, __LINE__, sw_chain_cons);
4364                                 bce_breakpoint(sc));
4365
4366                         if (sw_chain_cons != sw_chain_prod) {
4367                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4368                                           "drop!\n", sw_chain_cons,
4369                                           sw_chain_prod);
4370                                 ifp->if_ierrors++;
4371
4372                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4373                                                      &sw_prod_bseq);
4374                                 m = NULL;
4375                                 goto bce_rx_int_next_rx;
4376                         }
4377
4378                         /* Unmap the mbuf from DMA space. */
4379                         bus_dmamap_sync(sc->rx_mbuf_tag,
4380                                         sc->rx_mbuf_map[sw_chain_cons],
4381                                         BUS_DMASYNC_POSTREAD);
4382
4383                         /* Save the mbuf from the driver's chain. */
4384                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4385
4386                         /*
4387                          * Frames received on the NetXteme II are prepended
4388                          * with an l2_fhdr structure which provides status
4389                          * information about the received frame (including
4390                          * VLAN tags and checksum info).  The frames are also
4391                          * automatically adjusted to align the IP header
4392                          * (i.e. two null bytes are inserted before the
4393                          * Ethernet header).  As a result the data DMA'd by
4394                          * the controller into the mbuf is as follows:
4395                          *
4396                          * +---------+-----+---------------------+-----+
4397                          * | l2_fhdr | pad | packet data         | FCS |
4398                          * +---------+-----+---------------------+-----+
4399                          *
4400                          * The l2_fhdr needs to be checked and skipped and the
4401                          * FCS needs to be stripped before sending the packet
4402                          * up the stack.
4403                          */
4404                         l2fhdr = mtod(m, struct l2_fhdr *);
4405
4406                         len = l2fhdr->l2_fhdr_pkt_len;
4407                         status = l2fhdr->l2_fhdr_status;
4408
4409                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4410                                 if_printf(ifp,
4411                                 "Simulating l2_fhdr status error.\n");
4412                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4413
4414                         /* Watch for unusual sized frames. */
4415                         DBRUNIF((len < BCE_MIN_MTU ||
4416                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4417                                 if_printf(ifp,
4418                                 "%s(%d): Unusual frame size found. "
4419                                 "Min(%d), Actual(%d), Max(%d)\n",
4420                                 __FILE__, __LINE__,
4421                                 (int)BCE_MIN_MTU, len,
4422                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4423                                 bce_dump_mbuf(sc, m);
4424                                 bce_breakpoint(sc));
4425
4426                         len -= ETHER_CRC_LEN;
4427
4428                         /* Check the received frame for errors. */
4429                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4430                                       L2_FHDR_ERRORS_PHY_DECODE |
4431                                       L2_FHDR_ERRORS_ALIGNMENT |
4432                                       L2_FHDR_ERRORS_TOO_SHORT |
4433                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4434                                 ifp->if_ierrors++;
4435                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4436
4437                                 /* Reuse the mbuf for a new frame. */
4438                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4439                                                      &sw_prod_bseq);
4440                                 m = NULL;
4441                                 goto bce_rx_int_next_rx;
4442                         }
4443
4444                         /*
4445                          * Get a new mbuf for the rx_bd.   If no new
4446                          * mbufs are available then reuse the current mbuf,
4447                          * log an ierror on the interface, and generate
4448                          * an error in the system log.
4449                          */
4450                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4451                                            &sw_prod_bseq, 0)) {
4452                                 DBRUN(BCE_WARN,
4453                                       if_printf(ifp,
4454                                       "%s(%d): Failed to allocate new mbuf, "
4455                                       "incoming frame dropped!\n",
4456                                       __FILE__, __LINE__));
4457
4458                                 ifp->if_ierrors++;
4459
4460                                 /* Try and reuse the exisitng mbuf. */
4461                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4462                                                      &sw_prod_bseq);
4463                                 m = NULL;
4464                                 goto bce_rx_int_next_rx;
4465                         }
4466
4467                         /*
4468                          * Skip over the l2_fhdr when passing
4469                          * the data up the stack.
4470                          */
4471                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4472
4473                         m->m_pkthdr.len = m->m_len = len;
4474                         m->m_pkthdr.rcvif = ifp;
4475
4476                         DBRUN(BCE_VERBOSE_RECV,
4477                               struct ether_header *eh;
4478                               eh = mtod(m, struct ether_header *);
4479                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4480                                         "type: 0x%04X\n", __func__,
4481                                         eh->ether_dhost, ":",
4482                                         eh->ether_shost, ":",
4483                                         htons(eh->ether_type)));
4484
4485                         /* Validate the checksum if offload enabled. */
4486                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4487                                 /* Check for an IP datagram. */
4488                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4489                                         m->m_pkthdr.csum_flags |=
4490                                                 CSUM_IP_CHECKED;
4491
4492                                         /* Check if the IP checksum is valid. */
4493                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4494                                              0xffff) == 0) {
4495                                                 m->m_pkthdr.csum_flags |=
4496                                                         CSUM_IP_VALID;
4497                                         } else {
4498                                                 DBPRINT(sc, BCE_WARN_RECV,
4499                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4500                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4501                                         }
4502                                 }
4503
4504                                 /* Check for a valid TCP/UDP frame. */
4505                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4506                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4507
4508                                         /* Check for a good TCP/UDP checksum. */
4509                                         if ((status &
4510                                              (L2_FHDR_ERRORS_TCP_XSUM |
4511                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4512                                                 m->m_pkthdr.csum_data =
4513                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4514                                                 m->m_pkthdr.csum_flags |=
4515                                                         CSUM_DATA_VALID |
4516                                                         CSUM_PSEUDO_HDR;
4517                                         } else {
4518                                                 DBPRINT(sc, BCE_WARN_RECV,
4519                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4520                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4521                                         }
4522                                 }
4523                         }
4524
4525                         ifp->if_ipackets++;
4526 bce_rx_int_next_rx:
4527                         sw_prod = NEXT_RX_BD(sw_prod);
4528                 }
4529
4530                 sw_cons = NEXT_RX_BD(sw_cons);
4531
4532                 /* If we have a packet, pass it up the stack */
4533                 if (m) {
4534                         DBPRINT(sc, BCE_VERBOSE_RECV,
4535                                 "%s(): Passing received frame up.\n", __func__);
4536
4537                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4538                                 m->m_flags |= M_VLANTAG;
4539                                 m->m_pkthdr.ether_vlantag =
4540                                         l2fhdr->l2_fhdr_vlan_tag;
4541                         }
4542                         ether_input_chain(ifp, m, NULL, chain);
4543
4544                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4545                 }
4546
4547                 /*
4548                  * If polling(4) is not enabled, refresh hw_cons to see
4549                  * whether there's new work.
4550                  *
4551                  * If polling(4) is enabled, i.e count >= 0, refreshing
4552                  * should not be performed, so that we would not spend
4553                  * too much time in RX processing.
4554                  */
4555                 if (count < 0 && sw_cons == hw_cons)
4556                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4557
4558                 /*
4559                  * Prevent speculative reads from getting ahead
4560                  * of the status block.
4561                  */
4562                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4563                                   BUS_SPACE_BARRIER_READ);
4564         }
4565
4566         ether_input_dispatch(chain);
4567
4568         sc->rx_cons = sw_cons;
4569         sc->rx_prod = sw_prod;
4570         sc->rx_prod_bseq = sw_prod_bseq;
4571
4572         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4573             sc->rx_prod);
4574         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4575             sc->rx_prod_bseq);
4576
4577         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4578                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4579                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4580 }
4581
4582
4583 /****************************************************************************/
4584 /* Reads the transmit consumer value from the status block (skipping over   */
4585 /* chain page pointer if necessary).                                        */
4586 /*                                                                          */
4587 /* Returns:                                                                 */
4588 /*   hw_cons                                                                */
4589 /****************************************************************************/
4590 static __inline uint16_t
4591 bce_get_hw_tx_cons(struct bce_softc *sc)
4592 {
4593         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4594
4595         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4596                 hw_cons++;
4597         return hw_cons;
4598 }
4599
4600
4601 /****************************************************************************/
4602 /* Handles transmit completion interrupt events.                            */
4603 /*                                                                          */
4604 /* Returns:                                                                 */
4605 /*   Nothing.                                                               */
4606 /****************************************************************************/
4607 static void
4608 bce_tx_intr(struct bce_softc *sc)
4609 {
4610         struct ifnet *ifp = &sc->arpcom.ac_if;
4611         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4612
4613         ASSERT_SERIALIZED(ifp->if_serializer);
4614
4615         DBRUNIF(1, sc->tx_interrupts++);
4616
4617         /* Get the hardware's view of the TX consumer index. */
4618         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4619         sw_tx_cons = sc->tx_cons;
4620
4621         /* Prevent speculative reads from getting ahead of the status block. */
4622         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4623                           BUS_SPACE_BARRIER_READ);
4624
4625         /* Cycle through any completed TX chain page entries. */
4626         while (sw_tx_cons != hw_tx_cons) {
4627 #ifdef BCE_DEBUG
4628                 struct tx_bd *txbd = NULL;
4629 #endif
4630                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4631
4632                 DBPRINT(sc, BCE_INFO_SEND,
4633                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4634                         "sw_tx_chain_cons = 0x%04X\n",
4635                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4636
4637                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4638                         if_printf(ifp, "%s(%d): "
4639                                   "TX chain consumer out of range! "
4640                                   " 0x%04X > 0x%04X\n",
4641                                   __FILE__, __LINE__, sw_tx_chain_cons,
4642                                   (int)MAX_TX_BD);
4643                         bce_breakpoint(sc));
4644
4645                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4646                                 [TX_IDX(sw_tx_chain_cons)]);
4647
4648                 DBRUNIF((txbd == NULL),
4649                         if_printf(ifp, "%s(%d): "
4650                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4651                                   __FILE__, __LINE__, sw_tx_chain_cons);
4652                         bce_breakpoint(sc));
4653
4654                 DBRUN(BCE_INFO_SEND,
4655                       if_printf(ifp, "%s(): ", __func__);
4656                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4657
4658                 /*
4659                  * Free the associated mbuf. Remember
4660                  * that only the last tx_bd of a packet
4661                  * has an mbuf pointer and DMA map.
4662                  */
4663                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4664                         /* Validate that this is the last tx_bd. */
4665                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4666                                 if_printf(ifp, "%s(%d): "
4667                                 "tx_bd END flag not set but "
4668                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4669                                 bce_breakpoint(sc));
4670
4671                         DBRUN(BCE_INFO_SEND,
4672                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4673                                         "from tx_bd[0x%04X]\n", __func__,
4674                                         sw_tx_chain_cons));
4675
4676                         /* Unmap the mbuf. */
4677                         bus_dmamap_unload(sc->tx_mbuf_tag,
4678                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4679
4680                         /* Free the mbuf. */
4681                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4682                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4683                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4684
4685                         ifp->if_opackets++;
4686                 }
4687
4688                 sc->used_tx_bd--;
4689                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4690
4691                 if (sw_tx_cons == hw_tx_cons) {
4692                         /* Refresh hw_cons to see if there's new work. */
4693                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4694                 }
4695
4696                 /*
4697                  * Prevent speculative reads from getting
4698                  * ahead of the status block.
4699                  */
4700                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4701                                   BUS_SPACE_BARRIER_READ);
4702         }
4703
4704         if (sc->used_tx_bd == 0) {
4705                 /* Clear the TX timeout timer. */
4706                 ifp->if_timer = 0;
4707         }
4708
4709         /* Clear the tx hardware queue full flag. */
4710         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4711                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4712                         DBPRINT(sc, BCE_WARN_SEND,
4713                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4714                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4715                 ifp->if_flags &= ~IFF_OACTIVE;
4716         }
4717         sc->tx_cons = sw_tx_cons;
4718 }
4719
4720
4721 /****************************************************************************/
4722 /* Disables interrupt generation.                                           */
4723 /*                                                                          */
4724 /* Returns:                                                                 */
4725 /*   Nothing.                                                               */
4726 /****************************************************************************/
4727 static void
4728 bce_disable_intr(struct bce_softc *sc)
4729 {
4730         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4731         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4732         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4733 }
4734
4735
4736 /****************************************************************************/
4737 /* Enables interrupt generation.                                            */
4738 /*                                                                          */
4739 /* Returns:                                                                 */
4740 /*   Nothing.                                                               */
4741 /****************************************************************************/
4742 static void
4743 bce_enable_intr(struct bce_softc *sc, int coal_now)
4744 {
4745         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4746
4747         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4748                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4749                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4750
4751         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4752                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4753
4754         if (coal_now) {
4755                 REG_WR(sc, BCE_HC_COMMAND,
4756                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4757         }
4758 }
4759
4760
4761 /****************************************************************************/
4762 /* Handles controller initialization.                                       */
4763 /*                                                                          */
4764 /* Returns:                                                                 */
4765 /*   Nothing.                                                               */
4766 /****************************************************************************/
4767 static void
4768 bce_init(void *xsc)
4769 {
4770         struct bce_softc *sc = xsc;
4771         struct ifnet *ifp = &sc->arpcom.ac_if;
4772         uint32_t ether_mtu;
4773         int error;
4774
4775         ASSERT_SERIALIZED(ifp->if_serializer);
4776
4777         /* Check if the driver is still running and bail out if it is. */
4778         if (ifp->if_flags & IFF_RUNNING)
4779                 return;
4780
4781         bce_stop(sc);
4782
4783         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4784         if (error) {
4785                 if_printf(ifp, "Controller reset failed!\n");
4786                 goto back;
4787         }
4788
4789         error = bce_chipinit(sc);
4790         if (error) {
4791                 if_printf(ifp, "Controller initialization failed!\n");
4792                 goto back;
4793         }
4794
4795         error = bce_blockinit(sc);
4796         if (error) {
4797                 if_printf(ifp, "Block initialization failed!\n");
4798                 goto back;
4799         }
4800
4801         /* Load our MAC address. */
4802         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4803         bce_set_mac_addr(sc);
4804
4805         /* Calculate and program the Ethernet MTU size. */
4806         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4807
4808         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4809
4810         /*
4811          * Program the mtu, enabling jumbo frame
4812          * support if necessary.  Also set the mbuf
4813          * allocation count for RX frames.
4814          */
4815         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4816 #ifdef notyet
4817                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4818                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4819                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4820                 sc->mbuf_alloc_size = MJUM9BYTES;
4821 #else
4822                 panic("jumbo buffer is not supported yet\n");
4823 #endif
4824         } else {
4825                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4826                 sc->mbuf_alloc_size = MCLBYTES;
4827         }
4828
4829         /* Calculate the RX Ethernet frame size for rx_bd's. */
4830         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4831
4832         DBPRINT(sc, BCE_INFO,
4833                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4834                 "max_frame_size = %d\n",
4835                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4836                 sc->max_frame_size);
4837
4838         /* Program appropriate promiscuous/multicast filtering. */
4839         bce_set_rx_mode(sc);
4840
4841         /* Init RX buffer descriptor chain. */
4842         bce_init_rx_chain(sc);  /* XXX return value */
4843
4844         /* Init TX buffer descriptor chain. */
4845         bce_init_tx_chain(sc);  /* XXX return value */
4846
4847 #ifdef DEVICE_POLLING
4848         /* Disable interrupts if we are polling. */
4849         if (ifp->if_flags & IFF_POLLING) {
4850                 bce_disable_intr(sc);
4851
4852                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4853                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4854                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4855                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4856         } else
4857 #endif
4858         /* Enable host interrupts. */
4859         bce_enable_intr(sc, 1);
4860
4861         bce_ifmedia_upd(ifp);
4862
4863         ifp->if_flags |= IFF_RUNNING;
4864         ifp->if_flags &= ~IFF_OACTIVE;
4865
4866         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4867 back:
4868         if (error)
4869                 bce_stop(sc);
4870 }
4871
4872
4873 /****************************************************************************/
4874 /* Initialize the controller just enough so that any management firmware    */
4875 /* running on the device will continue to operate corectly.                 */
4876 /*                                                                          */
4877 /* Returns:                                                                 */
4878 /*   Nothing.                                                               */
4879 /****************************************************************************/
4880 static void
4881 bce_mgmt_init(struct bce_softc *sc)
4882 {
4883         struct ifnet *ifp = &sc->arpcom.ac_if;
4884
4885         /* Bail out if management firmware is not running. */
4886         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4887                 return;
4888
4889         /* Enable all critical blocks in the MAC. */
4890         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4891             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4892                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4893                     BCE_MISC_ENABLE_DEFAULT_XI);
4894         } else {
4895                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4896         }
4897         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4898         DELAY(20);
4899
4900         bce_ifmedia_upd(ifp);
4901 }
4902
4903
4904 /****************************************************************************/
4905 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4906 /* memory visible to the controller.                                        */
4907 /*                                                                          */
4908 /* Returns:                                                                 */
4909 /*   0 for success, positive value for failure.                             */
4910 /****************************************************************************/
4911 static int
4912 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4913 {
4914         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4915         bus_dmamap_t map, tmp_map;
4916         struct mbuf *m0 = *m_head;
4917         struct tx_bd *txbd = NULL;
4918         uint16_t vlan_tag = 0, flags = 0;
4919         uint16_t chain_prod, chain_prod_start, prod;
4920         uint32_t prod_bseq;
4921         int i, error, maxsegs, nsegs;
4922 #ifdef BCE_DEBUG
4923         uint16_t debug_prod;
4924 #endif
4925
4926         /* Transfer any checksum offload flags to the bd. */
4927         if (m0->m_pkthdr.csum_flags) {
4928                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4929                         flags |= TX_BD_FLAGS_IP_CKSUM;
4930                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4931                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4932         }
4933
4934         /* Transfer any VLAN tags to the bd. */
4935         if (m0->m_flags & M_VLANTAG) {
4936                 flags |= TX_BD_FLAGS_VLAN_TAG;
4937                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4938         }
4939
4940         prod = sc->tx_prod;
4941         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4942
4943         /* Map the mbuf into DMAable memory. */
4944         map = sc->tx_mbuf_map[chain_prod_start];
4945
4946         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4947         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4948                 ("not enough segements %d\n", maxsegs));
4949         if (maxsegs > BCE_MAX_SEGMENTS)
4950                 maxsegs = BCE_MAX_SEGMENTS;
4951
4952         /* Map the mbuf into our DMA address space. */
4953         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4954                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4955         if (error)
4956                 goto back;
4957         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4958
4959         /* Reset m0 */
4960         m0 = *m_head;
4961
4962         /* prod points to an empty tx_bd at this point. */
4963         prod_bseq  = sc->tx_prod_bseq;
4964
4965 #ifdef BCE_DEBUG
4966         debug_prod = chain_prod;
4967 #endif
4968
4969         DBPRINT(sc, BCE_INFO_SEND,
4970                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4971                 "prod_bseq = 0x%08X\n",
4972                 __func__, prod, chain_prod, prod_bseq);
4973
4974         /*
4975          * Cycle through each mbuf segment that makes up
4976          * the outgoing frame, gathering the mapping info
4977          * for that segment and creating a tx_bd to for
4978          * the mbuf.
4979          */
4980         for (i = 0; i < nsegs; i++) {
4981                 chain_prod = TX_CHAIN_IDX(prod);
4982                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4983
4984                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4985                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4986                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4987                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4988                 txbd->tx_bd_flags = htole16(flags);
4989                 prod_bseq += segs[i].ds_len;
4990                 if (i == 0)
4991                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4992                 prod = NEXT_TX_BD(prod);
4993         }
4994
4995         /* Set the END flag on the last TX buffer descriptor. */
4996         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4997
4998         DBRUN(BCE_EXCESSIVE_SEND,
4999               bce_dump_tx_chain(sc, debug_prod, nsegs));
5000
5001         DBPRINT(sc, BCE_INFO_SEND,
5002                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5003                 "prod_bseq = 0x%08X\n",
5004                 __func__, prod, chain_prod, prod_bseq);
5005
5006         /*
5007          * Ensure that the mbuf pointer for this transmission
5008          * is placed at the array index of the last
5009          * descriptor in this chain.  This is done
5010          * because a single map is used for all
5011          * segments of the mbuf and we don't want to
5012          * unload the map before all of the segments
5013          * have been freed.
5014          */
5015         sc->tx_mbuf_ptr[chain_prod] = m0;
5016
5017         tmp_map = sc->tx_mbuf_map[chain_prod];
5018         sc->tx_mbuf_map[chain_prod] = map;
5019         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5020
5021         sc->used_tx_bd += nsegs;
5022
5023         /* Update some debug statistic counters */
5024         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5025                 sc->tx_hi_watermark = sc->used_tx_bd);
5026         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5027         DBRUNIF(1, sc->tx_mbuf_alloc++);
5028
5029         DBRUN(BCE_VERBOSE_SEND,
5030               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5031
5032         /* prod points to the next free tx_bd at this point. */
5033         sc->tx_prod = prod;
5034         sc->tx_prod_bseq = prod_bseq;
5035 back:
5036         if (error) {
5037                 m_freem(*m_head);
5038                 *m_head = NULL;
5039         }
5040         return error;
5041 }
5042
5043
5044 /****************************************************************************/
5045 /* Main transmit routine when called from another routine with a lock.      */
5046 /*                                                                          */
5047 /* Returns:                                                                 */
5048 /*   Nothing.                                                               */
5049 /****************************************************************************/
5050 static void
5051 bce_start(struct ifnet *ifp)
5052 {
5053         struct bce_softc *sc = ifp->if_softc;
5054         int count = 0;
5055
5056         ASSERT_SERIALIZED(ifp->if_serializer);
5057
5058         /* If there's no link or the transmit queue is empty then just exit. */
5059         if (!sc->bce_link) {
5060                 ifq_purge(&ifp->if_snd);
5061                 return;
5062         }
5063
5064         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5065                 return;
5066
5067         DBPRINT(sc, BCE_INFO_SEND,
5068                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5069                 "tx_prod_bseq = 0x%08X\n",
5070                 __func__,
5071                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5072
5073         for (;;) {
5074                 struct mbuf *m_head;
5075
5076                 /*
5077                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5078                  * unlikely to fail.
5079                  */
5080                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5081                         ifp->if_flags |= IFF_OACTIVE;
5082                         break;
5083                 }
5084
5085                 /* Check for any frames to send. */
5086                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5087                 if (m_head == NULL)
5088                         break;
5089
5090                 /*
5091                  * Pack the data into the transmit ring. If we
5092                  * don't have room, place the mbuf back at the
5093                  * head of the queue and set the OACTIVE flag
5094                  * to wait for the NIC to drain the chain.
5095                  */
5096                 if (bce_encap(sc, &m_head)) {
5097                         ifp->if_oerrors++;
5098                         if (sc->used_tx_bd == 0) {
5099                                 continue;
5100                         } else {
5101                                 ifp->if_flags |= IFF_OACTIVE;
5102                                 break;
5103                         }
5104                 }
5105
5106                 count++;
5107
5108                 /* Send a copy of the frame to any BPF listeners. */
5109                 ETHER_BPF_MTAP(ifp, m_head);
5110         }
5111
5112         if (count == 0) {
5113                 /* no packets were dequeued */
5114                 DBPRINT(sc, BCE_VERBOSE_SEND,
5115                         "%s(): No packets were dequeued\n", __func__);
5116                 return;
5117         }
5118
5119         DBPRINT(sc, BCE_INFO_SEND,
5120                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5121                 "tx_prod_bseq = 0x%08X\n",
5122                 __func__,
5123                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5124
5125         REG_WR(sc, BCE_MQ_COMMAND,
5126             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5127
5128         /* Start the transmit. */
5129         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5130         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5131
5132         /* Set the tx timeout. */
5133         ifp->if_timer = BCE_TX_TIMEOUT;
5134 }
5135
5136
5137 /****************************************************************************/
5138 /* Handles any IOCTL calls from the operating system.                       */
5139 /*                                                                          */
5140 /* Returns:                                                                 */
5141 /*   0 for success, positive value for failure.                             */
5142 /****************************************************************************/
5143 static int
5144 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5145 {
5146         struct bce_softc *sc = ifp->if_softc;
5147         struct ifreq *ifr = (struct ifreq *)data;
5148         struct mii_data *mii;
5149         int mask, error = 0;
5150
5151         ASSERT_SERIALIZED(ifp->if_serializer);
5152
5153         switch(command) {
5154         case SIOCSIFMTU:
5155                 /* Check that the MTU setting is supported. */
5156                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5157 #ifdef notyet
5158                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5159 #else
5160                     ifr->ifr_mtu > ETHERMTU
5161 #endif
5162                    ) {
5163                         error = EINVAL;
5164                         break;
5165                 }
5166
5167                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5168
5169                 ifp->if_mtu = ifr->ifr_mtu;
5170                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5171                 bce_init(sc);
5172                 break;
5173
5174         case SIOCSIFFLAGS:
5175                 if (ifp->if_flags & IFF_UP) {
5176                         if (ifp->if_flags & IFF_RUNNING) {
5177                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5178
5179                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5180                                         bce_set_rx_mode(sc);
5181                         } else {
5182                                 bce_init(sc);
5183                         }
5184                 } else if (ifp->if_flags & IFF_RUNNING) {
5185                         bce_stop(sc);
5186
5187                         /* If MFW is running, restart the controller a bit. */
5188                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5189                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5190                                 bce_chipinit(sc);
5191                                 bce_mgmt_init(sc);
5192                         }
5193                 }
5194                 sc->bce_if_flags = ifp->if_flags;
5195                 break;
5196
5197         case SIOCADDMULTI:
5198         case SIOCDELMULTI:
5199                 if (ifp->if_flags & IFF_RUNNING)
5200                         bce_set_rx_mode(sc);
5201                 break;
5202
5203         case SIOCSIFMEDIA:
5204         case SIOCGIFMEDIA:
5205                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5206                         sc->bce_phy_flags);
5207                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5208
5209                 mii = device_get_softc(sc->bce_miibus);
5210                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5211                 break;
5212
5213         case SIOCSIFCAP:
5214                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5215                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5216                         (uint32_t) mask);
5217
5218                 if (mask & IFCAP_HWCSUM) {
5219                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5220                         if (IFCAP_HWCSUM & ifp->if_capenable)
5221                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5222                         else
5223                                 ifp->if_hwassist = 0;
5224                 }
5225                 break;
5226
5227         default:
5228                 error = ether_ioctl(ifp, command, data);
5229                 break;
5230         }
5231         return error;
5232 }
5233
5234
5235 /****************************************************************************/
5236 /* Transmit timeout handler.                                                */
5237 /*                                                                          */
5238 /* Returns:                                                                 */
5239 /*   Nothing.                                                               */
5240 /****************************************************************************/
5241 static void
5242 bce_watchdog(struct ifnet *ifp)
5243 {
5244         struct bce_softc *sc = ifp->if_softc;
5245
5246         ASSERT_SERIALIZED(ifp->if_serializer);
5247
5248         DBRUN(BCE_VERBOSE_SEND,
5249               bce_dump_driver_state(sc);
5250               bce_dump_status_block(sc));
5251
5252         /*
5253          * If we are in this routine because of pause frames, then
5254          * don't reset the hardware.
5255          */
5256         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5257                 return;
5258
5259         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5260
5261         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5262
5263         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5264         bce_init(sc);
5265
5266         ifp->if_oerrors++;
5267
5268         if (!ifq_is_empty(&ifp->if_snd))
5269                 if_devstart(ifp);
5270 }
5271
5272
5273 #ifdef DEVICE_POLLING
5274
5275 static void
5276 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5277 {
5278         struct bce_softc *sc = ifp->if_softc;
5279         struct status_block *sblk = sc->status_block;
5280         uint16_t hw_tx_cons, hw_rx_cons;
5281
5282         ASSERT_SERIALIZED(ifp->if_serializer);
5283
5284         switch (cmd) {
5285         case POLL_REGISTER:
5286                 bce_disable_intr(sc);
5287
5288                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5289                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5290                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5291                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5292                 return;
5293         case POLL_DEREGISTER:
5294                 bce_enable_intr(sc, 1);
5295
5296                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5297                        (sc->bce_tx_quick_cons_trip_int << 16) |
5298                        sc->bce_tx_quick_cons_trip);
5299                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5300                        (sc->bce_rx_quick_cons_trip_int << 16) |
5301                        sc->bce_rx_quick_cons_trip);
5302                 return;
5303         default:
5304                 break;
5305         }
5306
5307         if (cmd == POLL_AND_CHECK_STATUS) {
5308                 uint32_t status_attn_bits;
5309
5310                 status_attn_bits = sblk->status_attn_bits;
5311
5312                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5313                         if_printf(ifp,
5314                         "Simulating unexpected status attention bit set.");
5315                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5316
5317                 /* Was it a link change interrupt? */
5318                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5319                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5320                         bce_phy_intr(sc);
5321
5322                 /* Clear any transient status updates during link state change. */
5323                 REG_WR(sc, BCE_HC_COMMAND,
5324                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5325                 REG_RD(sc, BCE_HC_COMMAND);
5326
5327                 /*
5328                  * If any other attention is asserted then
5329                  * the chip is toast.
5330                  */
5331                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5332                      (sblk->status_attn_bits_ack &
5333                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5334                         DBRUN(1, sc->unexpected_attentions++);
5335
5336                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5337                                   sblk->status_attn_bits);
5338
5339                         DBRUN(BCE_FATAL,
5340                         if (bce_debug_unexpected_attention == 0)
5341                                 bce_breakpoint(sc));
5342
5343                         bce_init(sc);
5344                         return;
5345                 }
5346         }
5347
5348         hw_rx_cons = bce_get_hw_rx_cons(sc);
5349         hw_tx_cons = bce_get_hw_tx_cons(sc);
5350
5351         /* Check for any completed RX frames. */
5352         if (hw_rx_cons != sc->hw_rx_cons)
5353                 bce_rx_intr(sc, count);
5354
5355         /* Check for any completed TX frames. */
5356         if (hw_tx_cons != sc->hw_tx_cons)
5357                 bce_tx_intr(sc);
5358
5359         /* Check for new frames to transmit. */
5360         if (!ifq_is_empty(&ifp->if_snd))
5361                 if_devstart(ifp);
5362 }
5363
5364 #endif  /* DEVICE_POLLING */
5365
5366
5367 /*
5368  * Interrupt handler.
5369  */
5370 /****************************************************************************/
5371 /* Main interrupt entry point.  Verifies that the controller generated the  */
5372 /* interrupt and then calls a separate routine for handle the various       */
5373 /* interrupt causes (PHY, TX, RX).                                          */
5374 /*                                                                          */
5375 /* Returns:                                                                 */
5376 /*   0 for success, positive value for failure.                             */
5377 /****************************************************************************/
5378 static void
5379 bce_intr(struct bce_softc *sc)
5380 {
5381         struct ifnet *ifp = &sc->arpcom.ac_if;
5382         struct status_block *sblk;
5383         uint16_t hw_rx_cons, hw_tx_cons;
5384
5385         ASSERT_SERIALIZED(ifp->if_serializer);
5386
5387         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5388         DBRUNIF(1, sc->interrupts_generated++);
5389
5390         sblk = sc->status_block;
5391
5392         /* Check if the hardware has finished any work. */
5393         hw_rx_cons = bce_get_hw_rx_cons(sc);
5394         hw_tx_cons = bce_get_hw_tx_cons(sc);
5395
5396         /* Keep processing data as long as there is work to do. */
5397         for (;;) {
5398                 uint32_t status_attn_bits;
5399
5400                 status_attn_bits = sblk->status_attn_bits;
5401
5402                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5403                         if_printf(ifp,
5404                         "Simulating unexpected status attention bit set.");
5405                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5406
5407                 /* Was it a link change interrupt? */
5408                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5409                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5410                         bce_phy_intr(sc);
5411
5412                         /*
5413                          * Clear any transient status updates during link state
5414                          * change.
5415                          */
5416                         REG_WR(sc, BCE_HC_COMMAND,
5417                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5418                         REG_RD(sc, BCE_HC_COMMAND);
5419                 }
5420
5421                 /*
5422                  * If any other attention is asserted then
5423                  * the chip is toast.
5424                  */
5425                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5426                      (sblk->status_attn_bits_ack &
5427                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5428                         DBRUN(1, sc->unexpected_attentions++);
5429
5430                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5431                                   sblk->status_attn_bits);
5432
5433                         DBRUN(BCE_FATAL,
5434                         if (bce_debug_unexpected_attention == 0)
5435                                 bce_breakpoint(sc));
5436
5437                         bce_init(sc);
5438                         return;
5439                 }
5440
5441                 /* Check for any completed RX frames. */
5442                 if (hw_rx_cons != sc->hw_rx_cons)
5443                         bce_rx_intr(sc, -1);
5444
5445                 /* Check for any completed TX frames. */
5446                 if (hw_tx_cons != sc->hw_tx_cons)
5447                         bce_tx_intr(sc);
5448
5449                 /*
5450                  * Save the status block index value
5451                  * for use during the next interrupt.
5452                  */
5453                 sc->last_status_idx = sblk->status_idx;
5454
5455                 /*
5456                  * Prevent speculative reads from getting
5457                  * ahead of the status block.
5458                  */
5459                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5460                                   BUS_SPACE_BARRIER_READ);
5461
5462                 /*
5463                  * If there's no work left then exit the
5464                  * interrupt service routine.
5465                  */
5466                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5467                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5468                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5469                         break;
5470         }
5471
5472         /* Re-enable interrupts. */
5473         bce_enable_intr(sc, 0);
5474
5475         if (sc->bce_coalchg_mask)
5476                 bce_coal_change(sc);
5477
5478         /* Handle any frames that arrived while handling the interrupt. */
5479         if (!ifq_is_empty(&ifp->if_snd))
5480                 if_devstart(ifp);
5481 }
5482
5483 static void
5484 bce_intr_legacy(void *xsc)
5485 {
5486         struct bce_softc *sc = xsc;
5487         struct status_block *sblk;
5488
5489         sblk = sc->status_block;
5490
5491         /*
5492          * If the hardware status block index matches the last value
5493          * read by the driver and we haven't asserted our interrupt
5494          * then there's nothing to do.
5495          */
5496         if (sblk->status_idx == sc->last_status_idx &&
5497             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5498              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5499                 return;
5500
5501         /* Ack the interrupt and stop others from occuring. */
5502         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5503                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5504                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5505
5506         /*
5507          * Read back to deassert IRQ immediately to avoid too
5508          * many spurious interrupts.
5509          */
5510         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5511
5512         bce_intr(sc);
5513 }
5514
5515 static void
5516 bce_intr_msi(void *xsc)
5517 {
5518         struct bce_softc *sc = xsc;
5519
5520         /* Ack the interrupt and stop others from occuring. */
5521         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5522                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5523                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5524
5525         bce_intr(sc);
5526 }
5527
5528 static void
5529 bce_intr_msi_oneshot(void *xsc)
5530 {
5531         bce_intr(xsc);
5532 }
5533
5534
5535 /****************************************************************************/
5536 /* Programs the various packet receive modes (broadcast and multicast).     */
5537 /*                                                                          */
5538 /* Returns:                                                                 */
5539 /*   Nothing.                                                               */
5540 /****************************************************************************/
5541 static void
5542 bce_set_rx_mode(struct bce_softc *sc)
5543 {
5544         struct ifnet *ifp = &sc->arpcom.ac_if;
5545         struct ifmultiaddr *ifma;
5546         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5547         uint32_t rx_mode, sort_mode;
5548         int h, i;
5549
5550         ASSERT_SERIALIZED(ifp->if_serializer);
5551
5552         /* Initialize receive mode default settings. */
5553         rx_mode = sc->rx_mode &
5554                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5555                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5556         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5557
5558         /*
5559          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5560          * be enbled.
5561          */
5562         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5563             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5564                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5565
5566         /*
5567          * Check for promiscuous, all multicast, or selected
5568          * multicast address filtering.
5569          */
5570         if (ifp->if_flags & IFF_PROMISC) {
5571                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5572
5573                 /* Enable promiscuous mode. */
5574                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5575                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5576         } else if (ifp->if_flags & IFF_ALLMULTI) {
5577                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5578
5579                 /* Enable all multicast addresses. */
5580                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5581                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5582                                0xffffffff);
5583                 }
5584                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5585         } else {
5586                 /* Accept one or more multicast(s). */
5587                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5588
5589                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5590                         if (ifma->ifma_addr->sa_family != AF_LINK)
5591                                 continue;
5592                         h = ether_crc32_le(
5593                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5594                             ETHER_ADDR_LEN) & 0xFF;
5595                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5596                 }
5597
5598                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5599                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5600                                hashes[i]);
5601                 }
5602                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5603         }
5604
5605         /* Only make changes if the recive mode has actually changed. */
5606         if (rx_mode != sc->rx_mode) {
5607                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5608                         rx_mode);
5609
5610                 sc->rx_mode = rx_mode;
5611                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5612         }
5613
5614         /* Disable and clear the exisitng sort before enabling a new sort. */
5615         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5616         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5617         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5618 }
5619
5620
5621 /****************************************************************************/
5622 /* Called periodically to updates statistics from the controllers           */
5623 /* statistics block.                                                        */
5624 /*                                                                          */
5625 /* Returns:                                                                 */
5626 /*   Nothing.                                                               */
5627 /****************************************************************************/
5628 static void
5629 bce_stats_update(struct bce_softc *sc)
5630 {
5631         struct ifnet *ifp = &sc->arpcom.ac_if;
5632         struct statistics_block *stats = sc->stats_block;
5633
5634         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5635
5636         ASSERT_SERIALIZED(ifp->if_serializer);
5637
5638         /*
5639          * Certain controllers don't report carrier sense errors correctly.
5640          * See errata E11_5708CA0_1165.
5641          */
5642         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5643             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5644                 ifp->if_oerrors +=
5645                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5646         }
5647
5648         /*
5649          * Update the sysctl statistics from the hardware statistics.
5650          */
5651         sc->stat_IfHCInOctets =
5652                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5653                  (uint64_t)stats->stat_IfHCInOctets_lo;
5654
5655         sc->stat_IfHCInBadOctets =
5656                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5657                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5658
5659         sc->stat_IfHCOutOctets =
5660                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5661                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5662
5663         sc->stat_IfHCOutBadOctets =
5664                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5665                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5666
5667         sc->stat_IfHCInUcastPkts =
5668                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5669                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5670
5671         sc->stat_IfHCInMulticastPkts =
5672                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5673                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5674
5675         sc->stat_IfHCInBroadcastPkts =
5676                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5677                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5678
5679         sc->stat_IfHCOutUcastPkts =
5680                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5681                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5682
5683         sc->stat_IfHCOutMulticastPkts =
5684                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5685                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5686
5687         sc->stat_IfHCOutBroadcastPkts =
5688                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5689                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5690
5691         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5692                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5693
5694         sc->stat_Dot3StatsCarrierSenseErrors =
5695                 stats->stat_Dot3StatsCarrierSenseErrors;
5696
5697         sc->stat_Dot3StatsFCSErrors =
5698                 stats->stat_Dot3StatsFCSErrors;
5699
5700         sc->stat_Dot3StatsAlignmentErrors =
5701                 stats->stat_Dot3StatsAlignmentErrors;
5702
5703         sc->stat_Dot3StatsSingleCollisionFrames =
5704                 stats->stat_Dot3StatsSingleCollisionFrames;
5705
5706         sc->stat_Dot3StatsMultipleCollisionFrames =
5707                 stats->stat_Dot3StatsMultipleCollisionFrames;
5708
5709         sc->stat_Dot3StatsDeferredTransmissions =
5710                 stats->stat_Dot3StatsDeferredTransmissions;
5711
5712         sc->stat_Dot3StatsExcessiveCollisions =
5713                 stats->stat_Dot3StatsExcessiveCollisions;
5714
5715         sc->stat_Dot3StatsLateCollisions =
5716                 stats->stat_Dot3StatsLateCollisions;
5717
5718         sc->stat_EtherStatsCollisions =
5719                 stats->stat_EtherStatsCollisions;
5720
5721         sc->stat_EtherStatsFragments =
5722                 stats->stat_EtherStatsFragments;
5723
5724         sc->stat_EtherStatsJabbers =
5725                 stats->stat_EtherStatsJabbers;
5726
5727         sc->stat_EtherStatsUndersizePkts =
5728                 stats->stat_EtherStatsUndersizePkts;
5729
5730         sc->stat_EtherStatsOverrsizePkts =
5731                 stats->stat_EtherStatsOverrsizePkts;
5732
5733         sc->stat_EtherStatsPktsRx64Octets =
5734                 stats->stat_EtherStatsPktsRx64Octets;
5735
5736         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5737                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5738
5739         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5740                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5741
5742         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5743                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5744
5745         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5746                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5747
5748         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5749                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5750
5751         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5752                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5753
5754         sc->stat_EtherStatsPktsTx64Octets =
5755                 stats->stat_EtherStatsPktsTx64Octets;
5756
5757         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5758                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5759
5760         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5761                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5762
5763         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5764                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5765
5766         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5767                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5768
5769         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5770                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5771
5772         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5773                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5774
5775         sc->stat_XonPauseFramesReceived =
5776                 stats->stat_XonPauseFramesReceived;
5777
5778         sc->stat_XoffPauseFramesReceived =
5779                 stats->stat_XoffPauseFramesReceived;
5780
5781         sc->stat_OutXonSent =
5782                 stats->stat_OutXonSent;
5783
5784         sc->stat_OutXoffSent =
5785                 stats->stat_OutXoffSent;
5786
5787         sc->stat_FlowControlDone =
5788                 stats->stat_FlowControlDone;
5789
5790         sc->stat_MacControlFramesReceived =
5791                 stats->stat_MacControlFramesReceived;
5792
5793         sc->stat_XoffStateEntered =
5794                 stats->stat_XoffStateEntered;
5795
5796         sc->stat_IfInFramesL2FilterDiscards =
5797                 stats->stat_IfInFramesL2FilterDiscards;
5798
5799         sc->stat_IfInRuleCheckerDiscards =
5800                 stats->stat_IfInRuleCheckerDiscards;
5801
5802         sc->stat_IfInFTQDiscards =
5803                 stats->stat_IfInFTQDiscards;
5804
5805         sc->stat_IfInMBUFDiscards =
5806                 stats->stat_IfInMBUFDiscards;
5807
5808         sc->stat_IfInRuleCheckerP4Hit =
5809                 stats->stat_IfInRuleCheckerP4Hit;
5810
5811         sc->stat_CatchupInRuleCheckerDiscards =
5812                 stats->stat_CatchupInRuleCheckerDiscards;
5813
5814         sc->stat_CatchupInFTQDiscards =
5815                 stats->stat_CatchupInFTQDiscards;
5816
5817         sc->stat_CatchupInMBUFDiscards =
5818                 stats->stat_CatchupInMBUFDiscards;
5819
5820         sc->stat_CatchupInRuleCheckerP4Hit =
5821                 stats->stat_CatchupInRuleCheckerP4Hit;
5822
5823         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5824
5825         /*
5826          * Update the interface statistics from the
5827          * hardware statistics.
5828          */
5829         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5830
5831         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5832             (u_long)sc->stat_EtherStatsOverrsizePkts +
5833             (u_long)sc->stat_IfInMBUFDiscards +
5834             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5835             (u_long)sc->stat_Dot3StatsFCSErrors +
5836             (u_long)sc->stat_IfInRuleCheckerDiscards +
5837             (u_long)sc->stat_IfInFTQDiscards +
5838             (u_long)sc->com_no_buffers;
5839
5840         ifp->if_oerrors =
5841             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5842             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5843             (u_long)sc->stat_Dot3StatsLateCollisions;
5844
5845         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5846 }
5847
5848
5849 /****************************************************************************/
5850 /* Periodic function to notify the bootcode that the driver is still        */
5851 /* present.                                                                 */
5852 /*                                                                          */
5853 /* Returns:                                                                 */
5854 /*   Nothing.                                                               */
5855 /****************************************************************************/
5856 static void
5857 bce_pulse(void *xsc)
5858 {
5859         struct bce_softc *sc = xsc;
5860         struct ifnet *ifp = &sc->arpcom.ac_if;
5861         uint32_t msg;
5862
5863         lwkt_serialize_enter(ifp->if_serializer);
5864
5865         /* Tell the firmware that the driver is still running. */
5866         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5867         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5868
5869         /* Update the bootcode condition. */
5870         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5871
5872         /* Report whether the bootcode still knows the driver is running. */
5873         if (!sc->bce_drv_cardiac_arrest) {
5874                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5875                         sc->bce_drv_cardiac_arrest = 1;
5876                         if_printf(ifp, "Bootcode lost the driver pulse! "
5877                             "(bc_state = 0x%08X)\n", sc->bc_state);
5878                 }
5879         } else {
5880                 /*
5881                  * Not supported by all bootcode versions.
5882                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5883                  * will require the driver to reset the
5884                  * controller to clear this condition.
5885                  */
5886                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5887                         sc->bce_drv_cardiac_arrest = 0;
5888                         if_printf(ifp, "Bootcode found the driver pulse! "
5889                             "(bc_state = 0x%08X)\n", sc->bc_state);
5890                 }
5891         }
5892
5893         /* Schedule the next pulse. */
5894         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5895
5896         lwkt_serialize_exit(ifp->if_serializer);
5897 }
5898
5899
5900 /****************************************************************************/
5901 /* Periodic function to perform maintenance tasks.                          */
5902 /*                                                                          */
5903 /* Returns:                                                                 */
5904 /*   Nothing.                                                               */
5905 /****************************************************************************/
5906 static void
5907 bce_tick_serialized(struct bce_softc *sc)
5908 {
5909         struct ifnet *ifp = &sc->arpcom.ac_if;
5910         struct mii_data *mii;
5911
5912         ASSERT_SERIALIZED(ifp->if_serializer);
5913
5914         /* Update the statistics from the hardware statistics block. */
5915         bce_stats_update(sc);
5916
5917         /* Schedule the next tick. */
5918         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5919
5920         /* If link is up already up then we're done. */
5921         if (sc->bce_link)
5922                 return;
5923
5924         mii = device_get_softc(sc->bce_miibus);
5925         mii_tick(mii);
5926
5927         /* Check if the link has come up. */
5928         if ((mii->mii_media_status & IFM_ACTIVE) &&
5929             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5930                 sc->bce_link++;
5931                 /* Now that link is up, handle any outstanding TX traffic. */
5932                 if (!ifq_is_empty(&ifp->if_snd))
5933                         if_devstart(ifp);
5934         }
5935 }
5936
5937
5938 static void
5939 bce_tick(void *xsc)
5940 {
5941         struct bce_softc *sc = xsc;
5942         struct ifnet *ifp = &sc->arpcom.ac_if;
5943
5944         lwkt_serialize_enter(ifp->if_serializer);
5945         bce_tick_serialized(sc);
5946         lwkt_serialize_exit(ifp->if_serializer);
5947 }
5948
5949
5950 #ifdef BCE_DEBUG
5951 /****************************************************************************/
5952 /* Allows the driver state to be dumped through the sysctl interface.       */
5953 /*                                                                          */
5954 /* Returns:                                                                 */
5955 /*   0 for success, positive value for failure.                             */
5956 /****************************************************************************/
5957 static int
5958 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5959 {
5960         int error;
5961         int result;
5962         struct bce_softc *sc;
5963
5964         result = -1;
5965         error = sysctl_handle_int(oidp, &result, 0, req);
5966
5967         if (error || !req->newptr)
5968                 return (error);
5969
5970         if (result == 1) {
5971                 sc = (struct bce_softc *)arg1;
5972                 bce_dump_driver_state(sc);
5973         }
5974
5975         return error;
5976 }
5977
5978
5979 /****************************************************************************/
5980 /* Allows the hardware state to be dumped through the sysctl interface.     */
5981 /*                                                                          */
5982 /* Returns:                                                                 */
5983 /*   0 for success, positive value for failure.                             */
5984 /****************************************************************************/
5985 static int
5986 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5987 {
5988         int error;
5989         int result;
5990         struct bce_softc *sc;
5991
5992         result = -1;
5993         error = sysctl_handle_int(oidp, &result, 0, req);
5994
5995         if (error || !req->newptr)
5996                 return (error);
5997
5998         if (result == 1) {
5999                 sc = (struct bce_softc *)arg1;
6000                 bce_dump_hw_state(sc);
6001         }
6002
6003         return error;
6004 }
6005
6006
6007 /****************************************************************************/
6008 /* Provides a sysctl interface to allows dumping the RX chain.              */
6009 /*                                                                          */
6010 /* Returns:                                                                 */
6011 /*   0 for success, positive value for failure.                             */
6012 /****************************************************************************/
6013 static int
6014 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6015 {
6016         int error;
6017         int result;
6018         struct bce_softc *sc;
6019
6020         result = -1;
6021         error = sysctl_handle_int(oidp, &result, 0, req);
6022
6023         if (error || !req->newptr)
6024                 return (error);
6025
6026         if (result == 1) {
6027                 sc = (struct bce_softc *)arg1;
6028                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
6029         }
6030
6031         return error;
6032 }
6033
6034
6035 /****************************************************************************/
6036 /* Provides a sysctl interface to allows dumping the TX chain.              */
6037 /*                                                                          */
6038 /* Returns:                                                                 */
6039 /*   0 for success, positive value for failure.                             */
6040 /****************************************************************************/
6041 static int
6042 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6043 {
6044         int error;
6045         int result;
6046         struct bce_softc *sc;
6047
6048         result = -1;
6049         error = sysctl_handle_int(oidp, &result, 0, req);
6050
6051         if (error || !req->newptr)
6052                 return (error);
6053
6054         if (result == 1) {
6055                 sc = (struct bce_softc *)arg1;
6056                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
6057         }
6058
6059         return error;
6060 }
6061
6062
6063 /****************************************************************************/
6064 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
6065 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
6066 /*                                                                          */
6067 /* Returns:                                                                 */
6068 /*   0 for success, positive value for failure.                             */
6069 /****************************************************************************/
6070 static int
6071 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6072 {
6073         struct bce_softc *sc;
6074         int error;
6075         uint32_t val, result;
6076
6077         result = -1;
6078         error = sysctl_handle_int(oidp, &result, 0, req);
6079         if (error || (req->newptr == NULL))
6080                 return (error);
6081
6082         /* Make sure the register is accessible. */
6083         if (result < 0x8000) {
6084                 sc = (struct bce_softc *)arg1;
6085                 val = REG_RD(sc, result);
6086                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6087                           result, val);
6088         } else if (result < 0x0280000) {
6089                 sc = (struct bce_softc *)arg1;
6090                 val = REG_RD_IND(sc, result);
6091                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6092                           result, val);
6093         }
6094         return (error);
6095 }
6096
6097
6098 /****************************************************************************/
6099 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
6100 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
6101 /*                                                                          */
6102 /* Returns:                                                                 */
6103 /*   0 for success, positive value for failure.                             */
6104 /****************************************************************************/
6105 static int
6106 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6107 {
6108         struct bce_softc *sc;
6109         device_t dev;
6110         int error, result;
6111         uint16_t val;
6112
6113         result = -1;
6114         error = sysctl_handle_int(oidp, &result, 0, req);
6115         if (error || (req->newptr == NULL))
6116                 return (error);
6117
6118         /* Make sure the register is accessible. */
6119         if (result < 0x20) {
6120                 sc = (struct bce_softc *)arg1;
6121                 dev = sc->bce_dev;
6122                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6123                 if_printf(&sc->arpcom.ac_if,
6124                           "phy 0x%02X = 0x%04X\n", result, val);
6125         }
6126         return (error);
6127 }
6128
6129
6130 /****************************************************************************/
6131 /* Provides a sysctl interface to forcing the driver to dump state and      */
6132 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
6133 /*                                                                          */
6134 /* Returns:                                                                 */
6135 /*   0 for success, positive value for failure.                             */
6136 /****************************************************************************/
6137 static int
6138 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6139 {
6140         int error;
6141         int result;
6142         struct bce_softc *sc;
6143
6144         result = -1;
6145         error = sysctl_handle_int(oidp, &result, 0, req);
6146
6147         if (error || !req->newptr)
6148                 return (error);
6149
6150         if (result == 1) {
6151                 sc = (struct bce_softc *)arg1;
6152                 bce_breakpoint(sc);
6153         }
6154
6155         return error;
6156 }
6157 #endif
6158
6159
6160 /****************************************************************************/
6161 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6162 /*                                                                          */
6163 /* Returns:                                                                 */
6164 /*   0 for success, positive value for failure.                             */
6165 /****************************************************************************/
6166 static void
6167 bce_add_sysctls(struct bce_softc *sc)
6168 {
6169         struct sysctl_ctx_list *ctx;
6170         struct sysctl_oid_list *children;
6171
6172         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6173         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6174                                               SYSCTL_STATIC_CHILDREN(_hw),
6175                                               OID_AUTO,
6176                                               device_get_nameunit(sc->bce_dev),
6177                                               CTLFLAG_RD, 0, "");
6178         if (sc->bce_sysctl_tree == NULL) {
6179                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6180                 return;
6181         }
6182
6183         ctx = &sc->bce_sysctl_ctx;
6184         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6185
6186         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6187                         CTLTYPE_INT | CTLFLAG_RW,
6188                         sc, 0, bce_sysctl_tx_bds_int, "I",
6189                         "Send max coalesced BD count during interrupt");
6190         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6191                         CTLTYPE_INT | CTLFLAG_RW,
6192                         sc, 0, bce_sysctl_tx_bds, "I",
6193                         "Send max coalesced BD count");
6194         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6195                         CTLTYPE_INT | CTLFLAG_RW,
6196                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6197                         "Send coalescing ticks during interrupt");
6198         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6199                         CTLTYPE_INT | CTLFLAG_RW,
6200                         sc, 0, bce_sysctl_tx_ticks, "I",
6201                         "Send coalescing ticks");
6202
6203         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6204                         CTLTYPE_INT | CTLFLAG_RW,
6205                         sc, 0, bce_sysctl_rx_bds_int, "I",
6206                         "Receive max coalesced BD count during interrupt");
6207         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6208                         CTLTYPE_INT | CTLFLAG_RW,
6209                         sc, 0, bce_sysctl_rx_bds, "I",
6210                         "Receive max coalesced BD count");
6211         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6212                         CTLTYPE_INT | CTLFLAG_RW,
6213                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6214                         "Receive coalescing ticks during interrupt");
6215         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6216                         CTLTYPE_INT | CTLFLAG_RW,
6217                         sc, 0, bce_sysctl_rx_ticks, "I",
6218                         "Receive coalescing ticks");
6219
6220 #ifdef BCE_DEBUG
6221         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6222                 "rx_low_watermark",
6223                 CTLFLAG_RD, &sc->rx_low_watermark,
6224                 0, "Lowest level of free rx_bd's");
6225
6226         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6227                 "rx_empty_count",
6228                 CTLFLAG_RD, &sc->rx_empty_count,
6229                 0, "Number of times the RX chain was empty");
6230
6231         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6232                 "tx_hi_watermark",
6233                 CTLFLAG_RD, &sc->tx_hi_watermark,
6234                 0, "Highest level of used tx_bd's");
6235
6236         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6237                 "tx_full_count",
6238                 CTLFLAG_RD, &sc->tx_full_count,
6239                 0, "Number of times the TX chain was full");
6240
6241         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6242                 "l2fhdr_status_errors",
6243                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6244                 0, "l2_fhdr status errors");
6245
6246         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6247                 "unexpected_attentions",
6248                 CTLFLAG_RD, &sc->unexpected_attentions,
6249                 0, "unexpected attentions");
6250
6251         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6252                 "lost_status_block_updates",
6253                 CTLFLAG_RD, &sc->lost_status_block_updates,
6254                 0, "lost status block updates");
6255
6256         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6257                 "mbuf_alloc_failed",
6258                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6259                 0, "mbuf cluster allocation failures");
6260 #endif
6261
6262         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6263                 "stat_IfHCInOctets",
6264                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6265                 "Bytes received");
6266
6267         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6268                 "stat_IfHCInBadOctets",
6269                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6270                 "Bad bytes received");
6271
6272         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6273                 "stat_IfHCOutOctets",
6274                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6275                 "Bytes sent");
6276
6277         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6278                 "stat_IfHCOutBadOctets",
6279                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6280                 "Bad bytes sent");
6281
6282         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6283                 "stat_IfHCInUcastPkts",
6284                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6285                 "Unicast packets received");
6286
6287         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6288                 "stat_IfHCInMulticastPkts",
6289                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6290                 "Multicast packets received");
6291
6292         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6293                 "stat_IfHCInBroadcastPkts",
6294                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6295                 "Broadcast packets received");
6296
6297         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6298                 "stat_IfHCOutUcastPkts",
6299                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6300                 "Unicast packets sent");
6301
6302         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6303                 "stat_IfHCOutMulticastPkts",
6304                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6305                 "Multicast packets sent");
6306
6307         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6308                 "stat_IfHCOutBroadcastPkts",
6309                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6310                 "Broadcast packets sent");
6311
6312         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6313                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6314                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6315                 0, "Internal MAC transmit errors");
6316
6317         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6318                 "stat_Dot3StatsCarrierSenseErrors",
6319                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6320                 0, "Carrier sense errors");
6321
6322         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6323                 "stat_Dot3StatsFCSErrors",
6324                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6325                 0, "Frame check sequence errors");
6326
6327         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6328                 "stat_Dot3StatsAlignmentErrors",
6329                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6330                 0, "Alignment errors");
6331
6332         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6333                 "stat_Dot3StatsSingleCollisionFrames",
6334                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6335                 0, "Single Collision Frames");
6336
6337         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6338                 "stat_Dot3StatsMultipleCollisionFrames",
6339                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6340                 0, "Multiple Collision Frames");
6341
6342         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6343                 "stat_Dot3StatsDeferredTransmissions",
6344                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6345                 0, "Deferred Transmissions");
6346
6347         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6348                 "stat_Dot3StatsExcessiveCollisions",
6349                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6350                 0, "Excessive Collisions");
6351
6352         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6353                 "stat_Dot3StatsLateCollisions",
6354                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6355                 0, "Late Collisions");
6356
6357         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6358                 "stat_EtherStatsCollisions",
6359                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6360                 0, "Collisions");
6361
6362         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6363                 "stat_EtherStatsFragments",
6364                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6365                 0, "Fragments");
6366
6367         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6368                 "stat_EtherStatsJabbers",
6369                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6370                 0, "Jabbers");
6371
6372         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6373                 "stat_EtherStatsUndersizePkts",
6374                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6375                 0, "Undersize packets");
6376
6377         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6378                 "stat_EtherStatsOverrsizePkts",
6379                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6380                 0, "stat_EtherStatsOverrsizePkts");
6381
6382         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6383                 "stat_EtherStatsPktsRx64Octets",
6384                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6385                 0, "Bytes received in 64 byte packets");
6386
6387         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6388                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6389                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6390                 0, "Bytes received in 65 to 127 byte packets");
6391
6392         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6393                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6394                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6395                 0, "Bytes received in 128 to 255 byte packets");
6396
6397         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6398                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6399                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6400                 0, "Bytes received in 256 to 511 byte packets");
6401
6402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6403                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6404                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6405                 0, "Bytes received in 512 to 1023 byte packets");
6406
6407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6408                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6409                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6410                 0, "Bytes received in 1024 t0 1522 byte packets");
6411
6412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6413                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6414                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6415                 0, "Bytes received in 1523 to 9022 byte packets");
6416
6417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6418                 "stat_EtherStatsPktsTx64Octets",
6419                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6420                 0, "Bytes sent in 64 byte packets");
6421
6422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6423                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6424                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6425                 0, "Bytes sent in 65 to 127 byte packets");
6426
6427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6428                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6429                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6430                 0, "Bytes sent in 128 to 255 byte packets");
6431
6432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6433                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6434                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6435                 0, "Bytes sent in 256 to 511 byte packets");
6436
6437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6438                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6439                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6440                 0, "Bytes sent in 512 to 1023 byte packets");
6441
6442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6443                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6444                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6445                 0, "Bytes sent in 1024 to 1522 byte packets");
6446
6447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6448                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6449                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6450                 0, "Bytes sent in 1523 to 9022 byte packets");
6451
6452         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6453                 "stat_XonPauseFramesReceived",
6454                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6455                 0, "XON pause frames receved");
6456
6457         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6458                 "stat_XoffPauseFramesReceived",
6459                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6460                 0, "XOFF pause frames received");
6461
6462         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6463                 "stat_OutXonSent",
6464                 CTLFLAG_RD, &sc->stat_OutXonSent,
6465                 0, "XON pause frames sent");
6466
6467         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6468                 "stat_OutXoffSent",
6469                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6470                 0, "XOFF pause frames sent");
6471
6472         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6473                 "stat_FlowControlDone",
6474                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6475                 0, "Flow control done");
6476
6477         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6478                 "stat_MacControlFramesReceived",
6479                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6480                 0, "MAC control frames received");
6481
6482         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6483                 "stat_XoffStateEntered",
6484                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6485                 0, "XOFF state entered");
6486
6487         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6488                 "stat_IfInFramesL2FilterDiscards",
6489                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6490                 0, "Received L2 packets discarded");
6491
6492         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6493                 "stat_IfInRuleCheckerDiscards",
6494                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6495                 0, "Received packets discarded by rule");
6496
6497         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6498                 "stat_IfInFTQDiscards",
6499                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6500                 0, "Received packet FTQ discards");
6501
6502         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6503                 "stat_IfInMBUFDiscards",
6504                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6505                 0, "Received packets discarded due to lack of controller buffer memory");
6506
6507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6508                 "stat_IfInRuleCheckerP4Hit",
6509                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6510                 0, "Received packets rule checker hits");
6511
6512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6513                 "stat_CatchupInRuleCheckerDiscards",
6514                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6515                 0, "Received packets discarded in Catchup path");
6516
6517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6518                 "stat_CatchupInFTQDiscards",
6519                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6520                 0, "Received packets discarded in FTQ in Catchup path");
6521
6522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6523                 "stat_CatchupInMBUFDiscards",
6524                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6525                 0, "Received packets discarded in controller buffer memory in Catchup path");
6526
6527         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6528                 "stat_CatchupInRuleCheckerP4Hit",
6529                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6530                 0, "Received packets rule checker hits in Catchup path");
6531
6532         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6533                 "com_no_buffers",
6534                 CTLFLAG_RD, &sc->com_no_buffers,
6535                 0, "Valid packets received but no RX buffers available");
6536
6537 #ifdef BCE_DEBUG
6538         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6539                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6540                 (void *)sc, 0,
6541                 bce_sysctl_driver_state, "I", "Drive state information");
6542
6543         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6544                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6545                 (void *)sc, 0,
6546                 bce_sysctl_hw_state, "I", "Hardware state information");
6547
6548         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6549                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6550                 (void *)sc, 0,
6551                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6552
6553         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6554                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6555                 (void *)sc, 0,
6556                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6557
6558         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6559                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6560                 (void *)sc, 0,
6561                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6562
6563         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6564                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6565                 (void *)sc, 0,
6566                 bce_sysctl_reg_read, "I", "Register read");
6567
6568         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6569                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6570                 (void *)sc, 0,
6571                 bce_sysctl_phy_read, "I", "PHY register read");
6572
6573 #endif
6574
6575 }
6576
6577
6578 /****************************************************************************/
6579 /* BCE Debug Routines                                                       */
6580 /****************************************************************************/
6581 #ifdef BCE_DEBUG
6582
6583 /****************************************************************************/
6584 /* Freezes the controller to allow for a cohesive state dump.               */
6585 /*                                                                          */
6586 /* Returns:                                                                 */
6587 /*   Nothing.                                                               */
6588 /****************************************************************************/
6589 static void
6590 bce_freeze_controller(struct bce_softc *sc)
6591 {
6592         uint32_t val;
6593
6594         val = REG_RD(sc, BCE_MISC_COMMAND);
6595         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6596         REG_WR(sc, BCE_MISC_COMMAND, val);
6597 }
6598
6599
6600 /****************************************************************************/
6601 /* Unfreezes the controller after a freeze operation.  This may not always  */
6602 /* work and the controller will require a reset!                            */
6603 /*                                                                          */
6604 /* Returns:                                                                 */
6605 /*   Nothing.                                                               */
6606 /****************************************************************************/
6607 static void
6608 bce_unfreeze_controller(struct bce_softc *sc)
6609 {
6610         uint32_t val;
6611
6612         val = REG_RD(sc, BCE_MISC_COMMAND);
6613         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6614         REG_WR(sc, BCE_MISC_COMMAND, val);
6615 }
6616
6617
6618 /****************************************************************************/
6619 /* Prints out information about an mbuf.                                    */
6620 /*                                                                          */
6621 /* Returns:                                                                 */
6622 /*   Nothing.                                                               */
6623 /****************************************************************************/
6624 static void
6625 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6626 {
6627         struct ifnet *ifp = &sc->arpcom.ac_if;
6628         uint32_t val_hi, val_lo;
6629         struct mbuf *mp = m;
6630
6631         if (m == NULL) {
6632                 /* Index out of range. */
6633                 if_printf(ifp, "mbuf: null pointer\n");
6634                 return;
6635         }
6636
6637         while (mp) {
6638                 val_hi = BCE_ADDR_HI(mp);
6639                 val_lo = BCE_ADDR_LO(mp);
6640                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6641                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6642
6643                 if (mp->m_flags & M_EXT)
6644                         kprintf("M_EXT ");
6645                 if (mp->m_flags & M_PKTHDR)
6646                         kprintf("M_PKTHDR ");
6647                 if (mp->m_flags & M_EOR)
6648                         kprintf("M_EOR ");
6649 #ifdef M_RDONLY
6650                 if (mp->m_flags & M_RDONLY)
6651                         kprintf("M_RDONLY ");
6652 #endif
6653
6654                 val_hi = BCE_ADDR_HI(mp->m_data);
6655                 val_lo = BCE_ADDR_LO(mp->m_data);
6656                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6657
6658                 if (mp->m_flags & M_PKTHDR) {
6659                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6660                         if (mp->m_flags & M_BCAST)
6661                                 kprintf("M_BCAST ");
6662                         if (mp->m_flags & M_MCAST)
6663                                 kprintf("M_MCAST ");
6664                         if (mp->m_flags & M_FRAG)
6665                                 kprintf("M_FRAG ");
6666                         if (mp->m_flags & M_FIRSTFRAG)
6667                                 kprintf("M_FIRSTFRAG ");
6668                         if (mp->m_flags & M_LASTFRAG)
6669                                 kprintf("M_LASTFRAG ");
6670 #ifdef M_VLANTAG
6671                         if (mp->m_flags & M_VLANTAG)
6672                                 kprintf("M_VLANTAG ");
6673 #endif
6674 #ifdef M_PROMISC
6675                         if (mp->m_flags & M_PROMISC)
6676                                 kprintf("M_PROMISC ");
6677 #endif
6678                         kprintf(") csum_flags = ( ");
6679                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6680                                 kprintf("CSUM_IP ");
6681                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6682                                 kprintf("CSUM_TCP ");
6683                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6684                                 kprintf("CSUM_UDP ");
6685                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6686                                 kprintf("CSUM_IP_FRAGS ");
6687                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6688                                 kprintf("CSUM_FRAGMENT ");
6689 #ifdef CSUM_TSO
6690                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6691                                 kprintf("CSUM_TSO ");
6692 #endif
6693                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6694                                 kprintf("CSUM_IP_CHECKED ");
6695                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6696                                 kprintf("CSUM_IP_VALID ");
6697                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6698                                 kprintf("CSUM_DATA_VALID ");
6699                         kprintf(")\n");
6700                 }
6701
6702                 if (mp->m_flags & M_EXT) {
6703                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6704                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6705                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6706                                   "ext_size = %d\n",
6707                                   val_hi, val_lo, mp->m_ext.ext_size);
6708                 }
6709                 mp = mp->m_next;
6710         }
6711 }
6712
6713
6714 /****************************************************************************/
6715 /* Prints out the mbufs in the TX mbuf chain.                               */
6716 /*                                                                          */
6717 /* Returns:                                                                 */
6718 /*   Nothing.                                                               */
6719 /****************************************************************************/
6720 static void
6721 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6722 {
6723         struct ifnet *ifp = &sc->arpcom.ac_if;
6724         int i;
6725
6726         if_printf(ifp,
6727         "----------------------------"
6728         "  tx mbuf data  "
6729         "----------------------------\n");
6730
6731         for (i = 0; i < count; i++) {
6732                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6733                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6734                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6735         }
6736
6737         if_printf(ifp,
6738         "----------------------------"
6739         "----------------"
6740         "----------------------------\n");
6741 }
6742
6743
6744 /****************************************************************************/
6745 /* Prints out the mbufs in the RX mbuf chain.                               */
6746 /*                                                                          */
6747 /* Returns:                                                                 */
6748 /*   Nothing.                                                               */
6749 /****************************************************************************/
6750 static void
6751 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6752 {
6753         struct ifnet *ifp = &sc->arpcom.ac_if;
6754         int i;
6755
6756         if_printf(ifp,
6757         "----------------------------"
6758         "  rx mbuf data  "
6759         "----------------------------\n");
6760
6761         for (i = 0; i < count; i++) {
6762                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6763                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6764                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6765         }
6766
6767         if_printf(ifp,
6768         "----------------------------"
6769         "----------------"
6770         "----------------------------\n");
6771 }
6772
6773
6774 /****************************************************************************/
6775 /* Prints out a tx_bd structure.                                            */
6776 /*                                                                          */
6777 /* Returns:                                                                 */
6778 /*   Nothing.                                                               */
6779 /****************************************************************************/
6780 static void
6781 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6782 {
6783         struct ifnet *ifp = &sc->arpcom.ac_if;
6784
6785         if (idx > MAX_TX_BD) {
6786                 /* Index out of range. */
6787                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6788         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6789                 /* TX Chain page pointer. */
6790                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6791                           "chain page pointer\n",
6792                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6793         } else {
6794                 /* Normal tx_bd entry. */
6795                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6796                           "nbytes = 0x%08X, "
6797                           "vlan tag= 0x%04X, flags = 0x%04X (",
6798                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6799                           txbd->tx_bd_mss_nbytes,
6800                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6801
6802                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6803                         kprintf(" CONN_FAULT");
6804
6805                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6806                         kprintf(" TCP_UDP_CKSUM");
6807
6808                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6809                         kprintf(" IP_CKSUM");
6810
6811                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6812                         kprintf("  VLAN");
6813
6814                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6815                         kprintf(" COAL_NOW");
6816
6817                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6818                         kprintf(" DONT_GEN_CRC");
6819
6820                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6821                         kprintf(" START");
6822
6823                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6824                         kprintf(" END");
6825
6826                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6827                         kprintf(" LSO");
6828
6829                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6830                         kprintf(" OPTION_WORD");
6831
6832                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6833                         kprintf(" FLAGS");
6834
6835                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6836                         kprintf(" SNAP");
6837
6838                 kprintf(" )\n");
6839         }
6840 }
6841
6842
6843 /****************************************************************************/
6844 /* Prints out a rx_bd structure.                                            */
6845 /*                                                                          */
6846 /* Returns:                                                                 */
6847 /*   Nothing.                                                               */
6848 /****************************************************************************/
6849 static void
6850 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6851 {
6852         struct ifnet *ifp = &sc->arpcom.ac_if;
6853
6854         if (idx > MAX_RX_BD) {
6855                 /* Index out of range. */
6856                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6857         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6858                 /* TX Chain page pointer. */
6859                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6860                           "chain page pointer\n",
6861                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6862         } else {
6863                 /* Normal tx_bd entry. */
6864                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6865                           "nbytes = 0x%08X, flags = 0x%08X\n",
6866                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6867                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6868         }
6869 }
6870
6871
6872 /****************************************************************************/
6873 /* Prints out a l2_fhdr structure.                                          */
6874 /*                                                                          */
6875 /* Returns:                                                                 */
6876 /*   Nothing.                                                               */
6877 /****************************************************************************/
6878 static void
6879 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6880 {
6881         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6882                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6883                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6884                   idx, l2fhdr->l2_fhdr_status,
6885                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6886                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6887 }
6888
6889
6890 /****************************************************************************/
6891 /* Prints out the tx chain.                                                 */
6892 /*                                                                          */
6893 /* Returns:                                                                 */
6894 /*   Nothing.                                                               */
6895 /****************************************************************************/
6896 static void
6897 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6898 {
6899         struct ifnet *ifp = &sc->arpcom.ac_if;
6900         int i;
6901
6902         /* First some info about the tx_bd chain structure. */
6903         if_printf(ifp,
6904         "----------------------------"
6905         "  tx_bd  chain  "
6906         "----------------------------\n");
6907
6908         if_printf(ifp, "page size      = 0x%08X, "
6909                   "tx chain pages        = 0x%08X\n",
6910                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6911
6912         if_printf(ifp, "tx_bd per page = 0x%08X, "
6913                   "usable tx_bd per page = 0x%08X\n",
6914                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6915                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6916
6917         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6918
6919         if_printf(ifp,
6920         "----------------------------"
6921         "  tx_bd data    "
6922         "----------------------------\n");
6923
6924         /* Now print out the tx_bd's themselves. */
6925         for (i = 0; i < count; i++) {
6926                 struct tx_bd *txbd;
6927
6928                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6929                 bce_dump_txbd(sc, tx_prod, txbd);
6930                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6931         }
6932
6933         if_printf(ifp,
6934         "----------------------------"
6935         "----------------"
6936         "----------------------------\n");
6937 }
6938
6939
6940 /****************************************************************************/
6941 /* Prints out the rx chain.                                                 */
6942 /*                                                                          */
6943 /* Returns:                                                                 */
6944 /*   Nothing.                                                               */
6945 /****************************************************************************/
6946 static void
6947 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6948 {
6949         struct ifnet *ifp = &sc->arpcom.ac_if;
6950         int i;
6951
6952         /* First some info about the tx_bd chain structure. */
6953         if_printf(ifp,
6954         "----------------------------"
6955         "  rx_bd  chain  "
6956         "----------------------------\n");
6957
6958         if_printf(ifp, "page size      = 0x%08X, "
6959                   "rx chain pages        = 0x%08X\n",
6960                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6961
6962         if_printf(ifp, "rx_bd per page = 0x%08X, "
6963                   "usable rx_bd per page = 0x%08X\n",
6964                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6965                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6966
6967         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6968
6969         if_printf(ifp,
6970         "----------------------------"
6971         "   rx_bd data   "
6972         "----------------------------\n");
6973
6974         /* Now print out the rx_bd's themselves. */
6975         for (i = 0; i < count; i++) {
6976                 struct rx_bd *rxbd;
6977
6978                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6979                 bce_dump_rxbd(sc, rx_prod, rxbd);
6980                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6981         }
6982
6983         if_printf(ifp,
6984         "----------------------------"
6985         "----------------"
6986         "----------------------------\n");
6987 }
6988
6989
6990 /****************************************************************************/
6991 /* Prints out the status block from host memory.                            */
6992 /*                                                                          */
6993 /* Returns:                                                                 */
6994 /*   Nothing.                                                               */
6995 /****************************************************************************/
6996 static void
6997 bce_dump_status_block(struct bce_softc *sc)
6998 {
6999         struct status_block *sblk = sc->status_block;
7000         struct ifnet *ifp = &sc->arpcom.ac_if;
7001
7002         if_printf(ifp,
7003         "----------------------------"
7004         "  Status Block  "
7005         "----------------------------\n");
7006
7007         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
7008
7009         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
7010                   sblk->status_attn_bits_ack);
7011
7012         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
7013             sblk->status_rx_quick_consumer_index0,
7014             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
7015
7016         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
7017             sblk->status_tx_quick_consumer_index0,
7018             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
7019
7020         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
7021
7022         /* Theses indices are not used for normal L2 drivers. */
7023         if (sblk->status_rx_quick_consumer_index1) {
7024                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
7025                 sblk->status_rx_quick_consumer_index1,
7026                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
7027         }
7028
7029         if (sblk->status_tx_quick_consumer_index1) {
7030                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7031                 sblk->status_tx_quick_consumer_index1,
7032                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
7033         }
7034
7035         if (sblk->status_rx_quick_consumer_index2) {
7036                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7037                 sblk->status_rx_quick_consumer_index2,
7038                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
7039         }
7040
7041         if (sblk->status_tx_quick_consumer_index2) {
7042                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7043                 sblk->status_tx_quick_consumer_index2,
7044                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
7045         }
7046
7047         if (sblk->status_rx_quick_consumer_index3) {
7048                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7049                 sblk->status_rx_quick_consumer_index3,
7050                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
7051         }
7052
7053         if (sblk->status_tx_quick_consumer_index3) {
7054                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7055                 sblk->status_tx_quick_consumer_index3,
7056                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
7057         }
7058
7059         if (sblk->status_rx_quick_consumer_index4 ||
7060             sblk->status_rx_quick_consumer_index5) {
7061                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
7062                           sblk->status_rx_quick_consumer_index4,
7063                           sblk->status_rx_quick_consumer_index5);
7064         }
7065
7066         if (sblk->status_rx_quick_consumer_index6 ||
7067             sblk->status_rx_quick_consumer_index7) {
7068                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
7069                           sblk->status_rx_quick_consumer_index6,
7070                           sblk->status_rx_quick_consumer_index7);
7071         }
7072
7073         if (sblk->status_rx_quick_consumer_index8 ||
7074             sblk->status_rx_quick_consumer_index9) {
7075                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
7076                           sblk->status_rx_quick_consumer_index8,
7077                           sblk->status_rx_quick_consumer_index9);
7078         }
7079
7080         if (sblk->status_rx_quick_consumer_index10 ||
7081             sblk->status_rx_quick_consumer_index11) {
7082                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
7083                           sblk->status_rx_quick_consumer_index10,
7084                           sblk->status_rx_quick_consumer_index11);
7085         }
7086
7087         if (sblk->status_rx_quick_consumer_index12 ||
7088             sblk->status_rx_quick_consumer_index13) {
7089                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
7090                           sblk->status_rx_quick_consumer_index12,
7091                           sblk->status_rx_quick_consumer_index13);
7092         }
7093
7094         if (sblk->status_rx_quick_consumer_index14 ||
7095             sblk->status_rx_quick_consumer_index15) {
7096                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
7097                           sblk->status_rx_quick_consumer_index14,
7098                           sblk->status_rx_quick_consumer_index15);
7099         }
7100
7101         if (sblk->status_completion_producer_index ||
7102             sblk->status_cmd_consumer_index) {
7103                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
7104                           sblk->status_completion_producer_index,
7105                           sblk->status_cmd_consumer_index);
7106         }
7107
7108         if_printf(ifp,
7109         "----------------------------"
7110         "----------------"
7111         "----------------------------\n");
7112 }
7113
7114
7115 /****************************************************************************/
7116 /* Prints out the statistics block.                                         */
7117 /*                                                                          */
7118 /* Returns:                                                                 */
7119 /*   Nothing.                                                               */
7120 /****************************************************************************/
7121 static void
7122 bce_dump_stats_block(struct bce_softc *sc)
7123 {
7124         struct statistics_block *sblk = sc->stats_block;
7125         struct ifnet *ifp = &sc->arpcom.ac_if;
7126
7127         if_printf(ifp,
7128         "---------------"
7129         " Stats Block  (All Stats Not Shown Are 0) "
7130         "---------------\n");
7131
7132         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7133                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7134                           sblk->stat_IfHCInOctets_hi,
7135                           sblk->stat_IfHCInOctets_lo);
7136         }
7137
7138         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7139                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7140                           sblk->stat_IfHCInBadOctets_hi,
7141                           sblk->stat_IfHCInBadOctets_lo);
7142         }
7143
7144         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7145                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7146                           sblk->stat_IfHCOutOctets_hi,
7147                           sblk->stat_IfHCOutOctets_lo);
7148         }
7149
7150         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7151                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7152                           sblk->stat_IfHCOutBadOctets_hi,
7153                           sblk->stat_IfHCOutBadOctets_lo);
7154         }
7155
7156         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7157                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7158                           sblk->stat_IfHCInUcastPkts_hi,
7159                           sblk->stat_IfHCInUcastPkts_lo);
7160         }
7161
7162         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7163             sblk->stat_IfHCInBroadcastPkts_lo) {
7164                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7165                           sblk->stat_IfHCInBroadcastPkts_hi,
7166                           sblk->stat_IfHCInBroadcastPkts_lo);
7167         }
7168
7169         if (sblk->stat_IfHCInMulticastPkts_hi ||
7170             sblk->stat_IfHCInMulticastPkts_lo) {
7171                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7172                           sblk->stat_IfHCInMulticastPkts_hi,
7173                           sblk->stat_IfHCInMulticastPkts_lo);
7174         }
7175
7176         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7177                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7178                           sblk->stat_IfHCOutUcastPkts_hi,
7179                           sblk->stat_IfHCOutUcastPkts_lo);
7180         }
7181
7182         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7183             sblk->stat_IfHCOutBroadcastPkts_lo) {
7184                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7185                           sblk->stat_IfHCOutBroadcastPkts_hi,
7186                           sblk->stat_IfHCOutBroadcastPkts_lo);
7187         }
7188
7189         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7190             sblk->stat_IfHCOutMulticastPkts_lo) {
7191                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7192                           sblk->stat_IfHCOutMulticastPkts_hi,
7193                           sblk->stat_IfHCOutMulticastPkts_lo);
7194         }
7195
7196         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7197                 if_printf(ifp, "         0x%08X : "
7198                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7199                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7200         }
7201
7202         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7203                 if_printf(ifp, "         0x%08X : "
7204                           "Dot3StatsCarrierSenseErrors\n",
7205                           sblk->stat_Dot3StatsCarrierSenseErrors);
7206         }
7207
7208         if (sblk->stat_Dot3StatsFCSErrors) {
7209                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7210                           sblk->stat_Dot3StatsFCSErrors);
7211         }
7212
7213         if (sblk->stat_Dot3StatsAlignmentErrors) {
7214                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7215                           sblk->stat_Dot3StatsAlignmentErrors);
7216         }
7217
7218         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7219                 if_printf(ifp, "         0x%08X : "
7220                           "Dot3StatsSingleCollisionFrames\n",
7221                           sblk->stat_Dot3StatsSingleCollisionFrames);
7222         }
7223
7224         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7225                 if_printf(ifp, "         0x%08X : "
7226                           "Dot3StatsMultipleCollisionFrames\n",
7227                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7228         }
7229
7230         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7231                 if_printf(ifp, "         0x%08X : "
7232                           "Dot3StatsDeferredTransmissions\n",
7233                           sblk->stat_Dot3StatsDeferredTransmissions);
7234         }
7235
7236         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7237                 if_printf(ifp, "         0x%08X : "
7238                           "Dot3StatsExcessiveCollisions\n",
7239                           sblk->stat_Dot3StatsExcessiveCollisions);
7240         }
7241
7242         if (sblk->stat_Dot3StatsLateCollisions) {
7243                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7244                           sblk->stat_Dot3StatsLateCollisions);
7245         }
7246
7247         if (sblk->stat_EtherStatsCollisions) {
7248                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7249                           sblk->stat_EtherStatsCollisions);
7250         }
7251
7252         if (sblk->stat_EtherStatsFragments)  {
7253                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7254                           sblk->stat_EtherStatsFragments);
7255         }
7256
7257         if (sblk->stat_EtherStatsJabbers) {
7258                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7259                           sblk->stat_EtherStatsJabbers);
7260         }
7261
7262         if (sblk->stat_EtherStatsUndersizePkts) {
7263                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7264                           sblk->stat_EtherStatsUndersizePkts);
7265         }
7266
7267         if (sblk->stat_EtherStatsOverrsizePkts) {
7268                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7269                           sblk->stat_EtherStatsOverrsizePkts);
7270         }
7271
7272         if (sblk->stat_EtherStatsPktsRx64Octets) {
7273                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7274                           sblk->stat_EtherStatsPktsRx64Octets);
7275         }
7276
7277         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7278                 if_printf(ifp, "         0x%08X : "
7279                           "EtherStatsPktsRx65Octetsto127Octets\n",
7280                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7281         }
7282
7283         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7284                 if_printf(ifp, "         0x%08X : "
7285                           "EtherStatsPktsRx128Octetsto255Octets\n",
7286                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7287         }
7288
7289         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7290                 if_printf(ifp, "         0x%08X : "
7291                           "EtherStatsPktsRx256Octetsto511Octets\n",
7292                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7293         }
7294
7295         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7296                 if_printf(ifp, "         0x%08X : "
7297                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7298                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7299         }
7300
7301         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7302                 if_printf(ifp, "         0x%08X : "
7303                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7304                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7305         }
7306
7307         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7308                 if_printf(ifp, "         0x%08X : "
7309                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7310                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7311         }
7312
7313         if (sblk->stat_EtherStatsPktsTx64Octets) {
7314                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7315                           sblk->stat_EtherStatsPktsTx64Octets);
7316         }
7317
7318         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7319                 if_printf(ifp, "         0x%08X : "
7320                           "EtherStatsPktsTx65Octetsto127Octets\n",
7321                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7322         }
7323
7324         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7325                 if_printf(ifp, "         0x%08X : "
7326                           "EtherStatsPktsTx128Octetsto255Octets\n",
7327                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7328         }
7329
7330         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7331                 if_printf(ifp, "         0x%08X : "
7332                           "EtherStatsPktsTx256Octetsto511Octets\n",
7333                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7334         }
7335
7336         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7337                 if_printf(ifp, "         0x%08X : "
7338                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7339                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7340         }
7341
7342         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7343                 if_printf(ifp, "         0x%08X : "
7344                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7345                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7346         }
7347
7348         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7349                 if_printf(ifp, "         0x%08X : "
7350                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7351                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7352         }
7353
7354         if (sblk->stat_XonPauseFramesReceived) {
7355                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7356                           sblk->stat_XonPauseFramesReceived);
7357         }
7358
7359         if (sblk->stat_XoffPauseFramesReceived) {
7360                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7361                           sblk->stat_XoffPauseFramesReceived);
7362         }
7363
7364         if (sblk->stat_OutXonSent) {
7365                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7366                           sblk->stat_OutXonSent);
7367         }
7368
7369         if (sblk->stat_OutXoffSent) {
7370                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7371                           sblk->stat_OutXoffSent);
7372         }
7373
7374         if (sblk->stat_FlowControlDone) {
7375                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7376                           sblk->stat_FlowControlDone);
7377         }
7378
7379         if (sblk->stat_MacControlFramesReceived) {
7380                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7381                           sblk->stat_MacControlFramesReceived);
7382         }
7383
7384         if (sblk->stat_XoffStateEntered) {
7385                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7386                           sblk->stat_XoffStateEntered);
7387         }
7388
7389         if (sblk->stat_IfInFramesL2FilterDiscards) {
7390                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7391         }
7392
7393         if (sblk->stat_IfInRuleCheckerDiscards) {
7394                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7395                           sblk->stat_IfInRuleCheckerDiscards);
7396         }
7397
7398         if (sblk->stat_IfInFTQDiscards) {
7399                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7400                           sblk->stat_IfInFTQDiscards);
7401         }
7402
7403         if (sblk->stat_IfInMBUFDiscards) {
7404                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7405                           sblk->stat_IfInMBUFDiscards);
7406         }
7407
7408         if (sblk->stat_IfInRuleCheckerP4Hit) {
7409                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7410                           sblk->stat_IfInRuleCheckerP4Hit);
7411         }
7412
7413         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7414                 if_printf(ifp, "         0x%08X : "
7415                           "CatchupInRuleCheckerDiscards\n",
7416                           sblk->stat_CatchupInRuleCheckerDiscards);
7417         }
7418
7419         if (sblk->stat_CatchupInFTQDiscards) {
7420                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7421                           sblk->stat_CatchupInFTQDiscards);
7422         }
7423
7424         if (sblk->stat_CatchupInMBUFDiscards) {
7425                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7426                           sblk->stat_CatchupInMBUFDiscards);
7427         }
7428
7429         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7430                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7431                           sblk->stat_CatchupInRuleCheckerP4Hit);
7432         }
7433
7434         if_printf(ifp,
7435         "----------------------------"
7436         "----------------"
7437         "----------------------------\n");
7438 }
7439
7440
7441 /****************************************************************************/
7442 /* Prints out a summary of the driver state.                                */
7443 /*                                                                          */
7444 /* Returns:                                                                 */
7445 /*   Nothing.                                                               */
7446 /****************************************************************************/
7447 static void
7448 bce_dump_driver_state(struct bce_softc *sc)
7449 {
7450         struct ifnet *ifp = &sc->arpcom.ac_if;
7451         uint32_t val_hi, val_lo;
7452
7453         if_printf(ifp,
7454         "-----------------------------"
7455         " Driver State "
7456         "-----------------------------\n");
7457
7458         val_hi = BCE_ADDR_HI(sc);
7459         val_lo = BCE_ADDR_LO(sc);
7460         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7461                   "virtual address\n", val_hi, val_lo);
7462
7463         val_hi = BCE_ADDR_HI(sc->status_block);
7464         val_lo = BCE_ADDR_LO(sc->status_block);
7465         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7466                   "virtual address\n", val_hi, val_lo);
7467
7468         val_hi = BCE_ADDR_HI(sc->stats_block);
7469         val_lo = BCE_ADDR_LO(sc->stats_block);
7470         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7471                   "virtual address\n", val_hi, val_lo);
7472
7473         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7474         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7475         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7476                   "virtual adddress\n", val_hi, val_lo);
7477
7478         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7479         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7480         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7481                   "virtual address\n", val_hi, val_lo);
7482
7483         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7484         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7485         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7486                   "virtual address\n", val_hi, val_lo);
7487
7488         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7489         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7490         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7491                   "virtual address\n", val_hi, val_lo);
7492
7493         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7494                   "h/w intrs\n", sc->interrupts_generated);
7495
7496         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7497                   "rx interrupts handled\n", sc->rx_interrupts);
7498
7499         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7500                   "tx interrupts handled\n", sc->tx_interrupts);
7501
7502         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7503                   "status block index\n", sc->last_status_idx);
7504
7505         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7506                   "tx producer index\n",
7507                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7508
7509         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7510                   "tx consumer index\n",
7511                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7512
7513         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7514                   "tx producer bseq index\n", sc->tx_prod_bseq);
7515
7516         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7517                   "rx producer index\n",
7518                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7519
7520         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7521                   "rx consumer index\n",
7522                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7523
7524         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7525                   "rx producer bseq index\n", sc->rx_prod_bseq);
7526
7527         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7528                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7529
7530         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7531                   "free rx_bd's\n", sc->free_rx_bd);
7532
7533         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7534                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7535
7536         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7537                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7538
7539         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7540                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7541
7542         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7543                   sc->used_tx_bd);
7544
7545         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7546                   sc->tx_hi_watermark, sc->max_tx_bd);
7547
7548         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7549                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7550
7551         if_printf(ifp,
7552         "----------------------------"
7553         "----------------"
7554         "----------------------------\n");
7555 }
7556
7557
7558 /****************************************************************************/
7559 /* Prints out the hardware state through a summary of important registers,  */
7560 /* followed by a complete register dump.                                    */
7561 /*                                                                          */
7562 /* Returns:                                                                 */
7563 /*   Nothing.                                                               */
7564 /****************************************************************************/
7565 static void
7566 bce_dump_hw_state(struct bce_softc *sc)
7567 {
7568         struct ifnet *ifp = &sc->arpcom.ac_if;
7569         uint32_t val1;
7570         int i;
7571
7572         if_printf(ifp,
7573         "----------------------------"
7574         " Hardware State "
7575         "----------------------------\n");
7576
7577         if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7578
7579         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7580         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7581                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7582
7583         val1 = REG_RD(sc, BCE_DMA_STATUS);
7584         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7585
7586         val1 = REG_RD(sc, BCE_CTX_STATUS);
7587         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7588
7589         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7590         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7591                   val1, BCE_EMAC_STATUS);
7592
7593         val1 = REG_RD(sc, BCE_RPM_STATUS);
7594         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7595
7596         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7597         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7598                   val1, BCE_TBDR_STATUS);
7599
7600         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7601         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7602                   val1, BCE_TDMA_STATUS);
7603
7604         val1 = REG_RD(sc, BCE_HC_STATUS);
7605         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7606
7607         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7608         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7609                   val1, BCE_TXP_CPU_STATE);
7610
7611         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7612         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7613                   val1, BCE_TPAT_CPU_STATE);
7614
7615         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7616         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7617                   val1, BCE_RXP_CPU_STATE);
7618
7619         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7620         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7621                   val1, BCE_COM_CPU_STATE);
7622
7623         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7624         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7625                   val1, BCE_MCP_CPU_STATE);
7626
7627         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7628         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7629                   val1, BCE_CP_CPU_STATE);
7630
7631         if_printf(ifp,
7632         "----------------------------"
7633         "----------------"
7634         "----------------------------\n");
7635
7636         if_printf(ifp,
7637         "----------------------------"
7638         " Register  Dump "
7639         "----------------------------\n");
7640
7641         for (i = 0x400; i < 0x8000; i += 0x10) {
7642                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7643                           REG_RD(sc, i),
7644                           REG_RD(sc, i + 0x4),
7645                           REG_RD(sc, i + 0x8),
7646                           REG_RD(sc, i + 0xc));
7647         }
7648
7649         if_printf(ifp,
7650         "----------------------------"
7651         "----------------"
7652         "----------------------------\n");
7653 }
7654
7655
7656 /****************************************************************************/
7657 /* Prints out the TXP state.                                                */
7658 /*                                                                          */
7659 /* Returns:                                                                 */
7660 /*   Nothing.                                                               */
7661 /****************************************************************************/
7662 static void
7663 bce_dump_txp_state(struct bce_softc *sc)
7664 {
7665         struct ifnet *ifp = &sc->arpcom.ac_if;
7666         uint32_t val1;
7667         int i;
7668
7669         if_printf(ifp,
7670         "----------------------------"
7671         "   TXP  State   "
7672         "----------------------------\n");
7673
7674         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7675         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7676                   val1, BCE_TXP_CPU_MODE);
7677
7678         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7679         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7680                   val1, BCE_TXP_CPU_STATE);
7681
7682         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7683         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7684                   val1, BCE_TXP_CPU_EVENT_MASK);
7685
7686         if_printf(ifp,
7687         "----------------------------"
7688         " Register  Dump "
7689         "----------------------------\n");
7690
7691         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7692                 /* Skip the big blank spaces */
7693                 if (i < 0x454000 && i > 0x5ffff) {
7694                         if_printf(ifp, "0x%04X: "
7695                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7696                                   REG_RD_IND(sc, i),
7697                                   REG_RD_IND(sc, i + 0x4),
7698                                   REG_RD_IND(sc, i + 0x8),
7699                                   REG_RD_IND(sc, i + 0xc));
7700                 }
7701         }
7702
7703         if_printf(ifp,
7704         "----------------------------"
7705         "----------------"
7706         "----------------------------\n");
7707 }
7708
7709
7710 /****************************************************************************/
7711 /* Prints out the RXP state.                                                */
7712 /*                                                                          */
7713 /* Returns:                                                                 */
7714 /*   Nothing.                                                               */
7715 /****************************************************************************/
7716 static void
7717 bce_dump_rxp_state(struct bce_softc *sc)
7718 {
7719         struct ifnet *ifp = &sc->arpcom.ac_if;
7720         uint32_t val1;
7721         int i;
7722
7723         if_printf(ifp,
7724         "----------------------------"
7725         "   RXP  State   "
7726         "----------------------------\n");
7727
7728         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7729         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7730                   val1, BCE_RXP_CPU_MODE);
7731
7732         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7733         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7734                   val1, BCE_RXP_CPU_STATE);
7735
7736         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7737         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7738                   val1, BCE_RXP_CPU_EVENT_MASK);
7739
7740         if_printf(ifp,
7741         "----------------------------"
7742         " Register  Dump "
7743         "----------------------------\n");
7744
7745         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7746                 /* Skip the big blank sapces */
7747                 if (i < 0xc5400 && i > 0xdffff) {
7748                         if_printf(ifp, "0x%04X: "
7749                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7750                                   REG_RD_IND(sc, i),
7751                                   REG_RD_IND(sc, i + 0x4),
7752                                   REG_RD_IND(sc, i + 0x8),
7753                                   REG_RD_IND(sc, i + 0xc));
7754                 }
7755         }
7756
7757         if_printf(ifp,
7758         "----------------------------"
7759         "----------------"
7760         "----------------------------\n");
7761 }
7762
7763
7764 /****************************************************************************/
7765 /* Prints out the TPAT state.                                               */
7766 /*                                                                          */
7767 /* Returns:                                                                 */
7768 /*   Nothing.                                                               */
7769 /****************************************************************************/
7770 static void
7771 bce_dump_tpat_state(struct bce_softc *sc)
7772 {
7773         struct ifnet *ifp = &sc->arpcom.ac_if;
7774         uint32_t val1;
7775         int i;
7776
7777         if_printf(ifp,
7778         "----------------------------"
7779         "   TPAT State   "
7780         "----------------------------\n");
7781
7782         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7783         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7784                   val1, BCE_TPAT_CPU_MODE);
7785
7786         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7787         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7788                   val1, BCE_TPAT_CPU_STATE);
7789
7790         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7791         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7792                   val1, BCE_TPAT_CPU_EVENT_MASK);
7793
7794         if_printf(ifp,
7795         "----------------------------"
7796         " Register  Dump "
7797         "----------------------------\n");
7798
7799         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7800                 /* Skip the big blank spaces */
7801                 if (i < 0x854000 && i > 0x9ffff) {
7802                         if_printf(ifp, "0x%04X: "
7803                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7804                                   REG_RD_IND(sc, i),
7805                                   REG_RD_IND(sc, i + 0x4),
7806                                   REG_RD_IND(sc, i + 0x8),
7807                                   REG_RD_IND(sc, i + 0xc));
7808                 }
7809         }
7810
7811         if_printf(ifp,
7812         "----------------------------"
7813         "----------------"
7814         "----------------------------\n");
7815 }
7816
7817
7818 /****************************************************************************/
7819 /* Prints out the driver state and then enters the debugger.                */
7820 /*                                                                          */
7821 /* Returns:                                                                 */
7822 /*   Nothing.                                                               */
7823 /****************************************************************************/
7824 static void
7825 bce_breakpoint(struct bce_softc *sc)
7826 {
7827 #if 0
7828         bce_freeze_controller(sc);
7829 #endif
7830
7831         bce_dump_driver_state(sc);
7832         bce_dump_status_block(sc);
7833         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7834         bce_dump_hw_state(sc);
7835         bce_dump_txp_state(sc);
7836
7837 #if 0
7838         bce_unfreeze_controller(sc);
7839 #endif
7840
7841         /* Call the debugger. */
7842         breakpoint();
7843 }
7844
7845 #endif  /* BCE_DEBUG */
7846
7847 static int
7848 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7849 {
7850         struct bce_softc *sc = arg1;
7851
7852         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7853                         &sc->bce_tx_quick_cons_trip_int,
7854                         BCE_COALMASK_TX_BDS_INT);
7855 }
7856
7857 static int
7858 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7859 {
7860         struct bce_softc *sc = arg1;
7861
7862         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7863                         &sc->bce_tx_quick_cons_trip,
7864                         BCE_COALMASK_TX_BDS);
7865 }
7866
7867 static int
7868 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7869 {
7870         struct bce_softc *sc = arg1;
7871
7872         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7873                         &sc->bce_tx_ticks_int,
7874                         BCE_COALMASK_TX_TICKS_INT);
7875 }
7876
7877 static int
7878 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7879 {
7880         struct bce_softc *sc = arg1;
7881
7882         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7883                         &sc->bce_tx_ticks,
7884                         BCE_COALMASK_TX_TICKS);
7885 }
7886
7887 static int
7888 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7889 {
7890         struct bce_softc *sc = arg1;
7891
7892         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7893                         &sc->bce_rx_quick_cons_trip_int,
7894                         BCE_COALMASK_RX_BDS_INT);
7895 }
7896
7897 static int
7898 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7899 {
7900         struct bce_softc *sc = arg1;
7901
7902         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7903                         &sc->bce_rx_quick_cons_trip,
7904                         BCE_COALMASK_RX_BDS);
7905 }
7906
7907 static int
7908 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7909 {
7910         struct bce_softc *sc = arg1;
7911
7912         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7913                         &sc->bce_rx_ticks_int,
7914                         BCE_COALMASK_RX_TICKS_INT);
7915 }
7916
7917 static int
7918 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7919 {
7920         struct bce_softc *sc = arg1;
7921
7922         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7923                         &sc->bce_rx_ticks,
7924                         BCE_COALMASK_RX_TICKS);
7925 }
7926
7927 static int
7928 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7929                        uint32_t coalchg_mask)
7930 {
7931         struct bce_softc *sc = arg1;
7932         struct ifnet *ifp = &sc->arpcom.ac_if;
7933         int error = 0, v;
7934
7935         lwkt_serialize_enter(ifp->if_serializer);
7936
7937         v = *coal;
7938         error = sysctl_handle_int(oidp, &v, 0, req);
7939         if (!error && req->newptr != NULL) {
7940                 if (v < 0) {
7941                         error = EINVAL;
7942                 } else {
7943                         *coal = v;
7944                         sc->bce_coalchg_mask |= coalchg_mask;
7945                 }
7946         }
7947
7948         lwkt_serialize_exit(ifp->if_serializer);
7949         return error;
7950 }
7951
7952 static void
7953 bce_coal_change(struct bce_softc *sc)
7954 {
7955         struct ifnet *ifp = &sc->arpcom.ac_if;
7956
7957         ASSERT_SERIALIZED(ifp->if_serializer);
7958
7959         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7960                 sc->bce_coalchg_mask = 0;
7961                 return;
7962         }
7963
7964         if (sc->bce_coalchg_mask &
7965             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7966                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7967                        (sc->bce_tx_quick_cons_trip_int << 16) |
7968                        sc->bce_tx_quick_cons_trip);
7969                 if (bootverbose) {
7970                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7971                                   sc->bce_tx_quick_cons_trip,
7972                                   sc->bce_tx_quick_cons_trip_int);
7973                 }
7974         }
7975
7976         if (sc->bce_coalchg_mask &
7977             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7978                 REG_WR(sc, BCE_HC_TX_TICKS,
7979                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7980                 if (bootverbose) {
7981                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7982                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7983                 }
7984         }
7985
7986         if (sc->bce_coalchg_mask &
7987             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7988                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7989                        (sc->bce_rx_quick_cons_trip_int << 16) |
7990                        sc->bce_rx_quick_cons_trip);
7991                 if (bootverbose) {
7992                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7993                                   sc->bce_rx_quick_cons_trip,
7994                                   sc->bce_rx_quick_cons_trip_int);
7995                 }
7996         }
7997
7998         if (sc->bce_coalchg_mask &
7999             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
8000                 REG_WR(sc, BCE_HC_RX_TICKS,
8001                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
8002                 if (bootverbose) {
8003                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
8004                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
8005                 }
8006         }
8007
8008         sc->bce_coalchg_mask = 0;
8009 }