2 * Copyright 1996 Massachusetts Institute of Technology
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5 * its documentation for any purpose and without fee is hereby
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/perfmon.c,v 1.8 2004/05/19 22:52:57 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/fcntl.h>
40 #include <machine/cputypes.h>
42 #include <machine/clock.h>
43 #include <machine/perfmon.h>
45 static int perfmon_inuse;
46 static int perfmon_cpuok;
48 static int msr_ctl[NPMC];
50 static int msr_pmc[NPMC];
51 static unsigned int ctl_shadow[NPMC];
52 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
53 static int (*writectl)(int);
55 static int writectl5(int);
56 static int writectl6(int);
59 static d_close_t perfmon_close;
60 static d_open_t perfmon_open;
61 static d_ioctl_t perfmon_ioctl;
63 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
64 static struct cdevsw perfmon_cdevsw = {
71 /* open */ perfmon_open,
72 /* close */ perfmon_close,
75 /* ioctl */ perfmon_ioctl,
78 /* strategy */ nostrategy,
84 * Must be called after cpu_class is set up.
105 writectl = writectl6;
114 /* NOTE: really a minor of mem. perfmon gets 32-47 */
115 cdevsw_add(&perfmon_cdevsw, 0xf0, 32);
116 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
122 return perfmon_cpuok;
126 perfmon_setup(int pmc, unsigned int control)
128 if (pmc < 0 || pmc >= NPMC)
131 perfmon_inuse |= (1 << pmc);
132 control &= ~(PMCF_SYS_FLAGS << 16);
133 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
134 ctl_shadow[pmc] = control;
136 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
142 perfmon_get(int pmc, unsigned int *control)
144 if (pmc < 0 || pmc >= NPMC)
147 if (perfmon_inuse & (1 << pmc)) {
148 *control = ctl_shadow[pmc];
151 return EBUSY; /* XXX reversed sense */
155 perfmon_fini(int pmc)
157 if (pmc < 0 || pmc >= NPMC)
160 if (perfmon_inuse & (1 << pmc)) {
163 perfmon_inuse &= ~(1 << pmc);
166 return EBUSY; /* XXX reversed sense */
170 perfmon_start(int pmc)
172 if (pmc < 0 || pmc >= NPMC)
175 if (perfmon_inuse & (1 << pmc)) {
176 mpintr_lock(); /* doesn't have to be mpintr YYY */
177 ctl_shadow[pmc] |= (PMCF_EN << 16);
178 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
187 perfmon_stop(int pmc)
189 if (pmc < 0 || pmc >= NPMC)
192 if (perfmon_inuse & (1 << pmc)) {
194 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
195 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
204 perfmon_read(int pmc, quad_t *val)
206 if (pmc < 0 || pmc >= NPMC)
209 if (perfmon_inuse & (1 << pmc)) {
210 if (ctl_shadow[pmc] & (PMCF_EN << 16))
211 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
213 *val = pmc_shadow[pmc];
221 perfmon_reset(int pmc)
223 if (pmc < 0 || pmc >= NPMC)
226 if (perfmon_inuse & (1 << pmc)) {
227 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
235 * Unfortunately, the performance-monitoring registers are laid out
236 * differently in the P5 and P6. We keep everything in P6 format
237 * internally (except for the event code), and convert to P5
238 * format as needed on those CPUs. The writectl function pointer
239 * is set up to point to one of these functions by perfmon_init().
244 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
245 wrmsr(msr_ctl[pmc], 0);
247 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
252 #define P5FLAG_P 0x200
253 #define P5FLAG_E 0x100
254 #define P5FLAG_USR 0x80
255 #define P5FLAG_OS 0x40
262 if (ctl_shadow[1] & (PMCF_EN << 16)) {
263 if (ctl_shadow[1] & (PMCF_USR << 16))
264 newval |= P5FLAG_USR << 16;
265 if (ctl_shadow[1] & (PMCF_OS << 16))
266 newval |= P5FLAG_OS << 16;
267 if (!(ctl_shadow[1] & (PMCF_E << 16)))
268 newval |= P5FLAG_E << 16;
269 newval |= (ctl_shadow[1] & 0x3f) << 16;
271 if (ctl_shadow[0] & (PMCF_EN << 16)) {
272 if (ctl_shadow[0] & (PMCF_USR << 16))
273 newval |= P5FLAG_USR;
274 if (ctl_shadow[0] & (PMCF_OS << 16))
276 if (!(ctl_shadow[0] & (PMCF_E << 16)))
278 newval |= ctl_shadow[0] & 0x3f;
281 wrmsr(msr_ctl[0], newval);
282 return 0; /* XXX should check for unimplemented bits */
287 * Now the user-mode interface, called from a subdevice of mem.c.
290 static int writerpmc;
293 perfmon_open(dev_t dev, int flags, int fmt, struct thread *td)
298 if (flags & FWRITE) {
310 perfmon_close(dev_t dev, int flags, int fmt, struct thread *td)
312 if (flags & FWRITE) {
315 for (i = 0; i < NPMC; i++) {
316 if (writerpmc & (1 << i))
325 perfmon_ioctl(dev_t dev, u_long cmd, caddr_t param, int flags, struct thread *td)
328 struct pmc_data *pmcd;
329 struct pmc_tstamp *pmct;
335 if (!(flags & FWRITE))
337 pmc = (struct pmc *)param;
339 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
341 writerpmc |= (1 << pmc->pmc_num);
346 pmc = (struct pmc *)param;
347 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
351 if (!(flags & FWRITE))
355 rv = perfmon_start(*ip);
359 if (!(flags & FWRITE))
363 rv = perfmon_stop(*ip);
367 if (!(flags & FWRITE))
371 rv = perfmon_reset(*ip);
375 pmcd = (struct pmc_data *)param;
376 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
384 pmct = (struct pmc_tstamp *)param;
385 /* XXX interface loses precision. */
386 pmct->pmct_rate = tsc_freq / 1000000;
387 pmct->pmct_value = rdtsc();