1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 /* $FreeBSD: src/contrib/binutils/gas/config/tc-i386.c,v 1.4.2.4 2002/09/01 23:44:03 obrien Exp $ */
25 /* $DragonFly: src/contrib/binutils/gas/config/Attic/tc-i386.c,v 1.2 2003/06/17 04:23:58 dillon Exp $ */
28 /* Intel 80386 machine specific gas.
29 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
30 x86_64 support by Jan Hubicka (jh@suse.cz)
31 Bugs & suggestions are completely welcome. This is free software.
32 Please help us make it better. */
35 #include "safe-ctype.h"
37 #include "dwarf2dbg.h"
38 #include "opcode/i386.h"
40 #ifndef REGISTER_WARNINGS
41 #define REGISTER_WARNINGS 1
44 #ifndef INFER_ADDR_PREFIX
45 #define INFER_ADDR_PREFIX 1
48 #ifndef SCALE1_WHEN_NO_INDEX
49 /* Specifying a scale factor besides 1 when there is no index is
50 futile. eg. `mov (%ebx,2),%al' does exactly the same as
51 `mov (%ebx),%al'. To slavishly follow what the programmer
52 specified, set SCALE1_WHEN_NO_INDEX to 0. */
53 #define SCALE1_WHEN_NO_INDEX 1
57 #define RELOC_ENUM enum bfd_reloc_code_real
59 #define RELOC_ENUM int
63 #define DEFAULT_ARCH "i386"
68 #define INLINE __inline__
74 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
75 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
76 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
77 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
78 static INLINE int fits_in_signed_word PARAMS ((offsetT));
79 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
80 static INLINE int fits_in_signed_long PARAMS ((offsetT));
81 static int smallest_imm_type PARAMS ((offsetT));
82 static offsetT offset_in_range PARAMS ((offsetT, int));
83 static int add_prefix PARAMS ((unsigned int));
84 static void set_code_flag PARAMS ((int));
85 static void set_16bit_gcc_code_flag PARAMS ((int));
86 static void set_intel_syntax PARAMS ((int));
87 static void set_cpu_arch PARAMS ((int));
88 static char *output_invalid PARAMS ((int c));
89 static int i386_operand PARAMS ((char *operand_string));
90 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
91 static const reg_entry *parse_register PARAMS ((char *reg_string,
93 static char *parse_insn PARAMS ((char *, char *));
94 static char *parse_operands PARAMS ((char *, const char *));
95 static void swap_operands PARAMS ((void));
96 static void optimize_imm PARAMS ((void));
97 static void optimize_disp PARAMS ((void));
98 static int match_template PARAMS ((void));
99 static int check_string PARAMS ((void));
100 static int process_suffix PARAMS ((void));
101 static int check_byte_reg PARAMS ((void));
102 static int check_long_reg PARAMS ((void));
103 static int check_qword_reg PARAMS ((void));
104 static int check_word_reg PARAMS ((void));
105 static int finalize_imm PARAMS ((void));
106 static int process_operands PARAMS ((void));
107 static const seg_entry *build_modrm_byte PARAMS ((void));
108 static void output_insn PARAMS ((void));
109 static void output_branch PARAMS ((void));
110 static void output_jump PARAMS ((void));
111 static void output_interseg_jump PARAMS ((void));
112 static void output_imm PARAMS ((void));
113 static void output_disp PARAMS ((void));
115 static void s_bss PARAMS ((int));
118 static const char *default_arch = DEFAULT_ARCH;
120 /* 'md_assemble ()' gathers together information and puts it into a
127 const reg_entry *regs;
132 /* TM holds the template for the insn were currently assembling. */
135 /* SUFFIX holds the instruction mnemonic suffix if given.
136 (e.g. 'l' for 'movl') */
139 /* OPERANDS gives the number of given operands. */
140 unsigned int operands;
142 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
143 of given register, displacement, memory operands and immediate
145 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147 /* TYPES [i] is the type (see above #defines) which tells us how to
148 use OP[i] for the corresponding operand. */
149 unsigned int types[MAX_OPERANDS];
151 /* Displacement expression, immediate expression, or register for each
153 union i386_op op[MAX_OPERANDS];
155 /* Flags for operands. */
156 unsigned int flags[MAX_OPERANDS];
157 #define Operand_PCrel 1
159 /* Relocation type for operand */
160 RELOC_ENUM reloc[MAX_OPERANDS];
162 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
163 the base index byte below. */
164 const reg_entry *base_reg;
165 const reg_entry *index_reg;
166 unsigned int log2_scale_factor;
168 /* SEG gives the seg_entries of this insn. They are zero unless
169 explicit segment overrides are given. */
170 const seg_entry *seg[2];
172 /* PREFIX holds all the given prefix opcodes (usually null).
173 PREFIXES is the number of prefix opcodes. */
174 unsigned int prefixes;
175 unsigned char prefix[MAX_PREFIXES];
177 /* RM and SIB are the modrm byte and the sib byte where the
178 addressing modes of this insn are encoded. */
185 typedef struct _i386_insn i386_insn;
187 /* List of chars besides those in app.c:symbol_chars that can start an
188 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars[] = "*%-(@[";
192 const char extra_symbol_chars[] = "*%-([";
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_FreeBSD) \
199 && !defined (TE_NetBSD)))
200 /* This array holds the chars that always start a comment. If the
201 pre-processor is disabled, these aren't very useful. */
202 const char comment_chars[] = "#/";
203 #define PREFIX_SEPARATOR '\\'
205 /* This array holds the chars that only start a comment at the beginning of
206 a line. If the line seems to have the form '# 123 filename'
207 .line and .file directives will appear in the pre-processed output.
208 Note that input_file.c hand checks for '#' at the beginning of the
209 first line of the input file. This is because the compiler outputs
210 #NO_APP at the beginning of its output.
211 Also note that comments started like this one will always work if
212 '/' isn't otherwise defined. */
213 const char line_comment_chars[] = "";
216 /* Putting '/' here makes it impossible to use the divide operator.
217 However, we need it for compatibility with SVR4 systems. */
218 const char comment_chars[] = "#";
219 #define PREFIX_SEPARATOR '/'
221 const char line_comment_chars[] = "/";
224 const char line_separator_chars[] = ";";
226 /* Chars that can be used to separate mant from exp in floating point
228 const char EXP_CHARS[] = "eE";
230 /* Chars that mean this number is a floating point constant
233 const char FLT_CHARS[] = "fFdDxX";
235 /* Tables for lexical analysis. */
236 static char mnemonic_chars[256];
237 static char register_chars[256];
238 static char operand_chars[256];
239 static char identifier_chars[256];
240 static char digit_chars[256];
242 /* Lexical macros. */
243 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
244 #define is_operand_char(x) (operand_chars[(unsigned char) x])
245 #define is_register_char(x) (register_chars[(unsigned char) x])
246 #define is_space_char(x) ((x) == ' ')
247 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
248 #define is_digit_char(x) (digit_chars[(unsigned char) x])
250 /* All non-digit non-letter charcters that may occur in an operand. */
251 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253 /* md_assemble() always leaves the strings it's passed unaltered. To
254 effect this we maintain a stack of saved characters that we've smashed
255 with '\0's (indicating end of strings for various sub-fields of the
256 assembler instruction). */
257 static char save_stack[32];
258 static char *save_stack_p;
259 #define END_STRING_AND_SAVE(s) \
260 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
261 #define RESTORE_END_STRING(s) \
262 do { *(s) = *--save_stack_p; } while (0)
264 /* The instruction we're assembling. */
267 /* Possible templates for current insn. */
268 static const templates *current_templates;
270 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
271 static expressionS disp_expressions[2], im_expressions[2];
273 /* Current operand we are working on. */
274 static int this_operand;
276 /* We support four different modes. FLAG_CODE variable is used to distinguish
283 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
285 static enum flag_code flag_code;
286 static int use_rela_relocations = 0;
288 /* The names used to print error messages. */
289 static const char *flag_code_names[] =
296 /* 1 for intel syntax,
298 static int intel_syntax = 0;
300 /* 1 if register prefix % not required. */
301 static int allow_naked_reg = 0;
303 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306 static char stackop_size = '\0';
308 /* Non-zero to quieten some warnings. */
309 static int quiet_warnings = 0;
312 static const char *cpu_arch_name = NULL;
314 /* CPU feature flags. */
315 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
317 /* If set, conditional jumps are not automatically promoted to handle
318 larger than a byte offset. */
319 static unsigned int no_cond_jump_promotion = 0;
321 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
324 /* Interface to relax_segment.
325 There are 3 major relax states for 386 jump insns because the
326 different types of jumps add different sizes to frags when we're
327 figuring out what sort of jump to choose to reach a given label. */
330 #define UNCOND_JUMP 0
332 #define COND_JUMP86 2
337 #define SMALL16 (SMALL | CODE16)
339 #define BIG16 (BIG | CODE16)
343 #define INLINE __inline__
349 #define ENCODE_RELAX_STATE(type, size) \
350 ((relax_substateT) (((type) << 2) | (size)))
351 #define TYPE_FROM_RELAX_STATE(s) \
353 #define DISP_SIZE_FROM_RELAX_STATE(s) \
354 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
356 /* This table is used by relax_frag to promote short jumps to long
357 ones where necessary. SMALL (short) jumps may be promoted to BIG
358 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
359 don't allow a short jump in a 32 bit code segment to be promoted to
360 a 16 bit offset jump because it's slower (requires data size
361 prefix), and doesn't work, unless the destination is in the bottom
362 64k of the code segment (The top 16 bits of eip are zeroed). */
364 const relax_typeS md_relax_table[] =
367 1) most positive reach of this state,
368 2) most negative reach of this state,
369 3) how many bytes this mode will have in the variable part of the frag
370 4) which index into the table to try if we can't fit into this one. */
372 /* UNCOND_JUMP states. */
373 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
374 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
375 /* dword jmp adds 4 bytes to frag:
376 0 extra opcode bytes, 4 displacement bytes. */
378 /* word jmp adds 2 byte2 to frag:
379 0 extra opcode bytes, 2 displacement bytes. */
382 /* COND_JUMP states. */
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
385 /* dword conditionals adds 5 bytes to frag:
386 1 extra opcode byte, 4 displacement bytes. */
388 /* word conditionals add 3 bytes to frag:
389 1 extra opcode byte, 2 displacement bytes. */
392 /* COND_JUMP86 states. */
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
395 /* dword conditionals adds 5 bytes to frag:
396 1 extra opcode byte, 4 displacement bytes. */
398 /* word conditionals add 4 bytes to frag:
399 1 displacement byte and a 3 byte long branch insn. */
403 static const arch_entry cpu_arch[] = {
405 {"i186", Cpu086|Cpu186 },
406 {"i286", Cpu086|Cpu186|Cpu286 },
407 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
408 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
409 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
410 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
411 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
412 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
413 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
414 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
415 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
416 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
420 const pseudo_typeS md_pseudo_table[] =
422 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
423 {"align", s_align_bytes, 0},
425 {"align", s_align_ptwo, 0},
427 {"arch", set_cpu_arch, 0},
431 {"ffloat", float_cons, 'f'},
432 {"dfloat", float_cons, 'd'},
433 {"tfloat", float_cons, 'x'},
435 {"noopt", s_ignore, 0},
436 {"optim", s_ignore, 0},
437 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
438 {"code16", set_code_flag, CODE_16BIT},
439 {"code32", set_code_flag, CODE_32BIT},
440 {"code64", set_code_flag, CODE_64BIT},
441 {"intel_syntax", set_intel_syntax, 1},
442 {"att_syntax", set_intel_syntax, 0},
443 {"file", dwarf2_directive_file, 0},
444 {"loc", dwarf2_directive_loc, 0},
448 /* For interface with expression (). */
449 extern char *input_line_pointer;
451 /* Hash table for instruction mnemonic lookup. */
452 static struct hash_control *op_hash;
454 /* Hash table for register lookup. */
455 static struct hash_control *reg_hash;
458 i386_align_code (fragP, count)
462 /* Various efficient no-op patterns for aligning code labels.
463 Note: Don't try to assemble the instructions in the comments.
464 0L and 0w are not legal. */
465 static const char f32_1[] =
467 static const char f32_2[] =
468 {0x89,0xf6}; /* movl %esi,%esi */
469 static const char f32_3[] =
470 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
471 static const char f32_4[] =
472 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_5[] =
475 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
476 static const char f32_6[] =
477 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
478 static const char f32_7[] =
479 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_8[] =
482 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
483 static const char f32_9[] =
484 {0x89,0xf6, /* movl %esi,%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_10[] =
487 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_11[] =
490 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
491 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
492 static const char f32_12[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
495 static const char f32_13[] =
496 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_14[] =
499 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
500 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
501 static const char f32_15[] =
502 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
503 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
504 static const char f16_3[] =
505 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
506 static const char f16_4[] =
507 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_5[] =
510 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
511 static const char f16_6[] =
512 {0x89,0xf6, /* mov %si,%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_7[] =
515 {0x8d,0x74,0x00, /* lea 0(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char f16_8[] =
518 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
519 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
520 static const char *const f32_patt[] = {
521 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
522 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
524 static const char *const f16_patt[] = {
525 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
526 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
529 /* ??? We can't use these fillers for x86_64, since they often kills the
530 upper halves. Solve later. */
531 if (flag_code == CODE_64BIT)
534 if (count > 0 && count <= 15)
536 if (flag_code == CODE_16BIT)
538 memcpy (fragP->fr_literal + fragP->fr_fix,
539 f16_patt[count - 1], count);
541 /* Adjust jump offset. */
542 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
545 memcpy (fragP->fr_literal + fragP->fr_fix,
546 f32_patt[count - 1], count);
547 fragP->fr_var = count;
551 static INLINE unsigned int
552 mode_from_disp_size (t)
555 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
559 fits_in_signed_byte (num)
562 return (num >= -128) && (num <= 127);
566 fits_in_unsigned_byte (num)
569 return (num & 0xff) == num;
573 fits_in_unsigned_word (num)
576 return (num & 0xffff) == num;
580 fits_in_signed_word (num)
583 return (-32768 <= num) && (num <= 32767);
586 fits_in_signed_long (num)
587 offsetT num ATTRIBUTE_UNUSED;
592 return (!(((offsetT) -1 << 31) & num)
593 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
595 } /* fits_in_signed_long() */
597 fits_in_unsigned_long (num)
598 offsetT num ATTRIBUTE_UNUSED;
603 return (num & (((offsetT) 2 << 31) - 1)) == num;
605 } /* fits_in_unsigned_long() */
608 smallest_imm_type (num)
611 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
613 /* This code is disabled on the 486 because all the Imm1 forms
614 in the opcode table are slower on the i486. They're the
615 versions with the implicitly specified single-position
616 displacement, which has another syntax if you really want to
619 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
621 return (fits_in_signed_byte (num)
622 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
623 : fits_in_unsigned_byte (num)
624 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
625 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
626 ? (Imm16 | Imm32 | Imm32S | Imm64)
627 : fits_in_signed_long (num)
628 ? (Imm32 | Imm32S | Imm64)
629 : fits_in_unsigned_long (num)
635 offset_in_range (val, size)
643 case 1: mask = ((addressT) 1 << 8) - 1; break;
644 case 2: mask = ((addressT) 1 << 16) - 1; break;
645 case 4: mask = ((addressT) 2 << 31) - 1; break;
647 case 8: mask = ((addressT) 2 << 63) - 1; break;
652 /* If BFD64, sign extend val. */
653 if (!use_rela_relocations)
654 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
655 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
657 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
659 char buf1[40], buf2[40];
661 sprint_value (buf1, val);
662 sprint_value (buf2, val & mask);
663 as_warn (_("%s shortened to %s"), buf1, buf2);
668 /* Returns 0 if attempting to add a prefix where one from the same
669 class already exists, 1 if non rep/repne added, 2 if rep/repne
678 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
679 && flag_code == CODE_64BIT)
687 case CS_PREFIX_OPCODE:
688 case DS_PREFIX_OPCODE:
689 case ES_PREFIX_OPCODE:
690 case FS_PREFIX_OPCODE:
691 case GS_PREFIX_OPCODE:
692 case SS_PREFIX_OPCODE:
696 case REPNE_PREFIX_OPCODE:
697 case REPE_PREFIX_OPCODE:
700 case LOCK_PREFIX_OPCODE:
708 case ADDR_PREFIX_OPCODE:
712 case DATA_PREFIX_OPCODE:
717 if (i.prefix[q] != 0)
719 as_bad (_("same type of prefix used twice"));
724 i.prefix[q] = prefix;
729 set_code_flag (value)
733 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
734 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
735 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
737 as_bad (_("64bit mode not supported on this CPU."));
739 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
741 as_bad (_("32bit mode not supported on this CPU."));
747 set_16bit_gcc_code_flag (new_code_flag)
750 flag_code = new_code_flag;
751 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
752 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
757 set_intel_syntax (syntax_flag)
760 /* Find out if register prefixing is specified. */
761 int ask_naked_reg = 0;
764 if (!is_end_of_line[(unsigned char) *input_line_pointer])
766 char *string = input_line_pointer;
767 int e = get_symbol_end ();
769 if (strcmp (string, "prefix") == 0)
771 else if (strcmp (string, "noprefix") == 0)
774 as_bad (_("bad argument to syntax directive."));
775 *input_line_pointer = e;
777 demand_empty_rest_of_line ();
779 intel_syntax = syntax_flag;
781 if (ask_naked_reg == 0)
784 allow_naked_reg = (intel_syntax
785 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
787 /* Conservative default. */
792 allow_naked_reg = (ask_naked_reg < 0);
797 int dummy ATTRIBUTE_UNUSED;
801 if (!is_end_of_line[(unsigned char) *input_line_pointer])
803 char *string = input_line_pointer;
804 int e = get_symbol_end ();
807 for (i = 0; cpu_arch[i].name; i++)
809 if (strcmp (string, cpu_arch[i].name) == 0)
811 cpu_arch_name = cpu_arch[i].name;
812 cpu_arch_flags = (cpu_arch[i].flags
813 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
817 if (!cpu_arch[i].name)
818 as_bad (_("no such architecture: `%s'"), string);
820 *input_line_pointer = e;
823 as_bad (_("missing cpu architecture"));
825 no_cond_jump_promotion = 0;
826 if (*input_line_pointer == ','
827 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
829 char *string = ++input_line_pointer;
830 int e = get_symbol_end ();
832 if (strcmp (string, "nojumps") == 0)
833 no_cond_jump_promotion = 1;
834 else if (strcmp (string, "jumps") == 0)
837 as_bad (_("no such architecture modifier: `%s'"), string);
839 *input_line_pointer = e;
842 demand_empty_rest_of_line ();
849 if (!strcmp (default_arch, "x86_64"))
850 return bfd_mach_x86_64;
851 else if (!strcmp (default_arch, "i386"))
852 return bfd_mach_i386_i386;
854 as_fatal (_("Unknown architecture"));
861 const char *hash_err;
863 /* Initialize op_hash hash table. */
864 op_hash = hash_new ();
867 const template *optab;
868 templates *core_optab;
870 /* Setup for loop. */
872 core_optab = (templates *) xmalloc (sizeof (templates));
873 core_optab->start = optab;
878 if (optab->name == NULL
879 || strcmp (optab->name, (optab - 1)->name) != 0)
881 /* different name --> ship out current template list;
882 add to hash table; & begin anew. */
883 core_optab->end = optab;
884 hash_err = hash_insert (op_hash,
889 as_fatal (_("Internal Error: Can't hash %s: %s"),
893 if (optab->name == NULL)
895 core_optab = (templates *) xmalloc (sizeof (templates));
896 core_optab->start = optab;
901 /* Initialize reg_hash hash table. */
902 reg_hash = hash_new ();
904 const reg_entry *regtab;
906 for (regtab = i386_regtab;
907 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
910 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
912 as_fatal (_("Internal Error: Can't hash %s: %s"),
918 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
923 for (c = 0; c < 256; c++)
928 mnemonic_chars[c] = c;
929 register_chars[c] = c;
930 operand_chars[c] = c;
932 else if (ISLOWER (c))
934 mnemonic_chars[c] = c;
935 register_chars[c] = c;
936 operand_chars[c] = c;
938 else if (ISUPPER (c))
940 mnemonic_chars[c] = TOLOWER (c);
941 register_chars[c] = mnemonic_chars[c];
942 operand_chars[c] = c;
945 if (ISALPHA (c) || ISDIGIT (c))
946 identifier_chars[c] = c;
949 identifier_chars[c] = c;
950 operand_chars[c] = c;
955 identifier_chars['@'] = '@';
957 digit_chars['-'] = '-';
958 identifier_chars['_'] = '_';
959 identifier_chars['.'] = '.';
961 for (p = operand_special_chars; *p != '\0'; p++)
962 operand_chars[(unsigned char) *p] = *p;
965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
966 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
968 record_alignment (text_section, 2);
969 record_alignment (data_section, 2);
970 record_alignment (bss_section, 2);
976 i386_print_statistics (file)
979 hash_print_statistics (file, "i386 opcode", op_hash);
980 hash_print_statistics (file, "i386 register", reg_hash);
985 /* Debugging routines for md_assemble. */
986 static void pi PARAMS ((char *, i386_insn *));
987 static void pte PARAMS ((template *));
988 static void pt PARAMS ((unsigned int));
989 static void pe PARAMS ((expressionS *));
990 static void ps PARAMS ((symbolS *));
999 fprintf (stdout, "%s: template ", line);
1001 fprintf (stdout, " address: base %s index %s scale %x\n",
1002 x->base_reg ? x->base_reg->reg_name : "none",
1003 x->index_reg ? x->index_reg->reg_name : "none",
1004 x->log2_scale_factor);
1005 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1006 x->rm.mode, x->rm.reg, x->rm.regmem);
1007 fprintf (stdout, " sib: base %x index %x scale %x\n",
1008 x->sib.base, x->sib.index, x->sib.scale);
1009 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1010 (x->rex & REX_MODE64) != 0,
1011 (x->rex & REX_EXTX) != 0,
1012 (x->rex & REX_EXTY) != 0,
1013 (x->rex & REX_EXTZ) != 0);
1014 for (i = 0; i < x->operands; i++)
1016 fprintf (stdout, " #%d: ", i + 1);
1018 fprintf (stdout, "\n");
1020 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1021 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1022 if (x->types[i] & Imm)
1024 if (x->types[i] & Disp)
1025 pe (x->op[i].disps);
1034 fprintf (stdout, " %d operands ", t->operands);
1035 fprintf (stdout, "opcode %x ", t->base_opcode);
1036 if (t->extension_opcode != None)
1037 fprintf (stdout, "ext %x ", t->extension_opcode);
1038 if (t->opcode_modifier & D)
1039 fprintf (stdout, "D");
1040 if (t->opcode_modifier & W)
1041 fprintf (stdout, "W");
1042 fprintf (stdout, "\n");
1043 for (i = 0; i < t->operands; i++)
1045 fprintf (stdout, " #%d type ", i + 1);
1046 pt (t->operand_types[i]);
1047 fprintf (stdout, "\n");
1055 fprintf (stdout, " operation %d\n", e->X_op);
1056 fprintf (stdout, " add_number %ld (%lx)\n",
1057 (long) e->X_add_number, (long) e->X_add_number);
1058 if (e->X_add_symbol)
1060 fprintf (stdout, " add_symbol ");
1061 ps (e->X_add_symbol);
1062 fprintf (stdout, "\n");
1066 fprintf (stdout, " op_symbol ");
1067 ps (e->X_op_symbol);
1068 fprintf (stdout, "\n");
1076 fprintf (stdout, "%s type %s%s",
1078 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1079 segment_name (S_GET_SEGMENT (s)));
1088 static const type_names[] =
1101 { BaseIndex, "BaseIndex" },
1105 { Disp32S, "d32s" },
1107 { InOutPortReg, "InOutPortReg" },
1108 { ShiftCount, "ShiftCount" },
1109 { Control, "control reg" },
1110 { Test, "test reg" },
1111 { Debug, "debug reg" },
1112 { FloatReg, "FReg" },
1113 { FloatAcc, "FAcc" },
1117 { JumpAbsolute, "Jump Absolute" },
1128 const struct type_name *ty;
1130 for (ty = type_names; ty->mask; ty++)
1132 fprintf (stdout, "%s, ", ty->tname);
1136 #endif /* DEBUG386 */
1139 tc_i386_force_relocation (fixp)
1142 #ifdef BFD_ASSEMBLER
1143 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1144 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1149 return fixp->fx_r_type == 7;
1153 #ifdef BFD_ASSEMBLER
1154 static bfd_reloc_code_real_type reloc
1155 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1157 static bfd_reloc_code_real_type
1158 reloc (size, pcrel, sign, other)
1162 bfd_reloc_code_real_type other;
1164 if (other != NO_RELOC)
1170 as_bad (_("There are no unsigned pc-relative relocations"));
1173 case 1: return BFD_RELOC_8_PCREL;
1174 case 2: return BFD_RELOC_16_PCREL;
1175 case 4: return BFD_RELOC_32_PCREL;
1177 as_bad (_("can not do %d byte pc-relative relocation"), size);
1184 case 4: return BFD_RELOC_X86_64_32S;
1189 case 1: return BFD_RELOC_8;
1190 case 2: return BFD_RELOC_16;
1191 case 4: return BFD_RELOC_32;
1192 case 8: return BFD_RELOC_64;
1194 as_bad (_("can not do %s %d byte relocation"),
1195 sign ? "signed" : "unsigned", size);
1199 return BFD_RELOC_NONE;
1202 /* Here we decide which fixups can be adjusted to make them relative to
1203 the beginning of the section instead of the symbol. Basically we need
1204 to make sure that the dynamic relocations are done correctly, so in
1205 some cases we force the original symbol to be used. */
1208 tc_i386_fix_adjustable (fixP)
1211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1212 /* Prevent all adjustments to global symbols, or else dynamic
1213 linking will not work correctly. */
1214 if (S_IS_EXTERNAL (fixP->fx_addsy)
1215 || S_IS_WEAK (fixP->fx_addsy)
1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1218 || (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1223 /* adjust_reloc_syms doesn't know about the GOT. */
1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1227 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1230 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1231 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1236 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1237 #define BFD_RELOC_16 0
1238 #define BFD_RELOC_32 0
1239 #define BFD_RELOC_16_PCREL 0
1240 #define BFD_RELOC_32_PCREL 0
1241 #define BFD_RELOC_386_PLT32 0
1242 #define BFD_RELOC_386_GOT32 0
1243 #define BFD_RELOC_386_GOTOFF 0
1244 #define BFD_RELOC_X86_64_PLT32 0
1245 #define BFD_RELOC_X86_64_GOT32 0
1246 #define BFD_RELOC_X86_64_GOTPCREL 0
1249 static int intel_float_operand PARAMS ((const char *mnemonic));
1252 intel_float_operand (mnemonic)
1253 const char *mnemonic;
1255 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1258 if (mnemonic[0] == 'f')
1264 /* This is the guts of the machine-dependent assembler. LINE points to a
1265 machine dependent instruction. This function is supposed to emit
1266 the frags/bytes it assembles to. */
1273 char mnemonic[MAX_MNEM_SIZE];
1275 /* Initialize globals. */
1276 memset (&i, '\0', sizeof (i));
1277 for (j = 0; j < MAX_OPERANDS; j++)
1278 i.reloc[j] = NO_RELOC;
1279 memset (disp_expressions, '\0', sizeof (disp_expressions));
1280 memset (im_expressions, '\0', sizeof (im_expressions));
1281 save_stack_p = save_stack;
1283 /* First parse an instruction mnemonic & call i386_operand for the operands.
1284 We assume that the scrubber has arranged it so that line[0] is the valid
1285 start of a (possibly prefixed) mnemonic. */
1287 line = parse_insn (line, mnemonic);
1291 line = parse_operands (line, mnemonic);
1295 /* Now we've parsed the mnemonic into a set of templates, and have the
1296 operands at hand. */
1298 /* All intel opcodes have reversed operands except for "bound" and
1299 "enter". We also don't reverse intersegment "jmp" and "call"
1300 instructions with 2 immediate operands so that the immediate segment
1301 precedes the offset, as it does when in AT&T mode. "enter" and the
1302 intersegment "jmp" and "call" instructions are the only ones that
1303 have two immediate operands. */
1304 if (intel_syntax && i.operands > 1
1305 && (strcmp (mnemonic, "bound") != 0)
1306 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1312 if (i.disp_operands)
1315 /* Next, we find a template that matches the given insn,
1316 making sure the overlap of the given operands types is consistent
1317 with the template operand types. */
1319 if (!match_template ())
1322 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1325 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1326 i.tm.base_opcode ^= FloatR;
1328 if (i.tm.opcode_modifier & FWait)
1329 if (!add_prefix (FWAIT_OPCODE))
1332 /* Check string instruction segment overrides. */
1333 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1335 if (!check_string ())
1339 if (!process_suffix ())
1342 /* Make still unresolved immediate matches conform to size of immediate
1343 given in i.suffix. */
1344 if (!finalize_imm ())
1347 if (i.types[0] & Imm1)
1348 i.imm_operands = 0; /* kludge for shift insns. */
1349 if (i.types[0] & ImplicitRegister)
1351 if (i.types[1] & ImplicitRegister)
1353 if (i.types[2] & ImplicitRegister)
1356 if (i.tm.opcode_modifier & ImmExt)
1358 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1359 opcode suffix which is coded in the same place as an 8-bit
1360 immediate field would be. Here we fake an 8-bit immediate
1361 operand from the opcode suffix stored in tm.extension_opcode. */
1365 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1367 exp = &im_expressions[i.imm_operands++];
1368 i.op[i.operands].imms = exp;
1369 i.types[i.operands++] = Imm8;
1370 exp->X_op = O_constant;
1371 exp->X_add_number = i.tm.extension_opcode;
1372 i.tm.extension_opcode = None;
1375 /* For insns with operands there are more diddles to do to the opcode. */
1378 if (!process_operands ())
1381 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1383 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1384 as_warn (_("translating to `%sp'"), i.tm.name);
1387 /* Handle conversion of 'int $3' --> special int3 insn. */
1388 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1390 i.tm.base_opcode = INT3_OPCODE;
1394 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1395 && i.op[0].disps->X_op == O_constant)
1397 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1398 the absolute address given by the constant. Since ix86 jumps and
1399 calls are pc relative, we need to generate a reloc. */
1400 i.op[0].disps->X_add_symbol = &abs_symbol;
1401 i.op[0].disps->X_op = O_symbol;
1404 if ((i.tm.opcode_modifier & Rex64) != 0)
1405 i.rex |= REX_MODE64;
1407 /* For 8 bit registers we need an empty rex prefix. Also if the
1408 instruction already has a prefix, we need to convert old
1409 registers to new ones. */
1411 if (((i.types[0] & Reg8) != 0
1412 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1413 || ((i.types[1] & Reg8) != 0
1414 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1415 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1420 i.rex |= REX_OPCODE;
1421 for (x = 0; x < 2; x++)
1423 /* Look for 8 bit operand that uses old registers. */
1424 if ((i.types[x] & Reg8) != 0
1425 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1427 /* In case it is "hi" register, give up. */
1428 if (i.op[x].regs->reg_num > 3)
1429 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1430 i.op[x].regs->reg_name);
1432 /* Otherwise it is equivalent to the extended register.
1433 Since the encoding doesn't change this is merely
1434 cosmetic cleanup for debug output. */
1436 i.op[x].regs = i.op[x].regs + 8;
1442 add_prefix (REX_OPCODE | i.rex);
1444 /* We are ready to output the insn. */
1449 parse_insn (line, mnemonic)
1454 char *token_start = l;
1457 /* Non-zero if we found a prefix only acceptable with string insns. */
1458 const char *expecting_string_instruction = NULL;
1463 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1466 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1468 as_bad (_("no such instruction: `%s'"), token_start);
1473 if (!is_space_char (*l)
1474 && *l != END_OF_INSN
1475 && *l != PREFIX_SEPARATOR
1478 as_bad (_("invalid character %s in mnemonic"),
1479 output_invalid (*l));
1482 if (token_start == l)
1484 if (*l == PREFIX_SEPARATOR)
1485 as_bad (_("expecting prefix; got nothing"));
1487 as_bad (_("expecting mnemonic; got nothing"));
1491 /* Look up instruction (or prefix) via hash table. */
1492 current_templates = hash_find (op_hash, mnemonic);
1494 if (*l != END_OF_INSN
1495 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1496 && current_templates
1497 && (current_templates->start->opcode_modifier & IsPrefix))
1499 /* If we are in 16-bit mode, do not allow addr16 or data16.
1500 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1501 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1502 && flag_code != CODE_64BIT
1503 && (((current_templates->start->opcode_modifier & Size32) != 0)
1504 ^ (flag_code == CODE_16BIT)))
1506 as_bad (_("redundant %s prefix"),
1507 current_templates->start->name);
1510 /* Add prefix, checking for repeated prefixes. */
1511 switch (add_prefix (current_templates->start->base_opcode))
1516 expecting_string_instruction = current_templates->start->name;
1519 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1526 if (!current_templates)
1528 /* See if we can get a match by trimming off a suffix. */
1531 case WORD_MNEM_SUFFIX:
1532 case BYTE_MNEM_SUFFIX:
1533 case QWORD_MNEM_SUFFIX:
1534 i.suffix = mnem_p[-1];
1536 current_templates = hash_find (op_hash, mnemonic);
1538 case SHORT_MNEM_SUFFIX:
1539 case LONG_MNEM_SUFFIX:
1542 i.suffix = mnem_p[-1];
1544 current_templates = hash_find (op_hash, mnemonic);
1552 if (intel_float_operand (mnemonic))
1553 i.suffix = SHORT_MNEM_SUFFIX;
1555 i.suffix = LONG_MNEM_SUFFIX;
1557 current_templates = hash_find (op_hash, mnemonic);
1561 if (!current_templates)
1563 as_bad (_("no such instruction: `%s'"), token_start);
1568 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1570 /* Check for a branch hint. We allow ",pt" and ",pn" for
1571 predict taken and predict not taken respectively.
1572 I'm not sure that branch hints actually do anything on loop
1573 and jcxz insns (JumpByte) for current Pentium4 chips. They
1574 may work in the future and it doesn't hurt to accept them
1576 if (l[0] == ',' && l[1] == 'p')
1580 if (!add_prefix (DS_PREFIX_OPCODE))
1584 else if (l[2] == 'n')
1586 if (!add_prefix (CS_PREFIX_OPCODE))
1592 /* Any other comma loses. */
1595 as_bad (_("invalid character %s in mnemonic"),
1596 output_invalid (*l));
1600 /* Check if instruction is supported on specified architecture. */
1601 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1602 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1604 as_warn (_("`%s' is not supported on `%s'"),
1605 current_templates->start->name, cpu_arch_name);
1607 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1609 as_warn (_("use .code16 to ensure correct addressing mode"));
1612 /* Check for rep/repne without a string instruction. */
1613 if (expecting_string_instruction
1614 && !(current_templates->start->opcode_modifier & IsString))
1616 as_bad (_("expecting string instruction after `%s'"),
1617 expecting_string_instruction);
1625 parse_operands (l, mnemonic)
1627 const char *mnemonic;
1631 /* 1 if operand is pending after ','. */
1632 unsigned int expecting_operand = 0;
1634 /* Non-zero if operand parens not balanced. */
1635 unsigned int paren_not_balanced;
1637 while (*l != END_OF_INSN)
1639 /* Skip optional white space before operand. */
1640 if (is_space_char (*l))
1642 if (!is_operand_char (*l) && *l != END_OF_INSN)
1644 as_bad (_("invalid character %s before operand %d"),
1645 output_invalid (*l),
1649 token_start = l; /* after white space */
1650 paren_not_balanced = 0;
1651 while (paren_not_balanced || *l != ',')
1653 if (*l == END_OF_INSN)
1655 if (paren_not_balanced)
1658 as_bad (_("unbalanced parenthesis in operand %d."),
1661 as_bad (_("unbalanced brackets in operand %d."),
1666 break; /* we are done */
1668 else if (!is_operand_char (*l) && !is_space_char (*l))
1670 as_bad (_("invalid character %s in operand %d"),
1671 output_invalid (*l),
1678 ++paren_not_balanced;
1680 --paren_not_balanced;
1685 ++paren_not_balanced;
1687 --paren_not_balanced;
1691 if (l != token_start)
1692 { /* Yes, we've read in another operand. */
1693 unsigned int operand_ok;
1694 this_operand = i.operands++;
1695 if (i.operands > MAX_OPERANDS)
1697 as_bad (_("spurious operands; (%d operands/instruction max)"),
1701 /* Now parse operand adding info to 'i' as we go along. */
1702 END_STRING_AND_SAVE (l);
1706 i386_intel_operand (token_start,
1707 intel_float_operand (mnemonic));
1709 operand_ok = i386_operand (token_start);
1711 RESTORE_END_STRING (l);
1717 if (expecting_operand)
1719 expecting_operand_after_comma:
1720 as_bad (_("expecting operand after ','; got nothing"));
1725 as_bad (_("expecting operand before ','; got nothing"));
1730 /* Now *l must be either ',' or END_OF_INSN. */
1733 if (*++l == END_OF_INSN)
1735 /* Just skip it, if it's \n complain. */
1736 goto expecting_operand_after_comma;
1738 expecting_operand = 1;
1747 union i386_op temp_op;
1748 unsigned int temp_type;
1749 RELOC_ENUM temp_reloc;
1753 if (i.operands == 2)
1758 else if (i.operands == 3)
1763 temp_type = i.types[xchg2];
1764 i.types[xchg2] = i.types[xchg1];
1765 i.types[xchg1] = temp_type;
1766 temp_op = i.op[xchg2];
1767 i.op[xchg2] = i.op[xchg1];
1768 i.op[xchg1] = temp_op;
1769 temp_reloc = i.reloc[xchg2];
1770 i.reloc[xchg2] = i.reloc[xchg1];
1771 i.reloc[xchg1] = temp_reloc;
1773 if (i.mem_operands == 2)
1775 const seg_entry *temp_seg;
1776 temp_seg = i.seg[0];
1777 i.seg[0] = i.seg[1];
1778 i.seg[1] = temp_seg;
1782 /* Try to ensure constant immediates are represented in the smallest
1787 char guess_suffix = 0;
1791 guess_suffix = i.suffix;
1792 else if (i.reg_operands)
1794 /* Figure out a suffix from the last register operand specified.
1795 We can't do this properly yet, ie. excluding InOutPortReg,
1796 but the following works for instructions with immediates.
1797 In any case, we can't set i.suffix yet. */
1798 for (op = i.operands; --op >= 0;)
1799 if (i.types[op] & Reg)
1801 if (i.types[op] & Reg8)
1802 guess_suffix = BYTE_MNEM_SUFFIX;
1803 else if (i.types[op] & Reg16)
1804 guess_suffix = WORD_MNEM_SUFFIX;
1805 else if (i.types[op] & Reg32)
1806 guess_suffix = LONG_MNEM_SUFFIX;
1807 else if (i.types[op] & Reg64)
1808 guess_suffix = QWORD_MNEM_SUFFIX;
1812 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1813 guess_suffix = WORD_MNEM_SUFFIX;
1815 for (op = i.operands; --op >= 0;)
1816 if (i.types[op] & Imm)
1818 switch (i.op[op].imms->X_op)
1821 /* If a suffix is given, this operand may be shortened. */
1822 switch (guess_suffix)
1824 case LONG_MNEM_SUFFIX:
1825 i.types[op] |= Imm32 | Imm64;
1827 case WORD_MNEM_SUFFIX:
1828 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1830 case BYTE_MNEM_SUFFIX:
1831 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1835 /* If this operand is at most 16 bits, convert it
1836 to a signed 16 bit number before trying to see
1837 whether it will fit in an even smaller size.
1838 This allows a 16-bit operand such as $0xffe0 to
1839 be recognised as within Imm8S range. */
1840 if ((i.types[op] & Imm16)
1841 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1843 i.op[op].imms->X_add_number =
1844 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1846 if ((i.types[op] & Imm32)
1847 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1850 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1851 ^ ((offsetT) 1 << 31))
1852 - ((offsetT) 1 << 31));
1854 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1856 /* We must avoid matching of Imm32 templates when 64bit
1857 only immediate is available. */
1858 if (guess_suffix == QWORD_MNEM_SUFFIX)
1859 i.types[op] &= ~Imm32;
1866 /* Symbols and expressions. */
1868 /* Convert symbolic operand to proper sizes for matching. */
1869 switch (guess_suffix)
1871 case QWORD_MNEM_SUFFIX:
1872 i.types[op] = Imm64 | Imm32S;
1874 case LONG_MNEM_SUFFIX:
1875 i.types[op] = Imm32 | Imm64;
1877 case WORD_MNEM_SUFFIX:
1878 i.types[op] = Imm16 | Imm32 | Imm64;
1881 case BYTE_MNEM_SUFFIX:
1882 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1891 /* Try to use the smallest displacement type too. */
1897 for (op = i.operands; --op >= 0;)
1898 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1900 offsetT disp = i.op[op].disps->X_add_number;
1902 if (i.types[op] & Disp16)
1904 /* We know this operand is at most 16 bits, so
1905 convert to a signed 16 bit number before trying
1906 to see whether it will fit in an even smaller
1909 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1911 else if (i.types[op] & Disp32)
1913 /* We know this operand is at most 32 bits, so convert to a
1914 signed 32 bit number before trying to see whether it will
1915 fit in an even smaller size. */
1916 disp &= (((offsetT) 2 << 31) - 1);
1917 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1919 if (flag_code == CODE_64BIT)
1921 if (fits_in_signed_long (disp))
1922 i.types[op] |= Disp32S;
1923 if (fits_in_unsigned_long (disp))
1924 i.types[op] |= Disp32;
1926 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1927 && fits_in_signed_byte (disp))
1928 i.types[op] |= Disp8;
1935 /* Points to template once we've found it. */
1937 unsigned int overlap0, overlap1, overlap2;
1938 unsigned int found_reverse_match;
1941 #define MATCH(overlap, given, template) \
1942 ((overlap & ~JumpAbsolute) \
1943 && (((given) & (BaseIndex | JumpAbsolute)) \
1944 == ((overlap) & (BaseIndex | JumpAbsolute))))
1946 /* If given types r0 and r1 are registers they must be of the same type
1947 unless the expected operand type register overlap is null.
1948 Note that Acc in a template matches every size of reg. */
1949 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1950 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1951 || ((g0) & Reg) == ((g1) & Reg) \
1952 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1957 found_reverse_match = 0;
1958 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1960 : (i.suffix == WORD_MNEM_SUFFIX
1962 : (i.suffix == SHORT_MNEM_SUFFIX
1964 : (i.suffix == LONG_MNEM_SUFFIX
1966 : (i.suffix == QWORD_MNEM_SUFFIX
1968 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1969 ? No_xSuf : 0))))));
1971 for (t = current_templates->start;
1972 t < current_templates->end;
1975 /* Must have right number of operands. */
1976 if (i.operands != t->operands)
1979 /* Check the suffix, except for some instructions in intel mode. */
1980 if ((t->opcode_modifier & suffix_check)
1982 && (t->opcode_modifier & IgnoreSize))
1984 && t->base_opcode == 0xd9
1985 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1986 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1989 /* Do not verify operands when there are none. */
1990 else if (!t->operands)
1992 if (t->cpu_flags & ~cpu_arch_flags)
1994 /* We've found a match; break out of loop. */
1998 overlap0 = i.types[0] & t->operand_types[0];
1999 switch (t->operands)
2002 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2007 overlap1 = i.types[1] & t->operand_types[1];
2008 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2009 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2010 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2011 t->operand_types[0],
2012 overlap1, i.types[1],
2013 t->operand_types[1]))
2015 /* Check if other direction is valid ... */
2016 if ((t->opcode_modifier & (D | FloatD)) == 0)
2019 /* Try reversing direction of operands. */
2020 overlap0 = i.types[0] & t->operand_types[1];
2021 overlap1 = i.types[1] & t->operand_types[0];
2022 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2023 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2024 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2025 t->operand_types[1],
2026 overlap1, i.types[1],
2027 t->operand_types[0]))
2029 /* Does not match either direction. */
2032 /* found_reverse_match holds which of D or FloatDR
2034 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2036 /* Found a forward 2 operand match here. */
2037 else if (t->operands == 3)
2039 /* Here we make use of the fact that there are no
2040 reverse match 3 operand instructions, and all 3
2041 operand instructions only need to be checked for
2042 register consistency between operands 2 and 3. */
2043 overlap2 = i.types[2] & t->operand_types[2];
2044 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2045 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2046 t->operand_types[1],
2047 overlap2, i.types[2],
2048 t->operand_types[2]))
2052 /* Found either forward/reverse 2 or 3 operand match here:
2053 slip through to break. */
2055 if (t->cpu_flags & ~cpu_arch_flags)
2057 found_reverse_match = 0;
2060 /* We've found a match; break out of loop. */
2064 if (t == current_templates->end)
2066 /* We found no match. */
2067 as_bad (_("suffix or operands invalid for `%s'"),
2068 current_templates->start->name);
2072 if (!quiet_warnings)
2075 && ((i.types[0] & JumpAbsolute)
2076 != (t->operand_types[0] & JumpAbsolute)))
2078 as_warn (_("indirect %s without `*'"), t->name);
2081 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2082 == (IsPrefix | IgnoreSize))
2084 /* Warn them that a data or address size prefix doesn't
2085 affect assembly of the next line of code. */
2086 as_warn (_("stand-alone `%s' prefix"), t->name);
2090 /* Copy the template we found. */
2092 if (found_reverse_match)
2094 /* If we found a reverse match we must alter the opcode
2095 direction bit. found_reverse_match holds bits to change
2096 (different for int & float insns). */
2098 i.tm.base_opcode ^= found_reverse_match;
2100 i.tm.operand_types[0] = t->operand_types[1];
2101 i.tm.operand_types[1] = t->operand_types[0];
2110 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2111 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2113 if (i.seg[0] != NULL && i.seg[0] != &es)
2115 as_bad (_("`%s' operand %d must use `%%es' segment"),
2120 /* There's only ever one segment override allowed per instruction.
2121 This instruction possibly has a legal segment override on the
2122 second operand, so copy the segment to where non-string
2123 instructions store it, allowing common code. */
2124 i.seg[0] = i.seg[1];
2126 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2128 if (i.seg[1] != NULL && i.seg[1] != &es)
2130 as_bad (_("`%s' operand %d must use `%%es' segment"),
2142 /* If matched instruction specifies an explicit instruction mnemonic
2144 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2146 if (i.tm.opcode_modifier & Size16)
2147 i.suffix = WORD_MNEM_SUFFIX;
2148 else if (i.tm.opcode_modifier & Size64)
2149 i.suffix = QWORD_MNEM_SUFFIX;
2151 i.suffix = LONG_MNEM_SUFFIX;
2153 else if (i.reg_operands)
2155 /* If there's no instruction mnemonic suffix we try to invent one
2156 based on register operands. */
2159 /* We take i.suffix from the last register operand specified,
2160 Destination register type is more significant than source
2163 for (op = i.operands; --op >= 0;)
2164 if ((i.types[op] & Reg)
2165 && !(i.tm.operand_types[op] & InOutPortReg))
2167 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2168 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2169 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2174 else if (i.suffix == BYTE_MNEM_SUFFIX)
2176 if (!check_byte_reg ())
2179 else if (i.suffix == LONG_MNEM_SUFFIX)
2181 if (!check_long_reg ())
2184 else if (i.suffix == QWORD_MNEM_SUFFIX)
2186 if (!check_qword_reg ())
2189 else if (i.suffix == WORD_MNEM_SUFFIX)
2191 if (!check_word_reg ())
2194 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2195 /* Do nothing if the instruction is going to ignore the prefix. */
2200 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2202 i.suffix = stackop_size;
2205 /* Change the opcode based on the operand size given by i.suffix;
2206 We need not change things for byte insns. */
2208 if (!i.suffix && (i.tm.opcode_modifier & W))
2210 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2214 /* For movzx and movsx, need to check the register type. */
2216 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
2217 && i.suffix == BYTE_MNEM_SUFFIX)
2219 unsigned int prefix = DATA_PREFIX_OPCODE;
2221 if ((i.op[1].regs->reg_type & Reg16) != 0)
2222 if (!add_prefix (prefix))
2226 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2228 /* It's not a byte, select word/dword operation. */
2229 if (i.tm.opcode_modifier & W)
2231 if (i.tm.opcode_modifier & ShortForm)
2232 i.tm.base_opcode |= 8;
2234 i.tm.base_opcode |= 1;
2237 /* Now select between word & dword operations via the operand
2238 size prefix, except for instructions that will ignore this
2240 if (i.suffix != QWORD_MNEM_SUFFIX
2241 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2242 && !(i.tm.opcode_modifier & IgnoreSize))
2244 unsigned int prefix = DATA_PREFIX_OPCODE;
2245 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2246 prefix = ADDR_PREFIX_OPCODE;
2248 if (!add_prefix (prefix))
2252 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2253 && !(i.tm.opcode_modifier & IgnoreSize)
2254 && (i.tm.opcode_modifier & JumpByte))
2256 if (!add_prefix (ADDR_PREFIX_OPCODE))
2260 /* Set mode64 for an operand. */
2261 if (i.suffix == QWORD_MNEM_SUFFIX
2262 && (i.tm.opcode_modifier & NoRex64) == 0)
2264 i.rex |= REX_MODE64;
2265 if (flag_code < CODE_64BIT)
2267 as_bad (_("64bit operations available only in 64bit modes."));
2272 /* Size floating point instruction. */
2273 if (i.suffix == LONG_MNEM_SUFFIX)
2275 if (i.tm.opcode_modifier & FloatMF)
2276 i.tm.base_opcode ^= 4;
2287 for (op = i.operands; --op >= 0;)
2289 /* If this is an eight bit register, it's OK. If it's the 16 or
2290 32 bit version of an eight bit register, we will just use the
2291 low portion, and that's OK too. */
2292 if (i.types[op] & Reg8)
2295 /* movzx and movsx should not generate this warning. */
2297 && (i.tm.base_opcode == 0xfb7
2298 || i.tm.base_opcode == 0xfb6
2299 || i.tm.base_opcode == 0x63
2300 || i.tm.base_opcode == 0xfbe
2301 || i.tm.base_opcode == 0xfbf))
2304 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2306 /* Check that the template allows eight bit regs. This
2307 kills insns such as `orb $1,%edx', which maybe should be
2309 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2313 /* Prohibit these changes in the 64bit mode, since the
2314 lowering is more complicated. */
2315 if (flag_code == CODE_64BIT
2316 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2318 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2319 i.op[op].regs->reg_name,
2323 #if REGISTER_WARNINGS
2325 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2326 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2327 (i.op[op].regs + (i.types[op] & Reg16
2328 ? REGNAM_AL - REGNAM_AX
2329 : REGNAM_AL - REGNAM_EAX))->reg_name,
2330 i.op[op].regs->reg_name,
2335 /* Any other register is bad. */
2336 if (i.types[op] & (Reg | RegMMX | RegXMM
2338 | Control | Debug | Test
2339 | FloatReg | FloatAcc))
2341 as_bad (_("`%%%s' not allowed with `%s%c'"),
2342 i.op[op].regs->reg_name,
2356 for (op = i.operands; --op >= 0;)
2357 /* Reject eight bit registers, except where the template requires
2358 them. (eg. movzb) */
2359 if ((i.types[op] & Reg8) != 0
2360 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2362 as_bad (_("`%%%s' not allowed with `%s%c'"),
2363 i.op[op].regs->reg_name,
2368 /* Warn if the e prefix on a general reg is missing. */
2369 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2370 && (i.types[op] & Reg16) != 0
2371 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2373 /* Prohibit these changes in the 64bit mode, since the
2374 lowering is more complicated. */
2375 if (flag_code == CODE_64BIT)
2377 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2378 i.op[op].regs->reg_name,
2382 #if REGISTER_WARNINGS
2384 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2385 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2386 i.op[op].regs->reg_name,
2390 /* Warn if the r prefix on a general reg is missing. */
2391 else if ((i.types[op] & Reg64) != 0
2392 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2394 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2395 i.op[op].regs->reg_name,
2407 for (op = i.operands; --op >= 0; )
2408 /* Reject eight bit registers, except where the template requires
2409 them. (eg. movzb) */
2410 if ((i.types[op] & Reg8) != 0
2411 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2413 as_bad (_("`%%%s' not allowed with `%s%c'"),
2414 i.op[op].regs->reg_name,
2419 /* Warn if the e prefix on a general reg is missing. */
2420 else if (((i.types[op] & Reg16) != 0
2421 || (i.types[op] & Reg32) != 0)
2422 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2424 /* Prohibit these changes in the 64bit mode, since the
2425 lowering is more complicated. */
2426 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2427 i.op[op].regs->reg_name,
2438 for (op = i.operands; --op >= 0;)
2439 /* Reject eight bit registers, except where the template requires
2440 them. (eg. movzb) */
2441 if ((i.types[op] & Reg8) != 0
2442 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2444 as_bad (_("`%%%s' not allowed with `%s%c'"),
2445 i.op[op].regs->reg_name,
2450 /* Warn if the e prefix on a general reg is present. */
2451 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2452 && (i.types[op] & Reg32) != 0
2453 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2455 /* Prohibit these changes in the 64bit mode, since the
2456 lowering is more complicated. */
2457 if (flag_code == CODE_64BIT)
2459 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2460 i.op[op].regs->reg_name,
2465 #if REGISTER_WARNINGS
2466 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2467 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2468 i.op[op].regs->reg_name,
2478 unsigned int overlap0, overlap1, overlap2;
2480 overlap0 = i.types[0] & i.tm.operand_types[0];
2481 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2482 && overlap0 != Imm8 && overlap0 != Imm8S
2483 && overlap0 != Imm16 && overlap0 != Imm32S
2484 && overlap0 != Imm32 && overlap0 != Imm64)
2488 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2490 : (i.suffix == WORD_MNEM_SUFFIX
2492 : (i.suffix == QWORD_MNEM_SUFFIX
2496 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2497 || overlap0 == (Imm16 | Imm32)
2498 || overlap0 == (Imm16 | Imm32S))
2500 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2503 if (overlap0 != Imm8 && overlap0 != Imm8S
2504 && overlap0 != Imm16 && overlap0 != Imm32S
2505 && overlap0 != Imm32 && overlap0 != Imm64)
2507 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2511 i.types[0] = overlap0;
2513 overlap1 = i.types[1] & i.tm.operand_types[1];
2514 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2515 && overlap1 != Imm8 && overlap1 != Imm8S
2516 && overlap1 != Imm16 && overlap1 != Imm32S
2517 && overlap1 != Imm32 && overlap1 != Imm64)
2521 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2523 : (i.suffix == WORD_MNEM_SUFFIX
2525 : (i.suffix == QWORD_MNEM_SUFFIX
2529 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2530 || overlap1 == (Imm16 | Imm32)
2531 || overlap1 == (Imm16 | Imm32S))
2533 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2536 if (overlap1 != Imm8 && overlap1 != Imm8S
2537 && overlap1 != Imm16 && overlap1 != Imm32S
2538 && overlap1 != Imm32 && overlap1 != Imm64)
2540 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2544 i.types[1] = overlap1;
2546 overlap2 = i.types[2] & i.tm.operand_types[2];
2547 assert ((overlap2 & Imm) == 0);
2548 i.types[2] = overlap2;
2556 /* Default segment register this instruction will use for memory
2557 accesses. 0 means unknown. This is only for optimizing out
2558 unnecessary segment overrides. */
2559 const seg_entry *default_seg = 0;
2561 /* The imul $imm, %reg instruction is converted into
2562 imul $imm, %reg, %reg, and the clr %reg instruction
2563 is converted into xor %reg, %reg. */
2564 if (i.tm.opcode_modifier & regKludge)
2566 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2567 /* Pretend we saw the extra register operand. */
2568 assert (i.op[first_reg_op + 1].regs == 0);
2569 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2570 i.types[first_reg_op + 1] = i.types[first_reg_op];
2574 if (i.tm.opcode_modifier & ShortForm)
2576 /* The register or float register operand is in operand 0 or 1. */
2577 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2578 /* Register goes in low 3 bits of opcode. */
2579 i.tm.base_opcode |= i.op[op].regs->reg_num;
2580 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2582 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2584 /* Warn about some common errors, but press on regardless.
2585 The first case can be generated by gcc (<= 2.8.1). */
2586 if (i.operands == 2)
2588 /* Reversed arguments on faddp, fsubp, etc. */
2589 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2590 i.op[1].regs->reg_name,
2591 i.op[0].regs->reg_name);
2595 /* Extraneous `l' suffix on fp insn. */
2596 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2597 i.op[0].regs->reg_name);
2601 else if (i.tm.opcode_modifier & Modrm)
2603 /* The opcode is completed (modulo i.tm.extension_opcode which
2604 must be put into the modrm byte).
2605 Now, we make the modrm & index base bytes based on all the
2606 info we've collected. */
2608 default_seg = build_modrm_byte ();
2610 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2612 if (i.tm.base_opcode == POP_SEG_SHORT
2613 && i.op[0].regs->reg_num == 1)
2615 as_bad (_("you can't `pop %%cs'"));
2618 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2619 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2622 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2626 else if ((i.tm.opcode_modifier & IsString) != 0)
2628 /* For the string instructions that allow a segment override
2629 on one of their operands, the default segment is ds. */
2633 /* If a segment was explicitly specified,
2634 and the specified segment is not the default,
2635 use an opcode prefix to select it.
2636 If we never figured out what the default segment is,
2637 then default_seg will be zero at this point,
2638 and the specified segment prefix will always be used. */
2639 if ((i.seg[0]) && (i.seg[0] != default_seg))
2641 if (!add_prefix (i.seg[0]->seg_prefix))
2647 static const seg_entry *
2650 const seg_entry *default_seg = 0;
2652 /* i.reg_operands MUST be the number of real register operands;
2653 implicit registers do not count. */
2654 if (i.reg_operands == 2)
2656 unsigned int source, dest;
2657 source = ((i.types[0]
2658 & (Reg | RegMMX | RegXMM
2660 | Control | Debug | Test))
2665 /* One of the register operands will be encoded in the i.tm.reg
2666 field, the other in the combined i.tm.mode and i.tm.regmem
2667 fields. If no form of this instruction supports a memory
2668 destination operand, then we assume the source operand may
2669 sometimes be a memory operand and so we need to store the
2670 destination in the i.rm.reg field. */
2671 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2673 i.rm.reg = i.op[dest].regs->reg_num;
2674 i.rm.regmem = i.op[source].regs->reg_num;
2675 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2677 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2682 i.rm.reg = i.op[source].regs->reg_num;
2683 i.rm.regmem = i.op[dest].regs->reg_num;
2684 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2686 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2691 { /* If it's not 2 reg operands... */
2694 unsigned int fake_zero_displacement = 0;
2695 unsigned int op = ((i.types[0] & AnyMem)
2697 : (i.types[1] & AnyMem) ? 1 : 2);
2701 if (i.base_reg == 0)
2704 if (!i.disp_operands)
2705 fake_zero_displacement = 1;
2706 if (i.index_reg == 0)
2708 /* Operand is just <disp> */
2709 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2710 && (flag_code != CODE_64BIT))
2712 i.rm.regmem = NO_BASE_REGISTER_16;
2713 i.types[op] &= ~Disp;
2714 i.types[op] |= Disp16;
2716 else if (flag_code != CODE_64BIT
2717 || (i.prefix[ADDR_PREFIX] != 0))
2719 i.rm.regmem = NO_BASE_REGISTER;
2720 i.types[op] &= ~Disp;
2721 i.types[op] |= Disp32;
2725 /* 64bit mode overwrites the 32bit absolute
2726 addressing by RIP relative addressing and
2727 absolute addressing is encoded by one of the
2728 redundant SIB forms. */
2729 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2730 i.sib.base = NO_BASE_REGISTER;
2731 i.sib.index = NO_INDEX_REGISTER;
2732 i.types[op] &= ~Disp;
2733 i.types[op] |= Disp32S;
2736 else /* !i.base_reg && i.index_reg */
2738 i.sib.index = i.index_reg->reg_num;
2739 i.sib.base = NO_BASE_REGISTER;
2740 i.sib.scale = i.log2_scale_factor;
2741 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2742 i.types[op] &= ~Disp;
2743 if (flag_code != CODE_64BIT)
2744 i.types[op] |= Disp32; /* Must be 32 bit */
2746 i.types[op] |= Disp32S;
2747 if ((i.index_reg->reg_flags & RegRex) != 0)
2751 /* RIP addressing for 64bit mode. */
2752 else if (i.base_reg->reg_type == BaseIndex)
2754 i.rm.regmem = NO_BASE_REGISTER;
2755 i.types[op] &= ~Disp;
2756 i.types[op] |= Disp32S;
2757 i.flags[op] = Operand_PCrel;
2759 else if (i.base_reg->reg_type & Reg16)
2761 switch (i.base_reg->reg_num)
2764 if (i.index_reg == 0)
2766 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2767 i.rm.regmem = i.index_reg->reg_num - 6;
2771 if (i.index_reg == 0)
2774 if ((i.types[op] & Disp) == 0)
2776 /* fake (%bp) into 0(%bp) */
2777 i.types[op] |= Disp8;
2778 fake_zero_displacement = 1;
2781 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2782 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2784 default: /* (%si) -> 4 or (%di) -> 5 */
2785 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2787 i.rm.mode = mode_from_disp_size (i.types[op]);
2789 else /* i.base_reg and 32/64 bit mode */
2791 if (flag_code == CODE_64BIT
2792 && (i.types[op] & Disp))
2794 if (i.types[op] & Disp8)
2795 i.types[op] = Disp8 | Disp32S;
2797 i.types[op] = Disp32S;
2799 i.rm.regmem = i.base_reg->reg_num;
2800 if ((i.base_reg->reg_flags & RegRex) != 0)
2802 i.sib.base = i.base_reg->reg_num;
2803 /* x86-64 ignores REX prefix bit here to avoid decoder
2805 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2808 if (i.disp_operands == 0)
2810 fake_zero_displacement = 1;
2811 i.types[op] |= Disp8;
2814 else if (i.base_reg->reg_num == ESP_REG_NUM)
2818 i.sib.scale = i.log2_scale_factor;
2819 if (i.index_reg == 0)
2821 /* <disp>(%esp) becomes two byte modrm with no index
2822 register. We've already stored the code for esp
2823 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2824 Any base register besides %esp will not use the
2825 extra modrm byte. */
2826 i.sib.index = NO_INDEX_REGISTER;
2827 #if !SCALE1_WHEN_NO_INDEX
2828 /* Another case where we force the second modrm byte. */
2829 if (i.log2_scale_factor)
2830 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2835 i.sib.index = i.index_reg->reg_num;
2836 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2837 if ((i.index_reg->reg_flags & RegRex) != 0)
2840 i.rm.mode = mode_from_disp_size (i.types[op]);
2843 if (fake_zero_displacement)
2845 /* Fakes a zero displacement assuming that i.types[op]
2846 holds the correct displacement size. */
2849 assert (i.op[op].disps == 0);
2850 exp = &disp_expressions[i.disp_operands++];
2851 i.op[op].disps = exp;
2852 exp->X_op = O_constant;
2853 exp->X_add_number = 0;
2854 exp->X_add_symbol = (symbolS *) 0;
2855 exp->X_op_symbol = (symbolS *) 0;
2859 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2860 (if any) based on i.tm.extension_opcode. Again, we must be
2861 careful to make sure that segment/control/debug/test/MMX
2862 registers are coded into the i.rm.reg field. */
2867 & (Reg | RegMMX | RegXMM
2869 | Control | Debug | Test))
2872 & (Reg | RegMMX | RegXMM
2874 | Control | Debug | Test))
2877 /* If there is an extension opcode to put here, the register
2878 number must be put into the regmem field. */
2879 if (i.tm.extension_opcode != None)
2881 i.rm.regmem = i.op[op].regs->reg_num;
2882 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2887 i.rm.reg = i.op[op].regs->reg_num;
2888 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2892 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2893 must set it to 3 to indicate this is a register operand
2894 in the regmem field. */
2895 if (!i.mem_operands)
2899 /* Fill in i.rm.reg field with extension opcode (if any). */
2900 if (i.tm.extension_opcode != None)
2901 i.rm.reg = i.tm.extension_opcode;
2912 relax_substateT subtype;
2917 if (flag_code == CODE_16BIT)
2921 if (i.prefix[DATA_PREFIX] != 0)
2927 /* Pentium4 branch hints. */
2928 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2929 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2934 if (i.prefix[REX_PREFIX] != 0)
2940 if (i.prefixes != 0 && !intel_syntax)
2941 as_warn (_("skipping prefixes on this instruction"));
2943 /* It's always a symbol; End frag & setup for relax.
2944 Make sure there is enough room in this frag for the largest
2945 instruction we may generate in md_convert_frag. This is 2
2946 bytes for the opcode and room for the prefix and largest
2948 frag_grow (prefix + 2 + 4);
2949 /* Prefix and 1 opcode byte go in fr_fix. */
2950 p = frag_more (prefix + 1);
2951 if (i.prefix[DATA_PREFIX] != 0)
2952 *p++ = DATA_PREFIX_OPCODE;
2953 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2954 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2955 *p++ = i.prefix[SEG_PREFIX];
2956 if (i.prefix[REX_PREFIX] != 0)
2957 *p++ = i.prefix[REX_PREFIX];
2958 *p = i.tm.base_opcode;
2960 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2961 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2962 else if ((cpu_arch_flags & Cpu386) != 0)
2963 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2965 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2968 sym = i.op[0].disps->X_add_symbol;
2969 off = i.op[0].disps->X_add_number;
2971 if (i.op[0].disps->X_op != O_constant
2972 && i.op[0].disps->X_op != O_symbol)
2974 /* Handle complex expressions. */
2975 sym = make_expr_symbol (i.op[0].disps);
2979 /* 1 possible extra opcode + 4 byte displacement go in var part.
2980 Pass reloc in fr_var. */
2981 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2990 if (i.tm.opcode_modifier & JumpByte)
2992 /* This is a loop or jecxz type instruction. */
2994 if (i.prefix[ADDR_PREFIX] != 0)
2996 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2999 /* Pentium4 branch hints. */
3000 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3001 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3003 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3012 if (flag_code == CODE_16BIT)
3015 if (i.prefix[DATA_PREFIX] != 0)
3017 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3027 if (i.prefix[REX_PREFIX] != 0)
3029 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3033 if (i.prefixes != 0 && !intel_syntax)
3034 as_warn (_("skipping prefixes on this instruction"));
3036 p = frag_more (1 + size);
3037 *p++ = i.tm.base_opcode;
3039 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3040 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3044 output_interseg_jump ()
3052 if (flag_code == CODE_16BIT)
3056 if (i.prefix[DATA_PREFIX] != 0)
3062 if (i.prefix[REX_PREFIX] != 0)
3072 if (i.prefixes != 0 && !intel_syntax)
3073 as_warn (_("skipping prefixes on this instruction"));
3075 /* 1 opcode; 2 segment; offset */
3076 p = frag_more (prefix + 1 + 2 + size);
3078 if (i.prefix[DATA_PREFIX] != 0)
3079 *p++ = DATA_PREFIX_OPCODE;
3081 if (i.prefix[REX_PREFIX] != 0)
3082 *p++ = i.prefix[REX_PREFIX];
3084 *p++ = i.tm.base_opcode;
3085 if (i.op[1].imms->X_op == O_constant)
3087 offsetT n = i.op[1].imms->X_add_number;
3090 && !fits_in_unsigned_word (n)
3091 && !fits_in_signed_word (n))
3093 as_bad (_("16-bit jump out of range"));
3096 md_number_to_chars (p, n, size);
3099 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3100 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3101 if (i.op[0].imms->X_op != O_constant)
3102 as_bad (_("can't handle non absolute segment in `%s'"),
3104 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3110 /* Tie dwarf2 debug info to the address at the start of the insn.
3111 We can't do this after the insn has been output as the current
3112 frag may have been closed off. eg. by frag_var. */
3113 dwarf2_emit_insn (0);
3116 if (i.tm.opcode_modifier & Jump)
3118 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3120 else if (i.tm.opcode_modifier & JumpInterSegment)
3121 output_interseg_jump ();
3124 /* Output normal instructions here. */
3128 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3129 byte for the SSE instructions to specify a prefix they require. */
3130 if (i.tm.base_opcode & 0xff0000)
3131 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3133 /* The prefix bytes. */
3135 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3141 md_number_to_chars (p, (valueT) *q, 1);
3145 /* Now the opcode; be careful about word order here! */
3146 if (fits_in_unsigned_byte (i.tm.base_opcode))
3148 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3153 /* Put out high byte first: can't use md_number_to_chars! */
3154 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3155 *p = i.tm.base_opcode & 0xff;
3158 /* Now the modrm byte and sib byte (if present). */
3159 if (i.tm.opcode_modifier & Modrm)
3162 md_number_to_chars (p,
3163 (valueT) (i.rm.regmem << 0
3167 /* If i.rm.regmem == ESP (4)
3168 && i.rm.mode != (Register mode)
3170 ==> need second modrm byte. */
3171 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3173 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3176 md_number_to_chars (p,
3177 (valueT) (i.sib.base << 0
3179 | i.sib.scale << 6),
3184 if (i.disp_operands)
3196 #endif /* DEBUG386 */
3205 for (n = 0; n < i.operands; n++)
3207 if (i.types[n] & Disp)
3209 if (i.op[n].disps->X_op == O_constant)
3215 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3218 if (i.types[n] & Disp8)
3220 if (i.types[n] & Disp64)
3223 val = offset_in_range (i.op[n].disps->X_add_number,
3225 p = frag_more (size);
3226 md_number_to_chars (p, val, size);
3232 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3234 /* The PC relative address is computed relative
3235 to the instruction boundary, so in case immediate
3236 fields follows, we need to adjust the value. */
3237 if (pcrel && i.imm_operands)
3242 for (n1 = 0; n1 < i.operands; n1++)
3243 if (i.types[n1] & Imm)
3245 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3248 if (i.types[n1] & (Imm8 | Imm8S))
3250 if (i.types[n1] & Imm64)
3255 /* We should find the immediate. */
3256 if (n1 == i.operands)
3258 i.op[n].disps->X_add_number -= imm_size;
3261 if (i.types[n] & Disp32S)
3264 if (i.types[n] & (Disp16 | Disp64))
3267 if (i.types[n] & Disp64)
3271 p = frag_more (size);
3272 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3273 i.op[n].disps, pcrel,
3274 reloc (size, pcrel, sign, i.reloc[n]));
3286 for (n = 0; n < i.operands; n++)
3288 if (i.types[n] & Imm)
3290 if (i.op[n].imms->X_op == O_constant)
3296 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3299 if (i.types[n] & (Imm8 | Imm8S))
3301 else if (i.types[n] & Imm64)
3304 val = offset_in_range (i.op[n].imms->X_add_number,
3306 p = frag_more (size);
3307 md_number_to_chars (p, val, size);
3311 /* Not absolute_section.
3312 Need a 32-bit fixup (don't support 8bit
3313 non-absolute imms). Try to support other
3315 RELOC_ENUM reloc_type;
3319 if ((i.types[n] & (Imm32S))
3320 && i.suffix == QWORD_MNEM_SUFFIX)
3322 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3325 if (i.types[n] & (Imm8 | Imm8S))
3327 if (i.types[n] & Imm64)
3331 p = frag_more (size);
3332 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3333 #ifdef BFD_ASSEMBLER
3334 if (reloc_type == BFD_RELOC_32
3336 && GOT_symbol == i.op[n].imms->X_add_symbol
3337 && (i.op[n].imms->X_op == O_symbol
3338 || (i.op[n].imms->X_op == O_add
3339 && ((symbol_get_value_expression
3340 (i.op[n].imms->X_op_symbol)->X_op)
3343 /* We don't support dynamic linking on x86-64 yet. */
3344 if (flag_code == CODE_64BIT)
3346 reloc_type = BFD_RELOC_386_GOTPC;
3347 i.op[n].imms->X_add_number += 3;
3350 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3351 i.op[n].imms, 0, reloc_type);
3358 static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3360 /* Parse operands of the form
3361 <symbol>@GOTOFF+<nnn>
3362 and similar .plt or .got references.
3364 If we find one, set up the correct relocation in RELOC and copy the
3365 input string, minus the `@GOTOFF' into a malloc'd buffer for
3366 parsing by the calling routine. Return this buffer, and if ADJUST
3367 is non-null set it to the length of the string we removed from the
3368 input line. Otherwise return NULL. */
3370 lex_got (reloc, adjust)
3374 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3375 static const struct {
3377 const RELOC_ENUM rel[NUM_FLAG_CODE];
3379 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3380 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3381 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3382 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3387 for (cp = input_line_pointer; *cp != '@'; cp++)
3388 if (is_end_of_line[(unsigned char) *cp])
3391 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3395 len = strlen (gotrel[j].str);
3396 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3398 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3401 char *tmpbuf, *past_reloc;
3403 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3407 if (GOT_symbol == NULL)
3408 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3410 /* Replace the relocation token with ' ', so that
3411 errors like foo@GOTOFF1 will be detected. */
3413 /* The length of the first part of our input line. */
3414 first = cp - input_line_pointer;
3416 /* The second part goes from after the reloc token until
3417 (and including) an end_of_line char. Don't use strlen
3418 here as the end_of_line char may not be a NUL. */
3419 past_reloc = cp + 1 + len;
3420 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3422 second = cp - past_reloc;
3424 /* Allocate and copy string. The trailing NUL shouldn't
3425 be necessary, but be safe. */
3426 tmpbuf = xmalloc (first + second + 2);
3427 memcpy (tmpbuf, input_line_pointer, first);
3428 tmpbuf[first] = ' ';
3429 memcpy (tmpbuf + first + 1, past_reloc, second);
3430 tmpbuf[first + second + 1] = '\0';
3434 as_bad (_("@%s reloc is not supported in %s bit mode"),
3435 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3440 /* Might be a symbol version string. Don't as_bad here. */
3444 /* x86_cons_fix_new is called via the expression parsing code when a
3445 reloc is needed. We use this hook to get the correct .got reloc. */
3446 static RELOC_ENUM got_reloc = NO_RELOC;
3449 x86_cons_fix_new (frag, off, len, exp)
3455 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3456 got_reloc = NO_RELOC;
3457 fix_new_exp (frag, off, len, exp, 0, r);
3461 x86_cons (exp, size)
3467 /* Handle @GOTOFF and the like in an expression. */
3469 char *gotfree_input_line;
3472 save = input_line_pointer;
3473 gotfree_input_line = lex_got (&got_reloc, &adjust);
3474 if (gotfree_input_line)
3475 input_line_pointer = gotfree_input_line;
3479 if (gotfree_input_line)
3481 /* expression () has merrily parsed up to the end of line,
3482 or a comma - in the wrong buffer. Transfer how far
3483 input_line_pointer has moved to the right buffer. */
3484 input_line_pointer = (save
3485 + (input_line_pointer - gotfree_input_line)
3487 free (gotfree_input_line);
3495 static int i386_immediate PARAMS ((char *));
3498 i386_immediate (imm_start)
3501 char *save_input_line_pointer;
3503 char *gotfree_input_line;
3508 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3510 as_bad (_("only 1 or 2 immediate operands are allowed"));
3514 exp = &im_expressions[i.imm_operands++];
3515 i.op[this_operand].imms = exp;
3517 if (is_space_char (*imm_start))
3520 save_input_line_pointer = input_line_pointer;
3521 input_line_pointer = imm_start;
3524 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3525 if (gotfree_input_line)
3526 input_line_pointer = gotfree_input_line;
3529 exp_seg = expression (exp);
3532 if (*input_line_pointer)
3533 as_bad (_("junk `%s' after expression"), input_line_pointer);
3535 input_line_pointer = save_input_line_pointer;
3537 if (gotfree_input_line)
3538 free (gotfree_input_line);
3541 if (exp->X_op == O_absent || exp->X_op == O_big)
3543 /* Missing or bad expr becomes absolute 0. */
3544 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3546 exp->X_op = O_constant;
3547 exp->X_add_number = 0;
3548 exp->X_add_symbol = (symbolS *) 0;
3549 exp->X_op_symbol = (symbolS *) 0;
3551 else if (exp->X_op == O_constant)
3553 /* Size it properly later. */
3554 i.types[this_operand] |= Imm64;
3555 /* If BFD64, sign extend val. */
3556 if (!use_rela_relocations)
3557 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3558 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3560 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3562 #ifdef BFD_ASSEMBLER
3563 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3565 && exp_seg != text_section
3566 && exp_seg != data_section
3567 && exp_seg != bss_section
3568 && exp_seg != undefined_section
3569 #ifdef BFD_ASSEMBLER
3570 && !bfd_is_com_section (exp_seg)
3574 #ifdef BFD_ASSEMBLER
3575 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3577 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3584 /* This is an address. The size of the address will be
3585 determined later, depending on destination register,
3586 suffix, or the default for the section. */
3587 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3593 static char *i386_scale PARAMS ((char *));
3600 char *save = input_line_pointer;
3602 input_line_pointer = scale;
3603 val = get_absolute_expression ();
3609 i.log2_scale_factor = 0;
3612 i.log2_scale_factor = 1;
3615 i.log2_scale_factor = 2;
3618 i.log2_scale_factor = 3;
3621 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3623 input_line_pointer = save;
3626 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3628 as_warn (_("scale factor of %d without an index register"),
3629 1 << i.log2_scale_factor);
3630 #if SCALE1_WHEN_NO_INDEX
3631 i.log2_scale_factor = 0;
3634 scale = input_line_pointer;
3635 input_line_pointer = save;
3639 static int i386_displacement PARAMS ((char *, char *));
3642 i386_displacement (disp_start, disp_end)
3648 char *save_input_line_pointer;
3650 char *gotfree_input_line;
3652 int bigdisp = Disp32;
3654 if (flag_code == CODE_64BIT)
3656 if (i.prefix[ADDR_PREFIX] == 0)
3659 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3661 i.types[this_operand] |= bigdisp;
3663 exp = &disp_expressions[i.disp_operands];
3664 i.op[this_operand].disps = exp;
3666 save_input_line_pointer = input_line_pointer;
3667 input_line_pointer = disp_start;
3668 END_STRING_AND_SAVE (disp_end);
3670 #ifndef GCC_ASM_O_HACK
3671 #define GCC_ASM_O_HACK 0
3674 END_STRING_AND_SAVE (disp_end + 1);
3675 if ((i.types[this_operand] & BaseIndex) != 0
3676 && displacement_string_end[-1] == '+')
3678 /* This hack is to avoid a warning when using the "o"
3679 constraint within gcc asm statements.
3682 #define _set_tssldt_desc(n,addr,limit,type) \
3683 __asm__ __volatile__ ( \
3685 "movw %w1,2+%0\n\t" \
3687 "movb %b1,4+%0\n\t" \
3688 "movb %4,5+%0\n\t" \
3689 "movb $0,6+%0\n\t" \
3690 "movb %h1,7+%0\n\t" \
3692 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3694 This works great except that the output assembler ends
3695 up looking a bit weird if it turns out that there is
3696 no offset. You end up producing code that looks like:
3709 So here we provide the missing zero. */
3711 *displacement_string_end = '0';
3715 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3716 if (gotfree_input_line)
3717 input_line_pointer = gotfree_input_line;
3720 exp_seg = expression (exp);
3723 if (*input_line_pointer)
3724 as_bad (_("junk `%s' after expression"), input_line_pointer);
3726 RESTORE_END_STRING (disp_end + 1);
3728 RESTORE_END_STRING (disp_end);
3729 input_line_pointer = save_input_line_pointer;
3731 if (gotfree_input_line)
3732 free (gotfree_input_line);
3735 #ifdef BFD_ASSEMBLER
3736 /* We do this to make sure that the section symbol is in
3737 the symbol table. We will ultimately change the relocation
3738 to be relative to the beginning of the section. */
3739 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3740 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3742 if (exp->X_op != O_symbol)
3744 as_bad (_("bad expression used with @%s"),
3745 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3751 if (S_IS_LOCAL (exp->X_add_symbol)
3752 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3753 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3754 exp->X_op = O_subtract;
3755 exp->X_op_symbol = GOT_symbol;
3756 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3757 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3759 i.reloc[this_operand] = BFD_RELOC_32;
3763 if (exp->X_op == O_absent || exp->X_op == O_big)
3765 /* Missing or bad expr becomes absolute 0. */
3766 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3768 exp->X_op = O_constant;
3769 exp->X_add_number = 0;
3770 exp->X_add_symbol = (symbolS *) 0;
3771 exp->X_op_symbol = (symbolS *) 0;
3774 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3775 if (exp->X_op != O_constant
3776 #ifdef BFD_ASSEMBLER
3777 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3779 && exp_seg != text_section
3780 && exp_seg != data_section
3781 && exp_seg != bss_section
3782 && exp_seg != undefined_section)
3784 #ifdef BFD_ASSEMBLER
3785 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3787 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3792 else if (flag_code == CODE_64BIT)
3793 i.types[this_operand] |= Disp32S | Disp32;
3797 static int i386_index_check PARAMS ((const char *));
3799 /* Make sure the memory operand we've been dealt is valid.
3800 Return 1 on success, 0 on a failure. */
3803 i386_index_check (operand_string)
3804 const char *operand_string;
3807 #if INFER_ADDR_PREFIX
3813 if (flag_code == CODE_64BIT)
3815 if (i.prefix[ADDR_PREFIX] == 0)
3819 && ((i.base_reg->reg_type & Reg64) == 0)
3820 && (i.base_reg->reg_type != BaseIndex
3823 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3824 != (Reg64 | BaseIndex))))
3831 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3833 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3834 != (Reg32 | BaseIndex))))
3840 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3844 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3845 != (Reg16 | BaseIndex)))
3847 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3848 != (Reg16 | BaseIndex))
3850 && i.base_reg->reg_num < 6
3851 && i.index_reg->reg_num >= 6
3852 && i.log2_scale_factor == 0))))
3859 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3861 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3862 != (Reg32 | BaseIndex))))
3868 #if INFER_ADDR_PREFIX
3869 if (flag_code != CODE_64BIT
3870 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3872 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3874 /* Change the size of any displacement too. At most one of
3875 Disp16 or Disp32 is set.
3876 FIXME. There doesn't seem to be any real need for separate
3877 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3878 Removing them would probably clean up the code quite a lot. */
3879 if (i.types[this_operand] & (Disp16 | Disp32))
3880 i.types[this_operand] ^= (Disp16 | Disp32);
3885 as_bad (_("`%s' is not a valid base/index expression"),
3889 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3891 flag_code_names[flag_code]);
3897 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3901 i386_operand (operand_string)
3902 char *operand_string;
3906 char *op_string = operand_string;
3908 if (is_space_char (*op_string))
3911 /* We check for an absolute prefix (differentiating,
3912 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3913 if (*op_string == ABSOLUTE_PREFIX)
3916 if (is_space_char (*op_string))
3918 i.types[this_operand] |= JumpAbsolute;
3921 /* Check if operand is a register. */
3922 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3923 && (r = parse_register (op_string, &end_op)) != NULL)
3925 /* Check for a segment override by searching for ':' after a
3926 segment register. */
3928 if (is_space_char (*op_string))
3930 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3935 i.seg[i.mem_operands] = &es;
3938 i.seg[i.mem_operands] = &cs;
3941 i.seg[i.mem_operands] = &ss;
3944 i.seg[i.mem_operands] = &ds;
3947 i.seg[i.mem_operands] = &fs;
3950 i.seg[i.mem_operands] = &gs;
3954 /* Skip the ':' and whitespace. */
3956 if (is_space_char (*op_string))
3959 if (!is_digit_char (*op_string)
3960 && !is_identifier_char (*op_string)
3961 && *op_string != '('
3962 && *op_string != ABSOLUTE_PREFIX)
3964 as_bad (_("bad memory operand `%s'"), op_string);
3967 /* Handle case of %es:*foo. */
3968 if (*op_string == ABSOLUTE_PREFIX)
3971 if (is_space_char (*op_string))
3973 i.types[this_operand] |= JumpAbsolute;
3975 goto do_memory_reference;
3979 as_bad (_("junk `%s' after register"), op_string);
3982 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3983 i.op[this_operand].regs = r;
3986 else if (*op_string == REGISTER_PREFIX)
3988 as_bad (_("bad register name `%s'"), op_string);
3991 else if (*op_string == IMMEDIATE_PREFIX)
3994 if (i.types[this_operand] & JumpAbsolute)
3996 as_bad (_("immediate operand illegal with absolute jump"));
3999 if (!i386_immediate (op_string))
4002 else if (is_digit_char (*op_string)
4003 || is_identifier_char (*op_string)
4004 || *op_string == '(')
4006 /* This is a memory reference of some sort. */
4009 /* Start and end of displacement string expression (if found). */
4010 char *displacement_string_start;
4011 char *displacement_string_end;
4013 do_memory_reference:
4014 if ((i.mem_operands == 1
4015 && (current_templates->start->opcode_modifier & IsString) == 0)
4016 || i.mem_operands == 2)
4018 as_bad (_("too many memory references for `%s'"),
4019 current_templates->start->name);
4023 /* Check for base index form. We detect the base index form by
4024 looking for an ')' at the end of the operand, searching
4025 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4027 base_string = op_string + strlen (op_string);
4030 if (is_space_char (*base_string))
4033 /* If we only have a displacement, set-up for it to be parsed later. */
4034 displacement_string_start = op_string;
4035 displacement_string_end = base_string + 1;
4037 if (*base_string == ')')
4040 unsigned int parens_balanced = 1;
4041 /* We've already checked that the number of left & right ()'s are
4042 equal, so this loop will not be infinite. */
4046 if (*base_string == ')')
4048 if (*base_string == '(')
4051 while (parens_balanced);
4053 temp_string = base_string;
4055 /* Skip past '(' and whitespace. */
4057 if (is_space_char (*base_string))
4060 if (*base_string == ','
4061 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4062 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4064 displacement_string_end = temp_string;
4066 i.types[this_operand] |= BaseIndex;
4070 base_string = end_op;
4071 if (is_space_char (*base_string))
4075 /* There may be an index reg or scale factor here. */
4076 if (*base_string == ',')
4079 if (is_space_char (*base_string))
4082 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4083 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4085 base_string = end_op;
4086 if (is_space_char (*base_string))
4088 if (*base_string == ',')
4091 if (is_space_char (*base_string))
4094 else if (*base_string != ')')
4096 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4101 else if (*base_string == REGISTER_PREFIX)
4103 as_bad (_("bad register name `%s'"), base_string);
4107 /* Check for scale factor. */
4108 if (*base_string != ')')
4110 char *end_scale = i386_scale (base_string);
4115 base_string = end_scale;
4116 if (is_space_char (*base_string))
4118 if (*base_string != ')')
4120 as_bad (_("expecting `)' after scale factor in `%s'"),
4125 else if (!i.index_reg)
4127 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4132 else if (*base_string != ')')
4134 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4139 else if (*base_string == REGISTER_PREFIX)
4141 as_bad (_("bad register name `%s'"), base_string);
4146 /* If there's an expression beginning the operand, parse it,
4147 assuming displacement_string_start and
4148 displacement_string_end are meaningful. */
4149 if (displacement_string_start != displacement_string_end)
4151 if (!i386_displacement (displacement_string_start,
4152 displacement_string_end))
4156 /* Special case for (%dx) while doing input/output op. */
4158 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4160 && i.log2_scale_factor == 0
4161 && i.seg[i.mem_operands] == 0
4162 && (i.types[this_operand] & Disp) == 0)
4164 i.types[this_operand] = InOutPortReg;
4168 if (i386_index_check (operand_string) == 0)
4174 /* It's not a memory operand; argh! */
4175 as_bad (_("invalid char %s beginning operand %d `%s'"),
4176 output_invalid (*op_string),
4181 return 1; /* Normal return. */
4184 /* md_estimate_size_before_relax()
4186 Called just before relax() for rs_machine_dependent frags. The x86
4187 assembler uses these frags to handle variable size jump
4190 Any symbol that is now undefined will not become defined.
4191 Return the correct fr_subtype in the frag.
4192 Return the initial "guess for variable size of frag" to caller.
4193 The guess is actually the growth beyond the fixed part. Whatever
4194 we do to grow the fixed or variable part contributes to our
4198 md_estimate_size_before_relax (fragP, segment)
4202 /* We've already got fragP->fr_subtype right; all we have to do is
4203 check for un-relaxable symbols. On an ELF system, we can't relax
4204 an externally visible symbol, because it may be overridden by a
4206 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4207 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4208 || S_IS_EXTERNAL (fragP->fr_symbol)
4209 || S_IS_WEAK (fragP->fr_symbol)
4213 /* Symbol is undefined in this segment, or we need to keep a
4214 reloc so that weak symbols can be overridden. */
4215 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4216 RELOC_ENUM reloc_type;
4217 unsigned char *opcode;
4220 if (fragP->fr_var != NO_RELOC)
4221 reloc_type = fragP->fr_var;
4223 reloc_type = BFD_RELOC_16_PCREL;
4225 reloc_type = BFD_RELOC_32_PCREL;
4227 old_fr_fix = fragP->fr_fix;
4228 opcode = (unsigned char *) fragP->fr_opcode;
4230 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4233 /* Make jmp (0xeb) a (d)word displacement jump. */
4235 fragP->fr_fix += size;
4236 fix_new (fragP, old_fr_fix, size,
4238 fragP->fr_offset, 1,
4244 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4246 /* Negate the condition, and branch past an
4247 unconditional jump. */
4250 /* Insert an unconditional jump. */
4252 /* We added two extra opcode bytes, and have a two byte
4254 fragP->fr_fix += 2 + 2;
4255 fix_new (fragP, old_fr_fix + 2, 2,
4257 fragP->fr_offset, 1,
4264 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4267 fix_new (fragP, old_fr_fix, 1,
4269 fragP->fr_offset, 1,
4274 /* This changes the byte-displacement jump 0x7N
4275 to the (d)word-displacement jump 0x0f,0x8N. */
4276 opcode[1] = opcode[0] + 0x10;
4277 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4278 /* We've added an opcode byte. */
4279 fragP->fr_fix += 1 + size;
4280 fix_new (fragP, old_fr_fix + 1, size,
4282 fragP->fr_offset, 1,
4287 BAD_CASE (fragP->fr_subtype);
4291 return fragP->fr_fix - old_fr_fix;
4294 /* Guess size depending on current relax state. Initially the relax
4295 state will correspond to a short jump and we return 1, because
4296 the variable part of the frag (the branch offset) is one byte
4297 long. However, we can relax a section more than once and in that
4298 case we must either set fr_subtype back to the unrelaxed state,
4299 or return the value for the appropriate branch. */
4300 return md_relax_table[fragP->fr_subtype].rlx_length;
4303 /* Called after relax() is finished.
4305 In: Address of frag.
4306 fr_type == rs_machine_dependent.
4307 fr_subtype is what the address relaxed to.
4309 Out: Any fixSs and constants are set up.
4310 Caller will turn frag into a ".space 0". */
4312 #ifndef BFD_ASSEMBLER
4314 md_convert_frag (headers, sec, fragP)
4315 object_headers *headers ATTRIBUTE_UNUSED;
4316 segT sec ATTRIBUTE_UNUSED;
4320 md_convert_frag (abfd, sec, fragP)
4321 bfd *abfd ATTRIBUTE_UNUSED;
4322 segT sec ATTRIBUTE_UNUSED;
4326 unsigned char *opcode;
4327 unsigned char *where_to_put_displacement = NULL;
4328 offsetT target_address;
4329 offsetT opcode_address;
4330 unsigned int extension = 0;
4331 offsetT displacement_from_opcode_start;
4333 opcode = (unsigned char *) fragP->fr_opcode;
4335 /* Address we want to reach in file space. */
4336 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4338 /* Address opcode resides at in file space. */
4339 opcode_address = fragP->fr_address + fragP->fr_fix;
4341 /* Displacement from opcode start to fill into instruction. */
4342 displacement_from_opcode_start = target_address - opcode_address;
4344 if ((fragP->fr_subtype & BIG) == 0)
4346 /* Don't have to change opcode. */
4347 extension = 1; /* 1 opcode + 1 displacement */
4348 where_to_put_displacement = &opcode[1];
4352 if (no_cond_jump_promotion
4353 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4354 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4356 switch (fragP->fr_subtype)
4358 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4359 extension = 4; /* 1 opcode + 4 displacement */
4361 where_to_put_displacement = &opcode[1];
4364 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4365 extension = 2; /* 1 opcode + 2 displacement */
4367 where_to_put_displacement = &opcode[1];
4370 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4371 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4372 extension = 5; /* 2 opcode + 4 displacement */
4373 opcode[1] = opcode[0] + 0x10;
4374 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4375 where_to_put_displacement = &opcode[2];
4378 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4379 extension = 3; /* 2 opcode + 2 displacement */
4380 opcode[1] = opcode[0] + 0x10;
4381 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4382 where_to_put_displacement = &opcode[2];
4385 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4390 where_to_put_displacement = &opcode[3];
4394 BAD_CASE (fragP->fr_subtype);
4399 /* Now put displacement after opcode. */
4400 md_number_to_chars ((char *) where_to_put_displacement,
4401 (valueT) (displacement_from_opcode_start - extension),
4402 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4403 fragP->fr_fix += extension;
4406 /* Size of byte displacement jmp. */
4407 int md_short_jump_size = 2;
4409 /* Size of dword displacement jmp. */
4410 int md_long_jump_size = 5;
4412 /* Size of relocation record. */
4413 const int md_reloc_size = 8;
4416 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4418 addressT from_addr, to_addr;
4419 fragS *frag ATTRIBUTE_UNUSED;
4420 symbolS *to_symbol ATTRIBUTE_UNUSED;
4424 offset = to_addr - (from_addr + 2);
4425 /* Opcode for byte-disp jump. */
4426 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4427 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4431 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4433 addressT from_addr, to_addr;
4434 fragS *frag ATTRIBUTE_UNUSED;
4435 symbolS *to_symbol ATTRIBUTE_UNUSED;
4439 offset = to_addr - (from_addr + 5);
4440 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4441 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4444 /* Apply a fixup (fixS) to segment data, once it has been determined
4445 by our caller that we have all the info we need to fix it up.
4447 On the 386, immediates, displacements, and data pointers are all in
4448 the same (little-endian) format, so we don't need to care about which
4452 md_apply_fix3 (fixP, valP, seg)
4453 /* The fix we're to put in. */
4455 /* Pointer to the value of the bits. */
4457 /* Segment fix is from. */
4458 segT seg ATTRIBUTE_UNUSED;
4460 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4461 valueT value = * valP;
4463 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4466 switch (fixP->fx_r_type)
4472 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4475 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4478 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4483 /* This is a hack. There should be a better way to handle this.
4484 This covers for the fact that bfd_install_relocation will
4485 subtract the current location (for partial_inplace, PC relative
4486 relocations); see more below. */
4487 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4488 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4489 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4490 && fixP->fx_addsy && !use_rela_relocations)
4493 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4495 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4498 value += fixP->fx_where + fixP->fx_frag->fr_address;
4500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4501 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4503 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4506 || (symbol_section_p (fixP->fx_addsy)
4507 && fseg != absolute_section))
4508 && !S_IS_EXTERNAL (fixP->fx_addsy)
4509 && !S_IS_WEAK (fixP->fx_addsy)
4510 && S_IS_DEFINED (fixP->fx_addsy)
4511 && !S_IS_COMMON (fixP->fx_addsy))
4513 /* Yes, we add the values in twice. This is because
4514 bfd_perform_relocation subtracts them out again. I think
4515 bfd_perform_relocation is broken, but I don't dare change
4517 value += fixP->fx_where + fixP->fx_frag->fr_address;
4521 #if defined (OBJ_COFF) && defined (TE_PE)
4522 /* For some reason, the PE format does not store a section
4523 address offset for a PC relative symbol. */
4524 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4525 value += md_pcrel_from (fixP);
4529 /* Fix a few things - the dynamic linker expects certain values here,
4530 and we must not dissappoint it. */
4531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4532 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4534 switch (fixP->fx_r_type)
4536 case BFD_RELOC_386_PLT32:
4537 case BFD_RELOC_X86_64_PLT32:
4538 /* Make the jump instruction point to the address of the operand. At
4539 runtime we merely add the offset to the actual PLT entry. */
4542 case BFD_RELOC_386_GOTPC:
4544 /* This is tough to explain. We end up with this one if we have
4545 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4546 * here is to obtain the absolute address of the GOT, and it is strongly
4547 * preferable from a performance point of view to avoid using a runtime
4548 * relocation for this. The actual sequence of instructions often look
4554 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4556 * The call and pop essentially return the absolute address of
4557 * the label .L66 and store it in %ebx. The linker itself will
4558 * ultimately change the first operand of the addl so that %ebx points to
4559 * the GOT, but to keep things simple, the .o file must have this operand
4560 * set so that it generates not the absolute address of .L66, but the
4561 * absolute address of itself. This allows the linker itself simply
4562 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4563 * added in, and the addend of the relocation is stored in the operand
4564 * field for the instruction itself.
4566 * Our job here is to fix the operand so that it would add the correct
4567 * offset so that %ebx would point to itself. The thing that is tricky is
4568 * that .-.L66 will point to the beginning of the instruction, so we need
4569 * to further modify the operand so that it will point to itself.
4570 * There are other cases where you have something like:
4572 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4574 * and here no correction would be required. Internally in the assembler
4575 * we treat operands of this form as not being pcrel since the '.' is
4576 * explicitly mentioned, and I wonder whether it would simplify matters
4577 * to do it this way. Who knows. In earlier versions of the PIC patches,
4578 * the pcrel_adjust field was used to store the correction, but since the
4579 * expression is not pcrel, I felt it would be confusing to do it this
4584 case BFD_RELOC_386_GOT32:
4585 case BFD_RELOC_X86_64_GOT32:
4586 value = 0; /* Fully resolved at runtime. No addend. */
4588 case BFD_RELOC_386_GOTOFF:
4589 case BFD_RELOC_X86_64_GOTPCREL:
4592 case BFD_RELOC_VTABLE_INHERIT:
4593 case BFD_RELOC_VTABLE_ENTRY:
4600 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4602 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4604 /* Are we finished with this relocation now? */
4605 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4607 #ifdef BFD_ASSEMBLER
4608 else if (use_rela_relocations)
4610 fixP->fx_no_overflow = 1;
4611 /* Remember value for tc_gen_reloc. */
4612 fixP->fx_addnumber = value;
4616 md_number_to_chars (p, value, fixP->fx_size);
4619 #define MAX_LITTLENUMS 6
4621 /* Turn the string pointed to by litP into a floating point constant
4622 of type TYPE, and emit the appropriate bytes. The number of
4623 LITTLENUMS emitted is stored in *SIZEP. An error message is
4624 returned, or NULL on OK. */
4627 md_atof (type, litP, sizeP)
4633 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4634 LITTLENUM_TYPE *wordP;
4656 return _("Bad call to md_atof ()");
4658 t = atof_ieee (input_line_pointer, type, words);
4660 input_line_pointer = t;
4662 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4663 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4664 the bigendian 386. */
4665 for (wordP = words + prec - 1; prec--;)
4667 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4668 litP += sizeof (LITTLENUM_TYPE);
4673 char output_invalid_buf[8];
4680 sprintf (output_invalid_buf, "'%c'", c);
4682 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4683 return output_invalid_buf;
4686 /* REG_STRING starts *before* REGISTER_PREFIX. */
4688 static const reg_entry *
4689 parse_register (reg_string, end_op)
4693 char *s = reg_string;
4695 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4698 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4699 if (*s == REGISTER_PREFIX)
4702 if (is_space_char (*s))
4706 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4708 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4709 return (const reg_entry *) NULL;
4713 /* For naked regs, make sure that we are not dealing with an identifier.
4714 This prevents confusing an identifier like `eax_var' with register
4716 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4717 return (const reg_entry *) NULL;
4721 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4723 /* Handle floating point regs, allowing spaces in the (i) part. */
4724 if (r == i386_regtab /* %st is first entry of table */)
4726 if (is_space_char (*s))
4731 if (is_space_char (*s))
4733 if (*s >= '0' && *s <= '7')
4735 r = &i386_float_regtab[*s - '0'];
4737 if (is_space_char (*s))
4745 /* We have "%st(" then garbage. */
4746 return (const reg_entry *) NULL;
4751 && (r->reg_flags & (RegRex64 | RegRex)) != 0
4752 && flag_code != CODE_64BIT)
4754 return (const reg_entry *) NULL;
4760 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4761 const char *md_shortopts = "kVQ:sq";
4763 const char *md_shortopts = "q";
4766 struct option md_longopts[] = {
4767 #define OPTION_32 (OPTION_MD_BASE + 0)
4768 {"32", no_argument, NULL, OPTION_32},
4769 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4770 #define OPTION_64 (OPTION_MD_BASE + 1)
4771 {"64", no_argument, NULL, OPTION_64},
4773 {NULL, no_argument, NULL, 0}
4775 size_t md_longopts_size = sizeof (md_longopts);
4778 md_parse_option (c, arg)
4780 char *arg ATTRIBUTE_UNUSED;
4788 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4789 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4790 should be emitted or not. FIXME: Not implemented. */
4794 /* -V: SVR4 argument to print version ID. */
4796 print_version_id ();
4799 /* -k: Ignore for FreeBSD compatibility. */
4804 /* -s: On i386 Solaris, this tells the native assembler to use
4805 .stab instead of .stab.excl. We always use .stab anyhow. */
4810 const char **list, **l;
4812 list = bfd_target_list ();
4813 for (l = list; *l != NULL; l++)
4814 if (strcmp (*l, "elf64-x86-64") == 0)
4816 default_arch = "x86_64";
4820 as_fatal (_("No compiled in support for x86_64"));
4827 default_arch = "i386";
4837 md_show_usage (stream)
4840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4841 fprintf (stream, _("\
4843 -V print assembler version number\n\
4845 -q quieten some warnings\n\
4848 fprintf (stream, _("\
4849 -q quieten some warnings\n"));
4853 #ifdef BFD_ASSEMBLER
4854 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4855 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4857 /* Pick the target format to use. */
4860 i386_target_format ()
4862 if (!strcmp (default_arch, "x86_64"))
4863 set_code_flag (CODE_64BIT);
4864 else if (!strcmp (default_arch, "i386"))
4865 set_code_flag (CODE_32BIT);
4867 as_fatal (_("Unknown architecture"));
4868 switch (OUTPUT_FLAVOR)
4870 #ifdef OBJ_MAYBE_AOUT
4871 case bfd_target_aout_flavour:
4872 return AOUT_TARGET_FORMAT;
4874 #ifdef OBJ_MAYBE_COFF
4875 case bfd_target_coff_flavour:
4878 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4879 case bfd_target_elf_flavour:
4881 if (flag_code == CODE_64BIT)
4882 use_rela_relocations = 1;
4883 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
4892 #endif /* OBJ_MAYBE_ more than one */
4894 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4895 void i386_elf_emit_arch_note ()
4897 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4898 && cpu_arch_name != NULL)
4901 asection *seg = now_seg;
4902 subsegT subseg = now_subseg;
4903 Elf_Internal_Note i_note;
4904 Elf_External_Note e_note;
4905 asection *note_secp;
4908 /* Create the .note section. */
4909 note_secp = subseg_new (".note", 0);
4910 bfd_set_section_flags (stdoutput,
4912 SEC_HAS_CONTENTS | SEC_READONLY);
4914 /* Process the arch string. */
4915 len = strlen (cpu_arch_name);
4917 i_note.namesz = len + 1;
4919 i_note.type = NT_ARCH;
4920 p = frag_more (sizeof (e_note.namesz));
4921 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4922 p = frag_more (sizeof (e_note.descsz));
4923 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4924 p = frag_more (sizeof (e_note.type));
4925 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4926 p = frag_more (len + 1);
4927 strcpy (p, cpu_arch_name);
4929 frag_align (2, 0, 0);
4931 subseg_set (seg, subseg);
4935 #endif /* BFD_ASSEMBLER */
4938 md_undefined_symbol (name)
4941 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4942 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4943 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4944 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4948 if (symbol_find (name))
4949 as_bad (_("GOT already in symbol table"));
4950 GOT_symbol = symbol_new (name, undefined_section,
4951 (valueT) 0, &zero_address_frag);
4958 /* Round up a section size to the appropriate boundary. */
4961 md_section_align (segment, size)
4962 segT segment ATTRIBUTE_UNUSED;
4965 #ifdef BFD_ASSEMBLER
4966 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4967 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4969 /* For a.out, force the section size to be aligned. If we don't do
4970 this, BFD will align it for us, but it will not write out the
4971 final bytes of the section. This may be a bug in BFD, but it is
4972 easier to fix it here since that is how the other a.out targets
4976 align = bfd_get_section_alignment (stdoutput, segment);
4977 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4985 /* On the i386, PC-relative offsets are relative to the start of the
4986 next instruction. That is, the address of the offset, plus its
4987 size, since the offset is always the last part of the insn. */
4990 md_pcrel_from (fixP)
4993 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5000 int ignore ATTRIBUTE_UNUSED;
5004 temp = get_absolute_expression ();
5005 subseg_set (bss_section, (subsegT) temp);
5006 demand_empty_rest_of_line ();
5011 #ifdef BFD_ASSEMBLER
5014 i386_validate_fix (fixp)
5017 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5019 /* GOTOFF relocation are nonsense in 64bit mode. */
5020 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5022 if (flag_code != CODE_64BIT)
5024 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5028 if (flag_code == CODE_64BIT)
5030 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5037 tc_gen_reloc (section, fixp)
5038 asection *section ATTRIBUTE_UNUSED;
5042 bfd_reloc_code_real_type code;
5044 switch (fixp->fx_r_type)
5046 case BFD_RELOC_X86_64_PLT32:
5047 case BFD_RELOC_X86_64_GOT32:
5048 case BFD_RELOC_X86_64_GOTPCREL:
5049 case BFD_RELOC_386_PLT32:
5050 case BFD_RELOC_386_GOT32:
5051 case BFD_RELOC_386_GOTOFF:
5052 case BFD_RELOC_386_GOTPC:
5053 case BFD_RELOC_X86_64_32S:
5055 case BFD_RELOC_VTABLE_ENTRY:
5056 case BFD_RELOC_VTABLE_INHERIT:
5057 code = fixp->fx_r_type;
5062 switch (fixp->fx_size)
5065 as_bad_where (fixp->fx_file, fixp->fx_line,
5066 _("can not do %d byte pc-relative relocation"),
5068 code = BFD_RELOC_32_PCREL;
5070 case 1: code = BFD_RELOC_8_PCREL; break;
5071 case 2: code = BFD_RELOC_16_PCREL; break;
5072 case 4: code = BFD_RELOC_32_PCREL; break;
5077 switch (fixp->fx_size)
5080 as_bad_where (fixp->fx_file, fixp->fx_line,
5081 _("can not do %d byte relocation"),
5083 code = BFD_RELOC_32;
5085 case 1: code = BFD_RELOC_8; break;
5086 case 2: code = BFD_RELOC_16; break;
5087 case 4: code = BFD_RELOC_32; break;
5089 case 8: code = BFD_RELOC_64; break;
5096 if (code == BFD_RELOC_32
5098 && fixp->fx_addsy == GOT_symbol)
5100 /* We don't support GOTPC on 64bit targets. */
5101 if (flag_code == CODE_64BIT)
5103 code = BFD_RELOC_386_GOTPC;
5106 rel = (arelent *) xmalloc (sizeof (arelent));
5107 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5108 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5110 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5111 if (!use_rela_relocations)
5113 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5114 vtable entry to be used in the relocation's section offset. */
5115 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5116 rel->address = fixp->fx_offset;
5119 rel->addend = fixp->fx_addnumber;
5123 /* Use the rela in 64bit mode. */
5126 if (!fixp->fx_pcrel)
5127 rel->addend = fixp->fx_offset;
5131 case BFD_RELOC_X86_64_PLT32:
5132 case BFD_RELOC_X86_64_GOT32:
5133 case BFD_RELOC_X86_64_GOTPCREL:
5134 rel->addend = fixp->fx_offset - fixp->fx_size;
5137 rel->addend = (section->vma
5139 + fixp->fx_addnumber
5140 + md_pcrel_from (fixp));
5145 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5146 if (rel->howto == NULL)
5148 as_bad_where (fixp->fx_file, fixp->fx_line,
5149 _("cannot represent relocation type %s"),
5150 bfd_get_reloc_code_name (code));
5151 /* Set howto to a garbage value so that we can keep going. */
5152 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5153 assert (rel->howto != NULL);
5159 #else /* !BFD_ASSEMBLER */
5161 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5163 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5166 relax_addressT segment_address_in_file;
5168 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5169 Out: GNU LD relocation length code: 0, 1, or 2. */
5171 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
5174 know (fixP->fx_addsy != NULL);
5176 md_number_to_chars (where,
5177 (valueT) (fixP->fx_frag->fr_address
5178 + fixP->fx_where - segment_address_in_file),
5181 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5182 ? S_GET_TYPE (fixP->fx_addsy)
5183 : fixP->fx_addsy->sy_number);
5185 where[6] = (r_symbolnum >> 16) & 0x0ff;
5186 where[5] = (r_symbolnum >> 8) & 0x0ff;
5187 where[4] = r_symbolnum & 0x0ff;
5188 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5189 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5190 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5193 #endif /* OBJ_AOUT or OBJ_BOUT. */
5195 #if defined (I386COFF)
5198 tc_coff_fix2rtype (fixP)
5201 if (fixP->fx_r_type == R_IMAGEBASE)
5204 return (fixP->fx_pcrel ?
5205 (fixP->fx_size == 1 ? R_PCRBYTE :
5206 fixP->fx_size == 2 ? R_PCRWORD :
5208 (fixP->fx_size == 1 ? R_RELBYTE :
5209 fixP->fx_size == 2 ? R_RELWORD :
5214 tc_coff_sizemachdep (frag)
5218 return (frag->fr_next->fr_address - frag->fr_address);
5223 #endif /* I386COFF */
5225 #endif /* !BFD_ASSEMBLER */
5227 /* Parse operands using Intel syntax. This implements a recursive descent
5228 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5231 FIXME: We do not recognize the full operand grammar defined in the MASM
5232 documentation. In particular, all the structure/union and
5233 high-level macro operands are missing.
5235 Uppercase words are terminals, lower case words are non-terminals.
5236 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5237 bars '|' denote choices. Most grammar productions are implemented in
5238 functions called 'intel_<production>'.
5240 Initial production is 'expr'.
5246 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5248 constant digits [[ radixOverride ]]
5250 dataType BYTE | WORD | DWORD | QWORD | XWORD
5283 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5284 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5286 hexdigit a | b | c | d | e | f
5287 | A | B | C | D | E | F
5297 register specialRegister
5301 segmentRegister CS | DS | ES | FS | GS | SS
5303 specialRegister CR0 | CR2 | CR3
5304 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5305 | TR3 | TR4 | TR5 | TR6 | TR7
5307 We simplify the grammar in obvious places (e.g., register parsing is
5308 done by calling parse_register) and eliminate immediate left recursion
5309 to implement a recursive-descent parser.
5349 /* Parsing structure for the intel syntax parser. Used to implement the
5350 semantic actions for the operand grammar. */
5351 struct intel_parser_s
5353 char *op_string; /* The string being parsed. */
5354 int got_a_float; /* Whether the operand is a float. */
5355 int op_modifier; /* Operand modifier. */
5356 int is_mem; /* 1 if operand is memory reference. */
5357 const reg_entry *reg; /* Last register reference found. */
5358 char *disp; /* Displacement string being built. */
5361 static struct intel_parser_s intel_parser;
5363 /* Token structure for parsing intel syntax. */
5366 int code; /* Token code. */
5367 const reg_entry *reg; /* Register entry for register tokens. */
5368 char *str; /* String representation. */
5371 static struct intel_token cur_token, prev_token;
5373 /* Token codes for the intel parser. Since T_SHORT is already used
5374 by COFF, undefine it first to prevent a warning. */
5389 /* Prototypes for intel parser functions. */
5390 static int intel_match_token PARAMS ((int code));
5391 static void intel_get_token PARAMS ((void));
5392 static void intel_putback_token PARAMS ((void));
5393 static int intel_expr PARAMS ((void));
5394 static int intel_e05 PARAMS ((void));
5395 static int intel_e05_1 PARAMS ((void));
5396 static int intel_e06 PARAMS ((void));
5397 static int intel_e06_1 PARAMS ((void));
5398 static int intel_e09 PARAMS ((void));
5399 static int intel_e09_1 PARAMS ((void));
5400 static int intel_e10 PARAMS ((void));
5401 static int intel_e10_1 PARAMS ((void));
5402 static int intel_e11 PARAMS ((void));
5405 i386_intel_operand (operand_string, got_a_float)
5406 char *operand_string;
5412 /* Initialize token holders. */
5413 cur_token.code = prev_token.code = T_NIL;
5414 cur_token.reg = prev_token.reg = NULL;
5415 cur_token.str = prev_token.str = NULL;
5417 /* Initialize parser structure. */
5418 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5421 strcpy (intel_parser.op_string, operand_string);
5422 intel_parser.got_a_float = got_a_float;
5423 intel_parser.op_modifier = -1;
5424 intel_parser.is_mem = 0;
5425 intel_parser.reg = NULL;
5426 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5427 if (intel_parser.disp == NULL)
5429 intel_parser.disp[0] = '\0';
5431 /* Read the first token and start the parser. */
5433 ret = intel_expr ();
5437 /* If we found a memory reference, hand it over to i386_displacement
5438 to fill in the rest of the operand fields. */
5439 if (intel_parser.is_mem)
5441 if ((i.mem_operands == 1
5442 && (current_templates->start->opcode_modifier & IsString) == 0)
5443 || i.mem_operands == 2)
5445 as_bad (_("too many memory references for '%s'"),
5446 current_templates->start->name);
5451 char *s = intel_parser.disp;
5454 /* Add the displacement expression. */
5456 ret = i386_displacement (s, s + strlen (s))
5457 && i386_index_check (s);
5461 /* Constant and OFFSET expressions are handled by i386_immediate. */
5462 else if (intel_parser.op_modifier == OFFSET_FLAT
5463 || intel_parser.reg == NULL)
5464 ret = i386_immediate (intel_parser.disp);
5468 free (intel_parser.disp);
5478 /* expr SHORT e05 */
5479 if (cur_token.code == T_SHORT)
5481 intel_parser.op_modifier = SHORT;
5482 intel_match_token (T_SHORT);
5484 return (intel_e05 ());
5489 return intel_e05 ();
5499 return (intel_e06 () && intel_e05_1 ());
5505 /* e05' addOp e06 e05' */
5506 if (cur_token.code == '+' || cur_token.code == '-')
5508 strcat (intel_parser.disp, cur_token.str);
5509 intel_match_token (cur_token.code);
5511 return (intel_e06 () && intel_e05_1 ());
5526 return (intel_e09 () && intel_e06_1 ());
5532 /* e06' mulOp e09 e06' */
5533 if (cur_token.code == '*' || cur_token.code == '/')
5535 strcat (intel_parser.disp, cur_token.str);
5536 intel_match_token (cur_token.code);
5538 return (intel_e09 () && intel_e06_1 ());
5546 /* e09 OFFSET e10 e09'
5555 /* e09 OFFSET e10 e09' */
5556 if (cur_token.code == T_OFFSET)
5558 intel_parser.is_mem = 0;
5559 intel_parser.op_modifier = OFFSET_FLAT;
5560 intel_match_token (T_OFFSET);
5562 return (intel_e10 () && intel_e09_1 ());
5567 return (intel_e10 () && intel_e09_1 ());
5573 /* e09' PTR e10 e09' */
5574 if (cur_token.code == T_PTR)
5576 if (prev_token.code == T_BYTE)
5577 i.suffix = BYTE_MNEM_SUFFIX;
5579 else if (prev_token.code == T_WORD)
5581 if (intel_parser.got_a_float == 2) /* "fi..." */
5582 i.suffix = SHORT_MNEM_SUFFIX;
5584 i.suffix = WORD_MNEM_SUFFIX;
5587 else if (prev_token.code == T_DWORD)
5589 if (intel_parser.got_a_float == 1) /* "f..." */
5590 i.suffix = SHORT_MNEM_SUFFIX;
5592 i.suffix = LONG_MNEM_SUFFIX;
5595 else if (prev_token.code == T_QWORD)
5597 if (intel_parser.got_a_float == 1) /* "f..." */
5598 i.suffix = LONG_MNEM_SUFFIX;
5600 i.suffix = QWORD_MNEM_SUFFIX;
5603 else if (prev_token.code == T_XWORD)
5604 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5608 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5612 intel_match_token (T_PTR);
5614 return (intel_e10 () && intel_e09_1 ());
5617 /* e09 : e10 e09' */
5618 else if (cur_token.code == ':')
5620 /* Mark as a memory operand only if it's not already known to be an
5621 offset expression. */
5622 if (intel_parser.op_modifier != OFFSET_FLAT)
5623 intel_parser.is_mem = 1;
5625 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5640 return (intel_e11 () && intel_e10_1 ());
5646 /* e10' [ expr ] e10' */
5647 if (cur_token.code == '[')
5649 intel_match_token ('[');
5651 /* Mark as a memory operand only if it's not already known to be an
5652 offset expression. If it's an offset expression, we need to keep
5654 if (intel_parser.op_modifier != OFFSET_FLAT)
5655 intel_parser.is_mem = 1;
5657 strcat (intel_parser.disp, "[");
5659 /* Add a '+' to the displacement string if necessary. */
5660 if (*intel_parser.disp != '\0'
5661 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5662 strcat (intel_parser.disp, "+");
5664 if (intel_expr () && intel_match_token (']'))
5666 /* Preserve brackets when the operand is an offset expression. */
5667 if (intel_parser.op_modifier == OFFSET_FLAT)
5668 strcat (intel_parser.disp, "]");
5670 return intel_e10_1 ();
5697 if (cur_token.code == '(')
5699 intel_match_token ('(');
5700 strcat (intel_parser.disp, "(");
5702 if (intel_expr () && intel_match_token (')'))
5704 strcat (intel_parser.disp, ")");
5712 else if (cur_token.code == '[')
5714 intel_match_token ('[');
5716 /* Mark as a memory operand only if it's not already known to be an
5717 offset expression. If it's an offset expression, we need to keep
5719 if (intel_parser.op_modifier != OFFSET_FLAT)
5720 intel_parser.is_mem = 1;
5722 strcat (intel_parser.disp, "[");
5724 /* Operands for jump/call inside brackets denote absolute addresses. */
5725 if (current_templates->start->opcode_modifier & Jump
5726 || current_templates->start->opcode_modifier & JumpDword
5727 || current_templates->start->opcode_modifier & JumpByte
5728 || current_templates->start->opcode_modifier & JumpInterSegment)
5729 i.types[this_operand] |= JumpAbsolute;
5731 /* Add a '+' to the displacement string if necessary. */
5732 if (*intel_parser.disp != '\0'
5733 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5734 strcat (intel_parser.disp, "+");
5736 if (intel_expr () && intel_match_token (']'))
5738 /* Preserve brackets when the operand is an offset expression. */
5739 if (intel_parser.op_modifier == OFFSET_FLAT)
5740 strcat (intel_parser.disp, "]");
5753 else if (cur_token.code == T_BYTE
5754 || cur_token.code == T_WORD
5755 || cur_token.code == T_DWORD
5756 || cur_token.code == T_QWORD
5757 || cur_token.code == T_XWORD)
5759 intel_match_token (cur_token.code);
5766 else if (cur_token.code == '$' || cur_token.code == '.')
5768 strcat (intel_parser.disp, cur_token.str);
5769 intel_match_token (cur_token.code);
5771 /* Mark as a memory operand only if it's not already known to be an
5772 offset expression. */
5773 if (intel_parser.op_modifier != OFFSET_FLAT)
5774 intel_parser.is_mem = 1;
5780 else if (cur_token.code == T_REG)
5782 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5784 intel_match_token (T_REG);
5786 /* Check for segment change. */
5787 if (cur_token.code == ':')
5789 if (reg->reg_type & (SReg2 | SReg3))
5791 switch (reg->reg_num)
5794 i.seg[i.mem_operands] = &es;
5797 i.seg[i.mem_operands] = &cs;
5800 i.seg[i.mem_operands] = &ss;
5803 i.seg[i.mem_operands] = &ds;
5806 i.seg[i.mem_operands] = &fs;
5809 i.seg[i.mem_operands] = &gs;
5815 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5820 /* Not a segment register. Check for register scaling. */
5821 else if (cur_token.code == '*')
5823 if (!intel_parser.is_mem)
5825 as_bad (_("Register scaling only allowed in memory operands."));
5829 /* What follows must be a valid scale. */
5830 if (intel_match_token ('*')
5831 && strchr ("01248", *cur_token.str))
5834 i.types[this_operand] |= BaseIndex;
5836 /* Set the scale after setting the register (otherwise,
5837 i386_scale will complain) */
5838 i386_scale (cur_token.str);
5839 intel_match_token (T_CONST);
5843 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5849 /* No scaling. If this is a memory operand, the register is either a
5850 base register (first occurrence) or an index register (second
5852 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5854 if (i.base_reg && i.index_reg)
5856 as_bad (_("Too many register references in memory operand.\n"));
5860 if (i.base_reg == NULL)
5865 i.types[this_operand] |= BaseIndex;
5868 /* Offset modifier. Add the register to the displacement string to be
5869 parsed as an immediate expression after we're done. */
5870 else if (intel_parser.op_modifier == OFFSET_FLAT)
5871 strcat (intel_parser.disp, reg->reg_name);
5873 /* It's neither base nor index nor offset. */
5876 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5877 i.op[this_operand].regs = reg;
5881 /* Since registers are not part of the displacement string (except
5882 when we're parsing offset operands), we may need to remove any
5883 preceding '+' from the displacement string. */
5884 if (*intel_parser.disp != '\0'
5885 && intel_parser.op_modifier != OFFSET_FLAT)
5887 char *s = intel_parser.disp;
5888 s += strlen (s) - 1;
5897 else if (cur_token.code == T_ID)
5899 /* Add the identifier to the displacement string. */
5900 strcat (intel_parser.disp, cur_token.str);
5901 intel_match_token (T_ID);
5903 /* The identifier represents a memory reference only if it's not
5904 preceded by an offset modifier. */
5905 if (intel_parser.op_modifier != OFFSET_FLAT)
5906 intel_parser.is_mem = 1;
5912 else if (cur_token.code == T_CONST
5913 || cur_token.code == '-'
5914 || cur_token.code == '+')
5918 /* Allow constants that start with `+' or `-'. */
5919 if (cur_token.code == '-' || cur_token.code == '+')
5921 strcat (intel_parser.disp, cur_token.str);
5922 intel_match_token (cur_token.code);
5923 if (cur_token.code != T_CONST)
5925 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5931 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5932 if (save_str == NULL)
5934 strcpy (save_str, cur_token.str);
5936 /* Get the next token to check for register scaling. */
5937 intel_match_token (cur_token.code);
5939 /* Check if this constant is a scaling factor for an index register. */
5940 if (cur_token.code == '*')
5942 if (intel_match_token ('*') && cur_token.code == T_REG)
5944 if (!intel_parser.is_mem)
5946 as_bad (_("Register scaling only allowed in memory operands."));
5950 /* The constant is followed by `* reg', so it must be
5952 if (strchr ("01248", *save_str))
5954 i.index_reg = cur_token.reg;
5955 i.types[this_operand] |= BaseIndex;
5957 /* Set the scale after setting the register (otherwise,
5958 i386_scale will complain) */
5959 i386_scale (save_str);
5960 intel_match_token (T_REG);
5962 /* Since registers are not part of the displacement
5963 string, we may need to remove any preceding '+' from
5964 the displacement string. */
5965 if (*intel_parser.disp != '\0')
5967 char *s = intel_parser.disp;
5968 s += strlen (s) - 1;
5981 /* The constant was not used for register scaling. Since we have
5982 already consumed the token following `*' we now need to put it
5983 back in the stream. */
5985 intel_putback_token ();
5988 /* Add the constant to the displacement string. */
5989 strcat (intel_parser.disp, save_str);
5995 as_bad (_("Unrecognized token '%s'"), cur_token.str);
5999 /* Match the given token against cur_token. If they match, read the next
6000 token from the operand string. */
6002 intel_match_token (code)
6005 if (cur_token.code == code)
6012 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6017 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6022 const reg_entry *reg;
6023 struct intel_token new_token;
6025 new_token.code = T_NIL;
6026 new_token.reg = NULL;
6027 new_token.str = NULL;
6029 /* Free the memory allocated to the previous token and move
6030 cur_token to prev_token. */
6032 free (prev_token.str);
6034 prev_token = cur_token;
6036 /* Skip whitespace. */
6037 while (is_space_char (*intel_parser.op_string))
6038 intel_parser.op_string++;
6040 /* Return an empty token if we find nothing else on the line. */
6041 if (*intel_parser.op_string == '\0')
6043 cur_token = new_token;
6047 /* The new token cannot be larger than the remainder of the operand
6049 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6050 if (new_token.str == NULL)
6052 new_token.str[0] = '\0';
6054 if (strchr ("0123456789", *intel_parser.op_string))
6056 char *p = new_token.str;
6057 char *q = intel_parser.op_string;
6058 new_token.code = T_CONST;
6060 /* Allow any kind of identifier char to encompass floating point and
6061 hexadecimal numbers. */
6062 while (is_identifier_char (*q))
6066 /* Recognize special symbol names [0-9][bf]. */
6067 if (strlen (intel_parser.op_string) == 2
6068 && (intel_parser.op_string[1] == 'b'
6069 || intel_parser.op_string[1] == 'f'))
6070 new_token.code = T_ID;
6073 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6075 new_token.code = *intel_parser.op_string;
6076 new_token.str[0] = *intel_parser.op_string;
6077 new_token.str[1] = '\0';
6080 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6081 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6083 new_token.code = T_REG;
6084 new_token.reg = reg;
6086 if (*intel_parser.op_string == REGISTER_PREFIX)
6088 new_token.str[0] = REGISTER_PREFIX;
6089 new_token.str[1] = '\0';
6092 strcat (new_token.str, reg->reg_name);
6095 else if (is_identifier_char (*intel_parser.op_string))
6097 char *p = new_token.str;
6098 char *q = intel_parser.op_string;
6100 /* A '.' or '$' followed by an identifier char is an identifier.
6101 Otherwise, it's operator '.' followed by an expression. */
6102 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6104 new_token.code = *q;
6105 new_token.str[0] = *q;
6106 new_token.str[1] = '\0';
6110 while (is_identifier_char (*q) || *q == '@')
6114 if (strcasecmp (new_token.str, "BYTE") == 0)
6115 new_token.code = T_BYTE;
6117 else if (strcasecmp (new_token.str, "WORD") == 0)
6118 new_token.code = T_WORD;
6120 else if (strcasecmp (new_token.str, "DWORD") == 0)
6121 new_token.code = T_DWORD;
6123 else if (strcasecmp (new_token.str, "QWORD") == 0)
6124 new_token.code = T_QWORD;
6126 else if (strcasecmp (new_token.str, "XWORD") == 0)
6127 new_token.code = T_XWORD;
6129 else if (strcasecmp (new_token.str, "PTR") == 0)
6130 new_token.code = T_PTR;
6132 else if (strcasecmp (new_token.str, "SHORT") == 0)
6133 new_token.code = T_SHORT;
6135 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6137 new_token.code = T_OFFSET;
6139 /* ??? This is not mentioned in the MASM grammar but gcc
6140 makes use of it with -mintel-syntax. OFFSET may be
6141 followed by FLAT: */
6142 if (strncasecmp (q, " FLAT:", 6) == 0)
6143 strcat (new_token.str, " FLAT:");
6146 /* ??? This is not mentioned in the MASM grammar. */
6147 else if (strcasecmp (new_token.str, "FLAT") == 0)
6148 new_token.code = T_OFFSET;
6151 new_token.code = T_ID;
6156 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6158 intel_parser.op_string += strlen (new_token.str);
6159 cur_token = new_token;
6162 /* Put cur_token back into the token stream and make cur_token point to
6165 intel_putback_token ()
6167 intel_parser.op_string -= strlen (cur_token.str);
6168 free (cur_token.str);
6169 cur_token = prev_token;
6171 /* Forget prev_token. */
6172 prev_token.code = T_NIL;
6173 prev_token.reg = NULL;
6174 prev_token.str = NULL;