2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
30 #include <linux/module.h>
31 #include <machine/clock.h>
33 #define FORCEWAKE_ACK_TIMEOUT_MS 2
35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
46 static bool intel_crtc_active(struct drm_crtc *crtc)
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
54 static void i8xx_disable_fbc(struct drm_device *dev)
56 struct drm_i915_private *dev_priv = dev->dev_private;
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
73 DRM_DEBUG_KMS("disabled FBC\n");
76 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
86 u32 fbc_ctl, fbc_ctl2;
88 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
116 cfb_pitch, crtc->y, intel_crtc->plane);
119 static bool i8xx_fbc_enabled(struct drm_device *dev)
121 struct drm_i915_private *dev_priv = dev->dev_private;
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
153 static void g4x_disable_fbc(struct drm_device *dev)
155 struct drm_i915_private *dev_priv = dev->dev_private;
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164 DRM_DEBUG_KMS("disabled FBC\n");
168 static bool g4x_fbc_enabled(struct drm_device *dev)
170 struct drm_i915_private *dev_priv = dev->dev_private;
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
175 static void sandybridge_blit_fbc_update(struct drm_device *dev)
177 struct drm_i915_private *dev_priv = dev->dev_private;
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
195 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
219 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
230 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
233 static void ironlake_disable_fbc(struct drm_device *dev)
235 struct drm_i915_private *dev_priv = dev->dev_private;
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244 DRM_DEBUG_KMS("disabled FBC\n");
248 static bool ironlake_fbc_enabled(struct drm_device *dev)
250 struct drm_i915_private *dev_priv = dev->dev_private;
252 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
255 bool intel_fbc_enabled(struct drm_device *dev)
257 struct drm_i915_private *dev_priv = dev->dev_private;
259 if (!dev_priv->display.fbc_enabled)
262 return dev_priv->display.fbc_enabled(dev);
265 static void intel_fbc_work_fn(struct work_struct *__work)
267 struct intel_fbc_work *work =
268 container_of(to_delayed_work(__work),
269 struct intel_fbc_work, work);
270 struct drm_device *dev = work->crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
273 mutex_lock(&dev->struct_mutex);
274 if (work == dev_priv->fbc_work) {
275 /* Double check that we haven't switched fb without cancelling
278 if (work->crtc->fb == work->fb) {
279 dev_priv->display.enable_fbc(work->crtc,
282 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
283 dev_priv->cfb_fb = work->crtc->fb->base.id;
284 dev_priv->cfb_y = work->crtc->y;
287 dev_priv->fbc_work = NULL;
289 mutex_unlock(&dev->struct_mutex);
294 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
296 if (dev_priv->fbc_work == NULL)
299 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
301 /* Synchronisation is provided by struct_mutex and checking of
302 * dev_priv->fbc_work, so we can perform the cancellation
303 * entirely asynchronously.
305 if (cancel_delayed_work(&dev_priv->fbc_work->work))
306 /* tasklet was killed before being run, clean up */
307 kfree(dev_priv->fbc_work, M_DRM);
309 /* Mark the work as no longer wanted so that if it does
310 * wake-up (because the work was already running and waiting
311 * for our mutex), it will discover that is no longer
314 dev_priv->fbc_work = NULL;
317 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
319 struct intel_fbc_work *work;
320 struct drm_device *dev = crtc->dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
323 if (!dev_priv->display.enable_fbc)
326 intel_cancel_fbc_work(dev_priv);
328 work = kmalloc(sizeof(*work), M_DRM, M_WAITOK | M_ZERO);
330 dev_priv->display.enable_fbc(crtc, interval);
336 work->interval = interval;
337 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
339 dev_priv->fbc_work = work;
341 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
343 /* Delay the actual enabling to let pageflipping cease and the
344 * display to settle before starting the compression. Note that
345 * this delay also serves a second purpose: it allows for a
346 * vblank to pass after disabling the FBC before we attempt
347 * to modify the control registers.
349 * A more complicated solution would involve tracking vblanks
350 * following the termination of the page-flipping sequence
351 * and indeed performing the enable as a co-routine and not
352 * waiting synchronously upon the vblank.
354 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
357 void intel_disable_fbc(struct drm_device *dev)
359 struct drm_i915_private *dev_priv = dev->dev_private;
361 intel_cancel_fbc_work(dev_priv);
363 if (!dev_priv->display.disable_fbc)
366 dev_priv->display.disable_fbc(dev);
367 dev_priv->cfb_plane = -1;
371 * intel_update_fbc - enable/disable FBC as needed
372 * @dev: the drm_device
374 * Set up the framebuffer compression hardware at mode set time. We
375 * enable it if possible:
376 * - plane A only (on pre-965)
377 * - no pixel mulitply/line duplication
378 * - no alpha buffer discard
380 * - framebuffer <= 2048 in width, 1536 in height
382 * We can't assume that any compression will take place (worst case),
383 * so the compressed buffer has to be the same size as the uncompressed
384 * one. It also must reside (along with the line length buffer) in
387 * We need to enable/disable FBC on a global basis.
389 void intel_update_fbc(struct drm_device *dev)
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 struct drm_crtc *crtc = NULL, *tmp_crtc;
393 struct intel_crtc *intel_crtc;
394 struct drm_framebuffer *fb;
395 struct intel_framebuffer *intel_fb;
396 struct drm_i915_gem_object *obj;
402 if (!I915_HAS_FBC(dev))
406 * If FBC is already on, we just have to verify that we can
407 * keep it that way...
408 * Need to disable if:
409 * - more than one pipe is active
410 * - changing FBC params (stride, fence, mode)
411 * - new fb is too large to fit in compressed buffer
412 * - going to an unsupported config (interlace, pixel multiply, etc.)
414 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
415 if (intel_crtc_active(tmp_crtc) &&
416 !to_intel_crtc(tmp_crtc)->primary_disabled) {
418 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
419 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
426 if (!crtc || crtc->fb == NULL) {
427 DRM_DEBUG_KMS("no output, disabling\n");
428 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
432 intel_crtc = to_intel_crtc(crtc);
434 intel_fb = to_intel_framebuffer(fb);
437 enable_fbc = i915_enable_fbc;
438 if (enable_fbc < 0) {
439 DRM_DEBUG_KMS("fbc set to per-chip default\n");
441 if (INTEL_INFO(dev)->gen <= 6)
445 DRM_DEBUG_KMS("fbc disabled per module param\n");
446 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
479 /* If the kernel debugger is active, always disable compression */
484 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
485 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
486 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
487 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
488 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
492 /* If the scanout has not changed, don't modify the FBC settings.
493 * Note that we make the fundamental assumption that the fb->obj
494 * cannot be unpinned (and have its GTT offset and fence revoked)
495 * without first being decoupled from the scanout and FBC disabled.
497 if (dev_priv->cfb_plane == intel_crtc->plane &&
498 dev_priv->cfb_fb == fb->base.id &&
499 dev_priv->cfb_y == crtc->y)
502 if (intel_fbc_enabled(dev)) {
503 /* We update FBC along two paths, after changing fb/crtc
504 * configuration (modeswitching) and after page-flipping
505 * finishes. For the latter, we know that not only did
506 * we disable the FBC at the start of the page-flip
507 * sequence, but also more than one vblank has passed.
509 * For the former case of modeswitching, it is possible
510 * to switch between two FBC valid configurations
511 * instantaneously so we do need to disable the FBC
512 * before we can modify its control registers. We also
513 * have to wait for the next vblank for that to take
514 * effect. However, since we delay enabling FBC we can
515 * assume that a vblank has passed since disabling and
516 * that we can safely alter the registers in the deferred
519 * In the scenario that we go from a valid to invalid
520 * and then back to valid FBC configuration we have
521 * no strict enforcement that a vblank occurred since
522 * disabling the FBC. However, along all current pipe
523 * disabling paths we do need to wait for a vblank at
524 * some point. And we wait before enabling FBC anyway.
526 DRM_DEBUG_KMS("disabling active FBC for update\n");
527 intel_disable_fbc(dev);
530 intel_enable_fbc(crtc, 500);
534 /* Multiple disables should be harmless */
535 if (intel_fbc_enabled(dev)) {
536 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
537 intel_disable_fbc(dev);
539 i915_gem_stolen_cleanup_compression(dev);
542 static void i915_pineview_get_mem_freq(struct drm_device *dev)
544 drm_i915_private_t *dev_priv = dev->dev_private;
547 tmp = I915_READ(CLKCFG);
549 switch (tmp & CLKCFG_FSB_MASK) {
551 dev_priv->fsb_freq = 533; /* 133*4 */
554 dev_priv->fsb_freq = 800; /* 200*4 */
557 dev_priv->fsb_freq = 667; /* 167*4 */
560 dev_priv->fsb_freq = 400; /* 100*4 */
564 switch (tmp & CLKCFG_MEM_MASK) {
566 dev_priv->mem_freq = 533;
569 dev_priv->mem_freq = 667;
572 dev_priv->mem_freq = 800;
576 /* detect pineview DDR3 setting */
577 tmp = I915_READ(CSHRDDR3CTL);
578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
581 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
583 drm_i915_private_t *dev_priv = dev->dev_private;
586 ddrpll = I915_READ16(DDRMPLL1);
587 csipll = I915_READ16(CSIPLL0);
589 switch (ddrpll & 0xff) {
591 dev_priv->mem_freq = 800;
594 dev_priv->mem_freq = 1066;
597 dev_priv->mem_freq = 1333;
600 dev_priv->mem_freq = 1600;
603 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
605 dev_priv->mem_freq = 0;
609 dev_priv->ips.r_t = dev_priv->mem_freq;
611 switch (csipll & 0x3ff) {
613 dev_priv->fsb_freq = 3200;
616 dev_priv->fsb_freq = 3733;
619 dev_priv->fsb_freq = 4266;
622 dev_priv->fsb_freq = 4800;
625 dev_priv->fsb_freq = 5333;
628 dev_priv->fsb_freq = 5866;
631 dev_priv->fsb_freq = 6400;
634 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
636 dev_priv->fsb_freq = 0;
640 if (dev_priv->fsb_freq == 3200) {
641 dev_priv->ips.c_m = 0;
642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
643 dev_priv->ips.c_m = 1;
645 dev_priv->ips.c_m = 2;
649 static const struct cxsr_latency cxsr_latency_table[] = {
650 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
651 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
652 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
653 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
654 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
656 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
657 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
658 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
659 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
660 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
662 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
663 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
664 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
665 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
666 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
668 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
669 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
670 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
671 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
672 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
674 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
675 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
676 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
677 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
678 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
680 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
681 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
682 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
683 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
684 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
687 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
692 const struct cxsr_latency *latency;
695 if (fsb == 0 || mem == 0)
698 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
699 latency = &cxsr_latency_table[i];
700 if (is_desktop == latency->is_desktop &&
701 is_ddr3 == latency->is_ddr3 &&
702 fsb == latency->fsb_freq && mem == latency->mem_freq)
706 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
711 static void pineview_disable_cxsr(struct drm_device *dev)
713 struct drm_i915_private *dev_priv = dev->dev_private;
715 /* deactivate cxsr */
716 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
720 * Latency for FIFO fetches is dependent on several factors:
721 * - memory configuration (speed, channels)
723 * - current MCH state
724 * It can be fairly high in some situations, so here we assume a fairly
725 * pessimal value. It's a tradeoff between extra memory fetches (if we
726 * set this value too high, the FIFO will fetch frequently to stay full)
727 * and power consumption (set it too low to save power and we might see
728 * FIFO underruns and display "flicker").
730 * A value of 5us seems to be a good balance; safe for very low end
731 * platforms but not overly aggressive on lower latency configs.
733 static const int latency_ns = 5000;
735 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
737 struct drm_i915_private *dev_priv = dev->dev_private;
738 uint32_t dsparb = I915_READ(DSPARB);
741 size = dsparb & 0x7f;
743 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
745 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
746 plane ? "B" : "A", size);
751 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 uint32_t dsparb = I915_READ(DSPARB);
757 size = dsparb & 0x1ff;
759 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
760 size >>= 1; /* Convert to cachelines */
762 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
763 plane ? "B" : "A", size);
768 static int i845_get_fifo_size(struct drm_device *dev, int plane)
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 uint32_t dsparb = I915_READ(DSPARB);
774 size = dsparb & 0x7f;
775 size >>= 2; /* Convert to cachelines */
777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
784 static int i830_get_fifo_size(struct drm_device *dev, int plane)
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 uint32_t dsparb = I915_READ(DSPARB);
790 size = dsparb & 0x7f;
791 size >>= 1; /* Convert to cachelines */
793 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
794 plane ? "B" : "A", size);
799 /* Pineview has different values for various configs */
800 static const struct intel_watermark_params pineview_display_wm = {
801 PINEVIEW_DISPLAY_FIFO,
805 PINEVIEW_FIFO_LINE_SIZE
807 static const struct intel_watermark_params pineview_display_hplloff_wm = {
808 PINEVIEW_DISPLAY_FIFO,
810 PINEVIEW_DFT_HPLLOFF_WM,
812 PINEVIEW_FIFO_LINE_SIZE
814 static const struct intel_watermark_params pineview_cursor_wm = {
815 PINEVIEW_CURSOR_FIFO,
816 PINEVIEW_CURSOR_MAX_WM,
817 PINEVIEW_CURSOR_DFT_WM,
818 PINEVIEW_CURSOR_GUARD_WM,
819 PINEVIEW_FIFO_LINE_SIZE,
821 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
822 PINEVIEW_CURSOR_FIFO,
823 PINEVIEW_CURSOR_MAX_WM,
824 PINEVIEW_CURSOR_DFT_WM,
825 PINEVIEW_CURSOR_GUARD_WM,
826 PINEVIEW_FIFO_LINE_SIZE
828 static const struct intel_watermark_params g4x_wm_info = {
835 static const struct intel_watermark_params g4x_cursor_wm_info = {
842 static const struct intel_watermark_params valleyview_wm_info = {
843 VALLEYVIEW_FIFO_SIZE,
849 static const struct intel_watermark_params valleyview_cursor_wm_info = {
851 VALLEYVIEW_CURSOR_MAX_WM,
856 static const struct intel_watermark_params i965_cursor_wm_info = {
863 static const struct intel_watermark_params i945_wm_info = {
870 static const struct intel_watermark_params i915_wm_info = {
877 static const struct intel_watermark_params i855_wm_info = {
884 static const struct intel_watermark_params i830_wm_info = {
892 static const struct intel_watermark_params ironlake_display_wm_info = {
899 static const struct intel_watermark_params ironlake_cursor_wm_info = {
906 static const struct intel_watermark_params ironlake_display_srwm_info = {
908 ILK_DISPLAY_MAX_SRWM,
909 ILK_DISPLAY_DFT_SRWM,
913 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
921 static const struct intel_watermark_params sandybridge_display_wm_info = {
928 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
935 static const struct intel_watermark_params sandybridge_display_srwm_info = {
937 SNB_DISPLAY_MAX_SRWM,
938 SNB_DISPLAY_DFT_SRWM,
942 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
952 * intel_calculate_wm - calculate watermark level
953 * @clock_in_khz: pixel clock
954 * @wm: chip FIFO params
955 * @pixel_size: display pixel size
956 * @latency_ns: memory latency for the platform
958 * Calculate the watermark level (the level at which the display plane will
959 * start fetching from memory again). Each chip has a different display
960 * FIFO size and allocation, so the caller needs to figure that out and pass
961 * in the correct intel_watermark_params structure.
963 * As the pixel clock runs, the FIFO will be drained at a rate that depends
964 * on the pixel size. When it reaches the watermark level, it'll start
965 * fetching FIFO line sized based chunks from memory until the FIFO fills
966 * past the watermark point. If the FIFO drains completely, a FIFO underrun
967 * will occur, and a display engine hang could result.
969 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
970 const struct intel_watermark_params *wm,
973 unsigned long latency_ns)
975 long entries_required, wm_size;
978 * Note: we need to make sure we don't overflow for various clock &
980 * clocks go from a few thousand to several hundred thousand.
981 * latency is usually a few thousand
983 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
987 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
989 wm_size = fifo_size - (entries_required + wm->guard_size);
991 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
993 /* Don't promote wm_size to unsigned... */
994 if (wm_size > (long)wm->max_wm)
995 wm_size = wm->max_wm;
997 wm_size = wm->default_wm;
1001 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1003 struct drm_crtc *crtc, *enabled = NULL;
1005 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1006 if (intel_crtc_active(crtc)) {
1016 static void pineview_update_wm(struct drm_device *dev)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 struct drm_crtc *crtc;
1020 const struct cxsr_latency *latency;
1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1025 dev_priv->fsb_freq, dev_priv->mem_freq);
1027 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1028 pineview_disable_cxsr(dev);
1032 crtc = single_enabled_crtc(dev);
1034 int clock = crtc->mode.clock;
1035 int pixel_size = crtc->fb->bits_per_pixel / 8;
1038 wm = intel_calculate_wm(clock, &pineview_display_wm,
1039 pineview_display_wm.fifo_size,
1040 pixel_size, latency->display_sr);
1041 reg = I915_READ(DSPFW1);
1042 reg &= ~DSPFW_SR_MASK;
1043 reg |= wm << DSPFW_SR_SHIFT;
1044 I915_WRITE(DSPFW1, reg);
1045 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1048 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1049 pineview_display_wm.fifo_size,
1050 pixel_size, latency->cursor_sr);
1051 reg = I915_READ(DSPFW3);
1052 reg &= ~DSPFW_CURSOR_SR_MASK;
1053 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1054 I915_WRITE(DSPFW3, reg);
1056 /* Display HPLL off SR */
1057 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1058 pineview_display_hplloff_wm.fifo_size,
1059 pixel_size, latency->display_hpll_disable);
1060 reg = I915_READ(DSPFW3);
1061 reg &= ~DSPFW_HPLL_SR_MASK;
1062 reg |= wm & DSPFW_HPLL_SR_MASK;
1063 I915_WRITE(DSPFW3, reg);
1065 /* cursor HPLL off SR */
1066 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1067 pineview_display_hplloff_wm.fifo_size,
1068 pixel_size, latency->cursor_hpll_disable);
1069 reg = I915_READ(DSPFW3);
1070 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1071 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1072 I915_WRITE(DSPFW3, reg);
1073 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1077 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1078 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1080 pineview_disable_cxsr(dev);
1081 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1085 static bool g4x_compute_wm0(struct drm_device *dev,
1087 const struct intel_watermark_params *display,
1088 int display_latency_ns,
1089 const struct intel_watermark_params *cursor,
1090 int cursor_latency_ns,
1094 struct drm_crtc *crtc;
1095 int htotal, hdisplay, clock, pixel_size;
1096 int line_time_us, line_count;
1097 int entries, tlb_miss;
1099 crtc = intel_get_crtc_for_plane(dev, plane);
1100 if (!intel_crtc_active(crtc)) {
1101 *cursor_wm = cursor->guard_size;
1102 *plane_wm = display->guard_size;
1106 htotal = crtc->mode.htotal;
1107 hdisplay = crtc->mode.hdisplay;
1108 clock = crtc->mode.clock;
1109 pixel_size = crtc->fb->bits_per_pixel / 8;
1111 /* Use the small buffer method to calculate plane watermark */
1112 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1115 entries += tlb_miss;
1116 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1117 *plane_wm = entries + display->guard_size;
1118 if (*plane_wm > (int)display->max_wm)
1119 *plane_wm = display->max_wm;
1121 /* Use the large buffer method to calculate cursor watermark */
1122 line_time_us = ((htotal * 1000) / clock);
1123 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1124 entries = line_count * 64 * pixel_size;
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1127 entries += tlb_miss;
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1129 *cursor_wm = entries + cursor->guard_size;
1130 if (*cursor_wm > (int)cursor->max_wm)
1131 *cursor_wm = (int)cursor->max_wm;
1137 * Check the wm result.
1139 * If any calculated watermark values is larger than the maximum value that
1140 * can be programmed into the associated watermark register, that watermark
1143 static bool g4x_check_srwm(struct drm_device *dev,
1144 int display_wm, int cursor_wm,
1145 const struct intel_watermark_params *display,
1146 const struct intel_watermark_params *cursor)
1148 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1149 display_wm, cursor_wm);
1151 if (display_wm > display->max_wm) {
1152 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1153 display_wm, display->max_wm);
1157 if (cursor_wm > cursor->max_wm) {
1158 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1159 cursor_wm, cursor->max_wm);
1163 if (!(display_wm || cursor_wm)) {
1164 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1171 static bool g4x_compute_srwm(struct drm_device *dev,
1174 const struct intel_watermark_params *display,
1175 const struct intel_watermark_params *cursor,
1176 int *display_wm, int *cursor_wm)
1178 struct drm_crtc *crtc;
1179 int hdisplay, htotal, pixel_size, clock;
1180 unsigned long line_time_us;
1181 int line_count, line_size;
1186 *display_wm = *cursor_wm = 0;
1190 crtc = intel_get_crtc_for_plane(dev, plane);
1191 hdisplay = crtc->mode.hdisplay;
1192 htotal = crtc->mode.htotal;
1193 clock = crtc->mode.clock;
1194 pixel_size = crtc->fb->bits_per_pixel / 8;
1196 line_time_us = (htotal * 1000) / clock;
1197 line_count = (latency_ns / line_time_us + 1000) / 1000;
1198 line_size = hdisplay * pixel_size;
1200 /* Use the minimum of the small and large buffer method for primary */
1201 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1202 large = line_count * line_size;
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1205 *display_wm = entries + display->guard_size;
1207 /* calculate the self-refresh watermark for display cursor */
1208 entries = line_count * pixel_size * 64;
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1210 *cursor_wm = entries + cursor->guard_size;
1212 return g4x_check_srwm(dev,
1213 *display_wm, *cursor_wm,
1217 static bool vlv_compute_drain_latency(struct drm_device *dev,
1219 int *plane_prec_mult,
1221 int *cursor_prec_mult,
1224 struct drm_crtc *crtc;
1225 int clock, pixel_size;
1228 crtc = intel_get_crtc_for_plane(dev, plane);
1229 if (!intel_crtc_active(crtc))
1232 clock = crtc->mode.clock; /* VESA DOT Clock */
1233 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1235 entries = (clock / 1000) * pixel_size;
1236 *plane_prec_mult = (entries > 256) ?
1237 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1238 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1241 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1242 *cursor_prec_mult = (entries > 256) ?
1243 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1244 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1250 * Update drain latency registers of memory arbiter
1252 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1253 * to be programmed. Each plane has a drain latency multiplier and a drain
1257 static void vlv_update_drain_latency(struct drm_device *dev)
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1261 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1262 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1265 /* For plane A, Cursor A */
1266 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1267 &cursor_prec_mult, &cursora_dl)) {
1268 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1269 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1270 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1273 I915_WRITE(VLV_DDL1, cursora_prec |
1274 (cursora_dl << DDL_CURSORA_SHIFT) |
1275 planea_prec | planea_dl);
1278 /* For plane B, Cursor B */
1279 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1280 &cursor_prec_mult, &cursorb_dl)) {
1281 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1283 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1284 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1286 I915_WRITE(VLV_DDL2, cursorb_prec |
1287 (cursorb_dl << DDL_CURSORB_SHIFT) |
1288 planeb_prec | planeb_dl);
1292 #define single_plane_enabled(mask) is_power_of_2(mask)
1294 static void valleyview_update_wm(struct drm_device *dev)
1296 static const int sr_latency_ns = 12000;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1299 int plane_sr, cursor_sr;
1300 int ignore_plane_sr, ignore_cursor_sr;
1301 unsigned int enabled = 0;
1303 vlv_update_drain_latency(dev);
1305 if (g4x_compute_wm0(dev, 0,
1306 &valleyview_wm_info, latency_ns,
1307 &valleyview_cursor_wm_info, latency_ns,
1308 &planea_wm, &cursora_wm))
1311 if (g4x_compute_wm0(dev, 1,
1312 &valleyview_wm_info, latency_ns,
1313 &valleyview_cursor_wm_info, latency_ns,
1314 &planeb_wm, &cursorb_wm))
1317 if (single_plane_enabled(enabled) &&
1318 g4x_compute_srwm(dev, ffs(enabled) - 1,
1320 &valleyview_wm_info,
1321 &valleyview_cursor_wm_info,
1322 &plane_sr, &ignore_cursor_sr) &&
1323 g4x_compute_srwm(dev, ffs(enabled) - 1,
1325 &valleyview_wm_info,
1326 &valleyview_cursor_wm_info,
1327 &ignore_plane_sr, &cursor_sr)) {
1328 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1330 I915_WRITE(FW_BLC_SELF_VLV,
1331 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1332 plane_sr = cursor_sr = 0;
1335 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1336 planea_wm, cursora_wm,
1337 planeb_wm, cursorb_wm,
1338 plane_sr, cursor_sr);
1341 (plane_sr << DSPFW_SR_SHIFT) |
1342 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1343 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1346 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1347 (cursora_wm << DSPFW_CURSORA_SHIFT));
1349 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1350 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1353 static void g4x_update_wm(struct drm_device *dev)
1355 static const int sr_latency_ns = 12000;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1358 int plane_sr, cursor_sr;
1359 unsigned int enabled = 0;
1361 if (g4x_compute_wm0(dev, 0,
1362 &g4x_wm_info, latency_ns,
1363 &g4x_cursor_wm_info, latency_ns,
1364 &planea_wm, &cursora_wm))
1367 if (g4x_compute_wm0(dev, 1,
1368 &g4x_wm_info, latency_ns,
1369 &g4x_cursor_wm_info, latency_ns,
1370 &planeb_wm, &cursorb_wm))
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1377 &g4x_cursor_wm_info,
1378 &plane_sr, &cursor_sr)) {
1379 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1381 I915_WRITE(FW_BLC_SELF,
1382 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1383 plane_sr = cursor_sr = 0;
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1399 /* HPLL off in SR has some issues on G4x... disable it */
1401 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1402 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1405 static void i965_update_wm(struct drm_device *dev)
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 struct drm_crtc *crtc;
1412 /* Calc sr entries for one plane configs */
1413 crtc = single_enabled_crtc(dev);
1415 /* self-refresh has much higher latency */
1416 static const int sr_latency_ns = 12000;
1417 int clock = crtc->mode.clock;
1418 int htotal = crtc->mode.htotal;
1419 int hdisplay = crtc->mode.hdisplay;
1420 int pixel_size = crtc->fb->bits_per_pixel / 8;
1421 unsigned long line_time_us;
1424 line_time_us = ((htotal * 1000) / clock);
1426 /* Use ns/us then divide to preserve precision */
1427 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1428 pixel_size * hdisplay;
1429 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1430 srwm = I965_FIFO_SIZE - entries;
1434 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1437 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1439 entries = DIV_ROUND_UP(entries,
1440 i965_cursor_wm_info.cacheline_size);
1441 cursor_sr = i965_cursor_wm_info.fifo_size -
1442 (entries + i965_cursor_wm_info.guard_size);
1444 if (cursor_sr > i965_cursor_wm_info.max_wm)
1445 cursor_sr = i965_cursor_wm_info.max_wm;
1447 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1448 "cursor %d\n", srwm, cursor_sr);
1450 if (IS_CRESTLINE(dev))
1451 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1453 /* Turn off self refresh if both pipes are enabled */
1454 if (IS_CRESTLINE(dev))
1455 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1459 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1462 /* 965 has limitations... */
1463 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1464 (8 << 16) | (8 << 8) | (8 << 0));
1465 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1466 /* update cursor SR watermark */
1467 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1470 static void i9xx_update_wm(struct drm_device *dev)
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 const struct intel_watermark_params *wm_info;
1478 int planea_wm, planeb_wm;
1479 struct drm_crtc *crtc, *enabled = NULL;
1482 wm_info = &i945_wm_info;
1483 else if (!IS_GEN2(dev))
1484 wm_info = &i915_wm_info;
1486 wm_info = &i855_wm_info;
1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1489 crtc = intel_get_crtc_for_plane(dev, 0);
1490 if (intel_crtc_active(crtc)) {
1491 int cpp = crtc->fb->bits_per_pixel / 8;
1495 planea_wm = intel_calculate_wm(crtc->mode.clock,
1496 wm_info, fifo_size, cpp,
1500 planea_wm = fifo_size - wm_info->guard_size;
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1503 crtc = intel_get_crtc_for_plane(dev, 1);
1504 if (intel_crtc_active(crtc)) {
1505 int cpp = crtc->fb->bits_per_pixel / 8;
1509 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1510 wm_info, fifo_size, cpp,
1512 if (enabled == NULL)
1517 planeb_wm = fifo_size - wm_info->guard_size;
1519 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1522 * Overlay gets an aggressive default since video jitter is bad.
1526 /* Play safe and disable self-refresh before adjusting watermarks. */
1527 if (IS_I945G(dev) || IS_I945GM(dev))
1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1529 else if (IS_I915GM(dev))
1530 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1532 /* Calc sr entries for one plane configs */
1533 if (HAS_FW_BLC(dev) && enabled) {
1534 /* self-refresh has much higher latency */
1535 static const int sr_latency_ns = 6000;
1536 int clock = enabled->mode.clock;
1537 int htotal = enabled->mode.htotal;
1538 int hdisplay = enabled->mode.hdisplay;
1539 int pixel_size = enabled->fb->bits_per_pixel / 8;
1540 unsigned long line_time_us;
1543 line_time_us = (htotal * 1000) / clock;
1545 /* Use ns/us then divide to preserve precision */
1546 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1547 pixel_size * hdisplay;
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1549 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1550 srwm = wm_info->fifo_size - entries;
1554 if (IS_I945G(dev) || IS_I945GM(dev))
1555 I915_WRITE(FW_BLC_SELF,
1556 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1557 else if (IS_I915GM(dev))
1558 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1561 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1562 planea_wm, planeb_wm, cwm, srwm);
1564 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1565 fwater_hi = (cwm & 0x1f);
1567 /* Set request length to 8 cachelines per fetch */
1568 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1569 fwater_hi = fwater_hi | (1 << 8);
1571 I915_WRITE(FW_BLC, fwater_lo);
1572 I915_WRITE(FW_BLC2, fwater_hi);
1574 if (HAS_FW_BLC(dev)) {
1576 if (IS_I945G(dev) || IS_I945GM(dev))
1577 I915_WRITE(FW_BLC_SELF,
1578 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1579 else if (IS_I915GM(dev))
1580 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1581 DRM_DEBUG_KMS("memory self refresh enabled\n");
1583 DRM_DEBUG_KMS("memory self refresh disabled\n");
1587 static void i830_update_wm(struct drm_device *dev)
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct drm_crtc *crtc;
1594 crtc = single_enabled_crtc(dev);
1598 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1599 dev_priv->display.get_fifo_size(dev, 0),
1601 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1602 fwater_lo |= (3<<8) | planea_wm;
1604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1606 I915_WRITE(FW_BLC, fwater_lo);
1609 #define ILK_LP0_PLANE_LATENCY 700
1610 #define ILK_LP0_CURSOR_LATENCY 1300
1613 * Check the wm result.
1615 * If any calculated watermark values is larger than the maximum value that
1616 * can be programmed into the associated watermark register, that watermark
1619 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1620 int fbc_wm, int display_wm, int cursor_wm,
1621 const struct intel_watermark_params *display,
1622 const struct intel_watermark_params *cursor)
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1626 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1627 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1629 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1630 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1631 fbc_wm, SNB_FBC_MAX_SRWM, level);
1633 /* fbc has it's own way to disable FBC WM */
1634 I915_WRITE(DISP_ARB_CTL,
1635 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1639 if (display_wm > display->max_wm) {
1640 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1641 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1645 if (cursor_wm > cursor->max_wm) {
1646 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1647 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1651 if (!(fbc_wm || display_wm || cursor_wm)) {
1652 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1660 * Compute watermark values of WM[1-3],
1662 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1664 const struct intel_watermark_params *display,
1665 const struct intel_watermark_params *cursor,
1666 int *fbc_wm, int *display_wm, int *cursor_wm)
1668 struct drm_crtc *crtc;
1669 unsigned long line_time_us;
1670 int hdisplay, htotal, pixel_size, clock;
1671 int line_count, line_size;
1676 *fbc_wm = *display_wm = *cursor_wm = 0;
1680 crtc = intel_get_crtc_for_plane(dev, plane);
1681 hdisplay = crtc->mode.hdisplay;
1682 htotal = crtc->mode.htotal;
1683 clock = crtc->mode.clock;
1684 pixel_size = crtc->fb->bits_per_pixel / 8;
1686 line_time_us = (htotal * 1000) / clock;
1687 line_count = (latency_ns / line_time_us + 1000) / 1000;
1688 line_size = hdisplay * pixel_size;
1690 /* Use the minimum of the small and large buffer method for primary */
1691 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1692 large = line_count * line_size;
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1695 *display_wm = entries + display->guard_size;
1699 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1701 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1703 /* calculate the self-refresh watermark for display cursor */
1704 entries = line_count * pixel_size * 64;
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1706 *cursor_wm = entries + cursor->guard_size;
1708 return ironlake_check_srwm(dev, level,
1709 *fbc_wm, *display_wm, *cursor_wm,
1713 static void ironlake_update_wm(struct drm_device *dev)
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 int fbc_wm, plane_wm, cursor_wm;
1717 unsigned int enabled;
1720 if (g4x_compute_wm0(dev, 0,
1721 &ironlake_display_wm_info,
1722 ILK_LP0_PLANE_LATENCY,
1723 &ironlake_cursor_wm_info,
1724 ILK_LP0_CURSOR_LATENCY,
1725 &plane_wm, &cursor_wm)) {
1726 I915_WRITE(WM0_PIPEA_ILK,
1727 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1728 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1729 " plane %d, " "cursor: %d\n",
1730 plane_wm, cursor_wm);
1734 if (g4x_compute_wm0(dev, 1,
1735 &ironlake_display_wm_info,
1736 ILK_LP0_PLANE_LATENCY,
1737 &ironlake_cursor_wm_info,
1738 ILK_LP0_CURSOR_LATENCY,
1739 &plane_wm, &cursor_wm)) {
1740 I915_WRITE(WM0_PIPEB_ILK,
1741 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1742 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1743 " plane %d, cursor: %d\n",
1744 plane_wm, cursor_wm);
1749 * Calculate and update the self-refresh watermark only when one
1750 * display plane is used.
1752 I915_WRITE(WM3_LP_ILK, 0);
1753 I915_WRITE(WM2_LP_ILK, 0);
1754 I915_WRITE(WM1_LP_ILK, 0);
1756 if (!single_plane_enabled(enabled))
1758 enabled = ffs(enabled) - 1;
1761 if (!ironlake_compute_srwm(dev, 1, enabled,
1762 ILK_READ_WM1_LATENCY() * 500,
1763 &ironlake_display_srwm_info,
1764 &ironlake_cursor_srwm_info,
1765 &fbc_wm, &plane_wm, &cursor_wm))
1768 I915_WRITE(WM1_LP_ILK,
1770 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1771 (fbc_wm << WM1_LP_FBC_SHIFT) |
1772 (plane_wm << WM1_LP_SR_SHIFT) |
1776 if (!ironlake_compute_srwm(dev, 2, enabled,
1777 ILK_READ_WM2_LATENCY() * 500,
1778 &ironlake_display_srwm_info,
1779 &ironlake_cursor_srwm_info,
1780 &fbc_wm, &plane_wm, &cursor_wm))
1783 I915_WRITE(WM2_LP_ILK,
1785 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1786 (fbc_wm << WM1_LP_FBC_SHIFT) |
1787 (plane_wm << WM1_LP_SR_SHIFT) |
1791 * WM3 is unsupported on ILK, probably because we don't have latency
1792 * data for that power state
1796 static void sandybridge_update_wm(struct drm_device *dev)
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1801 int fbc_wm, plane_wm, cursor_wm;
1802 unsigned int enabled;
1805 if (g4x_compute_wm0(dev, 0,
1806 &sandybridge_display_wm_info, latency,
1807 &sandybridge_cursor_wm_info, latency,
1808 &plane_wm, &cursor_wm)) {
1809 val = I915_READ(WM0_PIPEA_ILK);
1810 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1811 I915_WRITE(WM0_PIPEA_ILK, val |
1812 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1813 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1814 " plane %d, " "cursor: %d\n",
1815 plane_wm, cursor_wm);
1819 if (g4x_compute_wm0(dev, 1,
1820 &sandybridge_display_wm_info, latency,
1821 &sandybridge_cursor_wm_info, latency,
1822 &plane_wm, &cursor_wm)) {
1823 val = I915_READ(WM0_PIPEB_ILK);
1824 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1825 I915_WRITE(WM0_PIPEB_ILK, val |
1826 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1827 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1828 " plane %d, cursor: %d\n",
1829 plane_wm, cursor_wm);
1834 * Calculate and update the self-refresh watermark only when one
1835 * display plane is used.
1837 * SNB support 3 levels of watermark.
1839 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1840 * and disabled in the descending order
1843 I915_WRITE(WM3_LP_ILK, 0);
1844 I915_WRITE(WM2_LP_ILK, 0);
1845 I915_WRITE(WM1_LP_ILK, 0);
1847 if (!single_plane_enabled(enabled) ||
1848 dev_priv->sprite_scaling_enabled)
1850 enabled = ffs(enabled) - 1;
1853 if (!ironlake_compute_srwm(dev, 1, enabled,
1854 SNB_READ_WM1_LATENCY() * 500,
1855 &sandybridge_display_srwm_info,
1856 &sandybridge_cursor_srwm_info,
1857 &fbc_wm, &plane_wm, &cursor_wm))
1860 I915_WRITE(WM1_LP_ILK,
1862 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1863 (fbc_wm << WM1_LP_FBC_SHIFT) |
1864 (plane_wm << WM1_LP_SR_SHIFT) |
1868 if (!ironlake_compute_srwm(dev, 2, enabled,
1869 SNB_READ_WM2_LATENCY() * 500,
1870 &sandybridge_display_srwm_info,
1871 &sandybridge_cursor_srwm_info,
1872 &fbc_wm, &plane_wm, &cursor_wm))
1875 I915_WRITE(WM2_LP_ILK,
1877 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1878 (fbc_wm << WM1_LP_FBC_SHIFT) |
1879 (plane_wm << WM1_LP_SR_SHIFT) |
1883 if (!ironlake_compute_srwm(dev, 3, enabled,
1884 SNB_READ_WM3_LATENCY() * 500,
1885 &sandybridge_display_srwm_info,
1886 &sandybridge_cursor_srwm_info,
1887 &fbc_wm, &plane_wm, &cursor_wm))
1890 I915_WRITE(WM3_LP_ILK,
1892 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1893 (fbc_wm << WM1_LP_FBC_SHIFT) |
1894 (plane_wm << WM1_LP_SR_SHIFT) |
1898 static void ivybridge_update_wm(struct drm_device *dev)
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1903 int fbc_wm, plane_wm, cursor_wm;
1904 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1905 unsigned int enabled;
1908 if (g4x_compute_wm0(dev, 0,
1909 &sandybridge_display_wm_info, latency,
1910 &sandybridge_cursor_wm_info, latency,
1911 &plane_wm, &cursor_wm)) {
1912 val = I915_READ(WM0_PIPEA_ILK);
1913 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1914 I915_WRITE(WM0_PIPEA_ILK, val |
1915 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1916 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1917 " plane %d, " "cursor: %d\n",
1918 plane_wm, cursor_wm);
1922 if (g4x_compute_wm0(dev, 1,
1923 &sandybridge_display_wm_info, latency,
1924 &sandybridge_cursor_wm_info, latency,
1925 &plane_wm, &cursor_wm)) {
1926 val = I915_READ(WM0_PIPEB_ILK);
1927 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1928 I915_WRITE(WM0_PIPEB_ILK, val |
1929 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1930 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1931 " plane %d, cursor: %d\n",
1932 plane_wm, cursor_wm);
1936 if (g4x_compute_wm0(dev, 2,
1937 &sandybridge_display_wm_info, latency,
1938 &sandybridge_cursor_wm_info, latency,
1939 &plane_wm, &cursor_wm)) {
1940 val = I915_READ(WM0_PIPEC_IVB);
1941 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1942 I915_WRITE(WM0_PIPEC_IVB, val |
1943 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1944 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1945 " plane %d, cursor: %d\n",
1946 plane_wm, cursor_wm);
1951 * Calculate and update the self-refresh watermark only when one
1952 * display plane is used.
1954 * SNB support 3 levels of watermark.
1956 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1957 * and disabled in the descending order
1960 I915_WRITE(WM3_LP_ILK, 0);
1961 I915_WRITE(WM2_LP_ILK, 0);
1962 I915_WRITE(WM1_LP_ILK, 0);
1964 if (!single_plane_enabled(enabled) ||
1965 dev_priv->sprite_scaling_enabled)
1967 enabled = ffs(enabled) - 1;
1970 if (!ironlake_compute_srwm(dev, 1, enabled,
1971 SNB_READ_WM1_LATENCY() * 500,
1972 &sandybridge_display_srwm_info,
1973 &sandybridge_cursor_srwm_info,
1974 &fbc_wm, &plane_wm, &cursor_wm))
1977 I915_WRITE(WM1_LP_ILK,
1979 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1980 (fbc_wm << WM1_LP_FBC_SHIFT) |
1981 (plane_wm << WM1_LP_SR_SHIFT) |
1985 if (!ironlake_compute_srwm(dev, 2, enabled,
1986 SNB_READ_WM2_LATENCY() * 500,
1987 &sandybridge_display_srwm_info,
1988 &sandybridge_cursor_srwm_info,
1989 &fbc_wm, &plane_wm, &cursor_wm))
1992 I915_WRITE(WM2_LP_ILK,
1994 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1995 (fbc_wm << WM1_LP_FBC_SHIFT) |
1996 (plane_wm << WM1_LP_SR_SHIFT) |
1999 /* WM3, note we have to correct the cursor latency */
2000 if (!ironlake_compute_srwm(dev, 3, enabled,
2001 SNB_READ_WM3_LATENCY() * 500,
2002 &sandybridge_display_srwm_info,
2003 &sandybridge_cursor_srwm_info,
2004 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2005 !ironlake_compute_srwm(dev, 3, enabled,
2006 2 * SNB_READ_WM3_LATENCY() * 500,
2007 &sandybridge_display_srwm_info,
2008 &sandybridge_cursor_srwm_info,
2009 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2012 I915_WRITE(WM3_LP_ILK,
2014 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2015 (fbc_wm << WM1_LP_FBC_SHIFT) |
2016 (plane_wm << WM1_LP_SR_SHIFT) |
2021 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2022 struct drm_display_mode *mode)
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2027 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2028 temp &= ~PIPE_WM_LINETIME_MASK;
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2033 temp |= PIPE_WM_LINETIME_TIME(
2034 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2036 /* IPS watermarks are only used by pipe A, and are ignored by
2037 * pipes B and C. They are calculated similarly to the common
2038 * linetime values, except that we are using CD clock frequency
2039 * in MHz instead of pixel rate for the division.
2041 * This is a placeholder for the IPS watermark calculation code.
2044 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2048 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2049 uint32_t sprite_width, int pixel_size,
2050 const struct intel_watermark_params *display,
2051 int display_latency_ns, int *sprite_wm)
2053 struct drm_crtc *crtc;
2055 int entries, tlb_miss;
2057 crtc = intel_get_crtc_for_plane(dev, plane);
2058 if (!intel_crtc_active(crtc)) {
2059 *sprite_wm = display->guard_size;
2063 clock = crtc->mode.clock;
2065 /* Use the small buffer method to calculate the sprite watermark */
2066 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2067 tlb_miss = display->fifo_size*display->cacheline_size -
2070 entries += tlb_miss;
2071 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2072 *sprite_wm = entries + display->guard_size;
2073 if (*sprite_wm > (int)display->max_wm)
2074 *sprite_wm = display->max_wm;
2080 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2081 uint32_t sprite_width, int pixel_size,
2082 const struct intel_watermark_params *display,
2083 int latency_ns, int *sprite_wm)
2085 struct drm_crtc *crtc;
2086 unsigned long line_time_us;
2088 int line_count, line_size;
2097 crtc = intel_get_crtc_for_plane(dev, plane);
2098 clock = crtc->mode.clock;
2104 line_time_us = (sprite_width * 1000) / clock;
2105 if (!line_time_us) {
2110 line_count = (latency_ns / line_time_us + 1000) / 1000;
2111 line_size = sprite_width * pixel_size;
2113 /* Use the minimum of the small and large buffer method for primary */
2114 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2115 large = line_count * line_size;
2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2118 *sprite_wm = entries + display->guard_size;
2120 return *sprite_wm > 0x3ff ? false : true;
2123 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2124 uint32_t sprite_width, int pixel_size)
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2134 reg = WM0_PIPEA_ILK;
2137 reg = WM0_PIPEB_ILK;
2140 reg = WM0_PIPEC_IVB;
2143 return; /* bad pipe */
2146 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2147 &sandybridge_display_wm_info,
2148 latency, &sprite_wm);
2150 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2155 val = I915_READ(reg);
2156 val &= ~WM0_PIPE_SPRITE_MASK;
2157 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2158 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2161 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2163 &sandybridge_display_srwm_info,
2164 SNB_READ_WM1_LATENCY() * 500,
2167 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2171 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2173 /* Only IVB has two more LP watermarks for sprite */
2174 if (!IS_IVYBRIDGE(dev))
2177 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2179 &sandybridge_display_srwm_info,
2180 SNB_READ_WM2_LATENCY() * 500,
2183 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2187 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2189 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2191 &sandybridge_display_srwm_info,
2192 SNB_READ_WM3_LATENCY() * 500,
2195 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2199 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2203 * intel_update_watermarks - update FIFO watermark values based on current modes
2205 * Calculate watermark values for the various WM regs based on current mode
2206 * and plane configuration.
2208 * There are several cases to deal with here:
2209 * - normal (i.e. non-self-refresh)
2210 * - self-refresh (SR) mode
2211 * - lines are large relative to FIFO size (buffer can hold up to 2)
2212 * - lines are small relative to FIFO size (buffer can hold more than 2
2213 * lines), so need to account for TLB latency
2215 * The normal calculation is:
2216 * watermark = dotclock * bytes per pixel * latency
2217 * where latency is platform & configuration dependent (we assume pessimal
2220 * The SR calculation is:
2221 * watermark = (trunc(latency/line time)+1) * surface width *
2224 * line time = htotal / dotclock
2225 * surface width = hdisplay for normal plane and 64 for cursor
2226 * and latency is assumed to be high, as above.
2228 * The final value programmed to the register should always be rounded up,
2229 * and include an extra 2 entries to account for clock crossings.
2231 * We don't use the sprite, so we can ignore that. And on Crestline we have
2232 * to set the non-SR watermarks to 8.
2234 void intel_update_watermarks(struct drm_device *dev)
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2238 if (dev_priv->display.update_wm)
2239 dev_priv->display.update_wm(dev);
2242 void intel_update_linetime_watermarks(struct drm_device *dev,
2243 int pipe, struct drm_display_mode *mode)
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2247 if (dev_priv->display.update_linetime_wm)
2248 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2251 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2252 uint32_t sprite_width, int pixel_size)
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2256 if (dev_priv->display.update_sprite_wm)
2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2261 static struct drm_i915_gem_object *
2262 intel_alloc_context_page(struct drm_device *dev)
2264 struct drm_i915_gem_object *ctx;
2267 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2269 ctx = i915_gem_alloc_object(dev, 4096);
2271 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2275 ret = i915_gem_object_pin(ctx, 4096, true, false);
2277 DRM_ERROR("failed to pin power context: %d\n", ret);
2281 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2283 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2290 i915_gem_object_unpin(ctx);
2292 drm_gem_object_unreference(&ctx->base);
2297 * Lock protecting IPS related data structures
2299 struct lock mchdev_lock;
2300 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
2302 /* Global for IPS driver to get at the current i915 device. Protected by
2304 static struct drm_i915_private *i915_mch_dev;
2306 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2311 rgvswctl = I915_READ16(MEMSWCTL);
2312 if (rgvswctl & MEMCTL_CMD_STS) {
2313 DRM_DEBUG("gpu busy, RCS change rejected\n");
2314 return false; /* still busy with another command */
2317 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2318 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2319 I915_WRITE16(MEMSWCTL, rgvswctl);
2320 POSTING_READ16(MEMSWCTL);
2322 rgvswctl |= MEMCTL_CMD_STS;
2323 I915_WRITE16(MEMSWCTL, rgvswctl);
2328 static void ironlake_enable_drps(struct drm_device *dev)
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 u32 rgvmodectl = I915_READ(MEMMODECTL);
2332 u8 fmax, fmin, fstart, vstart;
2334 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2336 /* Enable temp reporting */
2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2340 /* 100ms RC evaluation intervals */
2341 I915_WRITE(RCUPEI, 100000);
2342 I915_WRITE(RCDNEI, 100000);
2344 /* Set max/min thresholds to 90ms and 80ms respectively */
2345 I915_WRITE(RCBMAXAVG, 90000);
2346 I915_WRITE(RCBMINAVG, 80000);
2348 I915_WRITE(MEMIHYST, 1);
2350 /* Set up min, max, and cur for interrupt handling */
2351 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2352 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2353 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2354 MEMMODE_FSTART_SHIFT;
2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2359 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2360 dev_priv->ips.fstart = fstart;
2362 dev_priv->ips.max_delay = fstart;
2363 dev_priv->ips.min_delay = fmin;
2364 dev_priv->ips.cur_delay = fstart;
2366 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2367 fmax, fmin, fstart);
2369 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2372 * Interrupts will be enabled in ironlake_irq_postinstall
2375 I915_WRITE(VIDSTART, vstart);
2376 POSTING_READ(VIDSTART);
2378 rgvmodectl |= MEMMODE_SWMODE_EN;
2379 I915_WRITE(MEMMODECTL, rgvmodectl);
2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2382 DRM_ERROR("stuck trying to change perf mode\n");
2385 ironlake_set_drps(dev, fstart);
2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2389 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2390 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2391 getrawmonotonic(&dev_priv->ips.last_time2);
2393 lockmgr(&mchdev_lock, LK_RELEASE);
2396 static void ironlake_disable_drps(struct drm_device *dev)
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2401 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2403 rgvswctl = I915_READ16(MEMSWCTL);
2405 /* Ack interrupts, disable EFC interrupt */
2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2407 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2409 I915_WRITE(DEIIR, DE_PCU_EVENT);
2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2412 /* Go back to the starting frequency */
2413 ironlake_set_drps(dev, dev_priv->ips.fstart);
2415 rgvswctl |= MEMCTL_CMD_STS;
2416 I915_WRITE(MEMSWCTL, rgvswctl);
2419 lockmgr(&mchdev_lock, LK_RELEASE);
2422 /* There's a funny hw issue where the hw returns all 0 when reading from
2423 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2424 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2425 * all limits and the gpu stuck at whatever frequency it is at atm).
2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2433 if (*val >= dev_priv->rps.max_delay)
2434 *val = dev_priv->rps.max_delay;
2435 limits |= dev_priv->rps.max_delay << 24;
2437 /* Only set the down limit when we've reached the lowest level to avoid
2438 * getting more interrupts, otherwise leave this clear. This prevents a
2439 * race in the hw when coming out of rc6: There's a tiny window where
2440 * the hw runs at the minimal clock before selecting the desired
2441 * frequency, if the down threshold expires in that window we will not
2442 * receive a down interrupt. */
2443 if (*val <= dev_priv->rps.min_delay) {
2444 *val = dev_priv->rps.min_delay;
2445 limits |= dev_priv->rps.min_delay << 16;
2451 void gen6_set_rps(struct drm_device *dev, u8 val)
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 u32 limits = gen6_rps_limits(dev_priv, &val);
2456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2457 WARN_ON(val > dev_priv->rps.max_delay);
2458 WARN_ON(val < dev_priv->rps.min_delay);
2460 if (val == dev_priv->rps.cur_delay)
2463 I915_WRITE(GEN6_RPNSWREQ,
2464 GEN6_FREQUENCY(val) |
2466 GEN6_AGGRESSIVE_TURBO);
2468 /* Make sure we continue to get interrupts
2469 * until we hit the minimum or maximum frequencies.
2471 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2473 POSTING_READ(GEN6_RPNSWREQ);
2475 dev_priv->rps.cur_delay = val;
2477 trace_intel_gpu_freq_change(val * 50);
2480 static void gen6_disable_rps(struct drm_device *dev)
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2484 I915_WRITE(GEN6_RC_CONTROL, 0);
2485 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2486 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2487 I915_WRITE(GEN6_PMIER, 0);
2488 /* Complete PM interrupt masking here doesn't race with the rps work
2489 * item again unmasking PM interrupts because that is using a different
2490 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2491 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2493 spin_lock(&dev_priv->rps.lock);
2494 dev_priv->rps.pm_iir = 0;
2495 spin_unlock(&dev_priv->rps.lock);
2497 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2500 int intel_enable_rc6(const struct drm_device *dev)
2502 /* Respect the kernel parameter if it is set */
2503 if (i915_enable_rc6 >= 0)
2504 return i915_enable_rc6;
2506 /* Disable RC6 on Ironlake */
2507 if (INTEL_INFO(dev)->gen == 5)
2510 if (IS_HASWELL(dev)) {
2511 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2512 return INTEL_RC6_ENABLE;
2515 /* snb/ivb have more than one rc6 state. */
2516 if (INTEL_INFO(dev)->gen == 6) {
2517 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2518 return INTEL_RC6_ENABLE;
2521 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2522 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2525 static void gen6_enable_rps(struct drm_device *dev)
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 struct intel_ring_buffer *ring;
2531 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2536 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2538 /* Here begins a magic sequence of register writes to enable
2539 * auto-downclocking.
2541 * Perhaps there might be some value in exposing these to
2544 I915_WRITE(GEN6_RC_STATE, 0);
2546 /* Clear the DBG now so we don't confuse earlier errors */
2547 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2548 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2549 I915_WRITE(GTFIFODBG, gtfifodbg);
2552 gen6_gt_force_wake_get(dev_priv);
2554 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2555 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2557 /* In units of 100MHz */
2558 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2559 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2560 dev_priv->rps.cur_delay = 0;
2562 /* disable the counters and set deterministic thresholds */
2563 I915_WRITE(GEN6_RC_CONTROL, 0);
2565 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2566 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2567 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2568 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2569 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2571 for_each_ring(ring, dev_priv, i)
2572 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2574 I915_WRITE(GEN6_RC_SLEEP, 0);
2575 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2576 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2577 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2578 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2580 /* Check if we are enabling RC6 */
2581 rc6_mode = intel_enable_rc6(dev_priv->dev);
2582 if (rc6_mode & INTEL_RC6_ENABLE)
2583 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2585 /* We don't use those on Haswell */
2586 if (!IS_HASWELL(dev)) {
2587 if (rc6_mode & INTEL_RC6p_ENABLE)
2588 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2590 if (rc6_mode & INTEL_RC6pp_ENABLE)
2591 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2594 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2595 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2596 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2597 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2599 I915_WRITE(GEN6_RC_CONTROL,
2601 GEN6_RC_CTL_EI_MODE(1) |
2602 GEN6_RC_CTL_HW_ENABLE);
2604 I915_WRITE(GEN6_RPNSWREQ,
2605 GEN6_FREQUENCY(10) |
2607 GEN6_AGGRESSIVE_TURBO);
2608 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2609 GEN6_FREQUENCY(12));
2611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2612 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2613 dev_priv->rps.max_delay << 24 |
2614 dev_priv->rps.min_delay << 16);
2616 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2617 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2618 I915_WRITE(GEN6_RP_UP_EI, 66000);
2619 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2621 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2622 I915_WRITE(GEN6_RP_CONTROL,
2623 GEN6_RP_MEDIA_TURBO |
2624 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2625 GEN6_RP_MEDIA_IS_GFX |
2627 GEN6_RP_UP_BUSY_AVG |
2628 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2630 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2633 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2634 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2635 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2636 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2639 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2642 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2644 /* requires MSI enabled */
2645 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2646 spin_lock(&dev_priv->rps.lock);
2647 WARN_ON(dev_priv->rps.pm_iir != 0);
2648 I915_WRITE(GEN6_PMIMR, 0);
2649 spin_unlock(&dev_priv->rps.lock);
2650 /* enable all PM interrupts */
2651 I915_WRITE(GEN6_PMINTRMSK, 0);
2654 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2655 if (IS_GEN6(dev) && ret) {
2656 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2657 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2658 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2659 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2660 rc6vids &= 0xffff00;
2661 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2662 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2664 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2667 gen6_gt_force_wake_put(dev_priv);
2670 static void gen6_update_ring_freq(struct drm_device *dev)
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2675 unsigned int ia_freq, max_ia_freq;
2676 int scaling_factor = 180;
2678 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2681 max_ia_freq = cpufreq_quick_get_max(0);
2683 * Default to measured freq if none found, PCU will ensure we don't go
2687 max_ia_freq = tsc_khz;
2689 max_ia_freq = tsc_frequency / 1000;
2692 /* Convert from kHz to MHz */
2693 max_ia_freq /= 1000;
2696 * For each potential GPU frequency, load a ring frequency we'd like
2697 * to use for memory access. We do this by specifying the IA frequency
2698 * the PCU should use as a reference to determine the ring frequency.
2700 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2702 int diff = dev_priv->rps.max_delay - gpu_freq;
2705 * For GPU frequencies less than 750MHz, just use the lowest
2708 if (gpu_freq < min_freq)
2711 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2712 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2713 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2715 sandybridge_pcode_write(dev_priv,
2716 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2717 ia_freq | gpu_freq);
2721 void ironlake_teardown_rc6(struct drm_device *dev)
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2725 if (dev_priv->ips.renderctx) {
2726 i915_gem_object_unpin(dev_priv->ips.renderctx);
2727 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2728 dev_priv->ips.renderctx = NULL;
2731 if (dev_priv->ips.pwrctx) {
2732 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2733 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2734 dev_priv->ips.pwrctx = NULL;
2738 static void ironlake_disable_rc6(struct drm_device *dev)
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2742 if (I915_READ(PWRCTXA)) {
2743 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2744 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2745 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2748 I915_WRITE(PWRCTXA, 0);
2749 POSTING_READ(PWRCTXA);
2751 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2752 POSTING_READ(RSTDBYCTL);
2756 static int ironlake_setup_rc6(struct drm_device *dev)
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2760 if (dev_priv->ips.renderctx == NULL)
2761 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2762 if (!dev_priv->ips.renderctx)
2765 if (dev_priv->ips.pwrctx == NULL)
2766 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2767 if (!dev_priv->ips.pwrctx) {
2768 ironlake_teardown_rc6(dev);
2775 static void ironlake_enable_rc6(struct drm_device *dev)
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2779 bool was_interruptible;
2782 /* rc6 disabled by default due to repeated reports of hanging during
2785 if (!intel_enable_rc6(dev))
2788 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2790 ret = ironlake_setup_rc6(dev);
2794 was_interruptible = dev_priv->mm.interruptible;
2795 dev_priv->mm.interruptible = false;
2798 * GPU can automatically power down the render unit if given a page
2801 ret = intel_ring_begin(ring, 6);
2803 ironlake_teardown_rc6(dev);
2804 dev_priv->mm.interruptible = was_interruptible;
2808 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2809 intel_ring_emit(ring, MI_SET_CONTEXT);
2810 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2812 MI_SAVE_EXT_STATE_EN |
2813 MI_RESTORE_EXT_STATE_EN |
2814 MI_RESTORE_INHIBIT);
2815 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2816 intel_ring_emit(ring, MI_NOOP);
2817 intel_ring_emit(ring, MI_FLUSH);
2818 intel_ring_advance(ring);
2821 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2822 * does an implicit flush, combined with MI_FLUSH above, it should be
2823 * safe to assume that renderctx is valid
2825 ret = intel_ring_idle(ring);
2826 dev_priv->mm.interruptible = was_interruptible;
2828 DRM_ERROR("failed to enable ironlake power power savings\n");
2829 ironlake_teardown_rc6(dev);
2833 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2834 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2837 static unsigned long intel_pxfreq(u32 vidfreq)
2840 int div = (vidfreq & 0x3f0000) >> 16;
2841 int post = (vidfreq & 0x3000) >> 12;
2842 int pre = (vidfreq & 0x7);
2847 freq = ((div * 133333) / ((1<<post) * pre));
2852 static const struct cparams {
2858 { 1, 1333, 301, 28664 },
2859 { 1, 1066, 294, 24460 },
2860 { 1, 800, 294, 25192 },
2861 { 0, 1333, 276, 27605 },
2862 { 0, 1066, 276, 27605 },
2863 { 0, 800, 231, 23784 },
2866 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2868 u64 total_count, diff, ret;
2869 u32 count1, count2, count3, m = 0, c = 0;
2870 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2873 diff1 = now - dev_priv->ips.last_time1;
2875 /* Prevent division-by-zero if we are asking too fast.
2876 * Also, we don't get interesting results if we are polling
2877 * faster than once in 10ms, so just return the saved value
2881 return dev_priv->ips.chipset_power;
2883 count1 = I915_READ(DMIEC);
2884 count2 = I915_READ(DDREC);
2885 count3 = I915_READ(CSIEC);
2887 total_count = count1 + count2 + count3;
2889 /* FIXME: handle per-counter overflow */
2890 if (total_count < dev_priv->ips.last_count1) {
2891 diff = ~0UL - dev_priv->ips.last_count1;
2892 diff += total_count;
2894 diff = total_count - dev_priv->ips.last_count1;
2897 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2898 if (cparams[i].i == dev_priv->ips.c_m &&
2899 cparams[i].t == dev_priv->ips.r_t) {
2906 diff = div_u64(diff, diff1);
2907 ret = ((m * diff) + c);
2908 ret = div_u64(ret, 10);
2910 dev_priv->ips.last_count1 = total_count;
2911 dev_priv->ips.last_time1 = now;
2913 dev_priv->ips.chipset_power = ret;
2918 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2922 if (dev_priv->info->gen != 5)
2925 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2927 val = __i915_chipset_val(dev_priv);
2929 lockmgr(&mchdev_lock, LK_RELEASE);
2934 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2936 unsigned long m, x, b;
2939 tsfs = I915_READ(TSFS);
2941 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2942 x = I915_READ8(TR1);
2944 b = tsfs & TSFS_INTR_MASK;
2946 return ((m * x) / 127) - b;
2949 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2951 static const struct v_table {
2952 u16 vd; /* in .1 mil */
2953 u16 vm; /* in .1 mil */
3084 if (dev_priv->info->is_mobile)
3085 return v_table[pxvid].vm;
3087 return v_table[pxvid].vd;
3090 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3092 struct timespec now, diff1;
3094 unsigned long diffms;
3097 getrawmonotonic(&now);
3098 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3100 /* Don't divide by 0 */
3101 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3105 count = I915_READ(GFXEC);
3107 if (count < dev_priv->ips.last_count2) {
3108 diff = ~0UL - dev_priv->ips.last_count2;
3111 diff = count - dev_priv->ips.last_count2;
3114 dev_priv->ips.last_count2 = count;
3115 dev_priv->ips.last_time2 = now;
3117 /* More magic constants... */
3119 diff = div_u64(diff, diffms * 10);
3120 dev_priv->ips.gfx_power = diff;
3123 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3125 if (dev_priv->info->gen != 5)
3128 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3130 __i915_update_gfx_val(dev_priv);
3132 lockmgr(&mchdev_lock, LK_RELEASE);
3135 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3137 unsigned long t, corr, state1, corr2, state2;
3140 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3141 pxvid = (pxvid >> 24) & 0x7f;
3142 ext_v = pvid_to_extvid(dev_priv, pxvid);
3146 t = i915_mch_val(dev_priv);
3148 /* Revel in the empirically derived constants */
3150 /* Correction factor in 1/100000 units */
3152 corr = ((t * 2349) + 135940);
3154 corr = ((t * 964) + 29317);
3156 corr = ((t * 301) + 1004);
3158 corr = corr * ((150142 * state1) / 10000 - 78642);
3160 corr2 = (corr * dev_priv->ips.corr);
3162 state2 = (corr2 * state1) / 10000;
3163 state2 /= 100; /* convert to mW */
3165 __i915_update_gfx_val(dev_priv);
3167 return dev_priv->ips.gfx_power + state2;
3170 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3174 if (dev_priv->info->gen != 5)
3177 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3179 val = __i915_gfx_val(dev_priv);
3181 lockmgr(&mchdev_lock, LK_RELEASE);
3187 * i915_read_mch_val - return value for IPS use
3189 * Calculate and return a value for the IPS driver to use when deciding whether
3190 * we have thermal and power headroom to increase CPU or GPU power budget.
3192 unsigned long i915_read_mch_val(void)
3194 struct drm_i915_private *dev_priv;
3195 unsigned long chipset_val, graphics_val, ret = 0;
3197 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3200 dev_priv = i915_mch_dev;
3202 chipset_val = __i915_chipset_val(dev_priv);
3203 graphics_val = __i915_gfx_val(dev_priv);
3205 ret = chipset_val + graphics_val;
3208 lockmgr(&mchdev_lock, LK_RELEASE);
3214 * i915_gpu_raise - raise GPU frequency limit
3216 * Raise the limit; IPS indicates we have thermal headroom.
3218 bool i915_gpu_raise(void)
3220 struct drm_i915_private *dev_priv;
3223 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3224 if (!i915_mch_dev) {
3228 dev_priv = i915_mch_dev;
3230 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3231 dev_priv->ips.max_delay--;
3234 lockmgr(&mchdev_lock, LK_RELEASE);
3240 * i915_gpu_lower - lower GPU frequency limit
3242 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3243 * frequency maximum.
3245 bool i915_gpu_lower(void)
3247 struct drm_i915_private *dev_priv;
3250 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3251 if (!i915_mch_dev) {
3255 dev_priv = i915_mch_dev;
3257 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3258 dev_priv->ips.max_delay++;
3261 lockmgr(&mchdev_lock, LK_RELEASE);
3267 * i915_gpu_busy - indicate GPU business to IPS
3269 * Tell the IPS driver whether or not the GPU is busy.
3271 bool i915_gpu_busy(void)
3273 struct drm_i915_private *dev_priv;
3274 struct intel_ring_buffer *ring;
3278 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3281 dev_priv = i915_mch_dev;
3283 for_each_ring(ring, dev_priv, i)
3284 ret |= !list_empty(&ring->request_list);
3287 lockmgr(&mchdev_lock, LK_RELEASE);
3293 * i915_gpu_turbo_disable - disable graphics turbo
3295 * Disable graphics turbo by resetting the max frequency and setting the
3296 * current frequency to the default.
3298 bool i915_gpu_turbo_disable(void)
3300 struct drm_i915_private *dev_priv;
3303 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3304 if (!i915_mch_dev) {
3308 dev_priv = i915_mch_dev;
3310 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3312 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3316 lockmgr(&mchdev_lock, LK_RELEASE);
3323 * Tells the intel_ips driver that the i915 driver is now loaded, if
3324 * IPS got loaded first.
3326 * This awkward dance is so that neither module has to depend on the
3327 * other in order for IPS to do the appropriate communication of
3328 * GPU turbo limits to i915.
3331 ips_ping_for_i915_load(void)
3335 link = symbol_get(ips_link_to_i915_driver);
3338 symbol_put(ips_link_to_i915_driver);
3343 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3345 /* We only register the i915 ips part with intel-ips once everything is
3346 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3347 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3348 i915_mch_dev = dev_priv;
3349 lockmgr(&mchdev_lock, LK_RELEASE);
3352 void intel_gpu_ips_teardown(void)
3354 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3355 i915_mch_dev = NULL;
3356 lockmgr(&mchdev_lock, LK_RELEASE);
3358 static void intel_init_emon(struct drm_device *dev)
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3365 /* Disable to program */
3369 /* Program energy weights for various events */
3370 I915_WRITE(SDEW, 0x15040d00);
3371 I915_WRITE(CSIEW0, 0x007f0000);
3372 I915_WRITE(CSIEW1, 0x1e220004);
3373 I915_WRITE(CSIEW2, 0x04000004);
3375 for (i = 0; i < 5; i++)
3376 I915_WRITE(PEW + (i * 4), 0);
3377 for (i = 0; i < 3; i++)
3378 I915_WRITE(DEW + (i * 4), 0);
3380 /* Program P-state weights to account for frequency power adjustment */
3381 for (i = 0; i < 16; i++) {
3382 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3383 unsigned long freq = intel_pxfreq(pxvidfreq);
3384 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3389 val *= (freq / 1000);
3391 val /= (127*127*900);
3393 DRM_ERROR("bad pxval: %ld\n", val);
3396 /* Render standby states get 0 weight */
3400 for (i = 0; i < 4; i++) {
3401 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3402 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3403 I915_WRITE(PXW + (i * 4), val);
3406 /* Adjust magic regs to magic values (more experimental results) */
3407 I915_WRITE(OGW0, 0);
3408 I915_WRITE(OGW1, 0);
3409 I915_WRITE(EG0, 0x00007f00);
3410 I915_WRITE(EG1, 0x0000000e);
3411 I915_WRITE(EG2, 0x000e0000);
3412 I915_WRITE(EG3, 0x68000300);
3413 I915_WRITE(EG4, 0x42000000);
3414 I915_WRITE(EG5, 0x00140031);
3418 for (i = 0; i < 8; i++)
3419 I915_WRITE(PXWL + (i * 4), 0);
3421 /* Enable PMON + select events */
3422 I915_WRITE(ECR, 0x80000019);
3424 lcfuse = I915_READ(LCFUSE02);
3426 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3429 void intel_disable_gt_powersave(struct drm_device *dev)
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3433 if (IS_IRONLAKE_M(dev)) {
3434 ironlake_disable_drps(dev);
3435 ironlake_disable_rc6(dev);
3436 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3437 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3438 mutex_lock(&dev_priv->rps.hw_lock);
3439 gen6_disable_rps(dev);
3440 mutex_unlock(&dev_priv->rps.hw_lock);
3444 static void intel_gen6_powersave_work(struct work_struct *work)
3446 struct drm_i915_private *dev_priv =
3447 container_of(work, struct drm_i915_private,
3448 rps.delayed_resume_work.work);
3449 struct drm_device *dev = dev_priv->dev;
3451 mutex_lock(&dev_priv->rps.hw_lock);
3452 gen6_enable_rps(dev);
3453 gen6_update_ring_freq(dev);
3454 mutex_unlock(&dev_priv->rps.hw_lock);
3457 void intel_enable_gt_powersave(struct drm_device *dev)
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3461 if (IS_IRONLAKE_M(dev)) {
3462 ironlake_enable_drps(dev);
3463 ironlake_enable_rc6(dev);
3464 intel_init_emon(dev);
3465 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3467 * PCU communication is slow and this doesn't need to be
3468 * done at any specific time, so do this out of our fast path
3469 * to make resume and init faster.
3471 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3472 round_jiffies_up_relative(HZ));
3476 static void ibx_init_clock_gating(struct drm_device *dev)
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3481 * On Ibex Peak and Cougar Point, we need to disable clock
3482 * gating for the panel power sequencer or it will fail to
3483 * start up when no ports are active.
3485 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3488 static void ironlake_init_clock_gating(struct drm_device *dev)
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3493 /* Required for FBC */
3494 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3495 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3496 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3498 I915_WRITE(PCH_3DCGDIS0,
3499 MARIUNIT_CLOCK_GATE_DISABLE |
3500 SVSMUNIT_CLOCK_GATE_DISABLE);
3501 I915_WRITE(PCH_3DCGDIS1,
3502 VFMUNIT_CLOCK_GATE_DISABLE);
3505 * According to the spec the following bits should be set in
3506 * order to enable memory self-refresh
3507 * The bit 22/21 of 0x42004
3508 * The bit 5 of 0x42020
3509 * The bit 15 of 0x45000
3511 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3512 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3513 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3514 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3515 I915_WRITE(DISP_ARB_CTL,
3516 (I915_READ(DISP_ARB_CTL) |
3518 I915_WRITE(WM3_LP_ILK, 0);
3519 I915_WRITE(WM2_LP_ILK, 0);
3520 I915_WRITE(WM1_LP_ILK, 0);
3523 * Based on the document from hardware guys the following bits
3524 * should be set unconditionally in order to enable FBC.
3525 * The bit 22 of 0x42000
3526 * The bit 22 of 0x42004
3527 * The bit 7,8,9 of 0x42020.
3529 if (IS_IRONLAKE_M(dev)) {
3530 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3531 I915_READ(ILK_DISPLAY_CHICKEN1) |
3533 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3534 I915_READ(ILK_DISPLAY_CHICKEN2) |
3538 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3540 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3541 I915_READ(ILK_DISPLAY_CHICKEN2) |
3542 ILK_ELPIN_409_SELECT);
3543 I915_WRITE(_3D_CHICKEN2,
3544 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3545 _3D_CHICKEN2_WM_READ_PIPELINED);
3547 /* WaDisableRenderCachePipelinedFlush */
3548 I915_WRITE(CACHE_MODE_0,
3549 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3551 ibx_init_clock_gating(dev);
3554 static void cpt_init_clock_gating(struct drm_device *dev)
3556 struct drm_i915_private *dev_priv = dev->dev_private;
3561 * On Ibex Peak and Cougar Point, we need to disable clock
3562 * gating for the panel power sequencer or it will fail to
3563 * start up when no ports are active.
3565 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3566 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3567 DPLS_EDP_PPS_FIX_DIS);
3568 /* The below fixes the weird display corruption, a few pixels shifted
3569 * downward, on (only) LVDS of some HP laptops with IVY.
3571 for_each_pipe(pipe) {
3572 val = TRANS_CHICKEN2_TIMING_OVERRIDE;
3573 if (dev_priv->fdi_rx_polarity_inverted)
3574 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3575 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3577 /* WADP0ClockGatingDisable */
3578 for_each_pipe(pipe) {
3579 I915_WRITE(TRANS_CHICKEN1(pipe),
3580 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3584 static void gen6_check_mch_setup(struct drm_device *dev)
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3589 tmp = I915_READ(MCH_SSKPD);
3590 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3591 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3592 DRM_INFO("This can cause pipe underruns and display issues.\n");
3593 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3597 static void gen6_init_clock_gating(struct drm_device *dev)
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3601 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3603 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3605 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3606 I915_READ(ILK_DISPLAY_CHICKEN2) |
3607 ILK_ELPIN_409_SELECT);
3609 /* WaDisableHiZPlanesWhenMSAAEnabled */
3610 I915_WRITE(_3D_CHICKEN,
3611 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3613 /* WaSetupGtModeTdRowDispatch */
3614 if (IS_SNB_GT1(dev))
3615 I915_WRITE(GEN6_GT_MODE,
3616 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3618 I915_WRITE(WM3_LP_ILK, 0);
3619 I915_WRITE(WM2_LP_ILK, 0);
3620 I915_WRITE(WM1_LP_ILK, 0);
3622 I915_WRITE(CACHE_MODE_0,
3623 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3625 I915_WRITE(GEN6_UCGCTL1,
3626 I915_READ(GEN6_UCGCTL1) |
3627 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3628 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3630 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3631 * gating disable must be set. Failure to set it results in
3632 * flickering pixels due to Z write ordering failures after
3633 * some amount of runtime in the Mesa "fire" demo, and Unigine
3634 * Sanctuary and Tropics, and apparently anything else with
3635 * alpha test or pixel discard.
3637 * According to the spec, bit 11 (RCCUNIT) must also be set,
3638 * but we didn't debug actual testcases to find it out.
3640 * Also apply WaDisableVDSUnitClockGating and
3641 * WaDisableRCPBUnitClockGating.
3643 I915_WRITE(GEN6_UCGCTL2,
3644 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3645 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3646 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3648 /* Bspec says we need to always set all mask bits. */
3649 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3650 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3653 * According to the spec the following bits should be
3654 * set in order to enable memory self-refresh and fbc:
3655 * The bit21 and bit22 of 0x42000
3656 * The bit21 and bit22 of 0x42004
3657 * The bit5 and bit7 of 0x42020
3658 * The bit14 of 0x70180
3659 * The bit14 of 0x71180
3661 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3662 I915_READ(ILK_DISPLAY_CHICKEN1) |
3663 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3664 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3665 I915_READ(ILK_DISPLAY_CHICKEN2) |
3666 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3667 I915_WRITE(ILK_DSPCLK_GATE_D,
3668 I915_READ(ILK_DSPCLK_GATE_D) |
3669 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3670 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3672 /* WaMbcDriverBootEnable */
3673 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3674 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3676 for_each_pipe(pipe) {
3677 I915_WRITE(DSPCNTR(pipe),
3678 I915_READ(DSPCNTR(pipe)) |
3679 DISPPLANE_TRICKLE_FEED_DISABLE);
3680 intel_flush_display_plane(dev_priv, pipe);
3683 /* The default value should be 0x200 according to docs, but the two
3684 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3685 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3686 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3688 cpt_init_clock_gating(dev);
3690 gen6_check_mch_setup(dev);
3693 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3695 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3697 reg &= ~GEN7_FF_SCHED_MASK;
3698 reg |= GEN7_FF_TS_SCHED_HW;
3699 reg |= GEN7_FF_VS_SCHED_HW;
3700 reg |= GEN7_FF_DS_SCHED_HW;
3702 /* WaVSRefCountFullforceMissDisable */
3703 if (IS_HASWELL(dev_priv->dev))
3704 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
3706 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3709 static void lpt_init_clock_gating(struct drm_device *dev)
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3714 * TODO: this bit should only be enabled when really needed, then
3715 * disabled when not needed anymore in order to save power.
3717 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3718 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3719 I915_READ(SOUTH_DSPCLK_GATE_D) |
3720 PCH_LP_PARTITION_LEVEL_DISABLE);
3723 static void haswell_init_clock_gating(struct drm_device *dev)
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3728 I915_WRITE(WM3_LP_ILK, 0);
3729 I915_WRITE(WM2_LP_ILK, 0);
3730 I915_WRITE(WM1_LP_ILK, 0);
3732 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3733 * This implements the WaDisableRCZUnitClockGating workaround.
3735 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3737 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3738 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3739 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3741 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3742 I915_WRITE(GEN7_L3CNTLREG1,
3743 GEN7_WA_FOR_GEN7_L3_CONTROL);
3744 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3745 GEN7_WA_L3_CHICKEN_MODE);
3747 /* This is required by WaCatErrorRejectionIssue */
3748 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3749 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3750 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3752 for_each_pipe(pipe) {
3753 I915_WRITE(DSPCNTR(pipe),
3754 I915_READ(DSPCNTR(pipe)) |
3755 DISPPLANE_TRICKLE_FEED_DISABLE);
3756 intel_flush_display_plane(dev_priv, pipe);
3759 gen7_setup_fixed_func_scheduler(dev_priv);
3761 /* WaDisable4x2SubspanOptimization */
3762 I915_WRITE(CACHE_MODE_1,
3763 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3765 /* WaMbcDriverBootEnable */
3766 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3767 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3769 /* XXX: This is a workaround for early silicon revisions and should be
3774 WM_DBG_DISALLOW_MULTIPLE_LP |
3775 WM_DBG_DISALLOW_SPRITE |
3776 WM_DBG_DISALLOW_MAXFIFO);
3778 lpt_init_clock_gating(dev);
3781 static void ivybridge_init_clock_gating(struct drm_device *dev)
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3787 I915_WRITE(WM3_LP_ILK, 0);
3788 I915_WRITE(WM2_LP_ILK, 0);
3789 I915_WRITE(WM1_LP_ILK, 0);
3791 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3793 /* WaDisableEarlyCull */
3794 I915_WRITE(_3D_CHICKEN3,
3795 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3797 /* WaDisableBackToBackFlipFix */
3798 I915_WRITE(IVB_CHICKEN3,
3799 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3800 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3802 /* WaDisablePSDDualDispatchEnable */
3803 if (IS_IVB_GT1(dev))
3804 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3805 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3807 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3808 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3810 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3811 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3812 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3814 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3815 I915_WRITE(GEN7_L3CNTLREG1,
3816 GEN7_WA_FOR_GEN7_L3_CONTROL);
3817 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3818 GEN7_WA_L3_CHICKEN_MODE);
3819 if (IS_IVB_GT1(dev))
3820 I915_WRITE(GEN7_ROW_CHICKEN2,
3821 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3823 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3824 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3827 /* WaForceL3Serialization */
3828 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3829 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3831 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3832 * gating disable must be set. Failure to set it results in
3833 * flickering pixels due to Z write ordering failures after
3834 * some amount of runtime in the Mesa "fire" demo, and Unigine
3835 * Sanctuary and Tropics, and apparently anything else with
3836 * alpha test or pixel discard.
3838 * According to the spec, bit 11 (RCCUNIT) must also be set,
3839 * but we didn't debug actual testcases to find it out.
3841 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3842 * This implements the WaDisableRCZUnitClockGating workaround.
3844 I915_WRITE(GEN6_UCGCTL2,
3845 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3846 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3848 /* This is required by WaCatErrorRejectionIssue */
3849 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3850 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3851 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3853 for_each_pipe(pipe) {
3854 I915_WRITE(DSPCNTR(pipe),
3855 I915_READ(DSPCNTR(pipe)) |
3856 DISPPLANE_TRICKLE_FEED_DISABLE);
3857 intel_flush_display_plane(dev_priv, pipe);
3860 /* WaMbcDriverBootEnable */
3861 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3862 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3864 gen7_setup_fixed_func_scheduler(dev_priv);
3866 /* WaDisable4x2SubspanOptimization */
3867 I915_WRITE(CACHE_MODE_1,
3868 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3870 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3871 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3872 snpcr |= GEN6_MBC_SNPCR_MED;
3873 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3875 cpt_init_clock_gating(dev);
3877 gen6_check_mch_setup(dev);
3880 static void valleyview_init_clock_gating(struct drm_device *dev)
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3885 I915_WRITE(WM3_LP_ILK, 0);
3886 I915_WRITE(WM2_LP_ILK, 0);
3887 I915_WRITE(WM1_LP_ILK, 0);
3889 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3891 /* WaDisableEarlyCull */
3892 I915_WRITE(_3D_CHICKEN3,
3893 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3895 /* WaDisableBackToBackFlipFix */
3896 I915_WRITE(IVB_CHICKEN3,
3897 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3898 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3900 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3901 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3903 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3904 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3905 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3907 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3908 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3909 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3911 /* WaForceL3Serialization */
3912 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3913 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3915 /* WaDisableDopClockGating */
3916 I915_WRITE(GEN7_ROW_CHICKEN2,
3917 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3919 /* WaForceL3Serialization */
3920 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3921 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3923 /* This is required by WaCatErrorRejectionIssue */
3924 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3925 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3926 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3928 /* WaMbcDriverBootEnable */
3929 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3930 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3933 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3934 * gating disable must be set. Failure to set it results in
3935 * flickering pixels due to Z write ordering failures after
3936 * some amount of runtime in the Mesa "fire" demo, and Unigine
3937 * Sanctuary and Tropics, and apparently anything else with
3938 * alpha test or pixel discard.
3940 * According to the spec, bit 11 (RCCUNIT) must also be set,
3941 * but we didn't debug actual testcases to find it out.
3943 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3944 * This implements the WaDisableRCZUnitClockGating workaround.
3946 * Also apply WaDisableVDSUnitClockGating and
3947 * WaDisableRCPBUnitClockGating.
3949 I915_WRITE(GEN6_UCGCTL2,
3950 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3951 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3952 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3953 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3954 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3956 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3958 for_each_pipe(pipe) {
3959 I915_WRITE(DSPCNTR(pipe),
3960 I915_READ(DSPCNTR(pipe)) |
3961 DISPPLANE_TRICKLE_FEED_DISABLE);
3962 intel_flush_display_plane(dev_priv, pipe);
3965 I915_WRITE(CACHE_MODE_1,
3966 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3969 * On ValleyView, the GUnit needs to signal the GT
3970 * when flip and other events complete. So enable
3971 * all the GUnit->GT interrupts here
3973 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3974 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3975 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3976 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3977 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3978 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3979 PLANEA_FLIPDONE_INT_EN);
3982 * WaDisableVLVClockGating_VBIIssue
3983 * Disable clock gating on th GCFG unit to prevent a delay
3984 * in the reporting of vblank events.
3986 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
3989 static void g4x_init_clock_gating(struct drm_device *dev)
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 uint32_t dspclk_gate;
3994 I915_WRITE(RENCLK_GATE_D1, 0);
3995 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3996 GS_UNIT_CLOCK_GATE_DISABLE |
3997 CL_UNIT_CLOCK_GATE_DISABLE);
3998 I915_WRITE(RAMCLK_GATE_D, 0);
3999 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4000 OVRUNIT_CLOCK_GATE_DISABLE |
4001 OVCUNIT_CLOCK_GATE_DISABLE;
4003 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4004 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4006 /* WaDisableRenderCachePipelinedFlush */
4007 I915_WRITE(CACHE_MODE_0,
4008 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4011 static void crestline_init_clock_gating(struct drm_device *dev)
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4015 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4016 I915_WRITE(RENCLK_GATE_D2, 0);
4017 I915_WRITE(DSPCLK_GATE_D, 0);
4018 I915_WRITE(RAMCLK_GATE_D, 0);
4019 I915_WRITE16(DEUC, 0);
4022 static void broadwater_init_clock_gating(struct drm_device *dev)
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4026 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4027 I965_RCC_CLOCK_GATE_DISABLE |
4028 I965_RCPB_CLOCK_GATE_DISABLE |
4029 I965_ISC_CLOCK_GATE_DISABLE |
4030 I965_FBC_CLOCK_GATE_DISABLE);
4031 I915_WRITE(RENCLK_GATE_D2, 0);
4034 static void gen3_init_clock_gating(struct drm_device *dev)
4036 struct drm_i915_private *dev_priv = dev->dev_private;
4037 u32 dstate = I915_READ(D_STATE);
4039 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4040 DSTATE_DOT_CLOCK_GATING;
4041 I915_WRITE(D_STATE, dstate);
4043 if (IS_PINEVIEW(dev))
4044 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4046 /* IIR "flip pending" means done if this bit is set */
4047 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4050 static void i85x_init_clock_gating(struct drm_device *dev)
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4054 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4057 static void i830_init_clock_gating(struct drm_device *dev)
4059 struct drm_i915_private *dev_priv = dev->dev_private;
4061 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4064 void intel_init_clock_gating(struct drm_device *dev)
4066 struct drm_i915_private *dev_priv = dev->dev_private;
4068 dev_priv->display.init_clock_gating(dev);
4071 void intel_set_power_well(struct drm_device *dev, bool enable)
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 bool is_enabled, enable_requested;
4077 if (!IS_HASWELL(dev))
4080 if (!i915_disable_power_well && !enable)
4083 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4084 is_enabled = tmp & HSW_PWR_WELL_STATE;
4085 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4088 if (!enable_requested)
4089 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4092 DRM_DEBUG_KMS("Enabling power well\n");
4093 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4094 HSW_PWR_WELL_STATE), 20))
4095 DRM_ERROR("Timeout enabling power well\n");
4098 if (enable_requested) {
4099 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4100 DRM_DEBUG_KMS("Requesting to disable the power well\n");
4106 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4107 * when not needed anymore. We have 4 registers that can request the power well
4108 * to be enabled, and it will only be disabled if none of the registers is
4109 * requesting it to be enabled.
4111 void intel_init_power_well(struct drm_device *dev)
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4115 if (!IS_HASWELL(dev))
4118 /* For now, we need the power well to be always enabled. */
4119 intel_set_power_well(dev, true);
4121 /* We're taking over the BIOS, so clear any requests made by it since
4122 * the driver is in charge now. */
4123 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4124 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4127 /* Set up chip specific power management-related functions */
4128 void intel_init_pm(struct drm_device *dev)
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4132 if (I915_HAS_FBC(dev)) {
4133 if (HAS_PCH_SPLIT(dev)) {
4134 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4135 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4136 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4137 } else if (IS_GM45(dev)) {
4138 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4139 dev_priv->display.enable_fbc = g4x_enable_fbc;
4140 dev_priv->display.disable_fbc = g4x_disable_fbc;
4141 } else if (IS_CRESTLINE(dev)) {
4142 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4143 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4144 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4146 /* 855GM needs testing */
4150 if (IS_PINEVIEW(dev))
4151 i915_pineview_get_mem_freq(dev);
4152 else if (IS_GEN5(dev))
4153 i915_ironlake_get_mem_freq(dev);
4155 /* For FIFO watermark updates */
4156 if (HAS_PCH_SPLIT(dev)) {
4158 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4159 dev_priv->display.update_wm = ironlake_update_wm;
4161 DRM_DEBUG_KMS("Failed to get proper latency. "
4163 dev_priv->display.update_wm = NULL;
4165 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4166 } else if (IS_GEN6(dev)) {
4167 if (SNB_READ_WM0_LATENCY()) {
4168 dev_priv->display.update_wm = sandybridge_update_wm;
4169 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4171 DRM_DEBUG_KMS("Failed to read display plane latency. "
4173 dev_priv->display.update_wm = NULL;
4175 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4176 } else if (IS_IVYBRIDGE(dev)) {
4177 /* FIXME: detect B0+ stepping and use auto training */
4178 if (SNB_READ_WM0_LATENCY()) {
4179 dev_priv->display.update_wm = ivybridge_update_wm;
4180 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4182 DRM_DEBUG_KMS("Failed to read display plane latency. "
4184 dev_priv->display.update_wm = NULL;
4186 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4187 } else if (IS_HASWELL(dev)) {
4188 if (SNB_READ_WM0_LATENCY()) {
4189 dev_priv->display.update_wm = sandybridge_update_wm;
4190 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4191 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4193 DRM_DEBUG_KMS("Failed to read display plane latency. "
4195 dev_priv->display.update_wm = NULL;
4197 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4199 dev_priv->display.update_wm = NULL;
4200 } else if (IS_VALLEYVIEW(dev)) {
4201 dev_priv->display.update_wm = valleyview_update_wm;
4202 dev_priv->display.init_clock_gating =
4203 valleyview_init_clock_gating;
4204 } else if (IS_PINEVIEW(dev)) {
4205 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4208 dev_priv->mem_freq)) {
4209 DRM_INFO("failed to find known CxSR latency "
4210 "(found ddr%s fsb freq %d, mem freq %d), "
4212 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4213 dev_priv->fsb_freq, dev_priv->mem_freq);
4214 /* Disable CxSR and never update its watermark again */
4215 pineview_disable_cxsr(dev);
4216 dev_priv->display.update_wm = NULL;
4218 dev_priv->display.update_wm = pineview_update_wm;
4219 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4220 } else if (IS_G4X(dev)) {
4221 dev_priv->display.update_wm = g4x_update_wm;
4222 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4223 } else if (IS_GEN4(dev)) {
4224 dev_priv->display.update_wm = i965_update_wm;
4225 if (IS_CRESTLINE(dev))
4226 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4227 else if (IS_BROADWATER(dev))
4228 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4229 } else if (IS_GEN3(dev)) {
4230 dev_priv->display.update_wm = i9xx_update_wm;
4231 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4232 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4233 } else if (IS_I865G(dev)) {
4234 dev_priv->display.update_wm = i830_update_wm;
4235 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4236 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4237 } else if (IS_I85X(dev)) {
4238 dev_priv->display.update_wm = i9xx_update_wm;
4239 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4240 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4242 dev_priv->display.update_wm = i830_update_wm;
4243 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4245 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4247 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4251 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4253 u32 gt_thread_status_mask;
4255 if (IS_HASWELL(dev_priv->dev))
4256 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4258 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4260 /* w/a for a sporadic read returning 0 by waiting for the GT
4261 * thread to wake up.
4263 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4264 DRM_ERROR("GT thread status wait timed out\n");
4267 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4269 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4270 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4273 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4277 if (IS_HASWELL(dev_priv->dev))
4278 forcewake_ack = FORCEWAKE_ACK_HSW;
4280 forcewake_ack = FORCEWAKE_ACK;
4282 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4283 FORCEWAKE_ACK_TIMEOUT_MS))
4284 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4286 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4287 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4289 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4290 FORCEWAKE_ACK_TIMEOUT_MS))
4291 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4293 __gen6_gt_wait_for_thread_c0(dev_priv);
4296 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4298 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4299 /* something from same cacheline, but !FORCEWAKE_MT */
4300 POSTING_READ(ECOBUS);
4303 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4307 if (IS_HASWELL(dev_priv->dev))
4308 forcewake_ack = FORCEWAKE_ACK_HSW;
4310 forcewake_ack = FORCEWAKE_MT_ACK;
4312 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4313 FORCEWAKE_ACK_TIMEOUT_MS))
4314 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4316 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4317 /* something from same cacheline, but !FORCEWAKE_MT */
4318 POSTING_READ(ECOBUS);
4320 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4321 FORCEWAKE_ACK_TIMEOUT_MS))
4322 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4324 __gen6_gt_wait_for_thread_c0(dev_priv);
4328 * Generally this is called implicitly by the register read function. However,
4329 * if some sequence requires the GT to not power down then this function should
4330 * be called at the beginning of the sequence followed by a call to
4331 * gen6_gt_force_wake_put() at the end of the sequence.
4333 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4336 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
4337 if (dev_priv->forcewake_count++ == 0)
4338 dev_priv->gt.force_wake_get(dev_priv);
4339 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
4342 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4345 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4346 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4347 "MMIO read or write has been dropped %x\n", gtfifodbg))
4348 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4351 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4353 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4354 /* something from same cacheline, but !FORCEWAKE */
4355 POSTING_READ(ECOBUS);
4356 gen6_gt_check_fifodbg(dev_priv);
4359 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4361 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4362 /* something from same cacheline, but !FORCEWAKE_MT */
4363 POSTING_READ(ECOBUS);
4364 gen6_gt_check_fifodbg(dev_priv);
4368 * see gen6_gt_force_wake_get()
4370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4372 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
4373 if (--dev_priv->forcewake_count == 0)
4374 dev_priv->gt.force_wake_put(dev_priv);
4375 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
4378 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4382 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4384 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4385 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4387 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4389 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4391 dev_priv->gt_fifo_count = fifo;
4393 dev_priv->gt_fifo_count--;
4398 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4400 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4401 /* something from same cacheline, but !FORCEWAKE_VLV */
4402 POSTING_READ(FORCEWAKE_ACK_VLV);
4405 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4407 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4408 FORCEWAKE_ACK_TIMEOUT_MS))
4409 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4411 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4413 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4414 FORCEWAKE_ACK_TIMEOUT_MS))
4415 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4417 __gen6_gt_wait_for_thread_c0(dev_priv);
4420 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4422 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4423 /* something from same cacheline, but !FORCEWAKE_VLV */
4424 POSTING_READ(FORCEWAKE_ACK_VLV);
4425 gen6_gt_check_fifodbg(dev_priv);
4428 void intel_gt_reset(struct drm_device *dev)
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4432 if (IS_VALLEYVIEW(dev)) {
4433 vlv_force_wake_reset(dev_priv);
4434 } else if (INTEL_INFO(dev)->gen >= 6) {
4435 __gen6_gt_force_wake_reset(dev_priv);
4436 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4437 __gen6_gt_force_wake_mt_reset(dev_priv);
4441 void intel_gt_init(struct drm_device *dev)
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4445 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
4447 intel_gt_reset(dev);
4449 if (IS_VALLEYVIEW(dev)) {
4450 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4451 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4452 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4453 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4454 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4455 } else if (IS_GEN6(dev)) {
4456 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4457 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4459 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4460 intel_gen6_powersave_work);
4463 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4467 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4468 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4472 I915_WRITE(GEN6_PCODE_DATA, *val);
4473 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4475 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4477 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4481 *val = I915_READ(GEN6_PCODE_DATA);
4482 I915_WRITE(GEN6_PCODE_DATA, 0);
4487 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4489 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4491 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4492 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4496 I915_WRITE(GEN6_PCODE_DATA, val);
4497 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4499 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4501 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4505 I915_WRITE(GEN6_PCODE_DATA, 0);