2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * SERIALIZATION API RULES:
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
74 * - ifmedia entry points will be serialized by the ifmedia code using the
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
83 * - The device driver typically holds the serializer at the time it wishes
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
96 #include "opt_ifpoll.h"
98 #include <sys/param.h>
100 #include <sys/endian.h>
101 #include <sys/interrupt.h>
102 #include <sys/kernel.h>
104 #include <sys/malloc.h>
105 #include <sys/mbuf.h>
106 #include <sys/proc.h>
107 #include <sys/rman.h>
108 #include <sys/serialize.h>
109 #include <sys/socket.h>
110 #include <sys/sockio.h>
111 #include <sys/sysctl.h>
112 #include <sys/systm.h>
115 #include <net/ethernet.h>
117 #include <net/if_arp.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_poll.h>
121 #include <net/ifq_var.h>
122 #include <net/vlan/if_vlan_var.h>
123 #include <net/vlan/if_vlan_ether.h>
125 #include <netinet/ip.h>
126 #include <netinet/tcp.h>
127 #include <netinet/udp.h>
129 #include <bus/pci/pcivar.h>
130 #include <bus/pci/pcireg.h>
132 #include <dev/netif/ig_hal/e1000_api.h>
133 #include <dev/netif/ig_hal/e1000_82571.h>
134 #include <dev/netif/em/if_em.h>
136 #define EM_NAME "Intel(R) PRO/1000 Network Connection "
137 #define EM_VER " 7.3.4"
139 #define _EM_DEVICE(id, ret) \
140 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
141 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
142 #define EM_DEVICE(id) _EM_DEVICE(id, 0)
143 #define EM_DEVICE_NULL { 0, 0, 0, NULL }
145 static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP_LOM),
150 EM_DEVICE(82540EP_LP),
154 EM_DEVICE(82541ER_LOM),
155 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI_LF),
158 EM_DEVICE(82541GI_MOBILE),
162 EM_DEVICE(82543GC_FIBER),
163 EM_DEVICE(82543GC_COPPER),
165 EM_DEVICE(82544EI_COPPER),
166 EM_DEVICE(82544EI_FIBER),
167 EM_DEVICE(82544GC_COPPER),
168 EM_DEVICE(82544GC_LOM),
170 EM_DEVICE(82545EM_COPPER),
171 EM_DEVICE(82545EM_FIBER),
172 EM_DEVICE(82545GM_COPPER),
173 EM_DEVICE(82545GM_FIBER),
174 EM_DEVICE(82545GM_SERDES),
176 EM_DEVICE(82546EB_COPPER),
177 EM_DEVICE(82546EB_FIBER),
178 EM_DEVICE(82546EB_QUAD_COPPER),
179 EM_DEVICE(82546GB_COPPER),
180 EM_DEVICE(82546GB_FIBER),
181 EM_DEVICE(82546GB_SERDES),
182 EM_DEVICE(82546GB_PCIE),
183 EM_DEVICE(82546GB_QUAD_COPPER),
184 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
187 EM_DEVICE(82547EI_MOBILE),
190 EM_EMX_DEVICE(82571EB_COPPER),
191 EM_EMX_DEVICE(82571EB_FIBER),
192 EM_EMX_DEVICE(82571EB_SERDES),
193 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
194 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
195 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
198 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
199 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201 EM_EMX_DEVICE(82572EI_COPPER),
202 EM_EMX_DEVICE(82572EI_FIBER),
203 EM_EMX_DEVICE(82572EI_SERDES),
204 EM_EMX_DEVICE(82572EI),
206 EM_EMX_DEVICE(82573E),
207 EM_EMX_DEVICE(82573E_IAMT),
208 EM_EMX_DEVICE(82573L),
212 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
213 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
215 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
217 EM_DEVICE(ICH8_IGP_M_AMT),
218 EM_DEVICE(ICH8_IGP_AMT),
219 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE_GT),
222 EM_DEVICE(ICH8_IFE_G),
223 EM_DEVICE(ICH8_IGP_M),
224 EM_DEVICE(ICH8_82567V_3),
226 EM_DEVICE(ICH9_IGP_M_AMT),
227 EM_DEVICE(ICH9_IGP_AMT),
228 EM_DEVICE(ICH9_IGP_C),
229 EM_DEVICE(ICH9_IGP_M),
230 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE_GT),
233 EM_DEVICE(ICH9_IFE_G),
236 EM_EMX_DEVICE(82574L),
237 EM_EMX_DEVICE(82574LA),
239 EM_DEVICE(ICH10_R_BM_LM),
240 EM_DEVICE(ICH10_R_BM_LF),
241 EM_DEVICE(ICH10_R_BM_V),
242 EM_DEVICE(ICH10_D_BM_LM),
243 EM_DEVICE(ICH10_D_BM_LF),
244 EM_DEVICE(ICH10_D_BM_V),
246 EM_DEVICE(PCH_M_HV_LM),
247 EM_DEVICE(PCH_M_HV_LC),
248 EM_DEVICE(PCH_D_HV_DM),
249 EM_DEVICE(PCH_D_HV_DC),
251 EM_DEVICE(PCH2_LV_LM),
252 EM_DEVICE(PCH2_LV_V),
254 /* required last entry */
258 static int em_probe(device_t);
259 static int em_attach(device_t);
260 static int em_detach(device_t);
261 static int em_shutdown(device_t);
262 static int em_suspend(device_t);
263 static int em_resume(device_t);
265 static void em_init(void *);
266 static void em_stop(struct adapter *);
267 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
268 static void em_start(struct ifnet *, struct ifaltq_subque *);
270 static void em_npoll(struct ifnet *, struct ifpoll_info *);
271 static void em_npoll_compat(struct ifnet *, void *, int);
273 static void em_watchdog(struct ifnet *);
274 static void em_media_status(struct ifnet *, struct ifmediareq *);
275 static int em_media_change(struct ifnet *);
276 static void em_timer(void *);
278 static void em_intr(void *);
279 static void em_intr_mask(void *);
280 static void em_intr_body(struct adapter *, boolean_t);
281 static void em_rxeof(struct adapter *, int);
282 static void em_txeof(struct adapter *);
283 static void em_tx_collect(struct adapter *);
284 static void em_tx_purge(struct adapter *);
285 static void em_enable_intr(struct adapter *);
286 static void em_disable_intr(struct adapter *);
288 static int em_dma_malloc(struct adapter *, bus_size_t,
289 struct em_dma_alloc *);
290 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
291 static void em_init_tx_ring(struct adapter *);
292 static int em_init_rx_ring(struct adapter *);
293 static int em_create_tx_ring(struct adapter *);
294 static int em_create_rx_ring(struct adapter *);
295 static void em_destroy_tx_ring(struct adapter *, int);
296 static void em_destroy_rx_ring(struct adapter *, int);
297 static int em_newbuf(struct adapter *, int, int);
298 static int em_encap(struct adapter *, struct mbuf **, int *, int *);
299 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
301 static int em_txcsum(struct adapter *, struct mbuf *,
302 uint32_t *, uint32_t *);
303 static int em_tso_pullup(struct adapter *, struct mbuf **);
304 static int em_tso_setup(struct adapter *, struct mbuf *,
305 uint32_t *, uint32_t *);
307 static int em_get_hw_info(struct adapter *);
308 static int em_is_valid_eaddr(const uint8_t *);
309 static int em_alloc_pci_res(struct adapter *);
310 static void em_free_pci_res(struct adapter *);
311 static int em_reset(struct adapter *);
312 static void em_setup_ifp(struct adapter *);
313 static void em_init_tx_unit(struct adapter *);
314 static void em_init_rx_unit(struct adapter *);
315 static void em_update_stats(struct adapter *);
316 static void em_set_promisc(struct adapter *);
317 static void em_disable_promisc(struct adapter *);
318 static void em_set_multi(struct adapter *);
319 static void em_update_link_status(struct adapter *);
320 static void em_smartspeed(struct adapter *);
321 static void em_set_itr(struct adapter *, uint32_t);
322 static void em_disable_aspm(struct adapter *);
324 /* Hardware workarounds */
325 static int em_82547_fifo_workaround(struct adapter *, int);
326 static void em_82547_update_fifo_head(struct adapter *, int);
327 static int em_82547_tx_fifo_reset(struct adapter *);
328 static void em_82547_move_tail(void *);
329 static void em_82547_move_tail_serialized(struct adapter *);
330 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
332 static void em_print_debug_info(struct adapter *);
333 static void em_print_nvm_info(struct adapter *);
334 static void em_print_hw_stats(struct adapter *);
336 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
337 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
338 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
339 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
340 static void em_add_sysctl(struct adapter *adapter);
342 /* Management and WOL Support */
343 static void em_get_mgmt(struct adapter *);
344 static void em_rel_mgmt(struct adapter *);
345 static void em_get_hw_control(struct adapter *);
346 static void em_rel_hw_control(struct adapter *);
347 static void em_enable_wol(device_t);
349 static device_method_t em_methods[] = {
350 /* Device interface */
351 DEVMETHOD(device_probe, em_probe),
352 DEVMETHOD(device_attach, em_attach),
353 DEVMETHOD(device_detach, em_detach),
354 DEVMETHOD(device_shutdown, em_shutdown),
355 DEVMETHOD(device_suspend, em_suspend),
356 DEVMETHOD(device_resume, em_resume),
360 static driver_t em_driver = {
363 sizeof(struct adapter),
366 static devclass_t em_devclass;
368 DECLARE_DUMMY_MODULE(if_em);
369 MODULE_DEPEND(em, ig_hal, 1, 1, 1);
370 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
375 static int em_int_throttle_ceil = EM_DEFAULT_ITR;
376 static int em_rxd = EM_DEFAULT_RXD;
377 static int em_txd = EM_DEFAULT_TXD;
378 static int em_smart_pwr_down = 0;
380 /* Controls whether promiscuous also shows bad packets */
381 static int em_debug_sbp = FALSE;
383 static int em_82573_workaround = 1;
384 static int em_msi_enable = 1;
386 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
387 TUNABLE_INT("hw.em.rxd", &em_rxd);
388 TUNABLE_INT("hw.em.txd", &em_txd);
389 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
390 TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
391 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
392 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
394 /* Global used in WOL setup with multiport cards */
395 static int em_global_quad_port_a = 0;
397 /* Set this to one to display debug statistics */
398 static int em_display_debug_stats = 0;
400 #if !defined(KTR_IF_EM)
401 #define KTR_IF_EM KTR_ALL
403 KTR_INFO_MASTER(if_em);
404 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
405 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
406 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
407 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
408 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
409 #define logif(name) KTR_LOG(if_em_ ## name)
412 em_probe(device_t dev)
414 const struct em_vendor_info *ent;
417 vid = pci_get_vendor(dev);
418 did = pci_get_device(dev);
420 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
421 if (vid == ent->vendor_id && did == ent->device_id) {
422 device_set_desc(dev, ent->desc);
423 device_set_async_attach(dev, TRUE);
431 em_attach(device_t dev)
433 struct adapter *adapter = device_get_softc(dev);
434 struct ifnet *ifp = &adapter->arpcom.ac_if;
437 uint16_t eeprom_data, device_id, apme_mask;
438 driver_intr_t *intr_func;
440 adapter->dev = adapter->osdep.dev = dev;
442 callout_init_mp(&adapter->timer);
443 callout_init_mp(&adapter->tx_fifo_timer);
445 /* Determine hardware and mac info */
446 error = em_get_hw_info(adapter);
448 device_printf(dev, "Identify hardware failed\n");
452 /* Setup PCI resources */
453 error = em_alloc_pci_res(adapter);
455 device_printf(dev, "Allocation of PCI resources failed\n");
460 * For ICH8 and family we need to map the flash memory,
461 * and this must happen after the MAC is identified.
463 if (adapter->hw.mac.type == e1000_ich8lan ||
464 adapter->hw.mac.type == e1000_ich9lan ||
465 adapter->hw.mac.type == e1000_ich10lan ||
466 adapter->hw.mac.type == e1000_pchlan ||
467 adapter->hw.mac.type == e1000_pch2lan) {
468 adapter->flash_rid = EM_BAR_FLASH;
470 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
471 &adapter->flash_rid, RF_ACTIVE);
472 if (adapter->flash == NULL) {
473 device_printf(dev, "Mapping of Flash failed\n");
477 adapter->osdep.flash_bus_space_tag =
478 rman_get_bustag(adapter->flash);
479 adapter->osdep.flash_bus_space_handle =
480 rman_get_bushandle(adapter->flash);
483 * This is used in the shared code
484 * XXX this goof is actually not used.
486 adapter->hw.flash_address = (uint8_t *)adapter->flash;
489 switch (adapter->hw.mac.type) {
493 * Pullup extra 4bytes into the first data segment, see:
494 * 82571/82572 specification update errata #7
497 * 4bytes instead of 2bytes, which are mentioned in the
498 * errata, are pulled; mainly to keep rest of the data
501 adapter->flags |= EM_FLAG_TSO_PULLEX;
506 case e1000_80003es2lan:
507 adapter->flags |= EM_FLAG_TSO;
514 /* Do Shared Code initialization */
515 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
516 device_printf(dev, "Setup of Shared code failed\n");
521 e1000_get_bus_info(&adapter->hw);
524 * Validate number of transmit and receive descriptors. It
525 * must not exceed hardware maximum, and must be multiple
526 * of E1000_DBA_ALIGN.
528 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
529 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
530 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
531 em_txd < EM_MIN_TXD) {
532 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
533 EM_DEFAULT_TXD, em_txd);
534 adapter->num_tx_desc = EM_DEFAULT_TXD;
536 adapter->num_tx_desc = em_txd;
538 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
539 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
540 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
541 em_rxd < EM_MIN_RXD) {
542 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
543 EM_DEFAULT_RXD, em_rxd);
544 adapter->num_rx_desc = EM_DEFAULT_RXD;
546 adapter->num_rx_desc = em_rxd;
549 adapter->hw.mac.autoneg = DO_AUTO_NEG;
550 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
551 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
552 adapter->rx_buffer_len = MCLBYTES;
555 * Interrupt throttle rate
557 if (em_int_throttle_ceil == 0) {
558 adapter->int_throttle_ceil = 0;
560 int throttle = em_int_throttle_ceil;
563 throttle = EM_DEFAULT_ITR;
565 /* Recalculate the tunable value to get the exact frequency. */
566 throttle = 1000000000 / 256 / throttle;
568 /* Upper 16bits of ITR is reserved and should be zero */
569 if (throttle & 0xffff0000)
570 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
572 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
575 e1000_init_script_state_82541(&adapter->hw, TRUE);
576 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
579 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
580 adapter->hw.phy.mdix = AUTO_ALL_MODES;
581 adapter->hw.phy.disable_polarity_correction = FALSE;
582 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
585 /* Set the frame limits assuming standard ethernet sized frames. */
586 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
587 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
589 /* This controls when hardware reports transmit completion status. */
590 adapter->hw.mac.report_tx_early = 1;
593 * Create top level busdma tag
595 error = bus_dma_tag_create(NULL, 1, 0,
596 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
598 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
599 0, &adapter->parent_dtag);
601 device_printf(dev, "could not create top level DMA tag\n");
606 * Allocate Transmit Descriptor ring
608 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
610 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
612 device_printf(dev, "Unable to allocate tx_desc memory\n");
615 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
618 * Allocate Receive Descriptor ring
620 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
622 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
624 device_printf(dev, "Unable to allocate rx_desc memory\n");
627 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
629 /* Allocate multicast array memory. */
630 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
633 /* Indicate SOL/IDER usage */
634 if (e1000_check_reset_block(&adapter->hw)) {
636 "PHY reset is blocked due to SOL/IDER session.\n");
640 * Start from a known state, this is important in reading the
641 * nvm and mac from that.
643 e1000_reset_hw(&adapter->hw);
645 /* Make sure we have a good EEPROM before we read from it */
646 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
648 * Some PCI-E parts fail the first check due to
649 * the link being in sleep state, call it again,
650 * if it fails a second time its a real issue.
652 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
654 "The EEPROM Checksum Is Not Valid\n");
660 /* Copy the permanent MAC address out of the EEPROM */
661 if (e1000_read_mac_addr(&adapter->hw) < 0) {
662 device_printf(dev, "EEPROM read error while reading MAC"
667 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
668 device_printf(dev, "Invalid MAC address\n");
673 /* Allocate transmit descriptors and buffers */
674 error = em_create_tx_ring(adapter);
676 device_printf(dev, "Could not setup transmit structures\n");
680 /* Allocate receive descriptors and buffers */
681 error = em_create_rx_ring(adapter);
683 device_printf(dev, "Could not setup receive structures\n");
687 /* Manually turn off all interrupts */
688 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
690 /* Determine if we have to control management hardware */
691 if (e1000_enable_mng_pass_thru(&adapter->hw))
692 adapter->flags |= EM_FLAG_HAS_MGMT;
697 apme_mask = EM_EEPROM_APME;
699 switch (adapter->hw.mac.type) {
706 adapter->flags |= EM_FLAG_HAS_AMT;
710 case e1000_82546_rev_3:
713 case e1000_80003es2lan:
714 if (adapter->hw.bus.func == 1) {
715 e1000_read_nvm(&adapter->hw,
716 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
718 e1000_read_nvm(&adapter->hw,
719 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
728 apme_mask = E1000_WUC_APME;
729 adapter->flags |= EM_FLAG_HAS_AMT;
730 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
734 e1000_read_nvm(&adapter->hw,
735 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
738 if (eeprom_data & apme_mask)
739 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
742 * We have the eeprom settings, now apply the special cases
743 * where the eeprom may be wrong or the board won't support
744 * wake on lan on a particular port
746 device_id = pci_get_device(dev);
748 case E1000_DEV_ID_82546GB_PCIE:
752 case E1000_DEV_ID_82546EB_FIBER:
753 case E1000_DEV_ID_82546GB_FIBER:
754 case E1000_DEV_ID_82571EB_FIBER:
756 * Wake events only supported on port A for dual fiber
757 * regardless of eeprom setting
759 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
764 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
765 case E1000_DEV_ID_82571EB_QUAD_COPPER:
766 case E1000_DEV_ID_82571EB_QUAD_FIBER:
767 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
768 /* if quad port adapter, disable WoL on all but port A */
769 if (em_global_quad_port_a != 0)
771 /* Reset for multiple quad port adapters */
772 if (++em_global_quad_port_a == 4)
773 em_global_quad_port_a = 0;
777 /* XXX disable wol */
780 /* Setup OS specific network interface */
781 em_setup_ifp(adapter);
783 /* Add sysctl tree, must after em_setup_ifp() */
784 em_add_sysctl(adapter);
788 ifpoll_compat_setup(&adapter->npoll,
789 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev),
793 /* Reset the hardware */
794 error = em_reset(adapter);
796 device_printf(dev, "Unable to reset the hardware\n");
800 /* Initialize statistics */
801 em_update_stats(adapter);
803 adapter->hw.mac.get_link_status = 1;
804 em_update_link_status(adapter);
806 /* Do we need workaround for 82544 PCI-X adapter? */
807 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
808 adapter->hw.mac.type == e1000_82544)
809 adapter->pcix_82544 = TRUE;
811 adapter->pcix_82544 = FALSE;
813 if (adapter->pcix_82544) {
815 * 82544 on PCI-X may split one TX segment
816 * into two TX descs, so we double its number
817 * of spare TX desc here.
819 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
821 adapter->spare_tx_desc = EM_TX_SPARE;
823 if (adapter->flags & EM_FLAG_TSO)
824 adapter->spare_tx_desc = EM_TX_SPARE_TSO;
825 adapter->tx_wreg_nsegs = 8;
828 * Keep following relationship between spare_tx_desc, oact_tx_desc
830 * (spare_tx_desc + EM_TX_RESERVED) <=
831 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
833 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
834 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
835 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
836 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
837 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
839 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
840 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
841 adapter->tx_int_nsegs = adapter->oact_tx_desc;
843 /* Non-AMT based hardware can now take control from firmware */
844 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
845 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571)
846 em_get_hw_control(adapter);
849 * Missing Interrupt Following ICR read:
851 * 82571/82572 specification update errata #76
852 * 82573 specification update errata #31
853 * 82574 specification update errata #12
854 * 82583 specification update errata #4
857 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
858 (adapter->hw.mac.type == e1000_82571 ||
859 adapter->hw.mac.type == e1000_82572 ||
860 adapter->hw.mac.type == e1000_82573 ||
861 adapter->hw.mac.type == e1000_82574 ||
862 adapter->hw.mac.type == e1000_82583))
863 intr_func = em_intr_mask;
865 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
866 intr_func, adapter, &adapter->intr_tag,
869 device_printf(dev, "Failed to register interrupt handler");
870 ether_ifdetach(&adapter->arpcom.ac_if);
874 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
882 em_detach(device_t dev)
884 struct adapter *adapter = device_get_softc(dev);
886 if (device_is_attached(dev)) {
887 struct ifnet *ifp = &adapter->arpcom.ac_if;
889 lwkt_serialize_enter(ifp->if_serializer);
893 e1000_phy_hw_reset(&adapter->hw);
895 em_rel_mgmt(adapter);
896 em_rel_hw_control(adapter);
899 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
901 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
905 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
907 lwkt_serialize_exit(ifp->if_serializer);
910 } else if (adapter->memory != NULL) {
911 em_rel_hw_control(adapter);
913 bus_generic_detach(dev);
915 em_free_pci_res(adapter);
917 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
918 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
920 /* Free Transmit Descriptor ring */
921 if (adapter->tx_desc_base)
922 em_dma_free(adapter, &adapter->txdma);
924 /* Free Receive Descriptor ring */
925 if (adapter->rx_desc_base)
926 em_dma_free(adapter, &adapter->rxdma);
928 /* Free top level busdma tag */
929 if (adapter->parent_dtag != NULL)
930 bus_dma_tag_destroy(adapter->parent_dtag);
932 /* Free sysctl tree */
933 if (adapter->sysctl_tree != NULL)
934 sysctl_ctx_free(&adapter->sysctl_ctx);
936 if (adapter->mta != NULL)
937 kfree(adapter->mta, M_DEVBUF);
943 em_shutdown(device_t dev)
945 return em_suspend(dev);
949 em_suspend(device_t dev)
951 struct adapter *adapter = device_get_softc(dev);
952 struct ifnet *ifp = &adapter->arpcom.ac_if;
954 lwkt_serialize_enter(ifp->if_serializer);
958 em_rel_mgmt(adapter);
959 em_rel_hw_control(adapter);
962 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
963 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
967 lwkt_serialize_exit(ifp->if_serializer);
969 return bus_generic_suspend(dev);
973 em_resume(device_t dev)
975 struct adapter *adapter = device_get_softc(dev);
976 struct ifnet *ifp = &adapter->arpcom.ac_if;
978 lwkt_serialize_enter(ifp->if_serializer);
980 if (adapter->hw.mac.type == e1000_pch2lan)
981 e1000_resume_workarounds_pchlan(&adapter->hw);
984 em_get_mgmt(adapter);
987 lwkt_serialize_exit(ifp->if_serializer);
989 return bus_generic_resume(dev);
993 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
995 struct adapter *adapter = ifp->if_softc;
997 int idx = -1, nsegs = 0;
999 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1000 ASSERT_SERIALIZED(ifp->if_serializer);
1002 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1005 if (!adapter->link_active) {
1006 ifq_purge(&ifp->if_snd);
1010 while (!ifq_is_empty(&ifp->if_snd)) {
1011 /* Now do we at least have a minimal? */
1012 if (EM_IS_OACTIVE(adapter)) {
1013 em_tx_collect(adapter);
1014 if (EM_IS_OACTIVE(adapter)) {
1015 ifq_set_oactive(&ifp->if_snd);
1016 adapter->no_tx_desc_avail1++;
1022 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1026 if (em_encap(adapter, &m_head, &nsegs, &idx)) {
1028 em_tx_collect(adapter);
1032 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) {
1033 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
1038 /* Send a copy of the frame to the BPF listener */
1039 ETHER_BPF_MTAP(ifp, m_head);
1041 /* Set timeout in case hardware has problems transmitting. */
1042 ifp->if_timer = EM_TX_TIMEOUT;
1045 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
1049 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1051 struct adapter *adapter = ifp->if_softc;
1052 struct ifreq *ifr = (struct ifreq *)data;
1053 uint16_t eeprom_data = 0;
1054 int max_frame_size, mask, reinit;
1057 ASSERT_SERIALIZED(ifp->if_serializer);
1061 switch (adapter->hw.mac.type) {
1064 * 82573 only supports jumbo frames
1065 * if ASPM is disabled.
1067 e1000_read_nvm(&adapter->hw,
1068 NVM_INIT_3GIO_3, 1, &eeprom_data);
1069 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1070 max_frame_size = ETHER_MAX_LEN;
1075 /* Limit Jumbo Frame size */
1079 case e1000_ich10lan:
1083 case e1000_80003es2lan:
1084 max_frame_size = 9234;
1088 max_frame_size = 4096;
1091 /* Adapters that do not support jumbo frames */
1094 max_frame_size = ETHER_MAX_LEN;
1098 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1101 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1107 ifp->if_mtu = ifr->ifr_mtu;
1108 adapter->max_frame_size =
1109 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1111 if (ifp->if_flags & IFF_RUNNING)
1116 if (ifp->if_flags & IFF_UP) {
1117 if ((ifp->if_flags & IFF_RUNNING)) {
1118 if ((ifp->if_flags ^ adapter->if_flags) &
1119 (IFF_PROMISC | IFF_ALLMULTI)) {
1120 em_disable_promisc(adapter);
1121 em_set_promisc(adapter);
1126 } else if (ifp->if_flags & IFF_RUNNING) {
1129 adapter->if_flags = ifp->if_flags;
1134 if (ifp->if_flags & IFF_RUNNING) {
1135 em_disable_intr(adapter);
1136 em_set_multi(adapter);
1137 if (adapter->hw.mac.type == e1000_82542 &&
1138 adapter->hw.revision_id == E1000_REVISION_2)
1139 em_init_rx_unit(adapter);
1140 #ifdef IFPOLL_ENABLE
1141 if (!(ifp->if_flags & IFF_NPOLLING))
1143 em_enable_intr(adapter);
1148 /* Check SOL/IDER usage */
1149 if (e1000_check_reset_block(&adapter->hw)) {
1150 device_printf(adapter->dev, "Media change is"
1151 " blocked due to SOL/IDER session.\n");
1157 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1162 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1163 if (mask & IFCAP_RXCSUM) {
1164 ifp->if_capenable ^= IFCAP_RXCSUM;
1167 if (mask & IFCAP_TXCSUM) {
1168 ifp->if_capenable ^= IFCAP_TXCSUM;
1169 if (ifp->if_capenable & IFCAP_TXCSUM)
1170 ifp->if_hwassist |= EM_CSUM_FEATURES;
1172 ifp->if_hwassist &= ~EM_CSUM_FEATURES;
1174 if (mask & IFCAP_TSO) {
1175 ifp->if_capenable ^= IFCAP_TSO;
1176 if (ifp->if_capenable & IFCAP_TSO)
1177 ifp->if_hwassist |= CSUM_TSO;
1179 ifp->if_hwassist &= ~CSUM_TSO;
1181 if (mask & IFCAP_VLAN_HWTAGGING) {
1182 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1185 if (reinit && (ifp->if_flags & IFF_RUNNING))
1190 error = ether_ioctl(ifp, command, data);
1197 em_watchdog(struct ifnet *ifp)
1199 struct adapter *adapter = ifp->if_softc;
1201 ASSERT_SERIALIZED(ifp->if_serializer);
1204 * The timer is set to 5 every time start queues a packet.
1205 * Then txeof keeps resetting it as long as it cleans at
1206 * least one descriptor.
1207 * Finally, anytime all descriptors are clean the timer is
1211 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1212 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1214 * If we reach here, all TX jobs are completed and
1215 * the TX engine should have been idled for some time.
1216 * We don't need to call if_devstart() here.
1218 ifq_clr_oactive(&ifp->if_snd);
1224 * If we are in this routine because of pause frames, then
1225 * don't reset the hardware.
1227 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1228 E1000_STATUS_TXOFF) {
1229 ifp->if_timer = EM_TX_TIMEOUT;
1233 if (e1000_check_for_link(&adapter->hw) == 0)
1234 if_printf(ifp, "watchdog timeout -- resetting\n");
1237 adapter->watchdog_events++;
1241 if (!ifq_is_empty(&ifp->if_snd))
1248 struct adapter *adapter = xsc;
1249 struct ifnet *ifp = &adapter->arpcom.ac_if;
1250 device_t dev = adapter->dev;
1252 ASSERT_SERIALIZED(ifp->if_serializer);
1256 /* Get the latest mac address, User can use a LAA */
1257 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1259 /* Put the address into the Receive Address Array */
1260 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1263 * With the 82571 adapter, RAR[0] may be overwritten
1264 * when the other port is reset, we make a duplicate
1265 * in RAR[14] for that eventuality, this assures
1266 * the interface continues to function.
1268 if (adapter->hw.mac.type == e1000_82571) {
1269 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1270 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1271 E1000_RAR_ENTRIES - 1);
1274 /* Reset the hardware */
1275 if (em_reset(adapter)) {
1276 device_printf(dev, "Unable to reset the hardware\n");
1277 /* XXX em_stop()? */
1280 em_update_link_status(adapter);
1282 /* Setup VLAN support, basic and offload if available */
1283 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1285 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1288 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1289 ctrl |= E1000_CTRL_VME;
1290 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1293 /* Configure for OS presence */
1294 em_get_mgmt(adapter);
1296 /* Prepare transmit descriptors and buffers */
1297 em_init_tx_ring(adapter);
1298 em_init_tx_unit(adapter);
1300 /* Setup Multicast table */
1301 em_set_multi(adapter);
1303 /* Prepare receive descriptors and buffers */
1304 if (em_init_rx_ring(adapter)) {
1305 device_printf(dev, "Could not setup receive structures\n");
1309 em_init_rx_unit(adapter);
1311 /* Don't lose promiscuous settings */
1312 em_set_promisc(adapter);
1314 ifp->if_flags |= IFF_RUNNING;
1315 ifq_clr_oactive(&ifp->if_snd);
1317 callout_reset(&adapter->timer, hz, em_timer, adapter);
1318 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1320 /* MSI/X configuration for 82574 */
1321 if (adapter->hw.mac.type == e1000_82574) {
1324 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1325 tmp |= E1000_CTRL_EXT_PBA_CLR;
1326 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1329 * Set the IVAR - interrupt vector routing.
1330 * Each nibble represents a vector, high bit
1331 * is enable, other 3 bits are the MSIX table
1332 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1333 * Link (other) to 2, hence the magic number.
1335 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1338 #ifdef IFPOLL_ENABLE
1340 * Only enable interrupts if we are not polling, make sure
1341 * they are off otherwise.
1343 if (ifp->if_flags & IFF_NPOLLING)
1344 em_disable_intr(adapter);
1346 #endif /* IFPOLL_ENABLE */
1347 em_enable_intr(adapter);
1349 /* AMT based hardware can now take control from firmware */
1350 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
1351 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) &&
1352 adapter->hw.mac.type >= e1000_82571)
1353 em_get_hw_control(adapter);
1356 #ifdef IFPOLL_ENABLE
1359 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1361 struct adapter *adapter = ifp->if_softc;
1363 ASSERT_SERIALIZED(ifp->if_serializer);
1365 if (adapter->npoll.ifpc_stcount-- == 0) {
1368 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac;
1370 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1371 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1372 callout_stop(&adapter->timer);
1373 adapter->hw.mac.get_link_status = 1;
1374 em_update_link_status(adapter);
1375 callout_reset(&adapter->timer, hz, em_timer, adapter);
1379 em_rxeof(adapter, count);
1382 if (!ifq_is_empty(&ifp->if_snd))
1387 em_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1389 struct adapter *adapter = ifp->if_softc;
1391 ASSERT_SERIALIZED(ifp->if_serializer);
1394 int cpuid = adapter->npoll.ifpc_cpuid;
1396 info->ifpi_rx[cpuid].poll_func = em_npoll_compat;
1397 info->ifpi_rx[cpuid].arg = NULL;
1398 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1400 if (ifp->if_flags & IFF_RUNNING)
1401 em_disable_intr(adapter);
1402 ifq_set_cpuid(&ifp->if_snd, cpuid);
1404 if (ifp->if_flags & IFF_RUNNING)
1405 em_enable_intr(adapter);
1406 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
1410 #endif /* IFPOLL_ENABLE */
1415 em_intr_body(xsc, TRUE);
1419 em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1421 struct ifnet *ifp = &adapter->arpcom.ac_if;
1425 ASSERT_SERIALIZED(ifp->if_serializer);
1427 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1430 ((adapter->hw.mac.type >= e1000_82571 &&
1431 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1438 * XXX: some laptops trigger several spurious interrupts
1439 * on em(4) when in the resume cycle. The ICR register
1440 * reports all-ones value in this case. Processing such
1441 * interrupts would lead to a freeze. I don't know why.
1443 if (reg_icr == 0xffffffff) {
1448 if (ifp->if_flags & IFF_RUNNING) {
1450 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
1451 em_rxeof(adapter, -1);
1452 if (reg_icr & E1000_ICR_TXDW) {
1454 if (!ifq_is_empty(&ifp->if_snd))
1459 /* Link status change */
1460 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1461 callout_stop(&adapter->timer);
1462 adapter->hw.mac.get_link_status = 1;
1463 em_update_link_status(adapter);
1465 /* Deal with TX cruft when link lost */
1466 em_tx_purge(adapter);
1468 callout_reset(&adapter->timer, hz, em_timer, adapter);
1471 if (reg_icr & E1000_ICR_RXO)
1472 adapter->rx_overruns++;
1478 em_intr_mask(void *xsc)
1480 struct adapter *adapter = xsc;
1482 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1485 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1486 * so don't check it.
1488 em_intr_body(adapter, FALSE);
1489 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1493 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1495 struct adapter *adapter = ifp->if_softc;
1496 u_char fiber_type = IFM_1000_SX;
1498 ASSERT_SERIALIZED(ifp->if_serializer);
1500 em_update_link_status(adapter);
1502 ifmr->ifm_status = IFM_AVALID;
1503 ifmr->ifm_active = IFM_ETHER;
1505 if (!adapter->link_active)
1508 ifmr->ifm_status |= IFM_ACTIVE;
1510 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1511 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1512 if (adapter->hw.mac.type == e1000_82545)
1513 fiber_type = IFM_1000_LX;
1514 ifmr->ifm_active |= fiber_type | IFM_FDX;
1516 switch (adapter->link_speed) {
1518 ifmr->ifm_active |= IFM_10_T;
1521 ifmr->ifm_active |= IFM_100_TX;
1525 ifmr->ifm_active |= IFM_1000_T;
1528 if (adapter->link_duplex == FULL_DUPLEX)
1529 ifmr->ifm_active |= IFM_FDX;
1531 ifmr->ifm_active |= IFM_HDX;
1536 em_media_change(struct ifnet *ifp)
1538 struct adapter *adapter = ifp->if_softc;
1539 struct ifmedia *ifm = &adapter->media;
1541 ASSERT_SERIALIZED(ifp->if_serializer);
1543 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1546 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1548 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1549 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1555 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1556 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1560 adapter->hw.mac.autoneg = FALSE;
1561 adapter->hw.phy.autoneg_advertised = 0;
1562 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1563 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1565 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1569 adapter->hw.mac.autoneg = FALSE;
1570 adapter->hw.phy.autoneg_advertised = 0;
1571 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1572 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1574 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1578 if_printf(ifp, "Unsupported media type\n");
1588 em_encap(struct adapter *adapter, struct mbuf **m_headp,
1589 int *segs_used, int *idx)
1591 bus_dma_segment_t segs[EM_MAX_SCATTER];
1593 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1594 struct e1000_tx_desc *ctxd = NULL;
1595 struct mbuf *m_head = *m_headp;
1596 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
1597 int maxsegs, nsegs, i, j, first, last = 0, error;
1599 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1600 error = em_tso_pullup(adapter, m_headp);
1606 txd_upper = txd_lower = 0;
1610 * Capture the first descriptor index, this descriptor
1611 * will have the index of the EOP which is the only one
1612 * that now gets a DONE bit writeback.
1614 first = adapter->next_avail_tx_desc;
1615 tx_buffer = &adapter->tx_buffer_area[first];
1616 tx_buffer_mapped = tx_buffer;
1617 map = tx_buffer->map;
1619 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1620 KASSERT(maxsegs >= adapter->spare_tx_desc,
1621 ("not enough spare TX desc"));
1622 if (adapter->pcix_82544) {
1623 /* Half it; see the comment in em_attach() */
1626 if (maxsegs > EM_MAX_SCATTER)
1627 maxsegs = EM_MAX_SCATTER;
1629 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1630 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1632 if (error == ENOBUFS)
1633 adapter->mbuf_alloc_failed++;
1635 adapter->no_tx_dma_setup++;
1641 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1644 adapter->tx_nsegs += nsegs;
1645 *segs_used += nsegs;
1647 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1648 /* TSO will consume one TX desc */
1649 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower);
1650 adapter->tx_nsegs += i;
1652 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
1653 /* TX csum offloading will consume one TX desc */
1654 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower);
1655 adapter->tx_nsegs += i;
1658 i = adapter->next_avail_tx_desc;
1660 /* Set up our transmit descriptors */
1661 for (j = 0; j < nsegs; j++) {
1662 /* If adapter is 82544 and on PCIX bus */
1663 if(adapter->pcix_82544) {
1664 DESC_ARRAY desc_array;
1665 uint32_t array_elements, counter;
1668 * Check the Address and Length combination and
1669 * split the data accordingly
1671 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1672 segs[j].ds_len, &desc_array);
1673 for (counter = 0; counter < array_elements; counter++) {
1674 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1676 tx_buffer = &adapter->tx_buffer_area[i];
1677 ctxd = &adapter->tx_desc_base[i];
1679 ctxd->buffer_addr = htole64(
1680 desc_array.descriptor[counter].address);
1681 ctxd->lower.data = htole32(
1682 E1000_TXD_CMD_IFCS | txd_lower |
1683 desc_array.descriptor[counter].length);
1684 ctxd->upper.data = htole32(txd_upper);
1687 if (++i == adapter->num_tx_desc)
1693 tx_buffer = &adapter->tx_buffer_area[i];
1694 ctxd = &adapter->tx_desc_base[i];
1696 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1697 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1698 txd_lower | segs[j].ds_len);
1699 ctxd->upper.data = htole32(txd_upper);
1702 if (++i == adapter->num_tx_desc)
1707 adapter->next_avail_tx_desc = i;
1708 if (adapter->pcix_82544) {
1709 KKASSERT(adapter->num_tx_desc_avail > txd_used);
1710 adapter->num_tx_desc_avail -= txd_used;
1712 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1713 adapter->num_tx_desc_avail -= nsegs;
1716 /* Handle VLAN tag */
1717 if (m_head->m_flags & M_VLANTAG) {
1718 /* Set the vlan id. */
1719 ctxd->upper.fields.special =
1720 htole16(m_head->m_pkthdr.ether_vlantag);
1722 /* Tell hardware to add tag */
1723 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1726 tx_buffer->m_head = m_head;
1727 tx_buffer_mapped->map = tx_buffer->map;
1728 tx_buffer->map = map;
1730 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1731 adapter->tx_nsegs = 0;
1734 * Report Status (RS) is turned on
1735 * every tx_int_nsegs descriptors.
1737 cmd = E1000_TXD_CMD_RS;
1740 * Keep track of the descriptor, which will
1741 * be written back by hardware.
1743 adapter->tx_dd[adapter->tx_dd_tail] = last;
1744 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1745 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1749 * Last Descriptor of Packet needs End Of Packet (EOP)
1751 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1753 if (adapter->hw.mac.type == e1000_82547) {
1755 * Advance the Transmit Descriptor Tail (TDT), this tells the
1756 * E1000 that this frame is available to transmit.
1758 if (adapter->link_duplex == HALF_DUPLEX) {
1759 em_82547_move_tail_serialized(adapter);
1761 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1762 em_82547_update_fifo_head(adapter,
1763 m_head->m_pkthdr.len);
1767 * Defer TDT updating, until enough descriptors are setup
1775 * 82547 workaround to avoid controller hang in half-duplex environment.
1776 * The workaround is to avoid queuing a large packet that would span
1777 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1778 * in this case. We do that only when FIFO is quiescent.
1781 em_82547_move_tail_serialized(struct adapter *adapter)
1783 struct e1000_tx_desc *tx_desc;
1784 uint16_t hw_tdt, sw_tdt, length = 0;
1787 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1789 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
1790 sw_tdt = adapter->next_avail_tx_desc;
1792 while (hw_tdt != sw_tdt) {
1793 tx_desc = &adapter->tx_desc_base[hw_tdt];
1794 length += tx_desc->lower.flags.length;
1795 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1796 if (++hw_tdt == adapter->num_tx_desc)
1800 if (em_82547_fifo_workaround(adapter, length)) {
1801 adapter->tx_fifo_wrk_cnt++;
1802 callout_reset(&adapter->tx_fifo_timer, 1,
1803 em_82547_move_tail, adapter);
1806 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
1807 em_82547_update_fifo_head(adapter, length);
1814 em_82547_move_tail(void *xsc)
1816 struct adapter *adapter = xsc;
1817 struct ifnet *ifp = &adapter->arpcom.ac_if;
1819 lwkt_serialize_enter(ifp->if_serializer);
1820 em_82547_move_tail_serialized(adapter);
1821 lwkt_serialize_exit(ifp->if_serializer);
1825 em_82547_fifo_workaround(struct adapter *adapter, int len)
1827 int fifo_space, fifo_pkt_len;
1829 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1831 if (adapter->link_duplex == HALF_DUPLEX) {
1832 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1834 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1835 if (em_82547_tx_fifo_reset(adapter))
1845 em_82547_update_fifo_head(struct adapter *adapter, int len)
1847 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1849 /* tx_fifo_head is always 16 byte aligned */
1850 adapter->tx_fifo_head += fifo_pkt_len;
1851 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1852 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1856 em_82547_tx_fifo_reset(struct adapter *adapter)
1860 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1861 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1862 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1863 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1864 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1865 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1866 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
1867 /* Disable TX unit */
1868 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1869 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1870 tctl & ~E1000_TCTL_EN);
1872 /* Reset FIFO pointers */
1873 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1874 adapter->tx_head_addr);
1875 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1876 adapter->tx_head_addr);
1877 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1878 adapter->tx_head_addr);
1879 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1880 adapter->tx_head_addr);
1882 /* Re-enable TX unit */
1883 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
1884 E1000_WRITE_FLUSH(&adapter->hw);
1886 adapter->tx_fifo_head = 0;
1887 adapter->tx_fifo_reset_cnt++;
1896 em_set_promisc(struct adapter *adapter)
1898 struct ifnet *ifp = &adapter->arpcom.ac_if;
1901 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1903 if (ifp->if_flags & IFF_PROMISC) {
1904 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1905 /* Turn this on if you want to see bad packets */
1907 reg_rctl |= E1000_RCTL_SBP;
1908 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1909 } else if (ifp->if_flags & IFF_ALLMULTI) {
1910 reg_rctl |= E1000_RCTL_MPE;
1911 reg_rctl &= ~E1000_RCTL_UPE;
1912 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1917 em_disable_promisc(struct adapter *adapter)
1921 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1923 reg_rctl &= ~E1000_RCTL_UPE;
1924 reg_rctl &= ~E1000_RCTL_MPE;
1925 reg_rctl &= ~E1000_RCTL_SBP;
1926 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1930 em_set_multi(struct adapter *adapter)
1932 struct ifnet *ifp = &adapter->arpcom.ac_if;
1933 struct ifmultiaddr *ifma;
1934 uint32_t reg_rctl = 0;
1939 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1941 if (adapter->hw.mac.type == e1000_82542 &&
1942 adapter->hw.revision_id == E1000_REVISION_2) {
1943 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1944 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1945 e1000_pci_clear_mwi(&adapter->hw);
1946 reg_rctl |= E1000_RCTL_RST;
1947 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1951 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1952 if (ifma->ifma_addr->sa_family != AF_LINK)
1955 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1958 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1959 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1963 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1964 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1965 reg_rctl |= E1000_RCTL_MPE;
1966 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1968 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1971 if (adapter->hw.mac.type == e1000_82542 &&
1972 adapter->hw.revision_id == E1000_REVISION_2) {
1973 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1974 reg_rctl &= ~E1000_RCTL_RST;
1975 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1977 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1978 e1000_pci_set_mwi(&adapter->hw);
1983 * This routine checks for link status and updates statistics.
1988 struct adapter *adapter = xsc;
1989 struct ifnet *ifp = &adapter->arpcom.ac_if;
1991 lwkt_serialize_enter(ifp->if_serializer);
1993 em_update_link_status(adapter);
1994 em_update_stats(adapter);
1996 /* Reset LAA into RAR[0] on 82571 */
1997 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1998 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2000 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
2001 em_print_hw_stats(adapter);
2003 em_smartspeed(adapter);
2005 callout_reset(&adapter->timer, hz, em_timer, adapter);
2007 lwkt_serialize_exit(ifp->if_serializer);
2011 em_update_link_status(struct adapter *adapter)
2013 struct e1000_hw *hw = &adapter->hw;
2014 struct ifnet *ifp = &adapter->arpcom.ac_if;
2015 device_t dev = adapter->dev;
2016 uint32_t link_check = 0;
2018 /* Get the cached link value or read phy for real */
2019 switch (hw->phy.media_type) {
2020 case e1000_media_type_copper:
2021 if (hw->mac.get_link_status) {
2022 /* Do the work to read phy */
2023 e1000_check_for_link(hw);
2024 link_check = !hw->mac.get_link_status;
2025 if (link_check) /* ESB2 fix */
2026 e1000_cfg_on_link_up(hw);
2032 case e1000_media_type_fiber:
2033 e1000_check_for_link(hw);
2035 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2038 case e1000_media_type_internal_serdes:
2039 e1000_check_for_link(hw);
2040 link_check = adapter->hw.mac.serdes_has_link;
2043 case e1000_media_type_unknown:
2048 /* Now check for a transition */
2049 if (link_check && adapter->link_active == 0) {
2050 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2051 &adapter->link_duplex);
2054 * Check if we should enable/disable SPEED_MODE bit on
2057 if (adapter->link_speed != SPEED_1000 &&
2058 (hw->mac.type == e1000_82571 ||
2059 hw->mac.type == e1000_82572)) {
2062 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2063 tarc0 &= ~SPEED_MODE_BIT;
2064 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
2067 device_printf(dev, "Link is up %d Mbps %s\n",
2068 adapter->link_speed,
2069 ((adapter->link_duplex == FULL_DUPLEX) ?
2070 "Full Duplex" : "Half Duplex"));
2072 adapter->link_active = 1;
2073 adapter->smartspeed = 0;
2074 ifp->if_baudrate = adapter->link_speed * 1000000;
2075 ifp->if_link_state = LINK_STATE_UP;
2076 if_link_state_change(ifp);
2077 } else if (!link_check && adapter->link_active == 1) {
2078 ifp->if_baudrate = adapter->link_speed = 0;
2079 adapter->link_duplex = 0;
2081 device_printf(dev, "Link is Down\n");
2082 adapter->link_active = 0;
2084 /* Link down, disable watchdog */
2087 ifp->if_link_state = LINK_STATE_DOWN;
2088 if_link_state_change(ifp);
2093 em_stop(struct adapter *adapter)
2095 struct ifnet *ifp = &adapter->arpcom.ac_if;
2098 ASSERT_SERIALIZED(ifp->if_serializer);
2100 em_disable_intr(adapter);
2102 callout_stop(&adapter->timer);
2103 callout_stop(&adapter->tx_fifo_timer);
2105 ifp->if_flags &= ~IFF_RUNNING;
2106 ifq_clr_oactive(&ifp->if_snd);
2109 e1000_reset_hw(&adapter->hw);
2110 if (adapter->hw.mac.type >= e1000_82544)
2111 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2113 for (i = 0; i < adapter->num_tx_desc; i++) {
2114 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2116 if (tx_buffer->m_head != NULL) {
2117 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2118 m_freem(tx_buffer->m_head);
2119 tx_buffer->m_head = NULL;
2123 for (i = 0; i < adapter->num_rx_desc; i++) {
2124 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2126 if (rx_buffer->m_head != NULL) {
2127 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2128 m_freem(rx_buffer->m_head);
2129 rx_buffer->m_head = NULL;
2133 if (adapter->fmp != NULL)
2134 m_freem(adapter->fmp);
2135 adapter->fmp = NULL;
2136 adapter->lmp = NULL;
2138 adapter->csum_flags = 0;
2139 adapter->csum_lhlen = 0;
2140 adapter->csum_iphlen = 0;
2141 adapter->csum_thlen = 0;
2142 adapter->csum_mss = 0;
2143 adapter->csum_pktlen = 0;
2145 adapter->tx_dd_head = 0;
2146 adapter->tx_dd_tail = 0;
2147 adapter->tx_nsegs = 0;
2151 em_get_hw_info(struct adapter *adapter)
2153 device_t dev = adapter->dev;
2155 /* Save off the information about this board */
2156 adapter->hw.vendor_id = pci_get_vendor(dev);
2157 adapter->hw.device_id = pci_get_device(dev);
2158 adapter->hw.revision_id = pci_get_revid(dev);
2159 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
2160 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
2162 /* Do Shared Code Init and Setup */
2163 if (e1000_set_mac_type(&adapter->hw))
2169 em_alloc_pci_res(struct adapter *adapter)
2171 device_t dev = adapter->dev;
2173 int val, rid, msi_enable;
2175 /* Enable bus mastering */
2176 pci_enable_busmaster(dev);
2178 adapter->memory_rid = EM_BAR_MEM;
2179 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2180 &adapter->memory_rid, RF_ACTIVE);
2181 if (adapter->memory == NULL) {
2182 device_printf(dev, "Unable to allocate bus resource: memory\n");
2185 adapter->osdep.mem_bus_space_tag =
2186 rman_get_bustag(adapter->memory);
2187 adapter->osdep.mem_bus_space_handle =
2188 rman_get_bushandle(adapter->memory);
2190 /* XXX This is quite goofy, it is not actually used */
2191 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2193 /* Only older adapters use IO mapping */
2194 if (adapter->hw.mac.type > e1000_82543 &&
2195 adapter->hw.mac.type < e1000_82571) {
2196 /* Figure our where our IO BAR is ? */
2197 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
2198 val = pci_read_config(dev, rid, 4);
2199 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2200 adapter->io_rid = rid;
2204 /* check for 64bit BAR */
2205 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2208 if (rid >= PCIR_CARDBUSCIS) {
2209 device_printf(dev, "Unable to locate IO BAR\n");
2212 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2213 &adapter->io_rid, RF_ACTIVE);
2214 if (adapter->ioport == NULL) {
2215 device_printf(dev, "Unable to allocate bus resource: "
2219 adapter->hw.io_base = 0;
2220 adapter->osdep.io_bus_space_tag =
2221 rman_get_bustag(adapter->ioport);
2222 adapter->osdep.io_bus_space_handle =
2223 rman_get_bushandle(adapter->ioport);
2227 * Don't enable MSI-X on 82574, see:
2228 * 82574 specification update errata #15
2230 * Don't enable MSI on PCI/PCI-X chips, see:
2231 * 82540 specification update errata #6
2232 * 82545 specification update errata #4
2234 * Don't enable MSI on 82571/82572, see:
2235 * 82571/82572 specification update errata #63
2237 msi_enable = em_msi_enable;
2239 (!pci_is_pcie(dev) ||
2240 adapter->hw.mac.type == e1000_82571 ||
2241 adapter->hw.mac.type == e1000_82572))
2244 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
2245 &adapter->intr_rid, &intr_flags);
2247 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2250 unshared = device_getenv_int(dev, "irq.unshared", 0);
2252 adapter->flags |= EM_FLAG_SHARED_INTR;
2254 device_printf(dev, "IRQ shared\n");
2256 intr_flags &= ~RF_SHAREABLE;
2258 device_printf(dev, "IRQ unshared\n");
2262 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2263 &adapter->intr_rid, intr_flags);
2264 if (adapter->intr_res == NULL) {
2265 device_printf(dev, "Unable to allocate bus resource: "
2270 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2271 adapter->hw.back = &adapter->osdep;
2276 em_free_pci_res(struct adapter *adapter)
2278 device_t dev = adapter->dev;
2280 if (adapter->intr_res != NULL) {
2281 bus_release_resource(dev, SYS_RES_IRQ,
2282 adapter->intr_rid, adapter->intr_res);
2285 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2286 pci_release_msi(dev);
2288 if (adapter->memory != NULL) {
2289 bus_release_resource(dev, SYS_RES_MEMORY,
2290 adapter->memory_rid, adapter->memory);
2293 if (adapter->flash != NULL) {
2294 bus_release_resource(dev, SYS_RES_MEMORY,
2295 adapter->flash_rid, adapter->flash);
2298 if (adapter->ioport != NULL) {
2299 bus_release_resource(dev, SYS_RES_IOPORT,
2300 adapter->io_rid, adapter->ioport);
2305 em_reset(struct adapter *adapter)
2307 device_t dev = adapter->dev;
2308 uint16_t rx_buffer_size;
2311 /* When hardware is reset, fifo_head is also reset */
2312 adapter->tx_fifo_head = 0;
2314 /* Set up smart power down as default off on newer adapters. */
2315 if (!em_smart_pwr_down &&
2316 (adapter->hw.mac.type == e1000_82571 ||
2317 adapter->hw.mac.type == e1000_82572)) {
2318 uint16_t phy_tmp = 0;
2320 /* Speed up time to link by disabling smart power down. */
2321 e1000_read_phy_reg(&adapter->hw,
2322 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2323 phy_tmp &= ~IGP02E1000_PM_SPD;
2324 e1000_write_phy_reg(&adapter->hw,
2325 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2329 * Packet Buffer Allocation (PBA)
2330 * Writing PBA sets the receive portion of the buffer
2331 * the remainder is used for the transmit buffer.
2333 * Devices before the 82547 had a Packet Buffer of 64K.
2334 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
2335 * After the 82547 the buffer was reduced to 40K.
2336 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
2337 * Note: default does not leave enough room for Jumbo Frame >10k.
2339 switch (adapter->hw.mac.type) {
2341 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
2342 if (adapter->max_frame_size > 8192)
2343 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2345 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2346 adapter->tx_fifo_head = 0;
2347 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
2348 adapter->tx_fifo_size =
2349 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
2352 /* Total Packet Buffer on these is 48K */
2355 case e1000_80003es2lan:
2356 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2359 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2360 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2365 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2373 case e1000_ich10lan:
2374 #define E1000_PBA_10K 0x000A
2375 pba = E1000_PBA_10K;
2380 pba = E1000_PBA_26K;
2384 /* Devices before 82547 had a Packet Buffer of 64K. */
2385 if (adapter->max_frame_size > 8192)
2386 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2388 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2390 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2393 * These parameters control the automatic generation (Tx) and
2394 * response (Rx) to Ethernet PAUSE frames.
2395 * - High water mark should allow for at least two frames to be
2396 * received after sending an XOFF.
2397 * - Low water mark works best when it is very near the high water mark.
2398 * This allows the receiver to restart by sending XON when it has
2399 * drained a bit. Here we use an arbitary value of 1500 which will
2400 * restart after one full frame is pulled from the buffer. There
2401 * could be several smaller frames in the buffer and if so they will
2402 * not trigger the XON until their total number reduces the buffer
2404 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2407 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
2409 adapter->hw.fc.high_water = rx_buffer_size -
2410 roundup2(adapter->max_frame_size, 1024);
2411 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2413 if (adapter->hw.mac.type == e1000_80003es2lan)
2414 adapter->hw.fc.pause_time = 0xFFFF;
2416 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2418 adapter->hw.fc.send_xon = TRUE;
2420 adapter->hw.fc.requested_mode = e1000_fc_full;
2423 * Device specific overrides/settings
2425 switch (adapter->hw.mac.type) {
2427 /* Workaround: no TX flow ctrl for PCH */
2428 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2429 adapter->hw.fc.pause_time = 0xFFFF; /* override */
2430 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) {
2431 adapter->hw.fc.high_water = 0x3500;
2432 adapter->hw.fc.low_water = 0x1500;
2434 adapter->hw.fc.high_water = 0x5000;
2435 adapter->hw.fc.low_water = 0x3000;
2437 adapter->hw.fc.refresh_time = 0x1000;
2441 adapter->hw.fc.high_water = 0x5C20;
2442 adapter->hw.fc.low_water = 0x5048;
2443 adapter->hw.fc.pause_time = 0x0650;
2444 adapter->hw.fc.refresh_time = 0x0400;
2445 /* Jumbos need adjusted PBA */
2446 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2447 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2449 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2453 case e1000_ich10lan:
2454 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU) {
2455 adapter->hw.fc.high_water = 0x2800;
2456 adapter->hw.fc.low_water =
2457 adapter->hw.fc.high_water - 8;
2462 if (adapter->hw.mac.type == e1000_80003es2lan)
2463 adapter->hw.fc.pause_time = 0xFFFF;
2467 /* Issue a global reset */
2468 e1000_reset_hw(&adapter->hw);
2469 if (adapter->hw.mac.type >= e1000_82544)
2470 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2471 em_disable_aspm(adapter);
2473 if (e1000_init_hw(&adapter->hw) < 0) {
2474 device_printf(dev, "Hardware Initialization Failed\n");
2478 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2479 e1000_get_phy_info(&adapter->hw);
2480 e1000_check_for_link(&adapter->hw);
2486 em_setup_ifp(struct adapter *adapter)
2488 struct ifnet *ifp = &adapter->arpcom.ac_if;
2490 if_initname(ifp, device_get_name(adapter->dev),
2491 device_get_unit(adapter->dev));
2492 ifp->if_softc = adapter;
2493 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2494 ifp->if_init = em_init;
2495 ifp->if_ioctl = em_ioctl;
2496 ifp->if_start = em_start;
2497 #ifdef IFPOLL_ENABLE
2498 ifp->if_npoll = em_npoll;
2500 ifp->if_watchdog = em_watchdog;
2501 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2502 ifq_set_ready(&ifp->if_snd);
2504 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
2506 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2507 if (adapter->hw.mac.type >= e1000_82543)
2508 ifp->if_capabilities |= IFCAP_HWCSUM;
2509 if (adapter->flags & EM_FLAG_TSO)
2510 ifp->if_capabilities |= IFCAP_TSO;
2511 ifp->if_capenable = ifp->if_capabilities;
2513 if (ifp->if_capenable & IFCAP_TXCSUM)
2514 ifp->if_hwassist |= EM_CSUM_FEATURES;
2515 if (ifp->if_capenable & IFCAP_TSO)
2516 ifp->if_hwassist |= CSUM_TSO;
2519 * Tell the upper layer(s) we support long frames.
2521 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2524 * Specify the media types supported by this adapter and register
2525 * callbacks to update media and link information
2527 ifmedia_init(&adapter->media, IFM_IMASK,
2528 em_media_change, em_media_status);
2529 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2530 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2531 u_char fiber_type = IFM_1000_SX; /* default type */
2533 if (adapter->hw.mac.type == e1000_82545)
2534 fiber_type = IFM_1000_LX;
2535 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2537 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2539 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2540 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2542 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2544 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2546 if (adapter->hw.phy.type != e1000_phy_ife) {
2547 ifmedia_add(&adapter->media,
2548 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2549 ifmedia_add(&adapter->media,
2550 IFM_ETHER | IFM_1000_T, 0, NULL);
2553 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2554 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2559 * Workaround for SmartSpeed on 82541 and 82547 controllers
2562 em_smartspeed(struct adapter *adapter)
2566 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2567 adapter->hw.mac.autoneg == 0 ||
2568 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2571 if (adapter->smartspeed == 0) {
2573 * If Master/Slave config fault is asserted twice,
2574 * we assume back-to-back
2576 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2577 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2579 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2580 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2581 e1000_read_phy_reg(&adapter->hw,
2582 PHY_1000T_CTRL, &phy_tmp);
2583 if (phy_tmp & CR_1000T_MS_ENABLE) {
2584 phy_tmp &= ~CR_1000T_MS_ENABLE;
2585 e1000_write_phy_reg(&adapter->hw,
2586 PHY_1000T_CTRL, phy_tmp);
2587 adapter->smartspeed++;
2588 if (adapter->hw.mac.autoneg &&
2589 !e1000_phy_setup_autoneg(&adapter->hw) &&
2590 !e1000_read_phy_reg(&adapter->hw,
2591 PHY_CONTROL, &phy_tmp)) {
2592 phy_tmp |= MII_CR_AUTO_NEG_EN |
2593 MII_CR_RESTART_AUTO_NEG;
2594 e1000_write_phy_reg(&adapter->hw,
2595 PHY_CONTROL, phy_tmp);
2600 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2601 /* If still no link, perhaps using 2/3 pair cable */
2602 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2603 phy_tmp |= CR_1000T_MS_ENABLE;
2604 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2605 if (adapter->hw.mac.autoneg &&
2606 !e1000_phy_setup_autoneg(&adapter->hw) &&
2607 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2608 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2609 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2613 /* Restart process after EM_SMARTSPEED_MAX iterations */
2614 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2615 adapter->smartspeed = 0;
2619 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2620 struct em_dma_alloc *dma)
2622 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2623 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2624 &dma->dma_tag, &dma->dma_map,
2626 if (dma->dma_vaddr == NULL)
2633 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2635 if (dma->dma_tag == NULL)
2637 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2638 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2639 bus_dma_tag_destroy(dma->dma_tag);
2643 em_create_tx_ring(struct adapter *adapter)
2645 device_t dev = adapter->dev;
2646 struct em_buffer *tx_buffer;
2649 adapter->tx_buffer_area =
2650 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2651 M_DEVBUF, M_WAITOK | M_ZERO);
2654 * Create DMA tags for tx buffers
2656 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2657 1, 0, /* alignment, bounds */
2658 BUS_SPACE_MAXADDR, /* lowaddr */
2659 BUS_SPACE_MAXADDR, /* highaddr */
2660 NULL, NULL, /* filter, filterarg */
2661 EM_TSO_SIZE, /* maxsize */
2662 EM_MAX_SCATTER, /* nsegments */
2663 PAGE_SIZE, /* maxsegsize */
2664 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2665 BUS_DMA_ONEBPAGE, /* flags */
2668 device_printf(dev, "Unable to allocate TX DMA tag\n");
2669 kfree(adapter->tx_buffer_area, M_DEVBUF);
2670 adapter->tx_buffer_area = NULL;
2675 * Create DMA maps for tx buffers
2677 for (i = 0; i < adapter->num_tx_desc; i++) {
2678 tx_buffer = &adapter->tx_buffer_area[i];
2680 error = bus_dmamap_create(adapter->txtag,
2681 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2684 device_printf(dev, "Unable to create TX DMA map\n");
2685 em_destroy_tx_ring(adapter, i);
2693 em_init_tx_ring(struct adapter *adapter)
2695 /* Clear the old ring contents */
2696 bzero(adapter->tx_desc_base,
2697 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2700 adapter->next_avail_tx_desc = 0;
2701 adapter->next_tx_to_clean = 0;
2702 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2706 em_init_tx_unit(struct adapter *adapter)
2708 uint32_t tctl, tarc, tipg = 0;
2711 /* Setup the Base and Length of the Tx Descriptor Ring */
2712 bus_addr = adapter->txdma.dma_paddr;
2713 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2714 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2715 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2716 (uint32_t)(bus_addr >> 32));
2717 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2718 (uint32_t)bus_addr);
2719 /* Setup the HW Tx Head and Tail descriptor pointers */
2720 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2721 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
2723 /* Set the default values for the Tx Inter Packet Gap timer */
2724 switch (adapter->hw.mac.type) {
2726 tipg = DEFAULT_82542_TIPG_IPGT;
2727 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2728 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2731 case e1000_80003es2lan:
2732 tipg = DEFAULT_82543_TIPG_IPGR1;
2733 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2734 E1000_TIPG_IPGR2_SHIFT;
2738 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2739 adapter->hw.phy.media_type ==
2740 e1000_media_type_internal_serdes)
2741 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2743 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2744 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2745 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2749 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2751 /* NOTE: 0 is not allowed for TIDV */
2752 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2753 if(adapter->hw.mac.type >= e1000_82540)
2754 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
2756 if (adapter->hw.mac.type == e1000_82571 ||
2757 adapter->hw.mac.type == e1000_82572) {
2758 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2759 tarc |= SPEED_MODE_BIT;
2760 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2761 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2762 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2764 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2765 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2767 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2770 /* Program the Transmit Control Register */
2771 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2772 tctl &= ~E1000_TCTL_CT;
2773 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2774 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2776 if (adapter->hw.mac.type >= e1000_82571)
2777 tctl |= E1000_TCTL_MULR;
2779 /* This write will effectively turn on the transmit unit. */
2780 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2782 if (adapter->hw.mac.type == e1000_82571 ||
2783 adapter->hw.mac.type == e1000_82572 ||
2784 adapter->hw.mac.type == e1000_80003es2lan) {
2785 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2786 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2788 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2793 em_destroy_tx_ring(struct adapter *adapter, int ndesc)
2795 struct em_buffer *tx_buffer;
2798 if (adapter->tx_buffer_area == NULL)
2801 for (i = 0; i < ndesc; i++) {
2802 tx_buffer = &adapter->tx_buffer_area[i];
2804 KKASSERT(tx_buffer->m_head == NULL);
2805 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2807 bus_dma_tag_destroy(adapter->txtag);
2809 kfree(adapter->tx_buffer_area, M_DEVBUF);
2810 adapter->tx_buffer_area = NULL;
2814 * The offload context needs to be set when we transfer the first
2815 * packet of a particular protocol (TCP/UDP). This routine has been
2816 * enhanced to deal with inserted VLAN headers.
2818 * If the new packet's ether header length, ip header length and
2819 * csum offloading type are same as the previous packet, we should
2820 * avoid allocating a new csum context descriptor; mainly to take
2821 * advantage of the pipeline effect of the TX data read request.
2823 * This function returns number of TX descrptors allocated for
2827 em_txcsum(struct adapter *adapter, struct mbuf *mp,
2828 uint32_t *txd_upper, uint32_t *txd_lower)
2830 struct e1000_context_desc *TXD;
2831 int curr_txd, ehdrlen, csum_flags;
2832 uint32_t cmd, hdr_len, ip_hlen;
2834 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2835 ip_hlen = mp->m_pkthdr.csum_iphlen;
2836 ehdrlen = mp->m_pkthdr.csum_lhlen;
2838 if (adapter->csum_lhlen == ehdrlen &&
2839 adapter->csum_iphlen == ip_hlen &&
2840 adapter->csum_flags == csum_flags) {
2842 * Same csum offload context as the previous packets;
2845 *txd_upper = adapter->csum_txd_upper;
2846 *txd_lower = adapter->csum_txd_lower;
2851 * Setup a new csum offload context.
2854 curr_txd = adapter->next_avail_tx_desc;
2855 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2859 /* Setup of IP header checksum. */
2860 if (csum_flags & CSUM_IP) {
2862 * Start offset for header checksum calculation.
2863 * End offset for header checksum calculation.
2864 * Offset of place to put the checksum.
2866 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2867 TXD->lower_setup.ip_fields.ipcse =
2868 htole16(ehdrlen + ip_hlen - 1);
2869 TXD->lower_setup.ip_fields.ipcso =
2870 ehdrlen + offsetof(struct ip, ip_sum);
2871 cmd |= E1000_TXD_CMD_IP;
2872 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2874 hdr_len = ehdrlen + ip_hlen;
2876 if (csum_flags & CSUM_TCP) {
2878 * Start offset for payload checksum calculation.
2879 * End offset for payload checksum calculation.
2880 * Offset of place to put the checksum.
2882 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2883 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2884 TXD->upper_setup.tcp_fields.tucso =
2885 hdr_len + offsetof(struct tcphdr, th_sum);
2886 cmd |= E1000_TXD_CMD_TCP;
2887 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2888 } else if (csum_flags & CSUM_UDP) {
2890 * Start offset for header checksum calculation.
2891 * End offset for header checksum calculation.
2892 * Offset of place to put the checksum.
2894 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2895 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2896 TXD->upper_setup.tcp_fields.tucso =
2897 hdr_len + offsetof(struct udphdr, uh_sum);
2898 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2901 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2902 E1000_TXD_DTYP_D; /* Data descr */
2904 /* Save the information for this csum offloading context */
2905 adapter->csum_lhlen = ehdrlen;
2906 adapter->csum_iphlen = ip_hlen;
2907 adapter->csum_flags = csum_flags;
2908 adapter->csum_txd_upper = *txd_upper;
2909 adapter->csum_txd_lower = *txd_lower;
2911 TXD->tcp_seg_setup.data = htole32(0);
2912 TXD->cmd_and_length =
2913 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2915 if (++curr_txd == adapter->num_tx_desc)
2918 KKASSERT(adapter->num_tx_desc_avail > 0);
2919 adapter->num_tx_desc_avail--;
2921 adapter->next_avail_tx_desc = curr_txd;
2926 em_txeof(struct adapter *adapter)
2928 struct ifnet *ifp = &adapter->arpcom.ac_if;
2929 struct em_buffer *tx_buffer;
2930 int first, num_avail;
2932 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2935 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2938 num_avail = adapter->num_tx_desc_avail;
2939 first = adapter->next_tx_to_clean;
2941 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
2942 struct e1000_tx_desc *tx_desc;
2943 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2945 tx_desc = &adapter->tx_desc_base[dd_idx];
2946 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2947 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2949 if (++dd_idx == adapter->num_tx_desc)
2952 while (first != dd_idx) {
2957 tx_buffer = &adapter->tx_buffer_area[first];
2958 if (tx_buffer->m_head) {
2960 bus_dmamap_unload(adapter->txtag,
2962 m_freem(tx_buffer->m_head);
2963 tx_buffer->m_head = NULL;
2966 if (++first == adapter->num_tx_desc)
2973 adapter->next_tx_to_clean = first;
2974 adapter->num_tx_desc_avail = num_avail;
2976 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2977 adapter->tx_dd_head = 0;
2978 adapter->tx_dd_tail = 0;
2981 if (!EM_IS_OACTIVE(adapter)) {
2982 ifq_clr_oactive(&ifp->if_snd);
2984 /* All clean, turn off the timer */
2985 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2991 em_tx_collect(struct adapter *adapter)
2993 struct ifnet *ifp = &adapter->arpcom.ac_if;
2994 struct em_buffer *tx_buffer;
2995 int tdh, first, num_avail, dd_idx = -1;
2997 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3000 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
3001 if (tdh == adapter->next_tx_to_clean)
3004 if (adapter->tx_dd_head != adapter->tx_dd_tail)
3005 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3007 num_avail = adapter->num_tx_desc_avail;
3008 first = adapter->next_tx_to_clean;
3010 while (first != tdh) {
3015 tx_buffer = &adapter->tx_buffer_area[first];
3016 if (tx_buffer->m_head) {
3018 bus_dmamap_unload(adapter->txtag,
3020 m_freem(tx_buffer->m_head);
3021 tx_buffer->m_head = NULL;
3024 if (first == dd_idx) {
3025 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3026 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3027 adapter->tx_dd_head = 0;
3028 adapter->tx_dd_tail = 0;
3031 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3035 if (++first == adapter->num_tx_desc)
3038 adapter->next_tx_to_clean = first;
3039 adapter->num_tx_desc_avail = num_avail;
3041 if (!EM_IS_OACTIVE(adapter)) {
3042 ifq_clr_oactive(&ifp->if_snd);
3044 /* All clean, turn off the timer */
3045 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3051 * When Link is lost sometimes there is work still in the TX ring
3052 * which will result in a watchdog, rather than allow that do an
3053 * attempted cleanup and then reinit here. Note that this has been
3054 * seens mostly with fiber adapters.
3057 em_tx_purge(struct adapter *adapter)
3059 struct ifnet *ifp = &adapter->arpcom.ac_if;
3061 if (!adapter->link_active && ifp->if_timer) {
3062 em_tx_collect(adapter);
3063 if (ifp->if_timer) {
3064 if_printf(ifp, "Link lost, TX pending, reinit\n");
3072 em_newbuf(struct adapter *adapter, int i, int init)
3075 bus_dma_segment_t seg;
3077 struct em_buffer *rx_buffer;
3080 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3082 adapter->mbuf_cluster_failed++;
3084 if_printf(&adapter->arpcom.ac_if,
3085 "Unable to allocate RX mbuf\n");
3089 m->m_len = m->m_pkthdr.len = MCLBYTES;
3091 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3092 m_adj(m, ETHER_ALIGN);
3094 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3095 adapter->rx_sparemap, m,
3096 &seg, 1, &nseg, BUS_DMA_NOWAIT);
3100 if_printf(&adapter->arpcom.ac_if,
3101 "Unable to load RX mbuf\n");
3106 rx_buffer = &adapter->rx_buffer_area[i];
3107 if (rx_buffer->m_head != NULL)
3108 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3110 map = rx_buffer->map;
3111 rx_buffer->map = adapter->rx_sparemap;
3112 adapter->rx_sparemap = map;
3114 rx_buffer->m_head = m;
3116 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
3121 em_create_rx_ring(struct adapter *adapter)
3123 device_t dev = adapter->dev;
3124 struct em_buffer *rx_buffer;
3127 adapter->rx_buffer_area =
3128 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3129 M_DEVBUF, M_WAITOK | M_ZERO);
3132 * Create DMA tag for rx buffers
3134 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3135 1, 0, /* alignment, bounds */
3136 BUS_SPACE_MAXADDR, /* lowaddr */
3137 BUS_SPACE_MAXADDR, /* highaddr */
3138 NULL, NULL, /* filter, filterarg */
3139 MCLBYTES, /* maxsize */
3141 MCLBYTES, /* maxsegsize */
3142 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3145 device_printf(dev, "Unable to allocate RX DMA tag\n");
3146 kfree(adapter->rx_buffer_area, M_DEVBUF);
3147 adapter->rx_buffer_area = NULL;
3152 * Create spare DMA map for rx buffers
3154 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3155 &adapter->rx_sparemap);
3157 device_printf(dev, "Unable to create spare RX DMA map\n");
3158 bus_dma_tag_destroy(adapter->rxtag);
3159 kfree(adapter->rx_buffer_area, M_DEVBUF);
3160 adapter->rx_buffer_area = NULL;
3165 * Create DMA maps for rx buffers
3167 for (i = 0; i < adapter->num_rx_desc; i++) {
3168 rx_buffer = &adapter->rx_buffer_area[i];
3170 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3173 device_printf(dev, "Unable to create RX DMA map\n");
3174 em_destroy_rx_ring(adapter, i);
3182 em_init_rx_ring(struct adapter *adapter)
3186 /* Reset descriptor ring */
3187 bzero(adapter->rx_desc_base,
3188 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
3190 /* Allocate new ones. */
3191 for (i = 0; i < adapter->num_rx_desc; i++) {
3192 error = em_newbuf(adapter, i, 1);
3197 /* Setup our descriptor pointers */
3198 adapter->next_rx_desc_to_check = 0;
3204 em_init_rx_unit(struct adapter *adapter)
3206 struct ifnet *ifp = &adapter->arpcom.ac_if;
3211 * Make sure receives are disabled while setting
3212 * up the descriptor ring
3214 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3215 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3217 if (adapter->hw.mac.type >= e1000_82540) {
3221 * Set the interrupt throttling rate. Value is calculated
3222 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3224 if (adapter->int_throttle_ceil)
3225 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3228 em_set_itr(adapter, itr);
3231 /* Disable accelerated ackknowledge */
3232 if (adapter->hw.mac.type == e1000_82574) {
3233 E1000_WRITE_REG(&adapter->hw,
3234 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3237 /* Receive Checksum Offload for TCP and UDP */
3238 if (ifp->if_capenable & IFCAP_RXCSUM) {
3241 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3242 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3243 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3247 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3248 * long latencies are observed, like Lenovo X60. This
3249 * change eliminates the problem, but since having positive
3250 * values in RDTR is a known source of problems on other
3251 * platforms another solution is being sought.
3253 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3254 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3255 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3259 * Setup the Base and Length of the Rx Descriptor Ring
3261 bus_addr = adapter->rxdma.dma_paddr;
3262 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3263 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3264 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3265 (uint32_t)(bus_addr >> 32));
3266 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3267 (uint32_t)bus_addr);
3270 * Setup the HW Rx Head and Tail Descriptor Pointers
3272 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3273 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3275 /* Set PTHRESH for improved jumbo performance */
3276 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3277 (adapter->hw.mac.type == e1000_pch2lan) ||
3278 (adapter->hw.mac.type == e1000_ich10lan)) &&
3279 (ifp->if_mtu > ETHERMTU)) {
3282 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3283 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3286 if (adapter->hw.mac.type == e1000_pch2lan) {
3287 if (ifp->if_mtu > ETHERMTU)
3288 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3290 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3293 /* Setup the Receive Control Register */
3294 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3295 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3296 E1000_RCTL_RDMTS_HALF |
3297 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3299 /* Make sure VLAN Filters are off */
3300 rctl &= ~E1000_RCTL_VFE;
3302 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3303 rctl |= E1000_RCTL_SBP;
3305 rctl &= ~E1000_RCTL_SBP;
3307 switch (adapter->rx_buffer_len) {
3310 rctl |= E1000_RCTL_SZ_2048;
3314 rctl |= E1000_RCTL_SZ_4096 |
3315 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3319 rctl |= E1000_RCTL_SZ_8192 |
3320 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3324 rctl |= E1000_RCTL_SZ_16384 |
3325 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3329 if (ifp->if_mtu > ETHERMTU)
3330 rctl |= E1000_RCTL_LPE;
3332 rctl &= ~E1000_RCTL_LPE;
3334 /* Enable Receives */
3335 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3339 em_destroy_rx_ring(struct adapter *adapter, int ndesc)
3341 struct em_buffer *rx_buffer;
3344 if (adapter->rx_buffer_area == NULL)
3347 for (i = 0; i < ndesc; i++) {
3348 rx_buffer = &adapter->rx_buffer_area[i];
3350 KKASSERT(rx_buffer->m_head == NULL);
3351 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
3353 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);
3354 bus_dma_tag_destroy(adapter->rxtag);
3356 kfree(adapter->rx_buffer_area, M_DEVBUF);
3357 adapter->rx_buffer_area = NULL;
3361 em_rxeof(struct adapter *adapter, int count)
3363 struct ifnet *ifp = &adapter->arpcom.ac_if;
3364 uint8_t status, accept_frame = 0, eop = 0;
3365 uint16_t len, desc_len, prev_len_adj;
3366 struct e1000_rx_desc *current_desc;
3370 i = adapter->next_rx_desc_to_check;
3371 current_desc = &adapter->rx_desc_base[i];
3373 if (!(current_desc->status & E1000_RXD_STAT_DD))
3376 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3377 struct mbuf *m = NULL;
3381 mp = adapter->rx_buffer_area[i].m_head;
3384 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3385 * needs to access the last received byte in the mbuf.
3387 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3388 BUS_DMASYNC_POSTREAD);
3392 desc_len = le16toh(current_desc->length);
3393 status = current_desc->status;
3394 if (status & E1000_RXD_STAT_EOP) {
3397 if (desc_len < ETHER_CRC_LEN) {
3399 prev_len_adj = ETHER_CRC_LEN - desc_len;
3401 len = desc_len - ETHER_CRC_LEN;
3408 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3410 uint32_t pkt_len = desc_len;
3412 if (adapter->fmp != NULL)
3413 pkt_len += adapter->fmp->m_pkthdr.len;
3415 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3416 if (TBI_ACCEPT(&adapter->hw, status,
3417 current_desc->errors, pkt_len, last_byte,
3418 adapter->min_frame_size, adapter->max_frame_size)) {
3419 e1000_tbi_adjust_stats_82543(&adapter->hw,
3420 &adapter->stats, pkt_len,
3421 adapter->hw.mac.addr,
3422 adapter->max_frame_size);
3431 if (em_newbuf(adapter, i, 0) != 0) {
3436 /* Assign correct length to the current fragment */
3439 if (adapter->fmp == NULL) {
3440 mp->m_pkthdr.len = len;
3441 adapter->fmp = mp; /* Store the first mbuf */
3445 * Chain mbuf's together
3449 * Adjust length of previous mbuf in chain if
3450 * we received less than 4 bytes in the last
3453 if (prev_len_adj > 0) {
3454 adapter->lmp->m_len -= prev_len_adj;
3455 adapter->fmp->m_pkthdr.len -=
3458 adapter->lmp->m_next = mp;
3459 adapter->lmp = adapter->lmp->m_next;
3460 adapter->fmp->m_pkthdr.len += len;
3464 adapter->fmp->m_pkthdr.rcvif = ifp;
3467 if (ifp->if_capenable & IFCAP_RXCSUM) {
3468 em_rxcsum(adapter, current_desc,
3472 if (status & E1000_RXD_STAT_VP) {
3473 adapter->fmp->m_pkthdr.ether_vlantag =
3474 (le16toh(current_desc->special) &
3475 E1000_RXD_SPC_VLAN_MASK);
3476 adapter->fmp->m_flags |= M_VLANTAG;
3479 adapter->fmp = NULL;
3480 adapter->lmp = NULL;
3486 /* Reuse loaded DMA map and just update mbuf chain */
3487 mp = adapter->rx_buffer_area[i].m_head;
3488 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
3489 mp->m_data = mp->m_ext.ext_buf;
3491 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN))
3492 m_adj(mp, ETHER_ALIGN);
3494 if (adapter->fmp != NULL) {
3495 m_freem(adapter->fmp);
3496 adapter->fmp = NULL;
3497 adapter->lmp = NULL;
3502 /* Zero out the receive descriptors status. */
3503 current_desc->status = 0;
3506 ifp->if_input(ifp, m);
3508 /* Advance our pointers to the next descriptor. */
3509 if (++i == adapter->num_rx_desc)
3511 current_desc = &adapter->rx_desc_base[i];
3513 adapter->next_rx_desc_to_check = i;
3515 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3517 i = adapter->num_rx_desc - 1;
3518 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i);
3522 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc,
3525 /* 82543 or newer only */
3526 if (adapter->hw.mac.type < e1000_82543 ||
3527 /* Ignore Checksum bit is set */
3528 (rx_desc->status & E1000_RXD_STAT_IXSM))
3531 if ((rx_desc->status & E1000_RXD_STAT_IPCS) &&
3532 !(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3533 /* IP Checksum Good */
3534 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
3537 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) &&
3538 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3539 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3541 CSUM_FRAG_NOT_CHECKED;
3542 mp->m_pkthdr.csum_data = htons(0xffff);
3547 em_enable_intr(struct adapter *adapter)
3549 uint32_t ims_mask = IMS_ENABLE_MASK;
3551 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer);
3555 if (adapter->hw.mac.type == e1000_82574) {
3556 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK);
3557 ims_mask |= EM_MSIX_MASK;
3560 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask);
3564 em_disable_intr(struct adapter *adapter)
3566 uint32_t clear = 0xffffffff;
3569 * The first version of 82542 had an errata where when link was forced
3570 * it would stay up even up even if the cable was disconnected.
3571 * Sequence errors were used to detect the disconnect and then the
3572 * driver would unforce the link. This code in the in the ISR. For
3573 * this to work correctly the Sequence error interrupt had to be
3574 * enabled all the time.
3576 if (adapter->hw.mac.type == e1000_82542 &&
3577 adapter->hw.revision_id == E1000_REVISION_2)
3578 clear &= ~E1000_ICR_RXSEQ;
3579 else if (adapter->hw.mac.type == e1000_82574)
3580 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0);
3582 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear);
3584 adapter->npoll.ifpc_stcount = 0;
3586 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer);
3590 * Bit of a misnomer, what this really means is
3591 * to enable OS management of the system... aka
3592 * to disable special hardware management features
3595 em_get_mgmt(struct adapter *adapter)
3597 /* A shared code workaround */
3598 #define E1000_82542_MANC2H E1000_MANC2H
3599 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3600 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3601 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3603 /* disable hardware interception of ARP */
3604 manc &= ~(E1000_MANC_ARP_EN);
3606 /* enable receiving management packets to the host */
3607 if (adapter->hw.mac.type >= e1000_82571) {
3608 manc |= E1000_MANC_EN_MNG2HOST;
3609 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3610 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3611 manc2h |= E1000_MNG2HOST_PORT_623;
3612 manc2h |= E1000_MNG2HOST_PORT_664;
3613 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3616 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3621 * Give control back to hardware management
3622 * controller if there is one.
3625 em_rel_mgmt(struct adapter *adapter)
3627 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3628 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3630 /* re-enable hardware interception of ARP */
3631 manc |= E1000_MANC_ARP_EN;
3633 if (adapter->hw.mac.type >= e1000_82571)
3634 manc &= ~E1000_MANC_EN_MNG2HOST;
3636 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3641 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3642 * For ASF and Pass Through versions of f/w this means that
3643 * the driver is loaded. For AMT version (only with 82573)
3644 * of the f/w this means that the network i/f is open.
3647 em_get_hw_control(struct adapter *adapter)
3649 /* Let firmware know the driver has taken over */
3650 if (adapter->hw.mac.type == e1000_82573) {
3653 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3654 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3655 swsm | E1000_SWSM_DRV_LOAD);
3659 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3660 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3661 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3663 adapter->flags |= EM_FLAG_HW_CTRL;
3667 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3668 * For ASF and Pass Through versions of f/w this means that the
3669 * driver is no longer loaded. For AMT version (only with 82573)
3670 * of the f/w this means that the network i/f is closed.
3673 em_rel_hw_control(struct adapter *adapter)
3675 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0)
3677 adapter->flags &= ~EM_FLAG_HW_CTRL;
3679 /* Let firmware taken over control of h/w */
3680 if (adapter->hw.mac.type == e1000_82573) {
3683 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3684 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3685 swsm & ~E1000_SWSM_DRV_LOAD);
3689 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3690 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3691 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3696 em_is_valid_eaddr(const uint8_t *addr)
3698 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3700 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3707 * Enable PCI Wake On Lan capability
3710 em_enable_wol(device_t dev)
3712 uint16_t cap, status;
3715 /* First find the capabilities pointer*/
3716 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3718 /* Read the PM Capabilities */
3719 id = pci_read_config(dev, cap, 1);
3720 if (id != PCIY_PMG) /* Something wrong */
3724 * OK, we have the power capabilities,
3725 * so now get the status register
3727 cap += PCIR_POWER_STATUS;
3728 status = pci_read_config(dev, cap, 2);
3729 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3730 pci_write_config(dev, cap, status, 2);
3735 * 82544 Coexistence issue workaround.
3736 * There are 2 issues.
3737 * 1. Transmit Hang issue.
3738 * To detect this issue, following equation can be used...
3739 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3740 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3743 * To detect this issue, following equation can be used...
3744 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3745 * If SUM[3:0] is in between 9 to c, we will have this issue.
3748 * Make sure we do not have ending address
3749 * as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3752 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3754 uint32_t safe_terminator;
3757 * Since issue is sensitive to length and address.
3758 * Let us first check the address...
3761 desc_array->descriptor[0].address = address;
3762 desc_array->descriptor[0].length = length;
3763 desc_array->elements = 1;
3764 return (desc_array->elements);
3768 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3770 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3771 if (safe_terminator == 0 ||
3772 (safe_terminator > 4 && safe_terminator < 9) ||
3773 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3774 desc_array->descriptor[0].address = address;
3775 desc_array->descriptor[0].length = length;
3776 desc_array->elements = 1;
3777 return (desc_array->elements);
3780 desc_array->descriptor[0].address = address;
3781 desc_array->descriptor[0].length = length - 4;
3782 desc_array->descriptor[1].address = address + (length - 4);
3783 desc_array->descriptor[1].length = 4;
3784 desc_array->elements = 2;
3785 return (desc_array->elements);
3789 em_update_stats(struct adapter *adapter)
3791 struct ifnet *ifp = &adapter->arpcom.ac_if;
3793 if (adapter->hw.phy.media_type == e1000_media_type_copper ||
3794 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3795 adapter->stats.symerrs +=
3796 E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3797 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3799 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3800 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3801 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3802 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3804 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3805 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3806 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3807 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3808 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3809 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3810 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3811 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3812 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3813 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3814 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3815 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3816 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3817 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3818 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3819 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3820 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3821 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3822 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3823 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3825 /* For the 64-bit byte counters the low dword must be read first. */
3826 /* Both registers clear on the read of the high dword */
3828 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH);
3829 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH);
3831 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3832 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3833 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3834 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3835 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3837 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3838 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3840 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3841 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3842 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3843 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3844 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3845 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3846 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3847 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3848 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3849 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3851 if (adapter->hw.mac.type >= e1000_82543) {
3852 adapter->stats.algnerrc +=
3853 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3854 adapter->stats.rxerrc +=
3855 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3856 adapter->stats.tncrs +=
3857 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3858 adapter->stats.cexterr +=
3859 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3860 adapter->stats.tsctc +=
3861 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3862 adapter->stats.tsctfc +=
3863 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3866 ifp->if_collisions = adapter->stats.colc;
3870 adapter->dropped_pkts + adapter->stats.rxerrc +
3871 adapter->stats.crcerrs + adapter->stats.algnerrc +
3872 adapter->stats.ruc + adapter->stats.roc +
3873 adapter->stats.mpc + adapter->stats.cexterr;
3877 adapter->stats.ecol + adapter->stats.latecol +
3878 adapter->watchdog_events;
3882 em_print_debug_info(struct adapter *adapter)
3884 device_t dev = adapter->dev;
3885 uint8_t *hw_addr = adapter->hw.hw_addr;
3887 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3888 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3889 E1000_READ_REG(&adapter->hw, E1000_CTRL),
3890 E1000_READ_REG(&adapter->hw, E1000_RCTL));
3891 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3892 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\
3893 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) );
3894 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3895 adapter->hw.fc.high_water,
3896 adapter->hw.fc.low_water);
3897 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3898 E1000_READ_REG(&adapter->hw, E1000_TIDV),
3899 E1000_READ_REG(&adapter->hw, E1000_TADV));
3900 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3901 E1000_READ_REG(&adapter->hw, E1000_RDTR),
3902 E1000_READ_REG(&adapter->hw, E1000_RADV));
3903 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3904 (long long)adapter->tx_fifo_wrk_cnt,
3905 (long long)adapter->tx_fifo_reset_cnt);
3906 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3907 E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
3908 E1000_READ_REG(&adapter->hw, E1000_TDT(0)));
3909 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3910 E1000_READ_REG(&adapter->hw, E1000_RDH(0)),
3911 E1000_READ_REG(&adapter->hw, E1000_RDT(0)));
3912 device_printf(dev, "Num Tx descriptors avail = %d\n",
3913 adapter->num_tx_desc_avail);
3914 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3915 adapter->no_tx_desc_avail1);
3916 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3917 adapter->no_tx_desc_avail2);
3918 device_printf(dev, "Std mbuf failed = %ld\n",
3919 adapter->mbuf_alloc_failed);
3920 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3921 adapter->mbuf_cluster_failed);
3922 device_printf(dev, "Driver dropped packets = %ld\n",
3923 adapter->dropped_pkts);
3924 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3925 adapter->no_tx_dma_setup);
3929 em_print_hw_stats(struct adapter *adapter)
3931 device_t dev = adapter->dev;
3933 device_printf(dev, "Excessive collisions = %lld\n",
3934 (long long)adapter->stats.ecol);
3935 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3936 device_printf(dev, "Symbol errors = %lld\n",
3937 (long long)adapter->stats.symerrs);
3939 device_printf(dev, "Sequence errors = %lld\n",
3940 (long long)adapter->stats.sec);
3941 device_printf(dev, "Defer count = %lld\n",
3942 (long long)adapter->stats.dc);
3943 device_printf(dev, "Missed Packets = %lld\n",
3944 (long long)adapter->stats.mpc);
3945 device_printf(dev, "Receive No Buffers = %lld\n",
3946 (long long)adapter->stats.rnbc);
3947 /* RLEC is inaccurate on some hardware, calculate our own. */
3948 device_printf(dev, "Receive Length Errors = %lld\n",
3949 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc));
3950 device_printf(dev, "Receive errors = %lld\n",
3951 (long long)adapter->stats.rxerrc);
3952 device_printf(dev, "Crc errors = %lld\n",
3953 (long long)adapter->stats.crcerrs);
3954 device_printf(dev, "Alignment errors = %lld\n",
3955 (long long)adapter->stats.algnerrc);
3956 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3957 (long long)adapter->stats.cexterr);
3958 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns);
3959 device_printf(dev, "watchdog timeouts = %ld\n",
3960 adapter->watchdog_events);
3961 device_printf(dev, "XON Rcvd = %lld\n",
3962 (long long)adapter->stats.xonrxc);
3963 device_printf(dev, "XON Xmtd = %lld\n",
3964 (long long)adapter->stats.xontxc);
3965 device_printf(dev, "XOFF Rcvd = %lld\n",
3966 (long long)adapter->stats.xoffrxc);
3967 device_printf(dev, "XOFF Xmtd = %lld\n",
3968 (long long)adapter->stats.xofftxc);
3969 device_printf(dev, "Good Packets Rcvd = %lld\n",
3970 (long long)adapter->stats.gprc);
3971 device_printf(dev, "Good Packets Xmtd = %lld\n",
3972 (long long)adapter->stats.gptc);
3976 em_print_nvm_info(struct adapter *adapter)
3978 uint16_t eeprom_data;
3981 /* Its a bit crude, but it gets the job done */
3982 kprintf("\nInterface EEPROM Dump:\n");
3983 kprintf("Offset\n0x0000 ");
3984 for (i = 0, j = 0; i < 32; i++, j++) {
3985 if (j == 8) { /* Make the offset block */
3987 kprintf("\n0x00%x0 ",row);
3989 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
3990 kprintf("%04x ", eeprom_data);
3996 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3998 struct adapter *adapter;
4003 error = sysctl_handle_int(oidp, &result, 0, req);
4004 if (error || !req->newptr)
4007 adapter = (struct adapter *)arg1;
4008 ifp = &adapter->arpcom.ac_if;
4010 lwkt_serialize_enter(ifp->if_serializer);
4013 em_print_debug_info(adapter);
4016 * This value will cause a hex dump of the
4017 * first 32 16-bit words of the EEPROM to
4021 em_print_nvm_info(adapter);
4023 lwkt_serialize_exit(ifp->if_serializer);
4029 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
4034 error = sysctl_handle_int(oidp, &result, 0, req);
4035 if (error || !req->newptr)
4039 struct adapter *adapter = (struct adapter *)arg1;
4040 struct ifnet *ifp = &adapter->arpcom.ac_if;
4042 lwkt_serialize_enter(ifp->if_serializer);
4043 em_print_hw_stats(adapter);
4044 lwkt_serialize_exit(ifp->if_serializer);
4050 em_add_sysctl(struct adapter *adapter)
4052 sysctl_ctx_init(&adapter->sysctl_ctx);
4053 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
4054 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
4055 device_get_nameunit(adapter->dev),
4057 if (adapter->sysctl_tree == NULL) {
4058 device_printf(adapter->dev, "can't add sysctl node\n");
4060 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4061 SYSCTL_CHILDREN(adapter->sysctl_tree),
4062 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4063 em_sysctl_debug_info, "I", "Debug Information");
4065 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4066 SYSCTL_CHILDREN(adapter->sysctl_tree),
4067 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4068 em_sysctl_stats, "I", "Statistics");
4070 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4071 SYSCTL_CHILDREN(adapter->sysctl_tree),
4072 OID_AUTO, "rxd", CTLFLAG_RD,
4073 &adapter->num_rx_desc, 0, NULL);
4074 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4075 SYSCTL_CHILDREN(adapter->sysctl_tree),
4076 OID_AUTO, "txd", CTLFLAG_RD,
4077 &adapter->num_tx_desc, 0, NULL);
4079 if (adapter->hw.mac.type >= e1000_82540) {
4080 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4081 SYSCTL_CHILDREN(adapter->sysctl_tree),
4082 OID_AUTO, "int_throttle_ceil",
4083 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4084 em_sysctl_int_throttle, "I",
4085 "interrupt throttling rate");
4087 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4088 SYSCTL_CHILDREN(adapter->sysctl_tree),
4089 OID_AUTO, "int_tx_nsegs",
4090 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4091 em_sysctl_int_tx_nsegs, "I",
4092 "# segments per TX interrupt");
4093 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4094 SYSCTL_CHILDREN(adapter->sysctl_tree),
4095 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW,
4096 &adapter->tx_wreg_nsegs, 0,
4097 "# segments before write to hardware register");
4102 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
4104 struct adapter *adapter = (void *)arg1;
4105 struct ifnet *ifp = &adapter->arpcom.ac_if;
4106 int error, throttle;
4108 throttle = adapter->int_throttle_ceil;
4109 error = sysctl_handle_int(oidp, &throttle, 0, req);
4110 if (error || req->newptr == NULL)
4112 if (throttle < 0 || throttle > 1000000000 / 256)
4117 * Set the interrupt throttling rate in 256ns increments,
4118 * recalculate sysctl value assignment to get exact frequency.
4120 throttle = 1000000000 / 256 / throttle;
4122 /* Upper 16bits of ITR is reserved and should be zero */
4123 if (throttle & 0xffff0000)
4127 lwkt_serialize_enter(ifp->if_serializer);
4130 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
4132 adapter->int_throttle_ceil = 0;
4134 if (ifp->if_flags & IFF_RUNNING)
4135 em_set_itr(adapter, throttle);
4137 lwkt_serialize_exit(ifp->if_serializer);
4140 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
4141 adapter->int_throttle_ceil);
4147 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
4149 struct adapter *adapter = (void *)arg1;
4150 struct ifnet *ifp = &adapter->arpcom.ac_if;
4153 segs = adapter->tx_int_nsegs;
4154 error = sysctl_handle_int(oidp, &segs, 0, req);
4155 if (error || req->newptr == NULL)
4160 lwkt_serialize_enter(ifp->if_serializer);
4163 * Don't allow int_tx_nsegs to become:
4164 * o Less the oact_tx_desc
4165 * o Too large that no TX desc will cause TX interrupt to
4166 * be generated (OACTIVE will never recover)
4167 * o Too small that will cause tx_dd[] overflow
4169 if (segs < adapter->oact_tx_desc ||
4170 segs >= adapter->num_tx_desc - adapter->oact_tx_desc ||
4171 segs < adapter->num_tx_desc / EM_TXDD_SAFE) {
4175 adapter->tx_int_nsegs = segs;
4178 lwkt_serialize_exit(ifp->if_serializer);
4184 em_set_itr(struct adapter *adapter, uint32_t itr)
4186 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr);
4187 if (adapter->hw.mac.type == e1000_82574) {
4191 * When using MSIX interrupts we need to
4192 * throttle using the EITR register
4194 for (i = 0; i < 4; ++i) {
4195 E1000_WRITE_REG(&adapter->hw,
4196 E1000_EITR_82574(i), itr);
4202 em_disable_aspm(struct adapter *adapter)
4204 uint16_t link_cap, link_ctrl, disable;
4205 uint8_t pcie_ptr, reg;
4206 device_t dev = adapter->dev;
4208 switch (adapter->hw.mac.type) {
4213 * 82573 specification update
4214 * errata #8 disable L0s
4215 * errata #41 disable L1
4217 * 82571/82572 specification update
4218 # errata #13 disable L1
4219 * errata #68 disable L0s
4221 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4227 * 82574 specification update errata #20
4228 * 82583 specification update errata #9
4230 * There is no need to disable L1
4232 disable = PCIEM_LNKCTL_ASPM_L0S;
4239 pcie_ptr = pci_get_pciecap_ptr(dev);
4243 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4244 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4248 if_printf(&adapter->arpcom.ac_if,
4249 "disable ASPM %#02x\n", disable);
4252 reg = pcie_ptr + PCIER_LINKCTRL;
4253 link_ctrl = pci_read_config(dev, reg, 2);
4254 link_ctrl &= ~disable;
4255 pci_write_config(dev, reg, link_ctrl, 2);
4259 em_tso_pullup(struct adapter *adapter, struct mbuf **mp)
4261 int iphlen, hoff, thoff, ex = 0;
4266 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4268 iphlen = m->m_pkthdr.csum_iphlen;
4269 thoff = m->m_pkthdr.csum_thlen;
4270 hoff = m->m_pkthdr.csum_lhlen;
4272 KASSERT(iphlen > 0, ("invalid ip hlen"));
4273 KASSERT(thoff > 0, ("invalid tcp hlen"));
4274 KASSERT(hoff > 0, ("invalid ether hlen"));
4276 if (adapter->flags & EM_FLAG_TSO_PULLEX)
4279 if (m->m_len < hoff + iphlen + thoff + ex) {
4280 m = m_pullup(m, hoff + iphlen + thoff + ex);
4287 ip = mtodoff(m, struct ip *, hoff);
4294 em_tso_setup(struct adapter *adapter, struct mbuf *mp,
4295 uint32_t *txd_upper, uint32_t *txd_lower)
4297 struct e1000_context_desc *TXD;
4298 int hoff, iphlen, thoff, hlen;
4299 int mss, pktlen, curr_txd;
4301 iphlen = mp->m_pkthdr.csum_iphlen;
4302 thoff = mp->m_pkthdr.csum_thlen;
4303 hoff = mp->m_pkthdr.csum_lhlen;
4304 mss = mp->m_pkthdr.tso_segsz;
4305 pktlen = mp->m_pkthdr.len;
4307 if (adapter->csum_flags == CSUM_TSO &&
4308 adapter->csum_iphlen == iphlen &&
4309 adapter->csum_lhlen == hoff &&
4310 adapter->csum_thlen == thoff &&
4311 adapter->csum_mss == mss &&
4312 adapter->csum_pktlen == pktlen) {
4313 *txd_upper = adapter->csum_txd_upper;
4314 *txd_lower = adapter->csum_txd_lower;
4317 hlen = hoff + iphlen + thoff;
4320 * Setup a new TSO context.
4323 curr_txd = adapter->next_avail_tx_desc;
4324 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
4326 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4327 E1000_TXD_DTYP_D | /* Data descr type */
4328 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4330 /* IP and/or TCP header checksum calculation and insertion. */
4331 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4334 * Start offset for header checksum calculation.
4335 * End offset for header checksum calculation.
4336 * Offset of place put the checksum.
4338 TXD->lower_setup.ip_fields.ipcss = hoff;
4339 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4340 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4343 * Start offset for payload checksum calculation.
4344 * End offset for payload checksum calculation.
4345 * Offset of place to put the checksum.
4347 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4348 TXD->upper_setup.tcp_fields.tucse = 0;
4349 TXD->upper_setup.tcp_fields.tucso =
4350 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4353 * Payload size per packet w/o any headers.
4354 * Length of all headers up to payload.
4356 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4357 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4358 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4359 E1000_TXD_CMD_DEXT | /* Extended descr */
4360 E1000_TXD_CMD_TSE | /* TSE context */
4361 E1000_TXD_CMD_IP | /* Do IP csum */
4362 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4363 (pktlen - hlen)); /* Total len */
4365 /* Save the information for this TSO context */
4366 adapter->csum_flags = CSUM_TSO;
4367 adapter->csum_lhlen = hoff;
4368 adapter->csum_iphlen = iphlen;
4369 adapter->csum_thlen = thoff;
4370 adapter->csum_mss = mss;
4371 adapter->csum_pktlen = pktlen;
4372 adapter->csum_txd_upper = *txd_upper;
4373 adapter->csum_txd_lower = *txd_lower;
4375 if (++curr_txd == adapter->num_tx_desc)
4378 KKASSERT(adapter->num_tx_desc_avail > 0);
4379 adapter->num_tx_desc_avail--;
4381 adapter->next_avail_tx_desc = curr_txd;