2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
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14 * must display the following acknowledgement:
15 * This product includes software developed by Comtrol Corporation.
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20 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * $FreeBSD: src/sys/i386/isa/rpreg.h,v 1.2.6.1 2000/08/03 01:01:20 peter Exp $
33 * $DragonFly: src/sys/dev/serial/rp2/Attic/rpreg.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
37 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
40 typedef unsigned char Byte_t;
41 typedef unsigned int ByteIO_t;
43 typedef unsigned int Word_t;
44 typedef unsigned int WordIO_t;
46 typedef unsigned long DWord_t;
47 typedef unsigned int DWordIO_t;
49 #define sOutB(a, b) outb(a, b)
50 #define sOutW(a, b) outw(a, b)
51 #define sOutDW(a, b) outl(a, b)
52 #define sInB(a) (inb(a))
53 #define sInW(a) (inw(a))
54 #define sOutStrW(port, addr, count) outsw(port, addr, count)
55 #define sInStrW(port, addr, count) insw(port, addr, count)
58 * End of OS-specific defines
64 #define AIOP_CTL_SIZE 4
65 #define CHAN_AIOP_SIZE 8
66 #define MAX_PORTS_PER_AIOP 8
67 #define MAX_AIOPS_PER_BOARD 4
68 #define MAX_PORTS_PER_BOARD 32
75 /* Controller ID numbers */
76 #define CTLID_NULL -1 /* no controller exists */
77 #define CTLID_0001 0x0001 /* controller release 1 */
80 #define RP_VENDOR_ID 0x11FE
81 #define RP_DEVICE_ID_8OCTA 0x0001
82 #define RP_DEVICE_ID_8INTF 0x0002
83 #define RP_DEVICE_ID_16INTF 0x0003
84 #define RP_DEVICE_ID_32INTF 0x0004
86 /* AIOP ID numbers, identifies AIOP type implementing channel */
87 #define AIOPID_NULL -1 /* no AIOP or channel exists */
88 #define AIOPID_0001 0x0001 /* AIOP release 1 */
90 #define NULLDEV -1 /* identifies non-existant device */
91 #define NULLCTL -1 /* identifies non-existant controller */
92 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
93 #define NULLAIOP -1 /* identifies non-existant AIOP */
94 #define NULLCHAN -1 /* identifies non-existant channel */
96 /************************************************************************
97 Global Register Offsets - Direct Access - Fixed values
98 ************************************************************************/
100 #define _CMD_REG 0x38 /* Command Register 8 Write */
101 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
102 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
103 #define _UNUSED 0x3B /* Unused 8 */
104 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
105 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
107 /************************************************************************
108 Channel Register Offsets for 1st channel in AIOP - Direct Access
109 ************************************************************************/
110 #define _TD0 0x00 /* Transmit Data 16 Write */
111 #define _RD0 0x00 /* Receive Data 16 Read */
112 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
113 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
114 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
116 /************************************************************************
117 Tx Control Register Offsets - Indexed - External - Fixed
118 ************************************************************************/
119 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
120 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
121 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
122 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
123 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
124 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
126 /************************************************************************
128 ************************************************************************/
129 #define RXFIFO_DATA 0x5f
130 #define RXFIFO_OUT 0x5c
131 #define RXFIFO_EN 0x08
132 #define RXFIFO_DIS 0xa7
134 /************************************************************************
135 Memory Controller Register Offsets - Indexed - External - Fixed
136 ************************************************************************/
137 #define _RX_FIFO 0x000 /* Rx FIFO */
138 #define _TX_FIFO 0x800 /* Tx FIFO */
139 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
140 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
141 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
142 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
143 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
144 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
146 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
147 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
148 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
150 /************************************************************************
151 Tx Priority Buffer - Indexed - External - Fixed
152 ************************************************************************/
153 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
154 #define TXP_SIZE 0x20 /* 32 bytes */
156 /************************************************************************
157 Channel Register Offsets - Indexed - Internal - Fixed
158 ************************************************************************/
160 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
161 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
162 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
163 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
165 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
191 #define STMBREAK 0x08 /* BREAK */
192 #define STMFRAME 0x04 /* framing error */
193 #define STMRCVROVR 0x02 /* receiver over run error */
194 #define STMPARITY 0x01 /* parity error */
195 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
196 #define STMBREAKH 0x800 /* BREAK */
197 #define STMFRAMEH 0x400 /* framing error */
198 #define STMRCVROVRH 0x200 /* receiver over run error */
199 #define STMPARITYH 0x100 /* parity error */
200 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
202 #define CTS_ACT 0x20 /* CTS input asserted */
203 #define DSR_ACT 0x10 /* DSR input asserted */
204 #define CD_ACT 0x08 /* CD input asserted */
205 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
206 #define TXSHRMT 0x02 /* Tx shift register is empty */
207 #define RDA 0x01 /* Rx data available */
208 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
210 #define STATMODE 0x8000 /* status mode enable bit */
211 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
212 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
213 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
214 #define RXBREAK 0x0400 /* received BREAK */
215 #define RXFRAME 0x0200 /* received framing error */
216 #define RXPARITY 0x0100 /* received parity error */
217 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
219 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
220 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
221 #define TXINT_EN 0x10 /* transmit interrupt enable */
222 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
223 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
224 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
225 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
227 #define SETBREAK 0x10 /* send break condition (must clear) */
228 #define LOCALLOOP 0x08 /* local loopback set for test */
229 #define SET_DTR 0x04 /* assert DTR */
230 #define SET_RTS 0x02 /* assert RTS */
231 #define TX_ENABLE 0x01 /* enable transmitter */
233 #define RTSFC_EN 0x40 /* RTS flow control enable */
234 #define RXPROC_EN 0x20 /* receive processor enable */
235 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
236 #define TRIG_1 0x08 /* trigger level 1 char */
237 #define TRIG_1_2 0x10 /* trigger level 1/2 */
238 #define TRIG_7_8 0x18 /* trigger level 7/8 */
239 #define TRIG_MASK 0x18 /* trigger level mask */
240 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
241 #define RXINT_EN 0x02 /* Rx interrupt enable */
242 #define MCINT_EN 0x01 /* modem change interrupt enable */
244 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
245 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
246 #define SRC_INT 0x08 /* special receive condition interrupt */
247 #define DELTA_CD 0x04 /* CD change interrupt */
248 #define DELTA_CTS 0x02 /* CTS change interrupt */
249 #define DELTA_DSR 0x01 /* DSR change interrupt */
251 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
252 #define IGN2_EN 0x08 /* ignore byte 2 enable */
253 #define IGN1_EN 0x04 /* ignore byte 1 enable */
254 #define COMP2_EN 0x02 /* compare byte 2 enable */
255 #define COMP1_EN 0x01 /* compare byte 1 enable */
257 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
258 #define TXOVERIDE 0x40 /* Transmit software off override */
259 #define RESETUART 0x20 /* reset channel's UART */
260 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
261 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
263 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
264 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
265 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
266 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
268 #define INTR_EN 0x08 /* allow interrupts to host */
269 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
271 /**************************************************************************
272 MUDBAC remapped for PCI
273 **************************************************************************/
275 #define _CFG_INT_PCI 0x40
276 #define _PCI_INT_FUNC 0x3A
278 #define PCI_STROB 0x2000
279 #define INTR_EN_PCI 0x0010
281 #define CHAN3_EN 0x08 /* enable AIOP 3 */
282 #define CHAN2_EN 0x04 /* enable AIOP 2 */
283 #define CHAN1_EN 0x02 /* enable AIOP 1 */
284 #define CHAN0_EN 0x01 /* enable AIOP 0 */
285 #define FREQ_DIS 0x00
286 #define FREQ_274HZ 0x60
287 #define FREQ_137HZ 0x50
288 #define FREQ_69HZ 0x40
289 #define FREQ_34HZ 0x30
290 #define FREQ_17HZ 0x20
291 #define FREQ_9HZ 0x10
292 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
294 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
297 #define RREGDATASIZE 52
299 /* Controller level information structure */
313 WordIO_t AiopIO[AIOP_CTL_SIZE];
314 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
315 int AiopID[AIOP_CTL_SIZE];
316 int AiopNumChan[AIOP_CTL_SIZE];
319 typedef CONTROLLER_T CONTROLLER_t;
321 /* Channel level information structure */
348 Byte_t R[RREGDATASIZE];
355 Byte_t TxReplace1[4];
356 Byte_t TxReplace2[4];
359 typedef CHANNEL_T CHANNEL_t;
360 typedef CHANNEL_T * CHANPTR_T;
362 /***************************************************************************
364 Purpose: Stop sending a transmit BREAK signal
366 CHANNEL_T *ChP; Ptr to channel structure
368 #define sClrBreak(ChP) \
370 (ChP)->TxControl[3] &= ~SETBREAK; \
371 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
374 /***************************************************************************
376 Purpose: Clr the DTR output
378 CHANNEL_T *ChP; Ptr to channel structure
380 #define sClrDTR(ChP) \
382 (ChP)->TxControl[3] &= ~SET_DTR; \
383 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
386 /***************************************************************************
388 Purpose: Clr the RTS output
390 CHANNEL_T *ChP; Ptr to channel structure
392 #define sClrRTS(ChP) \
394 (ChP)->TxControl[3] &= ~SET_RTS; \
395 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
398 /***************************************************************************
400 Purpose: Clear any existing transmit software flow control off condition
401 Call: sClrTxXOFF(ChP)
402 CHANNEL_T *ChP; Ptr to channel structure
404 #define sClrTxXOFF(ChP) \
406 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
407 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
410 /***************************************************************************
411 Function: sCtlNumToCtlPtr
412 Purpose: Convert a controller number to controller structure pointer
413 Call: sCtlNumToCtlPtr(CtlNum)
414 int CtlNum; Controller number
415 Return: CONTROLLER_T *: Ptr to controller structure
417 #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
419 /***************************************************************************
420 Function: sControllerEOI
421 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
422 Call: sControllerEOI(CtlP)
423 CONTROLLER_T *CtlP; Ptr to controller structure
425 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
428 /***************************************************************************
429 Function: sPCIControllerEOI
430 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
431 Call: sPCIControllerEOI(CtlP)
432 CONTROLLER_T *CtlP; Ptr to controller structure
434 #define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB)
436 /***************************************************************************
438 Purpose: Disable I/O access to an AIOP
440 CONTROLLER_T *CtlP; Ptr to controller structure
441 int AiopNum; Number of AIOP on controller
443 #define sDisAiop(CTLP,AIOPNUM) \
445 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
446 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
449 /***************************************************************************
450 Function: sDisCTSFlowCtl
451 Purpose: Disable output flow control using CTS
452 Call: sDisCTSFlowCtl(ChP)
453 CHANNEL_T *ChP; Ptr to channel structure
455 #define sDisCTSFlowCtl(ChP) \
457 (ChP)->TxControl[2] &= ~CTSFC_EN; \
458 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
461 /***************************************************************************
463 Purpose: Disable parity
464 Call: sDisParity(ChP)
465 CHANNEL_T *ChP; Ptr to channel structure
466 Comments: Function sSetParity() can be used in place of functions sEnParity(),
467 sDisParity(), sSetOddParity(), and sSetEvenParity().
469 #define sDisParity(ChP) \
471 (ChP)->TxControl[2] &= ~PARITY_EN; \
472 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
475 /***************************************************************************
477 Purpose: Disable Rx FIFO
478 Call: sDisRxFIFO(ChP)
479 CHANNEL_T *ChP; Ptr to channel structure
481 #define sDisRxFIFO(ChP) \
483 (ChP)->R[0x32] = 0x0a; \
484 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
487 /***************************************************************************
488 Function: sDisRxStatusMode
489 Purpose: Disable the Rx status mode
490 Call: sDisRxStatusMode(ChP)
491 CHANNEL_T *ChP; Ptr to channel structure
492 Comments: This takes the channel out of the receive status mode. All
493 subsequent reads of receive data using sReadRxWord() will return
496 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
498 /***************************************************************************
499 Function: sDisTransmit
500 Purpose: Disable transmit
501 Call: sDisTransmit(ChP)
502 CHANNEL_T *ChP; Ptr to channel structure
503 This disables movement of Tx data from the Tx FIFO into the 1 byte
504 Tx buffer. Therefore there could be up to a 2 byte latency
505 between the time sDisTransmit() is called and the transmit buffer
506 and transmit shift register going completely empty.
508 #define sDisTransmit(ChP) \
510 (ChP)->TxControl[3] &= ~TX_ENABLE; \
511 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
514 /***************************************************************************
515 Function: sDisTxSoftFlowCtl
516 Purpose: Disable Tx Software Flow Control
517 Call: sDisTxSoftFlowCtl(ChP)
518 CHANNEL_T *ChP; Ptr to channel structure
520 #define sDisTxSoftFlowCtl(ChP) \
522 (ChP)->R[0x06] = 0x8a; \
523 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
526 /***************************************************************************
528 Purpose: Enable I/O access to an AIOP
530 CONTROLLER_T *CtlP; Ptr to controller structure
531 int AiopNum; Number of AIOP on controller
533 #define sEnAiop(CTLP,AIOPNUM) \
535 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
536 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
539 /***************************************************************************
540 Function: sEnCTSFlowCtl
541 Purpose: Enable output flow control using CTS
542 Call: sEnCTSFlowCtl(ChP)
543 CHANNEL_T *ChP; Ptr to channel structure
545 #define sEnCTSFlowCtl(ChP) \
547 (ChP)->TxControl[2] |= CTSFC_EN; \
548 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
551 /***************************************************************************
553 Purpose: Enable parity
555 CHANNEL_T *ChP; Ptr to channel structure
556 Comments: Function sSetParity() can be used in place of functions sEnParity(),
557 sDisParity(), sSetOddParity(), and sSetEvenParity().
559 Warnings: Before enabling parity odd or even parity should be chosen using
560 functions sSetOddParity() or sSetEvenParity().
562 #define sEnParity(ChP) \
564 (ChP)->TxControl[2] |= PARITY_EN; \
565 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
568 /***************************************************************************
569 Function: sEnRTSFlowCtl
572 #define sEnRTSFlowCtl(ChP) \
574 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
575 (ChP)->TxControl[3] &= ~SET_RTS; \
576 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
577 (ChP)->RxControl[2] |= RTSFC_EN; \
578 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
581 /***************************************************************************
582 Function: sDisRTSFlowCtl
585 #define sDisRTSFlowCtl(ChP) \
587 (ChP)->RxControl[2] &= ~RTSFC_EN; \
588 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
591 /***************************************************************************
593 Purpose: Enable Rx FIFO
595 CHANNEL_T *ChP; Ptr to channel structure
597 #define sEnRxFIFO(ChP) \
599 (ChP)->R[0x32] = 0x08; \
600 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
603 /***************************************************************************
604 Function: sEnRxProcessor
605 Purpose: Enable the receive processor
606 Call: sEnRxProcessor(ChP)
607 CHANNEL_T *ChP; Ptr to channel structure
608 Comments: This function is used to start the receive processor. When
609 the channel is in the reset state the receive processor is not
610 running. This is done to prevent the receive processor from
611 executing invalid microcode instructions prior to the
612 downloading of the microcode.
614 Warnings: This function must be called after valid microcode has been
615 downloaded to the AIOP, and it must not be called before the
616 microcode has been downloaded.
618 #define sEnRxProcessor(ChP) \
620 (ChP)->RxControl[2] |= RXPROC_EN; \
621 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
624 /***************************************************************************
625 Function: sEnRxStatusMode
626 Purpose: Enable the Rx status mode
627 Call: sEnRxStatusMode(ChP)
628 CHANNEL_T *ChP; Ptr to channel structure
629 Comments: This places the channel in the receive status mode. All subsequent
630 reads of receive data using sReadRxWord() will return a data byte
631 in the low word and a status byte in the high word.
634 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
636 /***************************************************************************
637 Function: sEnTransmit
638 Purpose: Enable transmit
639 Call: sEnTransmit(ChP)
640 CHANNEL_T *ChP; Ptr to channel structure
642 #define sEnTransmit(ChP) \
644 (ChP)->TxControl[3] |= TX_ENABLE; \
645 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
648 /***************************************************************************
649 Function: sGetAiopIntStatus
650 Purpose: Get the AIOP interrupt status
651 Call: sGetAiopIntStatus(CtlP,AiopNum)
652 CONTROLLER_T *CtlP; Ptr to controller structure
653 int AiopNum; AIOP number
654 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
655 represent channels 0 through 7 respectively. If a
656 bit is set that channel is interrupting.
658 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
660 /***************************************************************************
661 Function: sGetAiopNumChan
662 Purpose: Get the number of channels supported by an AIOP
663 Call: sGetAiopNumChan(CtlP,AiopNum)
664 CONTROLLER_T *CtlP; Ptr to controller structure
665 int AiopNum; AIOP number
666 Return: int: The number of channels supported by the AIOP
668 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
670 /***************************************************************************
671 Function: sGetChanIntID
672 Purpose: Get a channel's interrupt identification byte
673 Call: sGetChanIntID(ChP)
674 CHANNEL_T *ChP; Ptr to channel structure
675 Return: Byte_t: The channel interrupt ID. Can be any
676 combination of the following flags:
677 RXF_TRIG: Rx FIFO trigger level interrupt
678 TXFIFO_MT: Tx FIFO empty interrupt
679 SRC_INT: Special receive condition interrupt
680 DELTA_CD: CD change interrupt
681 DELTA_CTS: CTS change interrupt
682 DELTA_DSR: DSR change interrupt
684 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
686 /***************************************************************************
687 Function: sGetChanNum
688 Purpose: Get the number of a channel within an AIOP
689 Call: sGetChanNum(ChP)
690 CHANNEL_T *ChP; Ptr to channel structure
691 Return: int: Channel number within AIOP, or NULLCHAN if channel does
694 #define sGetChanNum(ChP) (ChP)->ChanNum
696 /***************************************************************************
697 Function: sGetChanStatus
698 Purpose: Get the channel status
699 Call: sGetChanStatus(ChP)
700 CHANNEL_T *ChP; Ptr to channel structure
701 Return: Word_t: The channel status. Can be any combination of
704 CTS_ACT: CTS input asserted
705 DSR_ACT: DSR input asserted
706 CD_ACT: CD input asserted
707 TXFIFOMT: Tx FIFO is empty
708 TXSHRMT: Tx shift register is empty
709 RDA: Rx data available
712 STATMODE: status mode enable bit
713 RXFOVERFL: receive FIFO overflow
714 RX2MATCH: receive compare byte 2 match
715 RX1MATCH: receive compare byte 1 match
716 RXBREAK: received BREAK
717 RXFRAME: received framing error
718 RXPARITY: received parity error
719 Warnings: This function will clear the high byte flags in the Channel
722 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
724 /***************************************************************************
725 Function: sGetChanStatusLo
726 Purpose: Get the low byte only of the channel status
727 Call: sGetChanStatusLo(ChP)
728 CHANNEL_T *ChP; Ptr to channel structure
729 Return: Byte_t: The channel status low byte. Can be any combination
730 of the following flags:
731 CTS_ACT: CTS input asserted
732 DSR_ACT: DSR input asserted
733 CD_ACT: CD input asserted
734 TXFIFOMT: Tx FIFO is empty
735 TXSHRMT: Tx shift register is empty
736 RDA: Rx data available
738 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
740 /***************************************************************************
741 Function: sGetControllerIntStatus
742 Purpose: Get the controller interrupt status
743 Call: sGetControllerIntStatus(CtlP)
744 CONTROLLER_T *CtlP; Ptr to controller structure
745 Return: Byte_t: The controller interrupt status in the lower 4
746 bits. Bits 0 through 3 represent AIOP's 0
747 through 3 respectively. If a bit is set that
748 AIOP is interrupting. Bits 4 through 7 will
751 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
753 /***************************************************************************
754 Function: sPCIGetControllerIntStatus
755 Purpose: Get the controller interrupt status
756 Call: sPCIGetControllerIntStatus(CtlP)
757 CONTROLLER_T *CtlP; Ptr to controller structure
758 Return: Byte_t: The controller interrupt status in the lower 4
759 bits. Bits 0 through 3 represent AIOP's 0
760 through 3 respectively. If a bit is set that
761 AIOP is interrupting. Bits 4 through 7 will
764 #define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f)
766 /***************************************************************************
768 Purpose: Get the number of data bytes in the Rx FIFO
770 CHANNEL_T *ChP; Ptr to channel structure
771 Return: int: The number of data bytes in the Rx FIFO.
772 Comments: Byte read of count register is required to obtain Rx count.
775 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
777 /***************************************************************************
779 Purpose: Get the number of data bytes in the Tx FIFO
781 CHANNEL_T *ChP; Ptr to channel structure
782 Return: Byte_t: The number of data bytes in the Tx FIFO.
783 Comments: Byte read of count register is required to obtain Tx count.
786 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
788 /*****************************************************************************
789 Function: sGetTxRxDataIO
790 Purpose: Get the I/O address of a channel's TxRx Data register
791 Call: sGetTxRxDataIO(ChP)
792 CHANNEL_T *ChP; Ptr to channel structure
793 Return: WordIO_t: I/O address of a channel's TxRx Data register
795 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
797 /***************************************************************************
798 Function: sInitChanDefaults
799 Purpose: Initialize a channel structure to its default state.
800 Call: sInitChanDefaults(ChP)
801 CHANNEL_T *ChP; Ptr to the channel structure
802 Comments: This function must be called once for every channel structure
803 that exists before any other SSCI calls can be made.
806 #define sInitChanDefaults(ChP) \
808 (ChP)->CtlP = NULLCTLPTR; \
809 (ChP)->AiopNum = NULLAIOP; \
810 (ChP)->ChanID = AIOPID_NULL; \
811 (ChP)->ChanNum = NULLCHAN; \
814 /***************************************************************************
815 Function: sResetAiopByNum
816 Purpose: Reset the AIOP by number
817 Call: sResetAiopByNum(CTLP,AIOPNUM)
818 CONTROLLER_T CTLP; Ptr to controller structure
821 #define sResetAiopByNum(CTLP,AIOPNUM) \
823 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
824 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
827 /***************************************************************************
829 Purpose: Send a transmit BREAK signal
830 Call: sSendBreak(ChP)
831 CHANNEL_T *ChP; Ptr to channel structure
833 #define sSendBreak(ChP) \
835 (ChP)->TxControl[3] |= SETBREAK; \
836 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
839 /***************************************************************************
841 Purpose: Set baud rate
842 Call: sSetBaud(ChP,Divisor)
843 CHANNEL_T *ChP; Ptr to channel structure
844 Word_t Divisor; 16 bit baud rate divisor for channel
846 #define sSetBaud(ChP,DIVISOR) \
848 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
849 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
850 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
853 /***************************************************************************
855 Purpose: Set data bits to 7
857 CHANNEL_T *ChP; Ptr to channel structure
859 #define sSetData7(ChP) \
861 (ChP)->TxControl[2] &= ~DATA8BIT; \
862 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
865 /***************************************************************************
867 Purpose: Set data bits to 8
869 CHANNEL_T *ChP; Ptr to channel structure
871 #define sSetData8(ChP) \
873 (ChP)->TxControl[2] |= DATA8BIT; \
874 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
877 /***************************************************************************
879 Purpose: Set the DTR output
881 CHANNEL_T *ChP; Ptr to channel structure
883 #define sSetDTR(ChP) \
885 (ChP)->TxControl[3] |= SET_DTR; \
886 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
889 /***************************************************************************
890 Function: sSetEvenParity
891 Purpose: Set even parity
892 Call: sSetEvenParity(ChP)
893 CHANNEL_T *ChP; Ptr to channel structure
894 Comments: Function sSetParity() can be used in place of functions sEnParity(),
895 sDisParity(), sSetOddParity(), and sSetEvenParity().
897 Warnings: This function has no effect unless parity is enabled with function
900 #define sSetEvenParity(ChP) \
902 (ChP)->TxControl[2] |= EVEN_PAR; \
903 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
906 /***************************************************************************
907 Function: sSetOddParity
908 Purpose: Set odd parity
909 Call: sSetOddParity(ChP)
910 CHANNEL_T *ChP; Ptr to channel structure
911 Comments: Function sSetParity() can be used in place of functions sEnParity(),
912 sDisParity(), sSetOddParity(), and sSetEvenParity().
914 Warnings: This function has no effect unless parity is enabled with function
917 #define sSetOddParity(ChP) \
919 (ChP)->TxControl[2] &= ~EVEN_PAR; \
920 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
923 /***************************************************************************
925 Purpose: Set the RTS output
927 CHANNEL_T *ChP; Ptr to channel structure
929 #define sSetRTS(ChP) \
931 (ChP)->TxControl[3] |= SET_RTS; \
932 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
935 /***************************************************************************
936 Function: sSetRxTrigger
937 Purpose: Set the Rx FIFO trigger level
938 Call: sSetRxProcessor(ChP,Level)
939 CHANNEL_T *ChP; Ptr to channel structure
940 Byte_t Level; Number of characters in Rx FIFO at which the
941 interrupt will be generated. Can be any of the following flags:
944 TRIG_1: 1 character in FIFO
945 TRIG_1_2: FIFO 1/2 full
946 TRIG_7_8: FIFO 7/8 full
947 Comments: An interrupt will be generated when the trigger level is reached
948 only if function sEnInterrupt() has been called with flag
949 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
950 register will be set whenever the trigger level is reached
951 regardless of the setting of RXINT_EN.
954 #define sSetRxTrigger(ChP,LEVEL) \
956 (ChP)->RxControl[2] &= ~TRIG_MASK; \
957 (ChP)->RxControl[2] |= LEVEL; \
958 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
961 /***************************************************************************
963 Purpose: Set stop bits to 1
965 CHANNEL_T *ChP; Ptr to channel structure
967 #define sSetStop1(ChP) \
969 (ChP)->TxControl[2] &= ~STOP2; \
970 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
973 /***************************************************************************
975 Purpose: Set stop bits to 2
977 CHANNEL_T *ChP; Ptr to channel structure
979 #define sSetStop2(ChP) \
981 (ChP)->TxControl[2] |= STOP2; \
982 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
985 /***************************************************************************
986 Function: sStartRxProcessor
987 Purpose: Start a channel's receive processor
988 Call: sStartRxProcessor(ChP)
989 CHANNEL_T *ChP; Ptr to channel structure
990 Comments: This function is used to start a Rx processor after it was
991 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
992 will restart both the Rx processor and software input flow control.
995 #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
997 /***************************************************************************
998 Function: sWriteTxByte
999 Purpose: Write a transmit data byte to a channel.
1000 ByteIO_t io: Channel transmit register I/O address. This can
1001 be obtained with sGetTxRxDataIO().
1002 Byte_t Data; The transmit data byte.
1003 Warnings: This function writes the data byte without checking to see if
1004 sMaxTxSize is exceeded in the Tx FIFO.
1006 #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1008 int sInitController( CONTROLLER_T *CtlP,
1011 ByteIO_t *AiopIOList,
1017 int sPCIInitController( CONTROLLER_T *CtlP,
1019 ByteIO_t *AiopIOList,
1025 int sReadAiopID(ByteIO_t io);
1026 int sReadAiopNumChan(WordIO_t io);
1027 int sInitChan( CONTROLLER_T *CtlP,
1031 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
1032 void sStopRxProcessor(CHANNEL_T *ChP);
1033 void sStopSWInFlowCtl(CHANNEL_T *ChP);
1034 void sFlushRxFIFO(CHANNEL_T *ChP);
1035 void sFlushTxFIFO(CHANNEL_T *ChP);
1036 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1037 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1038 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1041 extern Byte_t R[RDATASIZE];
1042 extern CONTROLLER_T sController[CTL_SIZE];
1043 extern Byte_t sIRQMap[16];
1044 extern Byte_t sBitMapClrTbl[8];
1045 extern Byte_t sBitMapSetTbl[8];