2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
34 #include <sys/param.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
38 #include <sys/interrupt.h>
39 #include <sys/malloc.h>
42 #include <sys/serialize.h>
43 #include <sys/serialize2.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
48 #include <net/ethernet.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/ifq_var.h>
55 #include <net/toeplitz.h>
56 #include <net/toeplitz2.h>
57 #include <net/vlan/if_vlan_var.h>
58 #include <net/vlan/if_vlan_ether.h>
60 #include <netinet/in.h>
62 #include <dev/netif/mii_layer/miivar.h>
63 #include <dev/netif/mii_layer/jmphyreg.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/jme/if_jmereg.h>
70 #include <dev/netif/jme/if_jmevar.h>
72 #include "miibus_if.h"
74 /* Define the following to disable printing Rx errors. */
75 #undef JME_SHOW_ERRORS
77 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82 if ((sc)->jme_rss_debug >= (lvl)) \
83 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85 #else /* !JME_RSS_DEBUG */
86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
87 #endif /* JME_RSS_DEBUG */
89 static int jme_probe(device_t);
90 static int jme_attach(device_t);
91 static int jme_detach(device_t);
92 static int jme_shutdown(device_t);
93 static int jme_suspend(device_t);
94 static int jme_resume(device_t);
96 static int jme_miibus_readreg(device_t, int, int);
97 static int jme_miibus_writereg(device_t, int, int, int);
98 static void jme_miibus_statchg(device_t);
100 static void jme_init(void *);
101 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void jme_start(struct ifnet *);
103 static void jme_watchdog(struct ifnet *);
104 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
105 static int jme_mediachange(struct ifnet *);
106 #ifdef DEVICE_POLLING
107 static void jme_poll(struct ifnet *, enum poll_cmd, int);
109 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
110 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
111 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
113 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
117 static void jme_intr(void *);
118 static void jme_msix_tx(void *);
119 static void jme_msix_rx(void *);
120 static void jme_txeof(struct jme_softc *);
121 static void jme_rxeof(struct jme_softc *, int, int);
122 static void jme_rx_intr(struct jme_softc *, uint32_t);
124 static int jme_msix_setup(device_t);
125 static void jme_msix_teardown(device_t, int);
126 static int jme_intr_setup(device_t);
127 static void jme_intr_teardown(device_t);
128 static void jme_msix_try_alloc(device_t);
129 static void jme_msix_free(device_t);
130 static int jme_intr_alloc(device_t);
131 static void jme_intr_free(device_t);
132 static int jme_dma_alloc(struct jme_softc *);
133 static void jme_dma_free(struct jme_softc *);
134 static int jme_init_rx_ring(struct jme_softc *, int);
135 static void jme_init_tx_ring(struct jme_softc *);
136 static void jme_init_ssb(struct jme_softc *);
137 static int jme_newbuf(struct jme_softc *, int, struct jme_rxdesc *, int);
138 static int jme_encap(struct jme_softc *, struct mbuf **);
139 static void jme_rxpkt(struct jme_softc *, int);
140 static int jme_rxring_dma_alloc(struct jme_softc *, int);
141 static int jme_rxbuf_dma_alloc(struct jme_softc *, int);
143 static void jme_tick(void *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_reset(struct jme_softc *);
146 static void jme_set_msinum(struct jme_softc *);
147 static void jme_set_vlan(struct jme_softc *);
148 static void jme_set_filter(struct jme_softc *);
149 static void jme_stop_tx(struct jme_softc *);
150 static void jme_stop_rx(struct jme_softc *);
151 static void jme_mac_config(struct jme_softc *);
152 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
156 static void jme_setwol(struct jme_softc *);
157 static void jme_setlinkspeed(struct jme_softc *);
159 static void jme_set_tx_coal(struct jme_softc *);
160 static void jme_set_rx_coal(struct jme_softc *);
161 static void jme_enable_rss(struct jme_softc *);
162 static void jme_disable_rss(struct jme_softc *);
164 static void jme_sysctl_node(struct jme_softc *);
165 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
166 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
167 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
168 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
171 * Devices supported by this driver.
173 static const struct jme_dev {
174 uint16_t jme_vendorid;
175 uint16_t jme_deviceid;
177 const char *jme_name;
179 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
181 "JMicron Inc, JMC250 Gigabit Ethernet" },
182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
184 "JMicron Inc, JMC260 Fast Ethernet" },
188 static device_method_t jme_methods[] = {
189 /* Device interface. */
190 DEVMETHOD(device_probe, jme_probe),
191 DEVMETHOD(device_attach, jme_attach),
192 DEVMETHOD(device_detach, jme_detach),
193 DEVMETHOD(device_shutdown, jme_shutdown),
194 DEVMETHOD(device_suspend, jme_suspend),
195 DEVMETHOD(device_resume, jme_resume),
198 DEVMETHOD(bus_print_child, bus_generic_print_child),
199 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
202 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
203 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
204 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
209 static driver_t jme_driver = {
212 sizeof(struct jme_softc)
215 static devclass_t jme_devclass;
217 DECLARE_DUMMY_MODULE(if_jme);
218 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
219 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
220 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
222 static const struct {
226 } jme_rx_status[JME_NRXRING_MAX] = {
227 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
228 INTR_RXQ0_DESC_EMPTY },
229 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
230 INTR_RXQ1_DESC_EMPTY },
231 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
232 INTR_RXQ2_DESC_EMPTY },
233 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
234 INTR_RXQ3_DESC_EMPTY }
237 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
238 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
239 static int jme_rx_ring_count = JME_NRXRING_DEF;
240 static int jme_msi_enable = 1;
241 static int jme_msix_enable = 1;
243 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
244 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
245 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
246 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
247 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
250 * Read a PHY register on the MII of the JMC250.
253 jme_miibus_readreg(device_t dev, int phy, int reg)
255 struct jme_softc *sc = device_get_softc(dev);
259 /* For FPGA version, PHY address 0 should be ignored. */
260 if (sc->jme_caps & JME_CAP_FPGA) {
264 if (sc->jme_phyaddr != phy)
268 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
269 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
271 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
273 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
277 device_printf(sc->jme_dev, "phy read timeout: "
278 "phy %d, reg %d\n", phy, reg);
282 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
286 * Write a PHY register on the MII of the JMC250.
289 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
291 struct jme_softc *sc = device_get_softc(dev);
294 /* For FPGA version, PHY address 0 should be ignored. */
295 if (sc->jme_caps & JME_CAP_FPGA) {
299 if (sc->jme_phyaddr != phy)
303 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
304 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
305 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
307 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
309 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
313 device_printf(sc->jme_dev, "phy write timeout: "
314 "phy %d, reg %d\n", phy, reg);
321 * Callback from MII layer when media changes.
324 jme_miibus_statchg(device_t dev)
326 struct jme_softc *sc = device_get_softc(dev);
327 struct ifnet *ifp = &sc->arpcom.ac_if;
328 struct mii_data *mii;
329 struct jme_txdesc *txd;
333 ASSERT_IFNET_SERIALIZED_ALL(ifp);
335 if ((ifp->if_flags & IFF_RUNNING) == 0)
338 mii = device_get_softc(sc->jme_miibus);
340 sc->jme_flags &= ~JME_FLAG_LINK;
341 if ((mii->mii_media_status & IFM_AVALID) != 0) {
342 switch (IFM_SUBTYPE(mii->mii_media_active)) {
345 sc->jme_flags |= JME_FLAG_LINK;
348 if (sc->jme_caps & JME_CAP_FASTETH)
350 sc->jme_flags |= JME_FLAG_LINK;
358 * Disabling Rx/Tx MACs have a side-effect of resetting
359 * JME_TXNDA/JME_RXNDA register to the first address of
360 * Tx/Rx descriptor address. So driver should reset its
361 * internal procucer/consumer pointer and reclaim any
362 * allocated resources. Note, just saving the value of
363 * JME_TXNDA and JME_RXNDA registers before stopping MAC
364 * and restoring JME_TXNDA/JME_RXNDA register is not
365 * sufficient to make sure correct MAC state because
366 * stopping MAC operation can take a while and hardware
367 * might have updated JME_TXNDA/JME_RXNDA registers
368 * during the stop operation.
371 /* Disable interrupts */
372 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
377 callout_stop(&sc->jme_tick_ch);
379 /* Stop receiver/transmitter. */
383 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
384 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
386 jme_rxeof(sc, r, -1);
387 if (rdata->jme_rxhead != NULL)
388 m_freem(rdata->jme_rxhead);
389 JME_RXCHAIN_RESET(sc, r);
392 * Reuse configured Rx descriptors and reset
393 * procuder/consumer index.
395 rdata->jme_rx_cons = 0;
399 if (sc->jme_cdata.jme_tx_cnt != 0) {
400 /* Remove queued packets for transmit. */
401 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
402 txd = &sc->jme_cdata.jme_txdesc[i];
403 if (txd->tx_m != NULL) {
405 sc->jme_cdata.jme_tx_tag,
414 jme_init_tx_ring(sc);
416 /* Initialize shadow status block. */
419 /* Program MAC with resolved speed/duplex/flow-control. */
420 if (sc->jme_flags & JME_FLAG_LINK) {
423 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
425 /* Set Tx ring address to the hardware. */
426 paddr = sc->jme_cdata.jme_tx_ring_paddr;
427 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
428 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
430 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
431 CSR_WRITE_4(sc, JME_RXCSR,
432 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
434 /* Set Rx ring address to the hardware. */
435 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
436 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
437 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
440 /* Restart receiver/transmitter. */
441 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
443 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
446 ifp->if_flags |= IFF_RUNNING;
447 ifp->if_flags &= ~IFF_OACTIVE;
448 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
450 #ifdef DEVICE_POLLING
451 if (!(ifp->if_flags & IFF_POLLING))
453 /* Reenable interrupts. */
454 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
458 * Get the current interface media status.
461 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
463 struct jme_softc *sc = ifp->if_softc;
464 struct mii_data *mii = device_get_softc(sc->jme_miibus);
466 ASSERT_IFNET_SERIALIZED_ALL(ifp);
469 ifmr->ifm_status = mii->mii_media_status;
470 ifmr->ifm_active = mii->mii_media_active;
474 * Set hardware to newly-selected media.
477 jme_mediachange(struct ifnet *ifp)
479 struct jme_softc *sc = ifp->if_softc;
480 struct mii_data *mii = device_get_softc(sc->jme_miibus);
483 ASSERT_IFNET_SERIALIZED_ALL(ifp);
485 if (mii->mii_instance != 0) {
486 struct mii_softc *miisc;
488 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
489 mii_phy_reset(miisc);
491 error = mii_mediachg(mii);
497 jme_probe(device_t dev)
499 const struct jme_dev *sp;
502 vid = pci_get_vendor(dev);
503 did = pci_get_device(dev);
504 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
505 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
506 struct jme_softc *sc = device_get_softc(dev);
508 sc->jme_caps = sp->jme_caps;
509 device_set_desc(dev, sp->jme_name);
517 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
523 for (i = JME_TIMEOUT; i > 0; i--) {
524 reg = CSR_READ_4(sc, JME_SMBCSR);
525 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
531 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
535 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
536 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
537 for (i = JME_TIMEOUT; i > 0; i--) {
539 reg = CSR_READ_4(sc, JME_SMBINTF);
540 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
545 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
549 reg = CSR_READ_4(sc, JME_SMBINTF);
550 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
556 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
558 uint8_t fup, reg, val;
563 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
564 fup != JME_EEPROM_SIG0)
566 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
567 fup != JME_EEPROM_SIG1)
571 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
573 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
574 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
575 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
577 if (reg >= JME_PAR0 &&
578 reg < JME_PAR0 + ETHER_ADDR_LEN) {
579 if (jme_eeprom_read_byte(sc, offset + 2,
582 eaddr[reg - JME_PAR0] = val;
586 /* Check for the end of EEPROM descriptor. */
587 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
589 /* Try next eeprom descriptor. */
590 offset += JME_EEPROM_DESC_BYTES;
591 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
593 if (match == ETHER_ADDR_LEN)
600 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
604 /* Read station address. */
605 par0 = CSR_READ_4(sc, JME_PAR0);
606 par1 = CSR_READ_4(sc, JME_PAR1);
608 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
609 device_printf(sc->jme_dev,
610 "generating fake ethernet address.\n");
611 par0 = karc4random();
612 /* Set OUI to JMicron. */
616 eaddr[3] = (par0 >> 16) & 0xff;
617 eaddr[4] = (par0 >> 8) & 0xff;
618 eaddr[5] = par0 & 0xff;
620 eaddr[0] = (par0 >> 0) & 0xFF;
621 eaddr[1] = (par0 >> 8) & 0xFF;
622 eaddr[2] = (par0 >> 16) & 0xFF;
623 eaddr[3] = (par0 >> 24) & 0xFF;
624 eaddr[4] = (par1 >> 0) & 0xFF;
625 eaddr[5] = (par1 >> 8) & 0xFF;
630 jme_attach(device_t dev)
632 struct jme_softc *sc = device_get_softc(dev);
633 struct ifnet *ifp = &sc->arpcom.ac_if;
636 uint8_t pcie_ptr, rev;
638 uint8_t eaddr[ETHER_ADDR_LEN];
640 lwkt_serialize_init(&sc->jme_serialize);
641 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
642 for (i = 0; i < JME_NRXRING_MAX; ++i) {
644 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
647 sc->jme_rx_desc_cnt = roundup(jme_rx_desc_count, JME_NDESC_ALIGN);
648 if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
649 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
651 sc->jme_tx_desc_cnt = roundup(jme_tx_desc_count, JME_NDESC_ALIGN);
652 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
653 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
656 * Calculate rx rings based on ncpus2
658 sc->jme_rx_ring_cnt = jme_rx_ring_count;
659 if (sc->jme_rx_ring_cnt <= 0)
660 sc->jme_rx_ring_cnt = JME_NRXRING_1;
661 if (sc->jme_rx_ring_cnt > ncpus2)
662 sc->jme_rx_ring_cnt = ncpus2;
664 if (sc->jme_rx_ring_cnt >= JME_NRXRING_4)
665 sc->jme_rx_ring_cnt = JME_NRXRING_4;
666 else if (sc->jme_rx_ring_cnt >= JME_NRXRING_2)
667 sc->jme_rx_ring_cnt = JME_NRXRING_2;
668 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
671 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
672 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
673 for (j = 0; j < sc->jme_rx_ring_cnt; ++j) {
674 sc->jme_serialize_arr[i++] =
675 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
677 KKASSERT(i <= JME_NSERIALIZE);
678 sc->jme_serialize_cnt = i;
680 sc->jme_cdata.jme_sc = sc;
681 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
682 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
685 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
686 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
687 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
688 rdata->jme_rx_idx = i;
692 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
694 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
696 callout_init(&sc->jme_tick_ch);
699 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
702 irq = pci_read_config(dev, PCIR_INTLINE, 4);
703 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
705 device_printf(dev, "chip is in D%d power mode "
706 "-- setting to D0\n", pci_get_powerstate(dev));
708 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
710 pci_write_config(dev, PCIR_INTLINE, irq, 4);
711 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
713 #endif /* !BURN_BRIDGE */
715 /* Enable bus mastering */
716 pci_enable_busmaster(dev);
721 * JMC250 supports both memory mapped and I/O register space
722 * access. Because I/O register access should use different
723 * BARs to access registers it's waste of time to use I/O
724 * register spce access. JMC250 uses 16K to map entire memory
727 sc->jme_mem_rid = JME_PCIR_BAR;
728 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
729 &sc->jme_mem_rid, RF_ACTIVE);
730 if (sc->jme_mem_res == NULL) {
731 device_printf(dev, "can't allocate IO memory\n");
734 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
735 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
740 error = jme_intr_alloc(dev);
747 reg = CSR_READ_4(sc, JME_CHIPMODE);
748 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
750 sc->jme_caps |= JME_CAP_FPGA;
752 device_printf(dev, "FPGA revision: 0x%04x\n",
753 (reg & CHIPMODE_FPGA_REV_MASK) >>
754 CHIPMODE_FPGA_REV_SHIFT);
758 /* NOTE: FM revision is put in the upper 4 bits */
759 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
760 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
762 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
764 did = pci_get_device(dev);
766 case PCI_PRODUCT_JMICRON_JMC250:
767 if (rev == JME_REV1_A2)
768 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
771 case PCI_PRODUCT_JMICRON_JMC260:
773 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
777 panic("unknown device id 0x%04x\n", did);
779 if (rev >= JME_REV2) {
780 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
781 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
782 GHC_TXMAC_CLKSRC_1000;
785 /* Reset the ethernet controller. */
788 /* Map MSI/MSI-X vectors */
791 /* Get station address. */
792 reg = CSR_READ_4(sc, JME_SMBCSR);
793 if (reg & SMBCSR_EEPROM_PRESENT)
794 error = jme_eeprom_macaddr(sc, eaddr);
795 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
796 if (error != 0 && (bootverbose)) {
797 device_printf(dev, "ethernet hardware address "
798 "not found in EEPROM.\n");
800 jme_reg_macaddr(sc, eaddr);
805 * Integrated JR0211 has fixed PHY address whereas FPGA version
806 * requires PHY probing to get correct PHY address.
808 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
809 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
810 GPREG0_PHY_ADDR_MASK;
812 device_printf(dev, "PHY is at address %d.\n",
819 /* Set max allowable DMA size. */
820 pcie_ptr = pci_get_pciecap_ptr(dev);
824 sc->jme_caps |= JME_CAP_PCIE;
825 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
827 device_printf(dev, "Read request size : %d bytes.\n",
828 128 << ((ctrl >> 12) & 0x07));
829 device_printf(dev, "TLP payload size : %d bytes.\n",
830 128 << ((ctrl >> 5) & 0x07));
832 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
833 case PCIEM_DEVCTL_MAX_READRQ_128:
834 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
836 case PCIEM_DEVCTL_MAX_READRQ_256:
837 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
840 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
843 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
845 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
846 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
850 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
851 sc->jme_caps |= JME_CAP_PMCAP;
859 /* Allocate DMA stuffs */
860 error = jme_dma_alloc(sc);
865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
866 ifp->if_init = jme_init;
867 ifp->if_ioctl = jme_ioctl;
868 ifp->if_start = jme_start;
869 #ifdef DEVICE_POLLING
870 ifp->if_poll = jme_poll;
872 ifp->if_watchdog = jme_watchdog;
873 ifp->if_serialize = jme_serialize;
874 ifp->if_deserialize = jme_deserialize;
875 ifp->if_tryserialize = jme_tryserialize;
877 ifp->if_serialize_assert = jme_serialize_assert;
879 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
880 ifq_set_ready(&ifp->if_snd);
882 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
883 ifp->if_capabilities = IFCAP_HWCSUM |
885 IFCAP_VLAN_HWTAGGING;
886 if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
887 ifp->if_capabilities |= IFCAP_RSS;
888 ifp->if_capenable = ifp->if_capabilities;
891 * Disable TXCSUM by default to improve bulk data
892 * transmit performance (+20Mbps improvement).
894 ifp->if_capenable &= ~IFCAP_TXCSUM;
896 if (ifp->if_capenable & IFCAP_TXCSUM)
897 ifp->if_hwassist = JME_CSUM_FEATURES;
899 /* Set up MII bus. */
900 error = mii_phy_probe(dev, &sc->jme_miibus,
901 jme_mediachange, jme_mediastatus);
903 device_printf(dev, "no PHY found!\n");
908 * Save PHYADDR for FPGA mode PHY.
910 if (sc->jme_caps & JME_CAP_FPGA) {
911 struct mii_data *mii = device_get_softc(sc->jme_miibus);
913 if (mii->mii_instance != 0) {
914 struct mii_softc *miisc;
916 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
917 if (miisc->mii_phy != 0) {
918 sc->jme_phyaddr = miisc->mii_phy;
922 if (sc->jme_phyaddr != 0) {
923 device_printf(sc->jme_dev,
924 "FPGA PHY is at %d\n", sc->jme_phyaddr);
926 jme_miibus_writereg(dev, sc->jme_phyaddr,
927 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
929 /* XXX should we clear JME_WA_EXTFIFO */
934 ether_ifattach(ifp, eaddr, NULL);
936 /* Tell the upper layer(s) we support long frames. */
937 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
939 error = jme_intr_setup(dev);
952 jme_detach(device_t dev)
954 struct jme_softc *sc = device_get_softc(dev);
956 if (device_is_attached(dev)) {
957 struct ifnet *ifp = &sc->arpcom.ac_if;
959 ifnet_serialize_all(ifp);
961 jme_intr_teardown(dev);
962 ifnet_deserialize_all(ifp);
967 if (sc->jme_sysctl_tree != NULL)
968 sysctl_ctx_free(&sc->jme_sysctl_ctx);
970 if (sc->jme_miibus != NULL)
971 device_delete_child(dev, sc->jme_miibus);
972 bus_generic_detach(dev);
976 if (sc->jme_mem_res != NULL) {
977 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
987 jme_sysctl_node(struct jme_softc *sc)
991 char rx_ring_pkt[32];
995 sysctl_ctx_init(&sc->jme_sysctl_ctx);
996 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
997 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
998 device_get_nameunit(sc->jme_dev),
1000 if (sc->jme_sysctl_tree == NULL) {
1001 device_printf(sc->jme_dev, "can't add sysctl node\n");
1005 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1006 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1007 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1008 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1010 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1011 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1012 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1013 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1015 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1016 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1017 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1018 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1020 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1021 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1022 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1023 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1025 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1026 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1027 "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
1028 0, "RX desc count");
1029 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1030 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1031 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
1032 0, "TX desc count");
1033 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1034 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1035 "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
1036 0, "RX ring count");
1037 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1038 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1039 "rx_ring_inuse", CTLFLAG_RD, &sc->jme_rx_ring_inuse,
1040 0, "RX ring in use");
1041 #ifdef JME_RSS_DEBUG
1042 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1043 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1044 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1045 0, "RSS debug level");
1046 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1047 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1048 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
1049 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1050 rx_ring_pkt, CTLFLAG_RW,
1051 &sc->jme_rx_ring_pkt[r],
1057 * Set default coalesce valves
1059 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1060 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1061 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1062 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1065 * Adjust coalesce valves, in case that the number of TX/RX
1066 * descs are set to small values by users.
1068 * NOTE: coal_max will not be zero, since number of descs
1069 * must aligned by JME_NDESC_ALIGN (16 currently)
1071 coal_max = sc->jme_tx_desc_cnt / 6;
1072 if (coal_max < sc->jme_tx_coal_pkt)
1073 sc->jme_tx_coal_pkt = coal_max;
1075 coal_max = sc->jme_rx_desc_cnt / 4;
1076 if (coal_max < sc->jme_rx_coal_pkt)
1077 sc->jme_rx_coal_pkt = coal_max;
1081 jme_dma_alloc(struct jme_softc *sc)
1083 struct jme_txdesc *txd;
1087 sc->jme_cdata.jme_txdesc =
1088 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1090 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1091 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1092 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1093 M_DEVBUF, M_WAITOK | M_ZERO);
1096 /* Create parent ring tag. */
1097 error = bus_dma_tag_create(NULL,/* parent */
1098 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1099 sc->jme_lowaddr, /* lowaddr */
1100 BUS_SPACE_MAXADDR, /* highaddr */
1101 NULL, NULL, /* filter, filterarg */
1102 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1104 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1106 &sc->jme_cdata.jme_ring_tag);
1108 device_printf(sc->jme_dev,
1109 "could not create parent ring DMA tag.\n");
1114 * Create DMA stuffs for TX ring
1116 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1117 JME_TX_RING_ALIGN, 0,
1118 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1119 JME_TX_RING_SIZE(sc),
1120 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1122 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1125 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1126 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1127 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1128 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1131 * Create DMA stuffs for RX rings
1133 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1134 error = jme_rxring_dma_alloc(sc, i);
1139 /* Create parent buffer tag. */
1140 error = bus_dma_tag_create(NULL,/* parent */
1141 1, 0, /* algnmnt, boundary */
1142 sc->jme_lowaddr, /* lowaddr */
1143 BUS_SPACE_MAXADDR, /* highaddr */
1144 NULL, NULL, /* filter, filterarg */
1145 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1147 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1149 &sc->jme_cdata.jme_buffer_tag);
1151 device_printf(sc->jme_dev,
1152 "could not create parent buffer DMA tag.\n");
1157 * Create DMA stuffs for shadow status block
1159 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1160 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1161 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1163 device_printf(sc->jme_dev,
1164 "could not create shadow status block.\n");
1167 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1168 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1169 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1170 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1173 * Create DMA stuffs for TX buffers
1176 /* Create tag for Tx buffers. */
1177 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1178 1, 0, /* algnmnt, boundary */
1179 BUS_SPACE_MAXADDR, /* lowaddr */
1180 BUS_SPACE_MAXADDR, /* highaddr */
1181 NULL, NULL, /* filter, filterarg */
1182 JME_JUMBO_FRAMELEN, /* maxsize */
1183 JME_MAXTXSEGS, /* nsegments */
1184 JME_MAXSEGSIZE, /* maxsegsize */
1185 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1186 &sc->jme_cdata.jme_tx_tag);
1188 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1192 /* Create DMA maps for Tx buffers. */
1193 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1194 txd = &sc->jme_cdata.jme_txdesc[i];
1195 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1196 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1201 device_printf(sc->jme_dev,
1202 "could not create %dth Tx dmamap.\n", i);
1204 for (j = 0; j < i; ++j) {
1205 txd = &sc->jme_cdata.jme_txdesc[j];
1206 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1209 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1210 sc->jme_cdata.jme_tx_tag = NULL;
1216 * Create DMA stuffs for RX buffers
1218 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1219 error = jme_rxbuf_dma_alloc(sc, i);
1227 jme_dma_free(struct jme_softc *sc)
1229 struct jme_txdesc *txd;
1230 struct jme_rxdesc *rxd;
1231 struct jme_rxdata *rdata;
1235 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1236 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1237 sc->jme_cdata.jme_tx_ring_map);
1238 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1239 sc->jme_cdata.jme_tx_ring,
1240 sc->jme_cdata.jme_tx_ring_map);
1241 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1242 sc->jme_cdata.jme_tx_ring_tag = NULL;
1246 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1247 rdata = &sc->jme_cdata.jme_rx_data[r];
1248 if (rdata->jme_rx_ring_tag != NULL) {
1249 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1250 rdata->jme_rx_ring_map);
1251 bus_dmamem_free(rdata->jme_rx_ring_tag,
1253 rdata->jme_rx_ring_map);
1254 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1255 rdata->jme_rx_ring_tag = NULL;
1260 if (sc->jme_cdata.jme_tx_tag != NULL) {
1261 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1262 txd = &sc->jme_cdata.jme_txdesc[i];
1263 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1266 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1267 sc->jme_cdata.jme_tx_tag = NULL;
1271 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1272 rdata = &sc->jme_cdata.jme_rx_data[r];
1273 if (rdata->jme_rx_tag != NULL) {
1274 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1275 rxd = &rdata->jme_rxdesc[i];
1276 bus_dmamap_destroy(rdata->jme_rx_tag,
1279 bus_dmamap_destroy(rdata->jme_rx_tag,
1280 rdata->jme_rx_sparemap);
1281 bus_dma_tag_destroy(rdata->jme_rx_tag);
1282 rdata->jme_rx_tag = NULL;
1286 /* Shadow status block. */
1287 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1288 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1289 sc->jme_cdata.jme_ssb_map);
1290 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1291 sc->jme_cdata.jme_ssb_block,
1292 sc->jme_cdata.jme_ssb_map);
1293 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1294 sc->jme_cdata.jme_ssb_tag = NULL;
1297 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1298 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1299 sc->jme_cdata.jme_buffer_tag = NULL;
1301 if (sc->jme_cdata.jme_ring_tag != NULL) {
1302 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1303 sc->jme_cdata.jme_ring_tag = NULL;
1306 if (sc->jme_cdata.jme_txdesc != NULL) {
1307 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1308 sc->jme_cdata.jme_txdesc = NULL;
1310 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1311 rdata = &sc->jme_cdata.jme_rx_data[r];
1312 if (rdata->jme_rxdesc != NULL) {
1313 kfree(rdata->jme_rxdesc, M_DEVBUF);
1314 rdata->jme_rxdesc = NULL;
1320 * Make sure the interface is stopped at reboot time.
1323 jme_shutdown(device_t dev)
1325 return jme_suspend(dev);
1330 * Unlike other ethernet controllers, JMC250 requires
1331 * explicit resetting link speed to 10/100Mbps as gigabit
1332 * link will cunsume more power than 375mA.
1333 * Note, we reset the link speed to 10/100Mbps with
1334 * auto-negotiation but we don't know whether that operation
1335 * would succeed or not as we have no control after powering
1336 * off. If the renegotiation fail WOL may not work. Running
1337 * at 1Gbps draws more power than 375mA at 3.3V which is
1338 * specified in PCI specification and that would result in
1339 * complete shutdowning power to ethernet controller.
1342 * Save current negotiated media speed/duplex/flow-control
1343 * to softc and restore the same link again after resuming.
1344 * PHY handling such as power down/resetting to 100Mbps
1345 * may be better handled in suspend method in phy driver.
1348 jme_setlinkspeed(struct jme_softc *sc)
1350 struct mii_data *mii;
1353 JME_LOCK_ASSERT(sc);
1355 mii = device_get_softc(sc->jme_miibus);
1358 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1359 switch IFM_SUBTYPE(mii->mii_media_active) {
1369 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1370 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1371 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1372 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1373 BMCR_AUTOEN | BMCR_STARTNEG);
1376 /* Poll link state until jme(4) get a 10/100 link. */
1377 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1379 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1380 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1390 pause("jmelnk", hz);
1393 if (i == MII_ANEGTICKS_GIGE)
1394 device_printf(sc->jme_dev, "establishing link failed, "
1395 "WOL may not work!");
1398 * No link, force MAC to have 100Mbps, full-duplex link.
1399 * This is the last resort and may/may not work.
1401 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1402 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1407 jme_setwol(struct jme_softc *sc)
1409 struct ifnet *ifp = &sc->arpcom.ac_if;
1414 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1415 /* No PME capability, PHY power down. */
1416 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1417 MII_BMCR, BMCR_PDOWN);
1421 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1422 pmcs = CSR_READ_4(sc, JME_PMCS);
1423 pmcs &= ~PMCS_WOL_ENB_MASK;
1424 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1425 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1426 /* Enable PME message. */
1427 gpr |= GPREG0_PME_ENB;
1428 /* For gigabit controllers, reset link speed to 10/100. */
1429 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1430 jme_setlinkspeed(sc);
1433 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1434 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1437 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1438 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1439 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1440 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1441 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1442 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1443 /* No WOL, PHY power down. */
1444 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1445 MII_BMCR, BMCR_PDOWN);
1451 jme_suspend(device_t dev)
1453 struct jme_softc *sc = device_get_softc(dev);
1454 struct ifnet *ifp = &sc->arpcom.ac_if;
1456 ifnet_serialize_all(ifp);
1461 ifnet_deserialize_all(ifp);
1467 jme_resume(device_t dev)
1469 struct jme_softc *sc = device_get_softc(dev);
1470 struct ifnet *ifp = &sc->arpcom.ac_if;
1475 ifnet_serialize_all(ifp);
1478 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1481 pmstat = pci_read_config(sc->jme_dev,
1482 pmc + PCIR_POWER_STATUS, 2);
1483 /* Disable PME clear PME status. */
1484 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1485 pci_write_config(sc->jme_dev,
1486 pmc + PCIR_POWER_STATUS, pmstat, 2);
1490 if (ifp->if_flags & IFF_UP)
1493 ifnet_deserialize_all(ifp);
1499 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1501 struct jme_txdesc *txd;
1502 struct jme_desc *desc;
1504 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1506 int error, i, prod, symbol_desc;
1507 uint32_t cflags, flag64;
1509 M_ASSERTPKTHDR((*m_head));
1511 prod = sc->jme_cdata.jme_tx_prod;
1512 txd = &sc->jme_cdata.jme_txdesc[prod];
1514 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1519 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1520 (JME_TXD_RSVD + symbol_desc);
1521 if (maxsegs > JME_MAXTXSEGS)
1522 maxsegs = JME_MAXTXSEGS;
1523 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1524 ("not enough segments %d\n", maxsegs));
1526 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1527 txd->tx_dmamap, m_head,
1528 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1532 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1533 BUS_DMASYNC_PREWRITE);
1538 /* Configure checksum offload. */
1539 if (m->m_pkthdr.csum_flags & CSUM_IP)
1540 cflags |= JME_TD_IPCSUM;
1541 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1542 cflags |= JME_TD_TCPCSUM;
1543 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1544 cflags |= JME_TD_UDPCSUM;
1546 /* Configure VLAN. */
1547 if (m->m_flags & M_VLANTAG) {
1548 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1549 cflags |= JME_TD_VLAN_TAG;
1552 desc = &sc->jme_cdata.jme_tx_ring[prod];
1553 desc->flags = htole32(cflags);
1554 desc->addr_hi = htole32(m->m_pkthdr.len);
1555 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1557 * Use 64bits TX desc chain format.
1559 * The first TX desc of the chain, which is setup here,
1560 * is just a symbol TX desc carrying no payload.
1562 flag64 = JME_TD_64BIT;
1566 /* No effective TX desc is consumed */
1570 * Use 32bits TX desc chain format.
1572 * The first TX desc of the chain, which is setup here,
1573 * is an effective TX desc carrying the first segment of
1577 desc->buflen = htole32(txsegs[0].ds_len);
1578 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1580 /* One effective TX desc is consumed */
1583 sc->jme_cdata.jme_tx_cnt++;
1584 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1585 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1586 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1588 txd->tx_ndesc = 1 - i;
1589 for (; i < nsegs; i++) {
1590 desc = &sc->jme_cdata.jme_tx_ring[prod];
1591 desc->flags = htole32(JME_TD_OWN | flag64);
1592 desc->buflen = htole32(txsegs[i].ds_len);
1593 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1594 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1596 sc->jme_cdata.jme_tx_cnt++;
1597 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1598 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1599 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1602 /* Update producer index. */
1603 sc->jme_cdata.jme_tx_prod = prod;
1605 * Finally request interrupt and give the first descriptor
1606 * owenership to hardware.
1608 desc = txd->tx_desc;
1609 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1612 txd->tx_ndesc += nsegs;
1622 jme_start(struct ifnet *ifp)
1624 struct jme_softc *sc = ifp->if_softc;
1625 struct mbuf *m_head;
1628 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1630 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1631 ifq_purge(&ifp->if_snd);
1635 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1638 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1641 while (!ifq_is_empty(&ifp->if_snd)) {
1643 * Check number of available TX descs, always
1644 * leave JME_TXD_RSVD free TX descs.
1646 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1647 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1648 ifp->if_flags |= IFF_OACTIVE;
1652 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1657 * Pack the data into the transmit ring. If we
1658 * don't have room, set the OACTIVE flag and wait
1659 * for the NIC to drain the ring.
1661 if (jme_encap(sc, &m_head)) {
1662 KKASSERT(m_head == NULL);
1664 ifp->if_flags |= IFF_OACTIVE;
1670 * If there's a BPF listener, bounce a copy of this frame
1673 ETHER_BPF_MTAP(ifp, m_head);
1678 * Reading TXCSR takes very long time under heavy load
1679 * so cache TXCSR value and writes the ORed value with
1680 * the kick command to the TXCSR. This saves one register
1683 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1684 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1685 /* Set a timeout in case the chip goes out to lunch. */
1686 ifp->if_timer = JME_TX_TIMEOUT;
1691 jme_watchdog(struct ifnet *ifp)
1693 struct jme_softc *sc = ifp->if_softc;
1695 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1697 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1698 if_printf(ifp, "watchdog timeout (missed link)\n");
1705 if (sc->jme_cdata.jme_tx_cnt == 0) {
1706 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1708 if (!ifq_is_empty(&ifp->if_snd))
1713 if_printf(ifp, "watchdog timeout\n");
1716 if (!ifq_is_empty(&ifp->if_snd))
1721 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1723 struct jme_softc *sc = ifp->if_softc;
1724 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1725 struct ifreq *ifr = (struct ifreq *)data;
1726 int error = 0, mask;
1728 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1732 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1733 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1734 ifr->ifr_mtu > JME_MAX_MTU)) {
1739 if (ifp->if_mtu != ifr->ifr_mtu) {
1741 * No special configuration is required when interface
1742 * MTU is changed but availability of Tx checksum
1743 * offload should be chcked against new MTU size as
1744 * FIFO size is just 2K.
1746 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1747 ifp->if_capenable &= ~IFCAP_TXCSUM;
1748 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1750 ifp->if_mtu = ifr->ifr_mtu;
1751 if (ifp->if_flags & IFF_RUNNING)
1757 if (ifp->if_flags & IFF_UP) {
1758 if (ifp->if_flags & IFF_RUNNING) {
1759 if ((ifp->if_flags ^ sc->jme_if_flags) &
1760 (IFF_PROMISC | IFF_ALLMULTI))
1766 if (ifp->if_flags & IFF_RUNNING)
1769 sc->jme_if_flags = ifp->if_flags;
1774 if (ifp->if_flags & IFF_RUNNING)
1780 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1784 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1786 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1787 ifp->if_capenable ^= IFCAP_TXCSUM;
1788 if (IFCAP_TXCSUM & ifp->if_capenable)
1789 ifp->if_hwassist |= JME_CSUM_FEATURES;
1791 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1793 if (mask & IFCAP_RXCSUM) {
1796 ifp->if_capenable ^= IFCAP_RXCSUM;
1797 reg = CSR_READ_4(sc, JME_RXMAC);
1798 reg &= ~RXMAC_CSUM_ENB;
1799 if (ifp->if_capenable & IFCAP_RXCSUM)
1800 reg |= RXMAC_CSUM_ENB;
1801 CSR_WRITE_4(sc, JME_RXMAC, reg);
1804 if (mask & IFCAP_VLAN_HWTAGGING) {
1805 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1809 if (mask & IFCAP_RSS) {
1810 ifp->if_capenable ^= IFCAP_RSS;
1811 if (ifp->if_flags & IFF_RUNNING)
1817 error = ether_ioctl(ifp, cmd, data);
1824 jme_mac_config(struct jme_softc *sc)
1826 struct mii_data *mii;
1827 uint32_t ghc, rxmac, txmac, txpause, gp1;
1828 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1830 mii = device_get_softc(sc->jme_miibus);
1832 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1834 CSR_WRITE_4(sc, JME_GHC, 0);
1836 rxmac = CSR_READ_4(sc, JME_RXMAC);
1837 rxmac &= ~RXMAC_FC_ENB;
1838 txmac = CSR_READ_4(sc, JME_TXMAC);
1839 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1840 txpause = CSR_READ_4(sc, JME_TXPFC);
1841 txpause &= ~TXPFC_PAUSE_ENB;
1842 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1843 ghc |= GHC_FULL_DUPLEX;
1844 rxmac &= ~RXMAC_COLL_DET_ENB;
1845 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1846 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1849 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1850 txpause |= TXPFC_PAUSE_ENB;
1851 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1852 rxmac |= RXMAC_FC_ENB;
1854 /* Disable retry transmit timer/retry limit. */
1855 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1856 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1858 rxmac |= RXMAC_COLL_DET_ENB;
1859 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1860 /* Enable retry transmit timer/retry limit. */
1861 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1862 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1866 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1868 gp1 = CSR_READ_4(sc, JME_GPREG1);
1869 gp1 &= ~GPREG1_WA_HDX;
1871 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1874 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1876 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1878 gp1 |= GPREG1_WA_HDX;
1882 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1884 gp1 |= GPREG1_WA_HDX;
1887 * Use extended FIFO depth to workaround CRC errors
1888 * emitted by chips before JMC250B
1890 phyconf = JMPHY_CONF_EXTFIFO;
1894 if (sc->jme_caps & JME_CAP_FASTETH)
1897 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1899 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1905 CSR_WRITE_4(sc, JME_GHC, ghc);
1906 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1907 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1908 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1910 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1911 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1912 JMPHY_CONF, phyconf);
1914 if (sc->jme_workaround & JME_WA_HDX)
1915 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1921 struct jme_softc *sc = xsc;
1922 struct ifnet *ifp = &sc->arpcom.ac_if;
1926 ASSERT_SERIALIZED(&sc->jme_serialize);
1928 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1929 if (status == 0 || status == 0xFFFFFFFF)
1932 /* Disable interrupts. */
1933 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1935 status = CSR_READ_4(sc, JME_INTR_STATUS);
1936 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1939 /* Reset PCC counter/timer and Ack interrupts. */
1940 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1942 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1943 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1945 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
1946 if (status & jme_rx_status[r].jme_coal) {
1947 status |= jme_rx_status[r].jme_coal |
1948 jme_rx_status[r].jme_comp;
1952 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1954 if (ifp->if_flags & IFF_RUNNING) {
1955 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1956 jme_rx_intr(sc, status);
1958 if (status & INTR_RXQ_DESC_EMPTY) {
1960 * Notify hardware availability of new Rx buffers.
1961 * Reading RXCSR takes very long time under heavy
1962 * load so cache RXCSR value and writes the ORed
1963 * value with the kick command to the RXCSR. This
1964 * saves one register access cycle.
1966 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1967 RXCSR_RX_ENB | RXCSR_RXQ_START);
1970 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1971 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1973 if (!ifq_is_empty(&ifp->if_snd))
1975 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1979 /* Reenable interrupts. */
1980 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1984 jme_txeof(struct jme_softc *sc)
1986 struct ifnet *ifp = &sc->arpcom.ac_if;
1987 struct jme_txdesc *txd;
1991 cons = sc->jme_cdata.jme_tx_cons;
1992 if (cons == sc->jme_cdata.jme_tx_prod)
1996 * Go through our Tx list and free mbufs for those
1997 * frames which have been transmitted.
1999 while (cons != sc->jme_cdata.jme_tx_prod) {
2000 txd = &sc->jme_cdata.jme_txdesc[cons];
2001 KASSERT(txd->tx_m != NULL,
2002 ("%s: freeing NULL mbuf!\n", __func__));
2004 status = le32toh(txd->tx_desc->flags);
2005 if ((status & JME_TD_OWN) == JME_TD_OWN)
2008 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2012 if (status & JME_TD_COLLISION) {
2013 ifp->if_collisions +=
2014 le32toh(txd->tx_desc->buflen) &
2015 JME_TD_BUF_LEN_MASK;
2020 * Only the first descriptor of multi-descriptor
2021 * transmission is updated so driver have to skip entire
2022 * chained buffers for the transmiited frame. In other
2023 * words, JME_TD_OWN bit is valid only at the first
2024 * descriptor of a multi-descriptor transmission.
2026 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2027 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2028 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
2031 /* Reclaim transferred mbufs. */
2032 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2035 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2036 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2037 ("%s: Active Tx desc counter was garbled\n", __func__));
2040 sc->jme_cdata.jme_tx_cons = cons;
2042 if (sc->jme_cdata.jme_tx_cnt == 0)
2045 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2046 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
2047 ifp->if_flags &= ~IFF_OACTIVE;
2050 static __inline void
2051 jme_discard_rxbufs(struct jme_softc *sc, int ring, int cons, int count)
2053 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2056 for (i = 0; i < count; ++i) {
2057 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2059 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2060 desc->buflen = htole32(MCLBYTES);
2061 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
2065 static __inline struct pktinfo *
2066 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2068 if (flags & JME_RD_IPV4)
2069 pi->pi_netisr = NETISR_IP;
2070 else if (flags & JME_RD_IPV6)
2071 pi->pi_netisr = NETISR_IPV6;
2076 pi->pi_l3proto = IPPROTO_UNKNOWN;
2078 if (flags & JME_RD_MORE_FRAG)
2079 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2080 else if (flags & JME_RD_TCP)
2081 pi->pi_l3proto = IPPROTO_TCP;
2082 else if (flags & JME_RD_UDP)
2083 pi->pi_l3proto = IPPROTO_UDP;
2089 /* Receive a frame. */
2091 jme_rxpkt(struct jme_softc *sc, int ring)
2093 struct ifnet *ifp = &sc->arpcom.ac_if;
2094 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2095 struct jme_desc *desc;
2096 struct jme_rxdesc *rxd;
2097 struct mbuf *mp, *m;
2098 uint32_t flags, status, hash, hashinfo;
2099 int cons, count, nsegs;
2101 cons = rdata->jme_rx_cons;
2102 desc = &rdata->jme_rx_ring[cons];
2103 flags = le32toh(desc->flags);
2104 status = le32toh(desc->buflen);
2105 hash = le32toh(desc->addr_hi);
2106 hashinfo = le32toh(desc->addr_lo);
2107 nsegs = JME_RX_NSEGS(status);
2109 JME_RSS_DPRINTF(sc, 15, "ring%d, flags 0x%08x, "
2110 "hash 0x%08x, hash info 0x%08x\n",
2111 ring, flags, hash, hashinfo);
2113 if (status & JME_RX_ERR_STAT) {
2115 jme_discard_rxbufs(sc, ring, cons, nsegs);
2116 #ifdef JME_SHOW_ERRORS
2117 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2118 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2120 rdata->jme_rx_cons += nsegs;
2121 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2125 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2126 for (count = 0; count < nsegs; count++,
2127 JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2128 rxd = &rdata->jme_rxdesc[cons];
2131 /* Add a new receive buffer to the ring. */
2132 if (jme_newbuf(sc, ring, rxd, 0) != 0) {
2135 jme_discard_rxbufs(sc, ring, cons, nsegs - count);
2136 if (rdata->jme_rxhead != NULL) {
2137 m_freem(rdata->jme_rxhead);
2138 JME_RXCHAIN_RESET(sc, ring);
2144 * Assume we've received a full sized frame.
2145 * Actual size is fixed when we encounter the end of
2146 * multi-segmented frame.
2148 mp->m_len = MCLBYTES;
2150 /* Chain received mbufs. */
2151 if (rdata->jme_rxhead == NULL) {
2152 rdata->jme_rxhead = mp;
2153 rdata->jme_rxtail = mp;
2156 * Receive processor can receive a maximum frame
2157 * size of 65535 bytes.
2159 rdata->jme_rxtail->m_next = mp;
2160 rdata->jme_rxtail = mp;
2163 if (count == nsegs - 1) {
2164 struct pktinfo pi0, *pi;
2166 /* Last desc. for this frame. */
2167 m = rdata->jme_rxhead;
2168 m->m_pkthdr.len = rdata->jme_rxlen;
2170 /* Set first mbuf size. */
2171 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2172 /* Set last mbuf size. */
2173 mp->m_len = rdata->jme_rxlen -
2174 ((MCLBYTES - JME_RX_PAD_BYTES) +
2175 (MCLBYTES * (nsegs - 2)));
2177 m->m_len = rdata->jme_rxlen;
2179 m->m_pkthdr.rcvif = ifp;
2182 * Account for 10bytes auto padding which is used
2183 * to align IP header on 32bit boundary. Also note,
2184 * CRC bytes is automatically removed by the
2187 m->m_data += JME_RX_PAD_BYTES;
2189 /* Set checksum information. */
2190 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2191 (flags & JME_RD_IPV4)) {
2192 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2193 if (flags & JME_RD_IPCSUM)
2194 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2195 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2196 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2197 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2198 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2199 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2200 m->m_pkthdr.csum_flags |=
2201 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2202 m->m_pkthdr.csum_data = 0xffff;
2206 /* Check for VLAN tagged packets. */
2207 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2208 (flags & JME_RD_VLAN_TAG)) {
2209 m->m_pkthdr.ether_vlantag =
2210 flags & JME_RD_VLAN_MASK;
2211 m->m_flags |= M_VLANTAG;
2216 if (ifp->if_capenable & IFCAP_RSS)
2217 pi = jme_pktinfo(&pi0, flags);
2222 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2223 m->m_flags |= M_HASH;
2224 m->m_pkthdr.hash = toeplitz_hash(hash);
2227 #ifdef JME_RSS_DEBUG
2229 JME_RSS_DPRINTF(sc, 10,
2230 "isr %d flags %08x, l3 %d %s\n",
2231 pi->pi_netisr, pi->pi_flags,
2233 (m->m_flags & M_HASH) ? "hash" : "");
2238 ether_input_pkt(ifp, m, pi);
2240 /* Reset mbuf chains. */
2241 JME_RXCHAIN_RESET(sc, ring);
2242 #ifdef JME_RSS_DEBUG
2243 sc->jme_rx_ring_pkt[ring]++;
2248 rdata->jme_rx_cons += nsegs;
2249 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2253 jme_rxeof(struct jme_softc *sc, int ring, int count)
2255 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2256 struct jme_desc *desc;
2260 #ifdef DEVICE_POLLING
2261 if (count >= 0 && count-- == 0)
2264 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2265 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2267 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2271 * Check number of segments against received bytes.
2272 * Non-matching value would indicate that hardware
2273 * is still trying to update Rx descriptors. I'm not
2274 * sure whether this check is needed.
2276 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2277 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2278 if (nsegs != howmany(pktlen, MCLBYTES)) {
2279 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2280 "and packet size(%d) mismach\n",
2285 /* Received a frame. */
2286 jme_rxpkt(sc, ring);
2293 struct jme_softc *sc = xsc;
2294 struct ifnet *ifp = &sc->arpcom.ac_if;
2295 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2297 ifnet_serialize_all(ifp);
2300 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2302 ifnet_deserialize_all(ifp);
2306 jme_reset(struct jme_softc *sc)
2310 /* Make sure that TX and RX are stopped */
2315 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2319 * Hold reset bit before stop reset
2322 /* Disable TXMAC and TXOFL clock sources */
2323 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2324 /* Disable RXMAC clock source */
2325 val = CSR_READ_4(sc, JME_GPREG1);
2326 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2328 CSR_READ_4(sc, JME_GHC);
2331 CSR_WRITE_4(sc, JME_GHC, 0);
2333 CSR_READ_4(sc, JME_GHC);
2336 * Clear reset bit after stop reset
2339 /* Enable TXMAC and TXOFL clock sources */
2340 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2341 /* Enable RXMAC clock source */
2342 val = CSR_READ_4(sc, JME_GPREG1);
2343 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2345 CSR_READ_4(sc, JME_GHC);
2347 /* Disable TXMAC and TXOFL clock sources */
2348 CSR_WRITE_4(sc, JME_GHC, 0);
2349 /* Disable RXMAC clock source */
2350 val = CSR_READ_4(sc, JME_GPREG1);
2351 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2353 CSR_READ_4(sc, JME_GHC);
2355 /* Enable TX and RX */
2356 val = CSR_READ_4(sc, JME_TXCSR);
2357 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2358 val = CSR_READ_4(sc, JME_RXCSR);
2359 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2361 CSR_READ_4(sc, JME_TXCSR);
2362 CSR_READ_4(sc, JME_RXCSR);
2364 /* Enable TXMAC and TXOFL clock sources */
2365 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2366 /* Eisable RXMAC clock source */
2367 val = CSR_READ_4(sc, JME_GPREG1);
2368 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2370 CSR_READ_4(sc, JME_GHC);
2372 /* Stop TX and RX */
2380 struct jme_softc *sc = xsc;
2381 struct ifnet *ifp = &sc->arpcom.ac_if;
2382 struct mii_data *mii;
2383 uint8_t eaddr[ETHER_ADDR_LEN];
2388 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2391 * Cancel any pending I/O.
2396 * Reset the chip to a known state.
2401 * Setup MSI/MSI-X vectors to interrupts mapping
2406 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2407 KKASSERT(sc->jme_txd_spare >= 1);
2410 * If we use 64bit address mode for transmitting, each Tx request
2411 * needs one more symbol descriptor.
2413 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2414 sc->jme_txd_spare += 1;
2416 if (ifp->if_capenable & IFCAP_RSS)
2419 jme_disable_rss(sc);
2421 /* Init RX descriptors */
2422 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2423 error = jme_init_rx_ring(sc, r);
2425 if_printf(ifp, "initialization failed: "
2426 "no memory for %dth RX ring.\n", r);
2432 /* Init TX descriptors */
2433 jme_init_tx_ring(sc);
2435 /* Initialize shadow status block. */
2438 /* Reprogram the station address. */
2439 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2440 CSR_WRITE_4(sc, JME_PAR0,
2441 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2442 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2445 * Configure Tx queue.
2446 * Tx priority queue weight value : 0
2447 * Tx FIFO threshold for processing next packet : 16QW
2448 * Maximum Tx DMA length : 512
2449 * Allow Tx DMA burst.
2451 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2452 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2453 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2454 sc->jme_txcsr |= sc->jme_tx_dma_size;
2455 sc->jme_txcsr |= TXCSR_DMA_BURST;
2456 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2458 /* Set Tx descriptor counter. */
2459 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2461 /* Set Tx ring address to the hardware. */
2462 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2463 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2464 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2466 /* Configure TxMAC parameters. */
2467 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2468 reg |= TXMAC_THRESH_1_PKT;
2469 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2470 CSR_WRITE_4(sc, JME_TXMAC, reg);
2473 * Configure Rx queue.
2474 * FIFO full threshold for transmitting Tx pause packet : 128T
2475 * FIFO threshold for processing next packet : 128QW
2477 * Max Rx DMA length : 128
2478 * Rx descriptor retry : 32
2479 * Rx descriptor retry time gap : 256ns
2480 * Don't receive runt/bad frame.
2482 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2485 * Since Rx FIFO size is 4K bytes, receiving frames larger
2486 * than 4K bytes will suffer from Rx FIFO overruns. So
2487 * decrease FIFO threshold to reduce the FIFO overruns for
2488 * frames larger than 4000 bytes.
2489 * For best performance of standard MTU sized frames use
2490 * maximum allowable FIFO threshold, 128QW.
2492 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2494 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2496 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2498 /* Improve PCI Express compatibility */
2499 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2501 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2502 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2503 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2504 /* XXX TODO DROP_BAD */
2506 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2507 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2509 /* Set Rx descriptor counter. */
2510 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2512 /* Set Rx ring address to the hardware. */
2513 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2514 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2515 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2518 /* Clear receive filter. */
2519 CSR_WRITE_4(sc, JME_RXMAC, 0);
2521 /* Set up the receive filter. */
2526 * Disable all WOL bits as WOL can interfere normal Rx
2527 * operation. Also clear WOL detection status bits.
2529 reg = CSR_READ_4(sc, JME_PMCS);
2530 reg &= ~PMCS_WOL_ENB_MASK;
2531 CSR_WRITE_4(sc, JME_PMCS, reg);
2534 * Pad 10bytes right before received frame. This will greatly
2535 * help Rx performance on strict-alignment architectures as
2536 * it does not need to copy the frame to align the payload.
2538 reg = CSR_READ_4(sc, JME_RXMAC);
2539 reg |= RXMAC_PAD_10BYTES;
2541 if (ifp->if_capenable & IFCAP_RXCSUM)
2542 reg |= RXMAC_CSUM_ENB;
2543 CSR_WRITE_4(sc, JME_RXMAC, reg);
2545 /* Configure general purpose reg0 */
2546 reg = CSR_READ_4(sc, JME_GPREG0);
2547 reg &= ~GPREG0_PCC_UNIT_MASK;
2548 /* Set PCC timer resolution to micro-seconds unit. */
2549 reg |= GPREG0_PCC_UNIT_US;
2551 * Disable all shadow register posting as we have to read
2552 * JME_INTR_STATUS register in jme_intr. Also it seems
2553 * that it's hard to synchronize interrupt status between
2554 * hardware and software with shadow posting due to
2555 * requirements of bus_dmamap_sync(9).
2557 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2558 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2559 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2560 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2561 /* Disable posting of DW0. */
2562 reg &= ~GPREG0_POST_DW0_ENB;
2563 /* Clear PME message. */
2564 reg &= ~GPREG0_PME_ENB;
2565 /* Set PHY address. */
2566 reg &= ~GPREG0_PHY_ADDR_MASK;
2567 reg |= sc->jme_phyaddr;
2568 CSR_WRITE_4(sc, JME_GPREG0, reg);
2570 /* Configure Tx queue 0 packet completion coalescing. */
2571 jme_set_tx_coal(sc);
2573 /* Configure Rx queue 0 packet completion coalescing. */
2574 jme_set_rx_coal(sc);
2576 /* Configure shadow status block but don't enable posting. */
2577 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2578 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2579 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2581 /* Disable Timer 1 and Timer 2. */
2582 CSR_WRITE_4(sc, JME_TIMER1, 0);
2583 CSR_WRITE_4(sc, JME_TIMER2, 0);
2585 /* Configure retry transmit period, retry limit value. */
2586 CSR_WRITE_4(sc, JME_TXTRHD,
2587 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2588 TXTRHD_RT_PERIOD_MASK) |
2589 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2590 TXTRHD_RT_LIMIT_SHIFT));
2592 #ifdef DEVICE_POLLING
2593 if (!(ifp->if_flags & IFF_POLLING))
2595 /* Initialize the interrupt mask. */
2596 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2597 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2600 * Enabling Tx/Rx DMA engines and Rx queue processing is
2601 * done after detection of valid link in jme_miibus_statchg.
2603 sc->jme_flags &= ~JME_FLAG_LINK;
2605 /* Set the current media. */
2606 mii = device_get_softc(sc->jme_miibus);
2609 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2611 ifp->if_flags |= IFF_RUNNING;
2612 ifp->if_flags &= ~IFF_OACTIVE;
2616 jme_stop(struct jme_softc *sc)
2618 struct ifnet *ifp = &sc->arpcom.ac_if;
2619 struct jme_txdesc *txd;
2620 struct jme_rxdesc *rxd;
2621 struct jme_rxdata *rdata;
2624 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2627 * Mark the interface down and cancel the watchdog timer.
2629 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2632 callout_stop(&sc->jme_tick_ch);
2633 sc->jme_flags &= ~JME_FLAG_LINK;
2636 * Disable interrupts.
2638 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2639 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2641 /* Disable updating shadow status block. */
2642 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2643 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2645 /* Stop receiver, transmitter. */
2650 * Free partial finished RX segments
2652 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2653 rdata = &sc->jme_cdata.jme_rx_data[r];
2654 if (rdata->jme_rxhead != NULL)
2655 m_freem(rdata->jme_rxhead);
2656 JME_RXCHAIN_RESET(sc, r);
2660 * Free RX and TX mbufs still in the queues.
2662 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2663 rdata = &sc->jme_cdata.jme_rx_data[r];
2664 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2665 rxd = &rdata->jme_rxdesc[i];
2666 if (rxd->rx_m != NULL) {
2667 bus_dmamap_unload(rdata->jme_rx_tag,
2674 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2675 txd = &sc->jme_cdata.jme_txdesc[i];
2676 if (txd->tx_m != NULL) {
2677 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2687 jme_stop_tx(struct jme_softc *sc)
2692 reg = CSR_READ_4(sc, JME_TXCSR);
2693 if ((reg & TXCSR_TX_ENB) == 0)
2695 reg &= ~TXCSR_TX_ENB;
2696 CSR_WRITE_4(sc, JME_TXCSR, reg);
2697 for (i = JME_TIMEOUT; i > 0; i--) {
2699 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2703 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2707 jme_stop_rx(struct jme_softc *sc)
2712 reg = CSR_READ_4(sc, JME_RXCSR);
2713 if ((reg & RXCSR_RX_ENB) == 0)
2715 reg &= ~RXCSR_RX_ENB;
2716 CSR_WRITE_4(sc, JME_RXCSR, reg);
2717 for (i = JME_TIMEOUT; i > 0; i--) {
2719 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2723 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2727 jme_init_tx_ring(struct jme_softc *sc)
2729 struct jme_chain_data *cd;
2730 struct jme_txdesc *txd;
2733 sc->jme_cdata.jme_tx_prod = 0;
2734 sc->jme_cdata.jme_tx_cons = 0;
2735 sc->jme_cdata.jme_tx_cnt = 0;
2737 cd = &sc->jme_cdata;
2738 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2739 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2740 txd = &sc->jme_cdata.jme_txdesc[i];
2742 txd->tx_desc = &cd->jme_tx_ring[i];
2748 jme_init_ssb(struct jme_softc *sc)
2750 struct jme_chain_data *cd;
2752 cd = &sc->jme_cdata;
2753 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2757 jme_init_rx_ring(struct jme_softc *sc, int ring)
2759 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2760 struct jme_rxdesc *rxd;
2763 KKASSERT(rdata->jme_rxhead == NULL &&
2764 rdata->jme_rxtail == NULL &&
2765 rdata->jme_rxlen == 0);
2766 rdata->jme_rx_cons = 0;
2768 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(sc));
2769 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2772 rxd = &rdata->jme_rxdesc[i];
2774 rxd->rx_desc = &rdata->jme_rx_ring[i];
2775 error = jme_newbuf(sc, ring, rxd, 1);
2783 jme_newbuf(struct jme_softc *sc, int ring, struct jme_rxdesc *rxd, int init)
2785 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2786 struct jme_desc *desc;
2788 bus_dma_segment_t segs;
2792 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2796 * JMC250 has 64bit boundary alignment limitation so jme(4)
2797 * takes advantage of 10 bytes padding feature of hardware
2798 * in order not to copy entire frame to align IP header on
2801 m->m_len = m->m_pkthdr.len = MCLBYTES;
2803 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2804 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2809 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2813 if (rxd->rx_m != NULL) {
2814 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2815 BUS_DMASYNC_POSTREAD);
2816 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2818 map = rxd->rx_dmamap;
2819 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2820 rdata->jme_rx_sparemap = map;
2823 desc = rxd->rx_desc;
2824 desc->buflen = htole32(segs.ds_len);
2825 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2826 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2827 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2833 jme_set_vlan(struct jme_softc *sc)
2835 struct ifnet *ifp = &sc->arpcom.ac_if;
2838 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2840 reg = CSR_READ_4(sc, JME_RXMAC);
2841 reg &= ~RXMAC_VLAN_ENB;
2842 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2843 reg |= RXMAC_VLAN_ENB;
2844 CSR_WRITE_4(sc, JME_RXMAC, reg);
2848 jme_set_filter(struct jme_softc *sc)
2850 struct ifnet *ifp = &sc->arpcom.ac_if;
2851 struct ifmultiaddr *ifma;
2856 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2858 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2859 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2863 * Always accept frames destined to our station address.
2864 * Always accept broadcast frames.
2866 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2868 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2869 if (ifp->if_flags & IFF_PROMISC)
2870 rxcfg |= RXMAC_PROMISC;
2871 if (ifp->if_flags & IFF_ALLMULTI)
2872 rxcfg |= RXMAC_ALLMULTI;
2873 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2874 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2875 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2880 * Set up the multicast address filter by passing all multicast
2881 * addresses through a CRC generator, and then using the low-order
2882 * 6 bits as an index into the 64 bit multicast hash table. The
2883 * high order bits select the register, while the rest of the bits
2884 * select the bit within the register.
2886 rxcfg |= RXMAC_MULTICAST;
2887 bzero(mchash, sizeof(mchash));
2889 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2890 if (ifma->ifma_addr->sa_family != AF_LINK)
2892 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2893 ifma->ifma_addr), ETHER_ADDR_LEN);
2895 /* Just want the 6 least significant bits. */
2898 /* Set the corresponding bit in the hash table. */
2899 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2902 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2903 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2904 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2908 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2910 struct jme_softc *sc = arg1;
2911 struct ifnet *ifp = &sc->arpcom.ac_if;
2914 ifnet_serialize_all(ifp);
2916 v = sc->jme_tx_coal_to;
2917 error = sysctl_handle_int(oidp, &v, 0, req);
2918 if (error || req->newptr == NULL)
2921 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2926 if (v != sc->jme_tx_coal_to) {
2927 sc->jme_tx_coal_to = v;
2928 if (ifp->if_flags & IFF_RUNNING)
2929 jme_set_tx_coal(sc);
2932 ifnet_deserialize_all(ifp);
2937 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2939 struct jme_softc *sc = arg1;
2940 struct ifnet *ifp = &sc->arpcom.ac_if;
2943 ifnet_serialize_all(ifp);
2945 v = sc->jme_tx_coal_pkt;
2946 error = sysctl_handle_int(oidp, &v, 0, req);
2947 if (error || req->newptr == NULL)
2950 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2955 if (v != sc->jme_tx_coal_pkt) {
2956 sc->jme_tx_coal_pkt = v;
2957 if (ifp->if_flags & IFF_RUNNING)
2958 jme_set_tx_coal(sc);
2961 ifnet_deserialize_all(ifp);
2966 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2968 struct jme_softc *sc = arg1;
2969 struct ifnet *ifp = &sc->arpcom.ac_if;
2972 ifnet_serialize_all(ifp);
2974 v = sc->jme_rx_coal_to;
2975 error = sysctl_handle_int(oidp, &v, 0, req);
2976 if (error || req->newptr == NULL)
2979 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2984 if (v != sc->jme_rx_coal_to) {
2985 sc->jme_rx_coal_to = v;
2986 if (ifp->if_flags & IFF_RUNNING)
2987 jme_set_rx_coal(sc);
2990 ifnet_deserialize_all(ifp);
2995 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2997 struct jme_softc *sc = arg1;
2998 struct ifnet *ifp = &sc->arpcom.ac_if;
3001 ifnet_serialize_all(ifp);
3003 v = sc->jme_rx_coal_pkt;
3004 error = sysctl_handle_int(oidp, &v, 0, req);
3005 if (error || req->newptr == NULL)
3008 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3013 if (v != sc->jme_rx_coal_pkt) {
3014 sc->jme_rx_coal_pkt = v;
3015 if (ifp->if_flags & IFF_RUNNING)
3016 jme_set_rx_coal(sc);
3019 ifnet_deserialize_all(ifp);
3024 jme_set_tx_coal(struct jme_softc *sc)
3028 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3030 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3031 PCCTX_COAL_PKT_MASK;
3032 reg |= PCCTX_COAL_TXQ0;
3033 CSR_WRITE_4(sc, JME_PCCTX, reg);
3037 jme_set_rx_coal(struct jme_softc *sc)
3042 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3044 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3045 PCCRX_COAL_PKT_MASK;
3046 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3047 if (r < sc->jme_rx_ring_inuse)
3048 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3050 CSR_WRITE_4(sc, JME_PCCRX(r), 0);
3054 #ifdef DEVICE_POLLING
3057 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3059 struct jme_softc *sc = ifp->if_softc;
3063 ASSERT_SERIALIZED(&sc->jme_serialize);
3067 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3070 case POLL_DEREGISTER:
3071 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3074 case POLL_AND_CHECK_STATUS:
3076 status = CSR_READ_4(sc, JME_INTR_STATUS);
3078 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3079 struct jme_rxdata *rdata =
3080 &sc->jme_cdata.jme_rx_data[r];
3082 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3083 jme_rxeof(sc, r, count);
3084 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3087 if (status & INTR_RXQ_DESC_EMPTY) {
3088 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3089 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3090 RXCSR_RX_ENB | RXCSR_RXQ_START);
3093 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3095 if (!ifq_is_empty(&ifp->if_snd))
3097 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3102 #endif /* DEVICE_POLLING */
3105 jme_rxring_dma_alloc(struct jme_softc *sc, int ring)
3107 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3111 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
3112 JME_RX_RING_ALIGN, 0,
3113 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3114 JME_RX_RING_SIZE(sc),
3115 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3117 device_printf(sc->jme_dev,
3118 "could not allocate %dth Rx ring.\n", ring);
3121 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3122 rdata->jme_rx_ring_map = dmem.dmem_map;
3123 rdata->jme_rx_ring = dmem.dmem_addr;
3124 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3130 jme_rxbuf_dma_alloc(struct jme_softc *sc, int ring)
3132 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3135 /* Create tag for Rx buffers. */
3136 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
3137 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3138 BUS_SPACE_MAXADDR, /* lowaddr */
3139 BUS_SPACE_MAXADDR, /* highaddr */
3140 NULL, NULL, /* filter, filterarg */
3141 MCLBYTES, /* maxsize */
3143 MCLBYTES, /* maxsegsize */
3144 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3145 &rdata->jme_rx_tag);
3147 device_printf(sc->jme_dev,
3148 "could not create %dth Rx DMA tag.\n", ring);
3152 /* Create DMA maps for Rx buffers. */
3153 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3154 &rdata->jme_rx_sparemap);
3156 device_printf(sc->jme_dev,
3157 "could not create %dth spare Rx dmamap.\n", ring);
3158 bus_dma_tag_destroy(rdata->jme_rx_tag);
3159 rdata->jme_rx_tag = NULL;
3162 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
3163 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3165 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3170 device_printf(sc->jme_dev,
3171 "could not create %dth Rx dmamap "
3172 "for %dth RX ring.\n", i, ring);
3174 for (j = 0; j < i; ++j) {
3175 rxd = &rdata->jme_rxdesc[j];
3176 bus_dmamap_destroy(rdata->jme_rx_tag,
3179 bus_dmamap_destroy(rdata->jme_rx_tag,
3180 rdata->jme_rx_sparemap);
3181 bus_dma_tag_destroy(rdata->jme_rx_tag);
3182 rdata->jme_rx_tag = NULL;
3190 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3194 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3195 if (status & jme_rx_status[r].jme_coal) {
3196 struct jme_rxdata *rdata =
3197 &sc->jme_cdata.jme_rx_data[r];
3199 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3200 jme_rxeof(sc, r, -1);
3201 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3207 jme_enable_rss(struct jme_softc *sc)
3210 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3213 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
3215 KASSERT(sc->jme_rx_ring_inuse == JME_NRXRING_2 ||
3216 sc->jme_rx_ring_inuse == JME_NRXRING_4,
3217 ("%s: invalid # of RX rings (%d)\n",
3218 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_inuse));
3220 rssc = RSSC_HASH_64_ENTRY;
3221 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3222 rssc |= sc->jme_rx_ring_inuse >> 1;
3223 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3224 CSR_WRITE_4(sc, JME_RSSC, rssc);
3226 toeplitz_get_key(key, sizeof(key));
3227 for (i = 0; i < RSSKEY_NREGS; ++i) {
3230 keyreg = RSSKEY_REGVAL(key, i);
3231 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3233 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3237 * Create redirect table in following fashion:
3238 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3241 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3244 q = i % sc->jme_rx_ring_inuse;
3245 ind |= q << (i * 8);
3247 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3249 for (i = 0; i < RSSTBL_NREGS; ++i)
3250 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3254 jme_disable_rss(struct jme_softc *sc)
3256 sc->jme_rx_ring_inuse = JME_NRXRING_1;
3257 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3261 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3263 struct jme_softc *sc = ifp->if_softc;
3266 case IFNET_SERIALIZE_ALL:
3267 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3268 sc->jme_serialize_cnt, 0);
3271 case IFNET_SERIALIZE_MAIN:
3272 lwkt_serialize_enter(&sc->jme_serialize);
3275 case IFNET_SERIALIZE_TX:
3276 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3279 case IFNET_SERIALIZE_RX(0):
3280 lwkt_serialize_enter(
3281 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3284 case IFNET_SERIALIZE_RX(1):
3285 lwkt_serialize_enter(
3286 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3289 case IFNET_SERIALIZE_RX(2):
3290 lwkt_serialize_enter(
3291 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3294 case IFNET_SERIALIZE_RX(3):
3295 lwkt_serialize_enter(
3296 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3300 panic("%s unsupported serialize type\n", ifp->if_xname);
3305 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3307 struct jme_softc *sc = ifp->if_softc;
3310 case IFNET_SERIALIZE_ALL:
3311 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3312 sc->jme_serialize_cnt, 0);
3315 case IFNET_SERIALIZE_MAIN:
3316 lwkt_serialize_exit(&sc->jme_serialize);
3319 case IFNET_SERIALIZE_TX:
3320 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3323 case IFNET_SERIALIZE_RX(0):
3324 lwkt_serialize_exit(
3325 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3328 case IFNET_SERIALIZE_RX(1):
3329 lwkt_serialize_exit(
3330 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3333 case IFNET_SERIALIZE_RX(2):
3334 lwkt_serialize_exit(
3335 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3338 case IFNET_SERIALIZE_RX(3):
3339 lwkt_serialize_exit(
3340 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3344 panic("%s unsupported serialize type\n", ifp->if_xname);
3349 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3351 struct jme_softc *sc = ifp->if_softc;
3354 case IFNET_SERIALIZE_ALL:
3355 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3356 sc->jme_serialize_cnt, 0);
3358 case IFNET_SERIALIZE_MAIN:
3359 return lwkt_serialize_try(&sc->jme_serialize);
3361 case IFNET_SERIALIZE_TX:
3362 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3364 case IFNET_SERIALIZE_RX(0):
3365 return lwkt_serialize_try(
3366 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3368 case IFNET_SERIALIZE_RX(1):
3369 return lwkt_serialize_try(
3370 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3372 case IFNET_SERIALIZE_RX(2):
3373 return lwkt_serialize_try(
3374 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3376 case IFNET_SERIALIZE_RX(3):
3377 return lwkt_serialize_try(
3378 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3381 panic("%s unsupported serialize type\n", ifp->if_xname);
3388 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3389 boolean_t serialized)
3391 struct jme_softc *sc = ifp->if_softc;
3392 struct jme_rxdata *rdata;
3396 case IFNET_SERIALIZE_ALL:
3398 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3399 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3401 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3402 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3406 case IFNET_SERIALIZE_MAIN:
3408 ASSERT_SERIALIZED(&sc->jme_serialize);
3410 ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3413 case IFNET_SERIALIZE_TX:
3415 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3417 ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3420 case IFNET_SERIALIZE_RX(0):
3421 rdata = &sc->jme_cdata.jme_rx_data[0];
3423 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3425 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3428 case IFNET_SERIALIZE_RX(1):
3429 rdata = &sc->jme_cdata.jme_rx_data[1];
3431 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3433 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3436 case IFNET_SERIALIZE_RX(2):
3437 rdata = &sc->jme_cdata.jme_rx_data[2];
3439 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3441 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3444 case IFNET_SERIALIZE_RX(3):
3445 rdata = &sc->jme_cdata.jme_rx_data[3];
3447 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3449 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3453 panic("%s unsupported serialize type\n", ifp->if_xname);
3457 #endif /* INVARIANTS */
3460 jme_msix_try_alloc(device_t dev)
3462 struct jme_softc *sc = device_get_softc(dev);
3463 struct jme_msix_data *msix;
3464 int error, i, r, msix_enable, msix_count;
3467 msix_count = 1 + sc->jme_rx_ring_cnt;
3468 KKASSERT(msix_count <= JME_NMSIX);
3470 msix_enable = jme_msix_enable;
3471 ksnprintf(env, sizeof(env), "hw.%s.msix.enable",
3472 device_get_nameunit(dev));
3473 kgetenv_int(env, &msix_enable);
3476 * We leave the 1st MSI-X vector unused, so we
3477 * actually need msix_count + 1 MSI-X vectors.
3479 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3482 for (i = 0; i < msix_count; ++i)
3483 sc->jme_msix[i].jme_msix_rid = -1;
3487 msix = &sc->jme_msix[i++];
3488 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3489 msix->jme_msix_arg = &sc->jme_cdata;
3490 msix->jme_msix_func = jme_msix_tx;
3491 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3492 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3493 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3494 device_get_nameunit(dev));
3496 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3497 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3499 msix = &sc->jme_msix[i++];
3500 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3501 msix->jme_msix_arg = rdata;
3502 msix->jme_msix_func = jme_msix_rx;
3503 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3504 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3505 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3506 "%s rx%d", device_get_nameunit(dev), r);
3509 KKASSERT(i == msix_count);
3511 error = pci_setup_msix(dev);
3515 /* Setup jme_msix_cnt early, so we could cleanup */
3516 sc->jme_msix_cnt = msix_count;
3518 for (i = 0; i < msix_count; ++i) {
3519 msix = &sc->jme_msix[i];
3521 msix->jme_msix_vector = i + 1;
3522 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3523 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3527 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3528 &msix->jme_msix_rid, RF_ACTIVE);
3529 if (msix->jme_msix_res == NULL) {
3535 for (i = 0; i < JME_INTR_CNT; ++i) {
3536 uint32_t intr_mask = (1 << i);
3539 if ((JME_INTRS & intr_mask) == 0)
3542 for (x = 0; x < msix_count; ++x) {
3543 msix = &sc->jme_msix[x];
3544 if (msix->jme_msix_intrs & intr_mask) {
3547 reg = i / JME_MSINUM_FACTOR;
3548 KKASSERT(reg < JME_MSINUM_CNT);
3550 shift = (i % JME_MSINUM_FACTOR) * 4;
3552 sc->jme_msinum[reg] |=
3553 (msix->jme_msix_vector << shift);
3561 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3562 device_printf(dev, "MSINUM%d: %#x\n", i,
3567 pci_enable_msix(dev);
3568 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3576 jme_intr_alloc(device_t dev)
3578 struct jme_softc *sc = device_get_softc(dev);
3581 jme_msix_try_alloc(dev);
3583 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3584 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3585 &sc->jme_irq_rid, &irq_flags);
3587 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3588 &sc->jme_irq_rid, irq_flags);
3589 if (sc->jme_irq_res == NULL) {
3590 device_printf(dev, "can't allocate irq\n");
3598 jme_msix_free(device_t dev)
3600 struct jme_softc *sc = device_get_softc(dev);
3603 KKASSERT(sc->jme_msix_cnt > 1);
3605 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3606 struct jme_msix_data *msix = &sc->jme_msix[i];
3608 if (msix->jme_msix_res != NULL) {
3609 bus_release_resource(dev, SYS_RES_IRQ,
3610 msix->jme_msix_rid, msix->jme_msix_res);
3611 msix->jme_msix_res = NULL;
3613 if (msix->jme_msix_rid >= 0) {
3614 pci_release_msix_vector(dev, msix->jme_msix_rid);
3615 msix->jme_msix_rid = -1;
3618 pci_teardown_msix(dev);
3622 jme_intr_free(device_t dev)
3624 struct jme_softc *sc = device_get_softc(dev);
3626 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3627 if (sc->jme_irq_res != NULL) {
3628 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3631 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3632 pci_release_msi(dev);
3639 jme_msix_tx(void *xcd)
3641 struct jme_chain_data *cd = xcd;
3642 struct jme_softc *sc = cd->jme_sc;
3643 struct ifnet *ifp = &sc->arpcom.ac_if;
3645 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3647 CSR_WRITE_4(sc, JME_INTR_STATUS,
3648 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3650 if (ifp->if_flags & IFF_RUNNING) {
3652 if (!ifq_is_empty(&ifp->if_snd))
3658 jme_msix_rx(void *xrdata)
3660 struct jme_rxdata *rdata = xrdata;
3661 struct jme_softc *sc = rdata->jme_sc;
3662 struct ifnet *ifp = &sc->arpcom.ac_if;
3665 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3667 status = CSR_READ_4(sc, JME_INTR_STATUS);
3668 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3670 if (status & rdata->jme_rx_coal) {
3671 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3672 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3675 if (ifp->if_flags & IFF_RUNNING) {
3676 if (status & rdata->jme_rx_coal)
3677 jme_rxeof(sc, rdata->jme_rx_idx, -1);
3679 if (status & rdata->jme_rx_empty) {
3680 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3681 RXCSR_RX_ENB | RXCSR_RXQ_START);
3687 jme_set_msinum(struct jme_softc *sc)
3691 for (i = 0; i < JME_MSINUM_CNT; ++i)
3692 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3696 jme_intr_setup(device_t dev)
3698 struct jme_softc *sc = device_get_softc(dev);
3699 struct ifnet *ifp = &sc->arpcom.ac_if;
3702 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3703 return jme_msix_setup(dev);
3705 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3706 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3708 device_printf(dev, "could not set up interrupt handler.\n");
3712 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3713 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3718 jme_intr_teardown(device_t dev)
3720 struct jme_softc *sc = device_get_softc(dev);
3722 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3723 jme_msix_teardown(dev, sc->jme_msix_cnt);
3725 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3729 jme_msix_setup(device_t dev)
3731 struct jme_softc *sc = device_get_softc(dev);
3732 struct ifnet *ifp = &sc->arpcom.ac_if;
3735 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3736 struct jme_msix_data *msix = &sc->jme_msix[x];
3739 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3740 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3741 &msix->jme_msix_handle, msix->jme_msix_serialize,
3742 msix->jme_msix_desc);
3744 device_printf(dev, "could not set up %s "
3745 "interrupt handler.\n", msix->jme_msix_desc);
3746 jme_msix_teardown(dev, x);
3750 ifp->if_cpuid = 0; /* XXX */
3755 jme_msix_teardown(device_t dev, int msix_count)
3757 struct jme_softc *sc = device_get_softc(dev);
3760 for (x = 0; x < msix_count; ++x) {
3761 struct jme_msix_data *msix = &sc->jme_msix[x];
3763 bus_teardown_intr(dev, msix->jme_msix_res,
3764 msix->jme_msix_handle);