sys/dev/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implemented via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 126               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 127         CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,
 128               .reg = { .offset = 1, .mask = 0x007FFFFC },
 129               .bits = {{
 130                         .offset = 0,
 131                         .mask = MI_GLOBAL_GTT,
 132                         .expected = 0,
 133               }},                                                      ),
 134         CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W | B,
 135               .reg = { .offset = 1, .mask = 0x007FFFFC },
 136               .bits = {{
 137                         .offset = 0,
 138                         .mask = MI_GLOBAL_GTT,
 139                         .expected = 0,
 140               }},                                                      ),
 141         /*
 142          * MI_BATCH_BUFFER_START requires some special handling. It's not
 143          * really a 'skip' action but it doesn't seem like it's worth adding
 144          * a new action. See i915_parse_cmds().
 145          */
 146         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 147 };
 148
 149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 150         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 151         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 152         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 153         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 154         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 155         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 156         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 157         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 158         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 159               .bits = {{
 160                         .offset = 0,
 161                         .mask = MI_GLOBAL_GTT,
 162                         .expected = 0,
 163               }},                                                      ),
 164         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 165         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 166               .bits = {{
 167                         .offset = 0,
 168                         .mask = MI_GLOBAL_GTT,
 169                         .expected = 0,
 170               }},                                                      ),
 171         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 172               .bits = {{
 173                         .offset = 1,
 174                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 175                         .expected = 0,
 176               }},                                                      ),
 177         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 178               .bits = {{
 179                         .offset = 0,
 180                         .mask = MI_GLOBAL_GTT,
 181                         .expected = 0,
 182               }},                                                      ),
 183         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 184         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 185         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 186               .bits = {{
 187                         .offset = 2,
 188                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 189                         .expected = 0,
 190               }},                                                      ),
 191         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 192         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 193         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 194         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 195               .bits = {{
 196                         .offset = 1,
 197                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 198                         .expected = 0,
 199               },
 200               {
 201                         .offset = 1,
 202                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 203                                  PIPE_CONTROL_STORE_DATA_INDEX),
 204                         .expected = 0,
 205                         .condition_offset = 1,
 206                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 207               }},                                                      ),
 208 };
 209
 210 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 211         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 212         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 213         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 214         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 215         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 216         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 217         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 218         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 219         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 220         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 221         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 222         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 223         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 224
 225         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 226         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 227         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 228         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 229         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 230 };
 231
 232 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 233         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 234         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 235         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 236               .bits = {{
 237                         .offset = 0,
 238                         .mask = MI_GLOBAL_GTT,
 239                         .expected = 0,
 240               }},                                                      ),
 241         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 242         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 243               .bits = {{
 244                         .offset = 0,
 245                         .mask = MI_FLUSH_DW_NOTIFY,
 246                         .expected = 0,
 247               },
 248               {
 249                         .offset = 1,
 250                         .mask = MI_FLUSH_DW_USE_GTT,
 251                         .expected = 0,
 252                         .condition_offset = 0,
 253                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 254               },
 255               {
 256                         .offset = 0,
 257                         .mask = MI_FLUSH_DW_STORE_INDEX,
 258                         .expected = 0,
 259                         .condition_offset = 0,
 260                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 261               }},                                                      ),
 262         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 263               .bits = {{
 264                         .offset = 0,
 265                         .mask = MI_GLOBAL_GTT,
 266                         .expected = 0,
 267               }},                                                      ),
 268         /*
 269          * MFX_WAIT doesn't fit the way we handle length for most commands.
 270          * It has a length field but it uses a non-standard length bias.
 271          * It is always 1 dword though, so just treat it as fixed length.
 272          */
 273         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 274 };
 275
 276 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 277         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 278         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 279         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 280               .bits = {{
 281                         .offset = 0,
 282                         .mask = MI_GLOBAL_GTT,
 283                         .expected = 0,
 284               }},                                                      ),
 285         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 286         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 287               .bits = {{
 288                         .offset = 0,
 289                         .mask = MI_FLUSH_DW_NOTIFY,
 290                         .expected = 0,
 291               },
 292               {
 293                         .offset = 1,
 294                         .mask = MI_FLUSH_DW_USE_GTT,
 295                         .expected = 0,
 296                         .condition_offset = 0,
 297                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 298               },
 299               {
 300                         .offset = 0,
 301                         .mask = MI_FLUSH_DW_STORE_INDEX,
 302                         .expected = 0,
 303                         .condition_offset = 0,
 304                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 305               }},                                                      ),
 306         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 307               .bits = {{
 308                         .offset = 0,
 309                         .mask = MI_GLOBAL_GTT,
 310                         .expected = 0,
 311               }},                                                      ),
 312 };
 313
 314 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 315         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 316         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 317               .bits = {{
 318                         .offset = 0,
 319                         .mask = MI_GLOBAL_GTT,
 320                         .expected = 0,
 321               }},                                                      ),
 322         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 323         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 324               .bits = {{
 325                         .offset = 0,
 326                         .mask = MI_FLUSH_DW_NOTIFY,
 327                         .expected = 0,
 328               },
 329               {
 330                         .offset = 1,
 331                         .mask = MI_FLUSH_DW_USE_GTT,
 332                         .expected = 0,
 333                         .condition_offset = 0,
 334                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 335               },
 336               {
 337                         .offset = 0,
 338                         .mask = MI_FLUSH_DW_STORE_INDEX,
 339                         .expected = 0,
 340                         .condition_offset = 0,
 341                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 342               }},                                                      ),
 343         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 344         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 345 };
 346
 347 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 348         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 349         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 350 };
 351
 352 #undef CMD
 353 #undef SMI
 354 #undef S3D
 355 #undef S2D
 356 #undef SMFX
 357 #undef F
 358 #undef S
 359 #undef R
 360 #undef W
 361 #undef B
 362 #undef M
 363
 364 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 365         { common_cmds, ARRAY_SIZE(common_cmds) },
 366         { render_cmds, ARRAY_SIZE(render_cmds) },
 367 };
 368
 369 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 370         { common_cmds, ARRAY_SIZE(common_cmds) },
 371         { render_cmds, ARRAY_SIZE(render_cmds) },
 372         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 373 };
 374
 375 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 376         { common_cmds, ARRAY_SIZE(common_cmds) },
 377         { video_cmds, ARRAY_SIZE(video_cmds) },
 378 };
 379
 380 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 381         { common_cmds, ARRAY_SIZE(common_cmds) },
 382         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 383 };
 384
 385 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 386         { common_cmds, ARRAY_SIZE(common_cmds) },
 387         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 388 };
 389
 390 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 391         { common_cmds, ARRAY_SIZE(common_cmds) },
 392         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 393         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 394 };
 395
 396 /*
 397  * Register whitelists, sorted by increasing register offset.
 398  *
 399  * Some registers that userspace accesses are 64 bits. The register
 400  * access commands only allow 32-bit accesses. Hence, we have to include
 401  * entries for both halves of the 64-bit registers.
 402  */
 403
 404 /* Convenience macro for adding 64-bit registers */
 405 #define REG64(addr) (addr), (addr + sizeof(u32))
 406
 407 static const u32 gen7_render_regs[] = {
 408         REG64(GPGPU_THREADS_DISPATCHED),
 409         REG64(HS_INVOCATION_COUNT),
 410         REG64(DS_INVOCATION_COUNT),
 411         REG64(IA_VERTICES_COUNT),
 412         REG64(IA_PRIMITIVES_COUNT),
 413         REG64(VS_INVOCATION_COUNT),
 414         REG64(GS_INVOCATION_COUNT),
 415         REG64(GS_PRIMITIVES_COUNT),
 416         REG64(CL_INVOCATION_COUNT),
 417         REG64(CL_PRIMITIVES_COUNT),
 418         REG64(PS_INVOCATION_COUNT),
 419         REG64(PS_DEPTH_COUNT),
 420         OACONTROL, /* Only allowed for LRI and SRM. See below. */
 421         REG64(MI_PREDICATE_SRC0),
 422         REG64(MI_PREDICATE_SRC1),
 423         GEN7_3DPRIM_END_OFFSET,
 424         GEN7_3DPRIM_START_VERTEX,
 425         GEN7_3DPRIM_VERTEX_COUNT,
 426         GEN7_3DPRIM_INSTANCE_COUNT,
 427         GEN7_3DPRIM_START_INSTANCE,
 428         GEN7_3DPRIM_BASE_VERTEX,
 429         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 430         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 431         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 432         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 433         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
 434         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
 435         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
 436         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
 437         GEN7_SO_WRITE_OFFSET(0),
 438         GEN7_SO_WRITE_OFFSET(1),
 439         GEN7_SO_WRITE_OFFSET(2),
 440         GEN7_SO_WRITE_OFFSET(3),
 441         GEN7_L3SQCREG1,
 442         GEN7_L3CNTLREG2,
 443         GEN7_L3CNTLREG3,
 444 };
 445
 446 static const u32 gen7_blt_regs[] = {
 447         BCS_SWCTRL,
 448 };
 449
 450 static const u32 ivb_master_regs[] = {
 451         FORCEWAKE_MT,
 452         DERRMR,
 453         GEN7_PIPE_DE_LOAD_SL(PIPE_A),
 454         GEN7_PIPE_DE_LOAD_SL(PIPE_B),
 455         GEN7_PIPE_DE_LOAD_SL(PIPE_C),
 456 };
 457
 458 static const u32 hsw_master_regs[] = {
 459         FORCEWAKE_MT,
 460         DERRMR,
 461 };
 462
 463 #undef REG64
 464
 465 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 466 {
 467         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 468         u32 subclient =
 469                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 470
 471         if (client == INSTR_MI_CLIENT)
 472                 return 0x3F;
 473         else if (client == INSTR_RC_CLIENT) {
 474                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 475                         return 0xFFFF;
 476                 else
 477                         return 0xFF;
 478         }
 479
 480         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 481         return 0;
 482 }
 483
 484 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 485 {
 486         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 487         u32 subclient =
 488                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 489         u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
 490
 491         if (client == INSTR_MI_CLIENT)
 492                 return 0x3F;
 493         else if (client == INSTR_RC_CLIENT) {
 494                 if (subclient == INSTR_MEDIA_SUBCLIENT) {
 495                         if (op == 6)
 496                                 return 0xFFFF;
 497                         else
 498                                 return 0xFFF;
 499                 } else
 500                         return 0xFF;
 501         }
 502
 503         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 504         return 0;
 505 }
 506
 507 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 508 {
 509         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 510
 511         if (client == INSTR_MI_CLIENT)
 512                 return 0x3F;
 513         else if (client == INSTR_BC_CLIENT)
 514                 return 0xFF;
 515
 516         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 517         return 0;
 518 }
 519
 520 static bool validate_cmds_sorted(struct intel_engine_cs *ring,
 521                                  const struct drm_i915_cmd_table *cmd_tables,
 522                                  int cmd_table_count)
 523 {
 524         int i;
 525         bool ret = true;
 526
 527         if (!cmd_tables || cmd_table_count == 0)
 528                 return true;
 529
 530         for (i = 0; i < cmd_table_count; i++) {
 531                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 532                 u32 previous = 0;
 533                 int j;
 534
 535                 for (j = 0; j < table->count; j++) {
 536                         const struct drm_i915_cmd_descriptor *desc =
 537                                 &table->table[i];
 538                         u32 curr = desc->cmd.value & desc->cmd.mask;
 539
 540                         if (curr < previous) {
 541                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 542                                           ring->id, i, j, curr, previous);
 543                                 ret = false;
 544                         }
 545
 546                         previous = curr;
 547                 }
 548         }
 549
 550         return ret;
 551 }
 552
 553 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
 554 {
 555         int i;
 556         u32 previous = 0;
 557         bool ret = true;
 558
 559         for (i = 0; i < reg_count; i++) {
 560                 u32 curr = reg_table[i];
 561
 562                 if (curr < previous) {
 563                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 564                                   ring_id, i, curr, previous);
 565                         ret = false;
 566                 }
 567
 568                 previous = curr;
 569         }
 570
 571         return ret;
 572 }
 573
 574 static bool validate_regs_sorted(struct intel_engine_cs *ring)
 575 {
 576         return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
 577                 check_sorted(ring->id, ring->master_reg_table,
 578                              ring->master_reg_count);
 579 }
 580
 581 struct cmd_node {
 582         const struct drm_i915_cmd_descriptor *desc;
 583         struct hlist_node node;
 584 };
 585
 586 /*
 587  * Different command ranges have different numbers of bits for the opcode. For
 588  * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
 589  * problem is that, for example, MI commands use bits 22:16 for other fields
 590  * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
 591  * we mask a command from a batch it could hash to the wrong bucket due to
 592  * non-opcode bits being set. But if we don't include those bits, some 3D
 593  * commands may hash to the same bucket due to not including opcode bits that
 594  * make the command unique. For now, we will risk hashing to the same bucket.
 595  *
 596  * If we attempt to generate a perfect hash, we should be able to look at bits
 597  * 31:29 of a command from a batch buffer and use the full mask for that
 598  * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
 599  */
 600 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
 601
 602 static int init_hash_table(struct intel_engine_cs *ring,
 603                            const struct drm_i915_cmd_table *cmd_tables,
 604                            int cmd_table_count)
 605 {
 606 #if 0
 607         int i, j;
 608
 609         hash_init(ring->cmd_hash);
 610
 611         for (i = 0; i < cmd_table_count; i++) {
 612                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 613
 614                 for (j = 0; j < table->count; j++) {
 615                         const struct drm_i915_cmd_descriptor *desc =
 616                                 &table->table[j];
 617                         struct cmd_node *desc_node =
 618                                 kmalloc(sizeof(*desc_node), M_DRM, M_WAITOK);
 619
 620                         if (!desc_node)
 621                                 return -ENOMEM;
 622
 623                         desc_node->desc = desc;
 624                         hash_add(ring->cmd_hash, &desc_node->node,
 625                                  desc->cmd.value & CMD_HASH_MASK);
 626                 }
 627         }
 628 #endif
 629
 630         return 0;
 631 }
 632
 633 static void fini_hash_table(struct intel_engine_cs *ring)
 634 {
 635 #if 0
 636         struct hlist_node *tmp;
 637         struct cmd_node *desc_node;
 638         int i;
 639
 640         hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) {
 641                 hash_del(&desc_node->node);
 642                 kfree(desc_node);
 643         }
 644 #endif
 645 }
 646
 647 /**
 648  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 649  * @ring: the ringbuffer to initialize
 650  *
 651  * Optionally initializes fields related to batch buffer command parsing in the
 652  * struct intel_engine_cs based on whether the platform requires software
 653  * command parsing.
 654  *
 655  * Return: non-zero if initialization fails
 656  */
 657 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
 658 {
 659         const struct drm_i915_cmd_table *cmd_tables;
 660         int cmd_table_count;
 661         int ret;
 662
 663         if (!IS_GEN7(ring->dev))
 664                 return 0;
 665
 666         switch (ring->id) {
 667         case RCS:
 668                 if (IS_HASWELL(ring->dev)) {
 669                         cmd_tables = hsw_render_ring_cmds;
 670                         cmd_table_count =
 671                                 ARRAY_SIZE(hsw_render_ring_cmds);
 672                 } else {
 673                         cmd_tables = gen7_render_cmds;
 674                         cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 675                 }
 676
 677                 ring->reg_table = gen7_render_regs;
 678                 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 679
 680                 if (IS_HASWELL(ring->dev)) {
 681                         ring->master_reg_table = hsw_master_regs;
 682                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 683                 } else {
 684                         ring->master_reg_table = ivb_master_regs;
 685                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 686                 }
 687
 688                 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 689                 break;
 690         case VCS:
 691                 cmd_tables = gen7_video_cmds;
 692                 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 693                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 694                 break;
 695         case BCS:
 696                 if (IS_HASWELL(ring->dev)) {
 697                         cmd_tables = hsw_blt_ring_cmds;
 698                         cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 699                 } else {
 700                         cmd_tables = gen7_blt_cmds;
 701                         cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 702                 }
 703
 704                 ring->reg_table = gen7_blt_regs;
 705                 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 706
 707                 if (IS_HASWELL(ring->dev)) {
 708                         ring->master_reg_table = hsw_master_regs;
 709                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 710                 } else {
 711                         ring->master_reg_table = ivb_master_regs;
 712                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 713                 }
 714
 715                 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 716                 break;
 717         case VECS:
 718                 cmd_tables = hsw_vebox_cmds;
 719                 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 720                 /* VECS can use the same length_mask function as VCS */
 721                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 722                 break;
 723         default:
 724                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 725                           ring->id);
 726                 BUG();
 727         }
 728
 729         BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
 730         BUG_ON(!validate_regs_sorted(ring));
 731
 732 #if 0
 733         WARN_ON(!hash_empty(ring->cmd_hash));
 734 #endif
 735
 736         ret = init_hash_table(ring, cmd_tables, cmd_table_count);
 737         if (ret) {
 738                 DRM_ERROR("CMD: cmd_parser_init failed!\n");
 739                 fini_hash_table(ring);
 740                 return ret;
 741         }
 742
 743         ring->needs_cmd_parser = true;
 744
 745         return 0;
 746 }
 747
 748 /**
 749  * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
 750  * @ring: the ringbuffer to clean up
 751  *
 752  * Releases any resources related to command parsing that may have been
 753  * initialized for the specified ring.
 754  */
 755 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring)
 756 {
 757         if (!ring->needs_cmd_parser)
 758                 return;
 759
 760         fini_hash_table(ring);
 761 }
 762
 763 static const struct drm_i915_cmd_descriptor*
 764 find_cmd_in_table(struct intel_engine_cs *ring,
 765                   u32 cmd_header)
 766 {
 767 #if 0
 768         struct cmd_node *desc_node;
 769
 770         hash_for_each_possible(ring->cmd_hash, desc_node, node,
 771                                cmd_header & CMD_HASH_MASK) {
 772                 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
 773                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 774                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 775
 776                 if (masked_cmd == masked_value)
 777                         return desc;
 778         }
 779 #endif
 780
 781         return NULL;
 782 }
 783
 784 /*
 785  * Returns a pointer to a descriptor for the command specified by cmd_header.
 786  *
 787  * The caller must supply space for a default descriptor via the default_desc
 788  * parameter. If no descriptor for the specified command exists in the ring's
 789  * command parser tables, this function fills in default_desc based on the
 790  * ring's default length encoding and returns default_desc.
 791  */
 792 static const struct drm_i915_cmd_descriptor*
 793 find_cmd(struct intel_engine_cs *ring,
 794          u32 cmd_header,
 795          struct drm_i915_cmd_descriptor *default_desc)
 796 {
 797         const struct drm_i915_cmd_descriptor *desc;
 798         u32 mask;
 799
 800         desc = find_cmd_in_table(ring, cmd_header);
 801         if (desc)
 802                 return desc;
 803
 804         mask = ring->get_cmd_length_mask(cmd_header);
 805         if (!mask)
 806                 return NULL;
 807
 808         BUG_ON(!default_desc);
 809         default_desc->flags = CMD_DESC_SKIP;
 810         default_desc->length.mask = mask;
 811
 812         return default_desc;
 813 }
 814
 815 static bool valid_reg(const u32 *table, int count, u32 addr)
 816 {
 817         if (table && count != 0) {
 818                 int i;
 819
 820                 for (i = 0; i < count; i++) {
 821                         if (table[i] == addr)
 822                                 return true;
 823                 }
 824         }
 825
 826         return false;
 827 }
 828
 829 static u32 *vmap_batch(struct drm_i915_gem_object *obj,
 830                        unsigned start, unsigned len)
 831 {
 832         int i;
 833         void *addr = NULL;
 834         int first_page = start >> PAGE_SHIFT;
 835         int last_page = (len + start + 4095) >> PAGE_SHIFT;
 836         int npages = last_page - first_page;
 837         struct vm_page **pages;
 838
 839         pages = drm_malloc_ab(npages, sizeof(*pages));
 840         if (pages == NULL) {
 841                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 842                 goto finish;
 843         }
 844
 845         i = 0;
 846         while (i < npages) {
 847                 pages[i] = obj->pages[first_page + i];
 848                 i++;
 849         }
 850
 851 #if 0
 852         addr = vmap(pages, i, 0, PAGE_KERNEL);
 853         if (addr == NULL) {
 854                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 855                 goto finish;
 856         }
 857 #endif
 858
 859 finish:
 860         if (pages)
 861                 drm_free_large(pages);
 862         return (u32*)addr;
 863 }
 864
 865 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
 866 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
 867                        struct drm_i915_gem_object *src_obj,
 868                        u32 batch_start_offset,
 869                        u32 batch_len)
 870 {
 871         int needs_clflush = 0;
 872         char *src_base, *src;
 873         void *dst = NULL;
 874         int ret;
 875
 876         if (batch_len > dest_obj->base.size ||
 877             batch_len + batch_start_offset > src_obj->base.size)
 878                 return ERR_PTR(-E2BIG);
 879
 880         ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
 881         if (ret) {
 882                 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
 883                 return ERR_PTR(ret);
 884         }
 885
 886         src_base = (char *)vmap_batch(src_obj, batch_start_offset, batch_len);
 887         if (!src_base) {
 888                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
 889                 ret = -ENOMEM;
 890                 goto unpin_src;
 891         }
 892
 893         ret = i915_gem_object_get_pages(dest_obj);
 894         if (ret) {
 895                 DRM_DEBUG_DRIVER("CMD: Failed to get pages for shadow batch\n");
 896                 goto unmap_src;
 897         }
 898         i915_gem_object_pin_pages(dest_obj);
 899
 900         ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
 901         if (ret) {
 902                 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
 903                 goto unmap_src;
 904         }
 905
 906         dst = vmap_batch(dest_obj, 0, batch_len);
 907         if (!dst) {
 908                 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
 909                 i915_gem_object_unpin_pages(dest_obj);
 910                 ret = -ENOMEM;
 911                 goto unmap_src;
 912         }
 913
 914         src = src_base + offset_in_page(batch_start_offset);
 915         if (needs_clflush)
 916                 drm_clflush_virt_range(src, batch_len);
 917
 918         memcpy(dst, src, batch_len);
 919
 920 unmap_src:
 921         vunmap(src_base);
 922 unpin_src:
 923         i915_gem_object_unpin_pages(src_obj);
 924
 925         return ret ? ERR_PTR(ret) : dst;
 926 }
 927
 928 /**
 929  * i915_needs_cmd_parser() - should a given ring use software command parsing?
 930  * @ring: the ring in question
 931  *
 932  * Only certain platforms require software batch buffer command parsing, and
 933  * only when enabled via module parameter.
 934  *
 935  * Return: true if the ring requires software command parsing
 936  */
 937 bool i915_needs_cmd_parser(struct intel_engine_cs *ring)
 938 {
 939         if (!ring->needs_cmd_parser)
 940                 return false;
 941
 942         if (!USES_PPGTT(ring->dev))
 943                 return false;
 944
 945         return (i915.enable_cmd_parser == 1);
 946 }
 947
 948 static bool check_cmd(const struct intel_engine_cs *ring,
 949                       const struct drm_i915_cmd_descriptor *desc,
 950                       const u32 *cmd,
 951                       const bool is_master,
 952                       bool *oacontrol_set)
 953 {
 954         if (desc->flags & CMD_DESC_REJECT) {
 955                 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
 956                 return false;
 957         }
 958
 959         if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
 960                 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
 961                                  *cmd);
 962                 return false;
 963         }
 964
 965         if (desc->flags & CMD_DESC_REGISTER) {
 966                 u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
 967
 968                 /*
 969                  * OACONTROL requires some special handling for writes. We
 970                  * want to make sure that any batch which enables OA also
 971                  * disables it before the end of the batch. The goal is to
 972                  * prevent one process from snooping on the perf data from
 973                  * another process. To do that, we need to check the value
 974                  * that will be written to the register. Hence, limit
 975                  * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
 976                  */
 977                 if (reg_addr == OACONTROL) {
 978                         if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 979                                 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 980                                 return false;
 981                         }
 982
 983                         if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
 984                                 *oacontrol_set = (cmd[2] != 0);
 985                 }
 986
 987                 if (!valid_reg(ring->reg_table,
 988                                ring->reg_count, reg_addr)) {
 989                         if (!is_master ||
 990                             !valid_reg(ring->master_reg_table,
 991                                        ring->master_reg_count,
 992                                        reg_addr)) {
 993                                 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
 994                                                  reg_addr,
 995                                                  *cmd,
 996                                                  ring->id);
 997                                 return false;
 998                         }
 999                 }
1000         }
1001
1002         if (desc->flags & CMD_DESC_BITMASK) {
1003                 int i;
1004
1005                 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1006                         u32 dword;
1007
1008                         if (desc->bits[i].mask == 0)
1009                                 break;
1010
1011                         if (desc->bits[i].condition_mask != 0) {
1012                                 u32 offset =
1013                                         desc->bits[i].condition_offset;
1014                                 u32 condition = cmd[offset] &
1015                                         desc->bits[i].condition_mask;
1016
1017                                 if (condition == 0)
1018                                         continue;
1019                         }
1020
1021                         dword = cmd[desc->bits[i].offset] &
1022                                 desc->bits[i].mask;
1023
1024                         if (dword != desc->bits[i].expected) {
1025                                 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
1026                                                  *cmd,
1027                                                  desc->bits[i].mask,
1028                                                  desc->bits[i].expected,
1029                                                  dword, ring->id);
1030                                 return false;
1031                         }
1032                 }
1033         }
1034
1035         return true;
1036 }
1037
1038 #define LENGTH_BIAS 2
1039
1040 /**
1041  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1042  * @ring: the ring on which the batch is to execute
1043  * @batch_obj: the batch buffer in question
1044  * @shadow_batch_obj: copy of the batch buffer in question
1045  * @batch_start_offset: byte offset in the batch at which execution starts
1046  * @batch_len: length of the commands in batch_obj
1047  * @is_master: is the submitting process the drm master?
1048  *
1049  * Parses the specified batch buffer looking for privilege violations as
1050  * described in the overview.
1051  *
1052  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1053  * if the batch appears legal but should use hardware parsing
1054  */
1055 int i915_parse_cmds(struct intel_engine_cs *ring,
1056                     struct drm_i915_gem_object *batch_obj,
1057                     struct drm_i915_gem_object *shadow_batch_obj,
1058                     u32 batch_start_offset,
1059                     u32 batch_len,
1060                     bool is_master)
1061 {
1062         u32 *cmd, *batch_base, *batch_end;
1063         struct drm_i915_cmd_descriptor default_desc = { 0 };
1064         bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
1065         int ret = 0;
1066
1067         batch_base = copy_batch(shadow_batch_obj, batch_obj,
1068                                 batch_start_offset, batch_len);
1069         if (IS_ERR(batch_base)) {
1070                 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1071                 return PTR_ERR(batch_base);
1072         }
1073
1074         /*
1075          * We use the batch length as size because the shadow object is as
1076          * large or larger and copy_batch() will write MI_NOPs to the extra
1077          * space. Parsing should be faster in some cases this way.
1078          */
1079         batch_end = batch_base + (batch_len / sizeof(*batch_end));
1080
1081         cmd = batch_base;
1082         while (cmd < batch_end) {
1083                 const struct drm_i915_cmd_descriptor *desc;
1084                 u32 length;
1085
1086                 if (*cmd == MI_BATCH_BUFFER_END)
1087                         break;
1088
1089                 desc = find_cmd(ring, *cmd, &default_desc);
1090                 if (!desc) {
1091                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1092                                          *cmd);
1093                         ret = -EINVAL;
1094                         break;
1095                 }
1096
1097                 /*
1098                  * If the batch buffer contains a chained batch, return an
1099                  * error that tells the caller to abort and dispatch the
1100                  * workload as a non-secure batch.
1101                  */
1102                 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1103                         ret = -EACCES;
1104                         break;
1105                 }
1106
1107                 if (desc->flags & CMD_DESC_FIXED)
1108                         length = desc->length.fixed;
1109                 else
1110                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1111
1112                 if ((batch_end - cmd) < length) {
1113                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1114                                          *cmd,
1115                                          length,
1116                                          batch_end - cmd);
1117                         ret = -EINVAL;
1118                         break;
1119                 }
1120
1121                 if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
1122                         ret = -EINVAL;
1123                         break;
1124                 }
1125
1126                 cmd += length;
1127         }
1128
1129         if (oacontrol_set) {
1130                 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1131                 ret = -EINVAL;
1132         }
1133
1134         if (cmd >= batch_end) {
1135                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1136                 ret = -EINVAL;
1137         }
1138
1139         vunmap(batch_base);
1140         i915_gem_object_unpin_pages(shadow_batch_obj);
1141
1142         return ret;
1143 }
1144
1145 /**
1146  * i915_cmd_parser_get_version() - get the cmd parser version number
1147  *
1148  * The cmd parser maintains a simple increasing integer version number suitable
1149  * for passing to userspace clients to determine what operations are permitted.
1150  *
1151  * Return: the current version number of the cmd parser
1152  */
1153 int i915_cmd_parser_get_version(void)
1154 {
1155         /*
1156          * Command parser version history
1157          *
1158          * 1. Initial version. Checks batches and reports violations, but leaves
1159          *    hardware parsing enabled (so does not allow new use cases).
1160          * 2. Allow access to the MI_PREDICATE_SRC0 and
1161          *    MI_PREDICATE_SRC1 registers.
1162          * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1163          */
1164         return 3;
1165 }