sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.12 2005/10/12 17:35:55 dillon Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59 #include <sys/thread2.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <net/if.h>
  66
  67 #include <net/i4b/include/machine/i4b_debug.h>
  68 #include <net/i4b/include/machine/i4b_ioctl.h>
  69 #include <net/i4b/include/machine/i4b_trace.h>
  70
  71 #include "../../include/i4b_global.h"
  72 #include "../../include/i4b_mbuf.h"
  73
  74 #include "../i4b_l1.h"
  75 #include "../isic/i4b_isic.h"
  76 #include "../isic/i4b_isac.h"
  77 #include "../isic/i4b_hscx.h"
  78
  79 #include "i4b_ifpi_ext.h"
  80
  81 #define PCI_AVMA1_VID 0x1244
  82 #define PCI_AVMA1_DID 0x0a00
  83
  84 /* prototypes */
  85 static void avma1pp_disable(device_t);
  86
  87 static void avma1pp_intr(void *);
  88 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
  89 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
  90 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
  91 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  92 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  93 static void avma1pp_hscx_int_handler(struct l1_softc *);
  94 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
  95 static void avma1pp_init_linktab(struct l1_softc *);
  96 static void avma1pp_bchannel_setup(int, int, int, int);
  97 static void avma1pp_bchannel_start(int, int);
  98 static void avma1pp_hscx_init(struct l1_softc *, int, int);
  99 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
 100 static void avma1pp_set_linktab(int, int, drvr_link_t *);
 101 static isdn_link_t * avma1pp_ret_linktab(int, int);
 102 static int avma1pp_pci_probe(device_t);
 103 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 104 int avma1pp_attach_avma1pp(device_t);
 105 static void ifpi_isac_intr(struct l1_softc *sc);
 106
 107 static device_method_t avma1pp_pci_methods[] = {
 108         /* Device interface */
 109         DEVMETHOD(device_probe,         avma1pp_pci_probe),
 110         DEVMETHOD(device_attach,        avma1pp_attach_avma1pp),
 111         DEVMETHOD(device_shutdown,      avma1pp_disable),
 112
 113         /* bus interface */
 114         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 115         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 116
 117         { 0, 0 }
 118 };
 119
 120 #if 0 /* use what's in l1_softc */
 121 /* a minimal softc for the Fritz!Card PCI */
 122 struct avma1pp_softc
 123 {
 124         bus_space_handle_t      avma1pp_bhandle;
 125         bus_space_tag_t         avma1pp_btag;
 126         void                    *avma1pp_intrhand;
 127         struct resource         *avma1pp_irq;
 128         struct resource         *avma1pp_res;
 129         /* pointer to ifpi_sc */
 130         struct l1_softc *avma1pp_isc;
 131 };
 132 #endif
 133
 134 static driver_t avma1pp_pci_driver = {
 135         "ifpi",
 136         avma1pp_pci_methods,
 137         sizeof(struct l1_softc)
 138 };
 139
 140 static devclass_t avma1pp_pci_devclass;
 141
 142 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
 143
 144 /* jump table for multiplex routines */
 145
 146 struct i4b_l1mux_func avma1pp_l1mux_func = {
 147         avma1pp_ret_linktab,
 148         avma1pp_set_linktab,
 149         ifpi_mph_command_req,
 150         ifpi_ph_data_req,
 151         ifpi_ph_activate_req,
 152 };
 153
 154 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
 155
 156 /*---------------------------------------------------------------------------*
 157  *      AVM PCI Fritz!Card special registers
 158  *---------------------------------------------------------------------------*/
 159
 160 /*
 161  *      register offsets from i/o base
 162  */
 163 #define STAT0_OFFSET            0x02
 164 #define STAT1_OFFSET            0x03
 165 #define ADDR_REG_OFFSET         0x04
 166 /*#define MODREG_OFFSET         0x06
 167 #define VERREG_OFFSET           0x07*/
 168
 169 /* these 2 are used to select an ISAC register set */
 170 #define ISAC_LO_REG_OFFSET      0x04
 171 #define ISAC_HI_REG_OFFSET      0x06
 172
 173 /* offset higher than this goes to the HI register set */
 174 #define MAX_LO_REG_OFFSET       0x2f
 175
 176 /* mask for the offset */
 177 #define ISAC_REGSET_MASK        0x0f
 178
 179 /* the offset from the base to the ISAC registers */
 180 #define ISAC_REG_OFFSET         0x10
 181
 182 /* the offset from the base to the ISAC FIFO */
 183 #define ISAC_FIFO               0x02
 184
 185 /* not really the HSCX, but sort of */
 186 #define HSCX_FIFO               0x00
 187 #define HSCX_STAT               0x04
 188
 189 /*
 190  *      AVM PCI Status Latch 0 read only bits
 191  */
 192 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 193 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 194 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 195 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 196 /* actually active LOW */
 197 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 198
 199 /*
 200  *      AVM Status Latch 0 write only bits
 201  */
 202 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 203 #define ASL_TIMERDISABLE        0x02  /* active high */
 204 #define ASL_TIMERRESET          0x04  /* active high */
 205 #define ASL_ENABLE_INT          0x08  /* active high */
 206 #define ASL_TESTBIT             0x10  /* active high */
 207
 208 /*
 209  *      AVM Status Latch 1 write only bits
 210  */
 211 #define ASL1_INTSEL              0x0f  /* active high */
 212 #define ASL1_ENABLE_IOM          0x80  /* active high */
 213
 214 /*
 215  * "HSCX" mode bits
 216  */
 217 #define  HSCX_MODE_ITF_FLG      0x01
 218 #define  HSCX_MODE_TRANS        0x02
 219 #define  HSCX_MODE_CCR_7        0x04
 220 #define  HSCX_MODE_CCR_16       0x08
 221 #define  HSCX_MODE_TESTLOOP     0x80
 222
 223 /*
 224  * "HSCX" status bits
 225  */
 226 #define  HSCX_STAT_RME          0x01
 227 #define  HSCX_STAT_RDO          0x10
 228 #define  HSCX_STAT_CRCVFRRAB    0x0E
 229 #define  HSCX_STAT_CRCVFR       0x06
 230 #define  HSCX_STAT_RML_MASK     0x3f00
 231
 232 /*
 233  * "HSCX" interrupt bits
 234  */
 235 #define  HSCX_INT_XPR           0x80
 236 #define  HSCX_INT_XDU           0x40
 237 #define  HSCX_INT_RPR           0x20
 238 #define  HSCX_INT_MASK          0xE0
 239
 240 /*
 241  * "HSCX" command bits
 242  */
 243 #define  HSCX_CMD_XRS           0x80
 244 #define  HSCX_CMD_XME           0x01
 245 #define  HSCX_CMD_RRS           0x20
 246 #define  HSCX_CMD_XML_MASK      0x3f00
 247
 248 /*
 249  * Commands and parameters are sent to the "HSCX" as a long, but the
 250  * fields are handled as bytes.
 251  *
 252  * The long contains:
 253  *      (prot << 16)|(txl << 8)|cmd
 254  *
 255  * where:
 256  *      prot = protocol to use
 257  *      txl = transmit length
 258  *      cmd = the command to be executed
 259  *
 260  * The fields are defined as u_char in struct l1_softc.
 261  *
 262  * Macro to coalesce the byte fields into a u_int
 263  */
 264 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 265                                         | (sc->avma1pp_prot << 16))
 266
 267 /*
 268  * to prevent deactivating the "HSCX" when both channels are active we
 269  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 270  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
 271  * It is set high to allow room for new flags.
 272  */
 273 #define HSCX_AVMA1PP_ACTIVE     0x1000
 274
 275 /*---------------------------------------------------------------------------*
 276  *      AVM read fifo routines
 277  *---------------------------------------------------------------------------*/
 278
 279 static void
 280 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 281 {
 282         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 283         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 284
 285         switch (what) {
 286                 case ISIC_WHAT_ISAC:
 287                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 288                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 289                         break;
 290                 case ISIC_WHAT_HSCXA:
 291                         hscx_read_fifo(0, buf, size, sc);
 292                         break;
 293                 case ISIC_WHAT_HSCXB:
 294                         hscx_read_fifo(1, buf, size, sc);
 295                         break;
 296         }
 297 }
 298
 299 static void
 300 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 301 {
 302         u_int32_t *ip;
 303         size_t cnt;
 304         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 305         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 306
 307         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 308         ip = (u_int32_t *)buf;
 309         cnt = 0;
 310         /* what if len isn't a multiple of sizeof(int) and buf is */
 311         /* too small ???? */
 312         while (cnt < len)
 313         {
 314                 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
 315                 cnt += 4;
 316         }
 317 }
 318
 319 /*---------------------------------------------------------------------------*
 320  *      AVM write fifo routines
 321  *---------------------------------------------------------------------------*/
 322 static void
 323 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 324 {
 325         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 326         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 327
 328         switch (what) {
 329                 case ISIC_WHAT_ISAC:
 330                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 331                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 332                         break;
 333                 case ISIC_WHAT_HSCXA:
 334                         hscx_write_fifo(0, buf, size, sc);
 335                         break;
 336                 case ISIC_WHAT_HSCXB:
 337                         hscx_write_fifo(1, buf, size, sc);
 338                         break;
 339         }
 340 }
 341
 342 static void
 343 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 344 {
 345         u_int32_t *ip;
 346         size_t cnt;
 347         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 348         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 349         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 350
 351
 352         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 353         sc->avma1pp_txl = 0;
 354         if (Bchan->out_mbuf_cur == NULL)
 355         {
 356           if (Bchan->bprot != BPROT_NONE)
 357                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 358         }
 359         if (len != sc->sc_bfifolen)
 360                 sc->avma1pp_txl = len;
 361
 362         cnt = 0; /* borrow cnt */
 363         AVMA1PPSETCMDLONG(cnt);
 364         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
 365
 366         ip = (u_int32_t *)buf;
 367         cnt = 0;
 368         while (cnt < len)
 369         {
 370                 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
 371                 ip++;
 372                 cnt += 4;
 373         }
 374 }
 375
 376 /*---------------------------------------------------------------------------*
 377  *      AVM write register routines
 378  *---------------------------------------------------------------------------*/
 379
 380 static void
 381 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 382 {
 383         u_char reg_bank;
 384         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 385         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 386
 387         switch (what) {
 388                 case ISIC_WHAT_ISAC:
 389                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 390 #ifdef AVMA1PCI_DEBUG
 391                         printf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 392 #endif
 393                         /* set the register bank */
 394                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 395                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 396                         break;
 397                 case ISIC_WHAT_HSCXA:
 398                         hscx_write_reg(0, offs, data, sc);
 399                         break;
 400                 case ISIC_WHAT_HSCXB:
 401                         hscx_write_reg(1, offs, data, sc);
 402                         break;
 403         }
 404 }
 405
 406 static void
 407 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
 408 {
 409         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 410         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 411
 412         /* point at the correct channel */
 413         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 414         bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
 415 }
 416
 417 /*---------------------------------------------------------------------------*
 418  *      AVM read register routines
 419  *---------------------------------------------------------------------------*/
 420 static u_int8_t
 421 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 422 {
 423         u_char reg_bank;
 424         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 425         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 426
 427         switch (what) {
 428                 case ISIC_WHAT_ISAC:
 429                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 430 #ifdef AVMA1PCI_DEBUG
 431                         printf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 432 #endif
 433                         /* set the register bank */
 434                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 435                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 436                                 (offs & ISAC_REGSET_MASK)));
 437                 case ISIC_WHAT_HSCXA:
 438                         return hscx_read_reg(0, offs, sc);
 439                 case ISIC_WHAT_HSCXB:
 440                         return hscx_read_reg(1, offs, sc);
 441         }
 442         return 0;
 443 }
 444
 445 static u_char
 446 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 447 {
 448         return(hscx_read_reg_int(chan, off, sc) & 0xff);
 449 }
 450
 451 /*
 452  * need to be able to return an int because the RBCH is in the 2nd
 453  * byte.
 454  */
 455 static u_int
 456 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
 457 {
 458         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 459         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 460
 461         /* point at the correct channel */
 462         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 463         return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
 464 }
 465
 466 /*---------------------------------------------------------------------------*
 467  *      avma1pp_probe - probe for a card
 468  *---------------------------------------------------------------------------*/
 469 static int
 470 avma1pp_pci_probe(dev)
 471         device_t                dev;
 472 {
 473         u_int16_t               did, vid;
 474
 475         vid = pci_get_vendor(dev);
 476         did = pci_get_device(dev);
 477
 478         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
 479                 device_set_desc(dev, "AVM Fritz!Card PCI");
 480                 return(0);
 481         }
 482
 483         return(ENXIO);
 484 }
 485
 486 /*---------------------------------------------------------------------------*
 487  *      avma1pp_attach_avma1pp - attach Fritz!Card PCI
 488  *---------------------------------------------------------------------------*/
 489 int
 490 avma1pp_attach_avma1pp(device_t dev)
 491 {
 492         struct l1_softc *sc;
 493         u_int v;
 494         int unit, error = 0;
 495         u_int16_t did, vid;
 496         void *ih = 0;
 497         bus_space_handle_t bhandle;
 498         bus_space_tag_t btag;
 499
 500         crit_enter();
 501
 502         vid = pci_get_vendor(dev);
 503         did = pci_get_device(dev);
 504         sc = device_get_softc(dev);
 505         unit = device_get_unit(dev);
 506         bzero(sc, sizeof(struct l1_softc));
 507
 508         /* probably not really required */
 509         if(unit > IFPI_MAXUNIT) {
 510                 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 511                 crit_exit();
 512                 return(ENXIO);
 513         }
 514
 515         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
 516                 printf("avma1pp%d: unknown device!?\n", unit);
 517                 goto fail;
 518         }
 519
 520         ifpi_scp[unit] = sc;
 521
 522         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 523         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 524                 &sc->sc_resources.io_rid[0],
 525                 0, ~0, 1, RF_ACTIVE);
 526
 527         if (sc->sc_resources.io_base[0] == NULL) {
 528                 printf("avma1pp%d: couldn't map IO port\n", unit);
 529                 error = ENXIO;
 530                 goto fail;
 531         }
 532
 533         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 534         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 535
 536         /* Allocate interrupt */
 537         sc->sc_resources.irq_rid = 0;
 538         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 539                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 540
 541         if (sc->sc_resources.irq == NULL) {
 542                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 543                 printf("avma1pp%d: couldn't map interrupt\n", unit);
 544                 error = ENXIO;
 545                 goto fail;
 546         }
 547
 548         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
 549                                avma1pp_intr, sc, &ih, NULL);
 550
 551         if (error) {
 552                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 553                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 554                 printf("avma1pp%d: couldn't set up irq\n", unit);
 555                 goto fail;
 556         }
 557
 558         sc->sc_unit = unit;
 559
 560         /* end of new-bus stuff */
 561
 562         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 563
 564         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 565         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 566
 567         /* setup access routines */
 568
 569         sc->clearirq = NULL;
 570         sc->readreg = avma1pp_read_reg;
 571         sc->writereg = avma1pp_write_reg;
 572
 573         sc->readfifo = avma1pp_read_fifo;
 574         sc->writefifo = avma1pp_write_fifo;
 575
 576         /* setup card type */
 577
 578         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
 579
 580         /* setup IOM bus type */
 581
 582         sc->sc_bustyp = BUS_TYPE_IOM2;
 583
 584         /* set up some other miscellaneous things */
 585         sc->sc_ipac = 0;
 586         sc->sc_bfifolen = HSCX_FIFO_LEN;
 587
 588         /* reset the card */
 589         /* the Linux driver does this to clear any pending ISAC interrupts */
 590         v = 0;
 591         v = ISAC_READ(I_STAR);
 592 #ifdef AVMA1PCI_DEBUG
 593         printf("avma1pp_attach: I_STAR %x...", v);
 594 #endif
 595         v = ISAC_READ(I_MODE);
 596 #ifdef AVMA1PCI_DEBUG
 597         printf("avma1pp_attach: I_MODE %x...", v);
 598 #endif
 599         v = ISAC_READ(I_ADF2);
 600 #ifdef AVMA1PCI_DEBUG
 601         printf("avma1pp_attach: I_ADF2 %x...", v);
 602 #endif
 603         v = ISAC_READ(I_ISTA);
 604 #ifdef AVMA1PCI_DEBUG
 605         printf("avma1pp_attach: I_ISTA %x...", v);
 606 #endif
 607         if (v & ISAC_ISTA_EXI)
 608         {
 609                  v = ISAC_READ(I_EXIR);
 610 #ifdef AVMA1PCI_DEBUG
 611                  printf("avma1pp_attach: I_EXIR %x...", v);
 612 #endif
 613         }
 614         v = ISAC_READ(I_CIRR);
 615 #ifdef AVMA1PCI_DEBUG
 616         printf("avma1pp_attach: I_CIRR %x...", v);
 617 #endif
 618         ISAC_WRITE(I_MASK, 0xff);
 619         /* the Linux driver does this to clear any pending HSCX interrupts */
 620         v = hscx_read_reg_int(0, HSCX_STAT, sc);
 621 #ifdef AVMA1PCI_DEBUG
 622         printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
 623 #endif
 624         v = hscx_read_reg_int(1, HSCX_STAT, sc);
 625 #ifdef AVMA1PCI_DEBUG
 626         printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
 627 #endif
 628
 629         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 630         DELAY(SEC_DELAY/100); /* 10 ms */
 631         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 632         DELAY(SEC_DELAY/100); /* 10 ms */
 633 #ifdef AVMA1PCI_DEBUG
 634         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 635         DELAY(SEC_DELAY/100); /* 10 ms */
 636         v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
 637         printf("after reset: S1 %#x\n", v);
 638
 639         v = bus_space_read_4(btag, bhandle, 0);
 640         printf("avma1pp_attach_avma1pp: v %#x\n", v);
 641 #endif
 642
 643    /* from here to the end would normally be done in isic_pciattach */
 644
 645          printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
 646                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 647                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 648
 649         /* init the ISAC */
 650         ifpi_isac_init(sc);
 651
 652         /* init the "HSCX" */
 653         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 654
 655         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 656
 657         /* can't use the normal B-Channel stuff */
 658         avma1pp_init_linktab(sc);
 659
 660         /* set trace level */
 661
 662         sc->sc_trace = TRACE_OFF;
 663
 664         sc->sc_state = ISAC_IDLE;
 665
 666         sc->sc_ibuf = NULL;
 667         sc->sc_ib = NULL;
 668         sc->sc_ilen = 0;
 669
 670         sc->sc_obuf = NULL;
 671         sc->sc_op = NULL;
 672         sc->sc_ol = 0;
 673         sc->sc_freeflag = 0;
 674
 675         sc->sc_obuf2 = NULL;
 676         sc->sc_freeflag2 = 0;
 677
 678         callout_init(&sc->sc_T3_timeout);
 679         callout_init(&sc->sc_T4_timeout);
 680
 681         /* init higher protocol layers */
 682
 683         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
 684
 685   fail:
 686         crit_exit();
 687         return(error);
 688 }
 689
 690 /*
 691  * this is the real interrupt routine
 692  */
 693 static void
 694 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 695 {
 696         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 697         int activity = -1;
 698         u_int param = 0;
 699
 700         NDBGL1(L1_H_IRQ, "%#x", stat);
 701
 702         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 703         {
 704                 chan->stat_XDU++;
 705                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 706                 /* abort the transmission */
 707                 sc->avma1pp_txl = 0;
 708                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 709                 AVMA1PPSETCMDLONG(param);
 710                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 711                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 712                 AVMA1PPSETCMDLONG(param);
 713                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 714
 715                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 716                 {
 717                         i4b_Bfreembuf(chan->out_mbuf_head);
 718                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 719                 }
 720         }
 721
 722         /*
 723          * The following is based on examination of the Linux driver.
 724          *
 725          * The logic here is different than with a "real" HSCX; all kinds
 726          * of information (interrupt/status bits) are in stat.
 727          *              HSCX_INT_RPR indicates a receive interrupt
 728          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 729          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 730          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 731          *                      CRC/framing errors are only reported in this state.
 732          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 733          *                                      CRC/framing error
 734          */
 735
 736         if(stat & HSCX_INT_RPR)
 737         {
 738                 int fifo_data_len;
 739                 int error = 0;
 740                 /* always have to read the FIFO, so use a scratch buffer */
 741                 u_char scrbuf[HSCX_FIFO_LEN];
 742
 743                 if(stat & HSCX_STAT_RDO)
 744                 {
 745                         chan->stat_RDO++;
 746                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 747                         error++;
 748                 }
 749
 750                 /*
 751                  * check whether we're receiving data for an inactive B-channel
 752                  * and discard it. This appears to happen for telephony when
 753                  * both B-channels are active and one is deactivated. Since
 754                  * it is not really possible to deactivate the channel in that
 755                  * case (the ASIC seems to deactivate _both_ channels), the
 756                  * "deactivated" channel keeps receiving data which can lead
 757                  * to exhaustion of mbufs and a kernel panic.
 758                  *
 759                  * This is a hack, but it's the only solution I can think of
 760                  * without having the documentation for the ASIC.
 761                  * GJ - 28 Nov 1999
 762                  */
 763                  if (chan->state == HSCX_IDLE)
 764                  {
 765                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 766                         error++;
 767                  }
 768
 769                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 770
 771                 if(fifo_data_len == 0)
 772                         fifo_data_len = sc->sc_bfifolen;
 773
 774                 /* ALWAYS read data from HSCX fifo */
 775
 776                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 777                 chan->rxcount += fifo_data_len;
 778
 779                 /* all error conditions checked, now decide and take action */
 780
 781                 if(error == 0)
 782                 {
 783                         if(chan->in_mbuf == NULL)
 784                         {
 785                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 786                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
 787                                 chan->in_cbptr = chan->in_mbuf->m_data;
 788                                 chan->in_len = 0;
 789                         }
 790
 791                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 792                         {
 793                                 /* OK to copy the data */
 794                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 795                                 chan->in_cbptr += fifo_data_len;
 796                                 chan->in_len += fifo_data_len;
 797
 798                                 /* setup mbuf data length */
 799
 800                                 chan->in_mbuf->m_len = chan->in_len;
 801                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 802
 803                                 if(sc->sc_trace & TRACE_B_RX)
 804                                 {
 805                                         i4b_trace_hdr_t hdr;
 806                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 807                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 808                                         hdr.dir = FROM_NT;
 809                                         hdr.count = ++sc->sc_trace_bcount;
 810                                         MICROTIME(hdr.time);
 811                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 812                                 }
 813
 814                                 if (stat & HSCX_STAT_RME)
 815                                 {
 816                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 817                                   {
 818                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 819                                          activity = ACT_RX;
 820
 821                                          /* mark buffer ptr as unused */
 822
 823                                          chan->in_mbuf = NULL;
 824                                          chan->in_cbptr = NULL;
 825                                          chan->in_len = 0;
 826                                   }
 827                                   else
 828                                   {
 829                                                 chan->stat_CRC++;
 830                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 831                                           if (chan->in_mbuf != NULL)
 832                                           {
 833                                                   i4b_Bfreembuf(chan->in_mbuf);
 834                                                   chan->in_mbuf = NULL;
 835                                                   chan->in_cbptr = NULL;
 836                                                   chan->in_len = 0;
 837                                           }
 838                                   }
 839                                 }
 840                         } /* END enough space in mbuf */
 841                         else
 842                         {
 843                                  if(chan->bprot == BPROT_NONE)
 844                                  {
 845                                           /* setup mbuf data length */
 846
 847                                           chan->in_mbuf->m_len = chan->in_len;
 848                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 849
 850                                           if(sc->sc_trace & TRACE_B_RX)
 851                                           {
 852                                                         i4b_trace_hdr_t hdr;
 853                                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 854                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 855                                                         hdr.dir = FROM_NT;
 856                                                         hdr.count = ++sc->sc_trace_bcount;
 857                                                         MICROTIME(hdr.time);
 858                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 859                                                 }
 860
 861                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 862                                                  activity = ACT_RX;
 863
 864                                           /* move rx'd data to rx queue */
 865
 866                                           if(!(IF_QFULL(&chan->rx_queue)))
 867                                           {
 868                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 869                                           }
 870                                           else
 871                                           {
 872                                                 i4b_Bfreembuf(chan->in_mbuf);
 873                                           }
 874                                           /* signal upper layer that data are available */
 875                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 876
 877                                           /* alloc new buffer */
 878
 879                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 880                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 881
 882                                           /* setup new data ptr */
 883
 884                                           chan->in_cbptr = chan->in_mbuf->m_data;
 885
 886                                           /* OK to copy the data */
 887                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 888
 889                                           chan->in_cbptr += fifo_data_len;
 890                                           chan->in_len = fifo_data_len;
 891
 892                                           chan->rxcount += fifo_data_len;
 893                                         }
 894                                  else
 895                                         {
 896                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 897                                           chan->in_cbptr = chan->in_mbuf->m_data;
 898                                           chan->in_len = 0;
 899                                         }
 900                           }
 901                 } /* if(error == 0) */
 902                 else
 903                 {
 904                         /* land here for RDO */
 905                         if (chan->in_mbuf != NULL)
 906                         {
 907                                 i4b_Bfreembuf(chan->in_mbuf);
 908                                 chan->in_mbuf = NULL;
 909                                 chan->in_cbptr = NULL;
 910                                 chan->in_len = 0;
 911                         }
 912                         sc->avma1pp_txl = 0;
 913                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 914                         AVMA1PPSETCMDLONG(param);
 915                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 916                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 917                         AVMA1PPSETCMDLONG(param);
 918                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 919                 }
 920         }
 921
 922
 923         /* transmit fifo empty, new data can be written to fifo */
 924
 925         if(stat & HSCX_INT_XPR)
 926         {
 927                 /*
 928                  * for a description what is going on here, please have
 929                  * a look at isic_bchannel_start() in i4b_bchan.c !
 930                  */
 931
 932                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 933
 934                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 935                 {
 936                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 937
 938                         if(chan->out_mbuf_head == NULL)
 939                         {
 940                                 chan->state &= ~HSCX_TX_ACTIVE;
 941                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 942                         }
 943                         else
 944                         {
 945                                 chan->state |= HSCX_TX_ACTIVE;
 946                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 947                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 948                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 949
 950                                 if(sc->sc_trace & TRACE_B_TX)
 951                                 {
 952                                         i4b_trace_hdr_t hdr;
 953                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 954                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 955                                         hdr.dir = FROM_TE;
 956                                         hdr.count = ++sc->sc_trace_bcount;
 957                                         MICROTIME(hdr.time);
 958                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 959                                 }
 960
 961                                 if(chan->bprot == BPROT_NONE)
 962                                 {
 963                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 964                                                 activity = ACT_TX;
 965                                 }
 966                                 else
 967                                 {
 968                                         activity = ACT_TX;
 969                                 }
 970                         }
 971                 }
 972
 973                 avma1pp_hscx_fifo(chan, sc);
 974         }
 975
 976         /* call timeout handling routine */
 977
 978         if(activity == ACT_RX || activity == ACT_TX)
 979                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 980 }
 981
 982 /*
 983  * this is the main routine which checks each channel and then calls
 984  * the real interrupt routine as appropriate
 985  */
 986 static void
 987 avma1pp_hscx_int_handler(struct l1_softc *sc)
 988 {
 989         u_int stat;
 990
 991         /* has to be a u_int because the byte count is in the 2nd byte */
 992         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
 993         if (stat & HSCX_INT_MASK)
 994           avma1pp_hscx_intr(0, stat, sc);
 995         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
 996         if (stat & HSCX_INT_MASK)
 997           avma1pp_hscx_intr(1, stat, sc);
 998 }
 999
1000 static void
1001 avma1pp_disable(device_t dev)
1002 {
1003         struct l1_softc *sc = device_get_softc(dev);
1004         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1005         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1006
1007         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1008 }
1009
1010 static void
1011 avma1pp_intr(void *xsc)
1012 {
1013         u_char stat;
1014         struct l1_softc *sc;
1015         bus_space_handle_t bhandle;
1016         bus_space_tag_t btag;
1017
1018         sc = xsc;
1019         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1020         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1021
1022         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1023         NDBGL1(L1_H_IRQ, "stat %x", stat);
1024         /* was there an interrupt from this card ? */
1025         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1026                 return; /* no */
1027         /* interrupts are low active */
1028         if (!(stat & ASL_IRQ_TIMER))
1029           NDBGL1(L1_H_IRQ, "timer interrupt ???");
1030         if (!(stat & ASL_IRQ_HSCX))
1031         {
1032           NDBGL1(L1_H_IRQ, "HSCX");
1033                 avma1pp_hscx_int_handler(sc);
1034         }
1035         if (!(stat & ASL_IRQ_ISAC))
1036         {
1037           NDBGL1(L1_H_IRQ, "ISAC");
1038                 ifpi_isac_intr(sc);
1039         }
1040 }
1041
1042 static void
1043 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1044 {
1045         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1046         u_int param = 0;
1047
1048         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1049                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1050
1051         if (activate == 0)
1052         {
1053                 /* only deactivate if both channels are idle */
1054                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1055                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1056                 {
1057                         return;
1058                 }
1059                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1060                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1061                 AVMA1PPSETCMDLONG(param);
1062                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1063                 return;
1064         }
1065         if(chan->bprot == BPROT_RHDLC)
1066         {
1067                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1068
1069                 /* HDLC Frames, transparent mode 0 */
1070                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1071                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1072                 AVMA1PPSETCMDLONG(param);
1073                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1074                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1075                 AVMA1PPSETCMDLONG(param);
1076                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1077                 sc->avma1pp_cmd = 0;
1078         }
1079         else
1080         {
1081                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1082
1083                 /* Raw Telephony, extended transparent mode 1 */
1084                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1085                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1086                 AVMA1PPSETCMDLONG(param);
1087                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1088                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1089                 AVMA1PPSETCMDLONG(param);
1090                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1091                 sc->avma1pp_cmd = 0;
1092         }
1093 }
1094
1095 static void
1096 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1097 {
1098         struct l1_softc *sc = ifpi_scp[unit];
1099         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1100
1101         crit_enter();
1102
1103         if(activate == 0)
1104         {
1105                 /* deactivation */
1106                 chan->state = HSCX_IDLE;
1107                 avma1pp_hscx_init(sc, h_chan, activate);
1108         }
1109
1110         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1111                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1112
1113         /* general part */
1114
1115         chan->unit = sc->sc_unit;       /* unit number */
1116         chan->channel = h_chan;         /* B channel */
1117         chan->bprot = bprot;            /* B channel protocol */
1118         chan->state = HSCX_IDLE;        /* B channel state */
1119
1120         /* receiver part */
1121
1122         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1123
1124         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1125
1126         chan->rxcount = 0;              /* reset rx counter */
1127
1128         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1129
1130         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1131         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1132         chan->in_len = 0;               /* reset mbuf data len */
1133
1134         /* transmitter part */
1135
1136         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1137
1138         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1139
1140         chan->txcount = 0;              /* reset tx counter */
1141
1142         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1143
1144         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1145         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1146         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1147         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1148
1149         if(activate != 0)
1150         {
1151                 /* activation */
1152                 avma1pp_hscx_init(sc, h_chan, activate);
1153                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1154         }
1155
1156         crit_exit();
1157 }
1158
1159 static void
1160 avma1pp_bchannel_start(int unit, int h_chan)
1161 {
1162         struct l1_softc *sc = ifpi_scp[unit];
1163         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1164         int activity = -1;
1165
1166         crit_enter();
1167         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1168         {
1169                 crit_exit();
1170                 return;                         /* yes, leave */
1171         }
1172
1173         /* get next mbuf from queue */
1174
1175         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1176
1177         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1178         {
1179                 crit_exit();
1180                 return;                         /* yes, exit */
1181         }
1182
1183         /* init current mbuf values */
1184
1185         chan->out_mbuf_cur = chan->out_mbuf_head;
1186         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1187         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1188
1189         /* activity indicator for timeout handling */
1190
1191         if(chan->bprot == BPROT_NONE)
1192         {
1193                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1194                         activity = ACT_TX;
1195         }
1196         else
1197         {
1198                 activity = ACT_TX;
1199         }
1200
1201         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1202
1203         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1204         {
1205                 i4b_trace_hdr_t hdr;
1206                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1207                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1208                 hdr.dir = FROM_TE;
1209                 hdr.count = ++sc->sc_trace_bcount;
1210                 MICROTIME(hdr.time);
1211                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1212         }
1213
1214         avma1pp_hscx_fifo(chan, sc);
1215
1216         /* call timeout handling routine */
1217
1218         if(activity == ACT_RX || activity == ACT_TX)
1219                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1220
1221         crit_exit();
1222 }
1223
1224 /*---------------------------------------------------------------------------*
1225  *      return the address of isic drivers linktab
1226  *---------------------------------------------------------------------------*/
1227 static isdn_link_t *
1228 avma1pp_ret_linktab(int unit, int channel)
1229 {
1230         struct l1_softc *sc = ifpi_scp[unit];
1231         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1232
1233         return(&chan->isic_isdn_linktab);
1234 }
1235
1236 /*---------------------------------------------------------------------------*
1237  *      set the driver linktab in the b channel softc
1238  *---------------------------------------------------------------------------*/
1239 static void
1240 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1241 {
1242         struct l1_softc *sc = ifpi_scp[unit];
1243         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1244
1245         chan->isic_drvr_linktab = dlt;
1246 }
1247
1248
1249 /*---------------------------------------------------------------------------*
1250  *      initialize our local linktab
1251  *---------------------------------------------------------------------------*/
1252 static void
1253 avma1pp_init_linktab(struct l1_softc *sc)
1254 {
1255         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1256         isdn_link_t *lt = &chan->isic_isdn_linktab;
1257
1258         /* make sure the hardware driver is known to layer 4 */
1259         /* avoid overwriting if already set */
1260         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1261         {
1262                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1263                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1264         }
1265
1266         /* local setup */
1267         lt->unit = sc->sc_unit;
1268         lt->channel = HSCX_CH_A;
1269         lt->bch_config = avma1pp_bchannel_setup;
1270         lt->bch_tx_start = avma1pp_bchannel_start;
1271         lt->bch_stat = avma1pp_bchannel_stat;
1272         lt->tx_queue = &chan->tx_queue;
1273
1274         /* used by non-HDLC data transfers, i.e. telephony drivers */
1275         lt->rx_queue = &chan->rx_queue;
1276
1277         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1278         lt->rx_mbuf = &chan->in_mbuf;
1279
1280         chan = &sc->sc_chan[HSCX_CH_B];
1281         lt = &chan->isic_isdn_linktab;
1282
1283         lt->unit = sc->sc_unit;
1284         lt->channel = HSCX_CH_B;
1285         lt->bch_config = avma1pp_bchannel_setup;
1286         lt->bch_tx_start = avma1pp_bchannel_start;
1287         lt->bch_stat = avma1pp_bchannel_stat;
1288         lt->tx_queue = &chan->tx_queue;
1289
1290         /* used by non-HDLC data transfers, i.e. telephony drivers */
1291         lt->rx_queue = &chan->rx_queue;
1292
1293         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1294         lt->rx_mbuf = &chan->in_mbuf;
1295 }
1296
1297 /*
1298  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1299  */
1300 static void
1301 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1302 {
1303         struct l1_softc *sc = ifpi_scp[unit];
1304         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1305
1306         crit_enter();
1307
1308         bsp->outbytes = chan->txcount;
1309         bsp->inbytes = chan->rxcount;
1310
1311         chan->txcount = 0;
1312         chan->rxcount = 0;
1313
1314         crit_exit();
1315 }
1316
1317 /*---------------------------------------------------------------------------*
1318  *      fill HSCX fifo with data from the current mbuf
1319  *      Put this here until it can go into i4b_hscx.c
1320  *---------------------------------------------------------------------------*/
1321 static int
1322 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1323 {
1324         int len;
1325         int nextlen;
1326         int i;
1327         int cmd = 0;
1328         /* using a scratch buffer simplifies writing to the FIFO */
1329         u_char scrbuf[HSCX_FIFO_LEN];
1330
1331         len = 0;
1332
1333         /*
1334          * fill the HSCX tx fifo with data from the current mbuf. if
1335          * current mbuf holds less data than HSCX fifo length, try to
1336          * get the next mbuf from (a possible) mbuf chain. if there is
1337          * not enough data in a single mbuf or in a chain, then this
1338          * is the last mbuf and we tell the HSCX that it has to send
1339          * CRC and closing flag
1340          */
1341
1342         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1343         {
1344                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1345
1346 #ifdef NOTDEF
1347                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1348                         chan->out_mbuf_head,
1349                         chan->out_mbuf_cur,
1350                         chan->out_mbuf_cur_ptr,
1351                         chan->out_mbuf_cur_len,
1352                         len,
1353                         nextlen);
1354 #endif
1355
1356                 cmd |= HSCX_CMDR_XTF;
1357                 /* collect the data in the scratch buffer */
1358                 for (i = 0; i < nextlen; i++)
1359                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1360
1361                 len += nextlen;
1362                 chan->txcount += nextlen;
1363
1364                 chan->out_mbuf_cur_ptr += nextlen;
1365                 chan->out_mbuf_cur_len -= nextlen;
1366
1367                 if(chan->out_mbuf_cur_len == 0)
1368                 {
1369                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1370                         {
1371                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1372                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1373
1374                                 if(sc->sc_trace & TRACE_B_TX)
1375                                 {
1376                                         i4b_trace_hdr_t hdr;
1377                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
1378                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1379                                         hdr.dir = FROM_TE;
1380                                         hdr.count = ++sc->sc_trace_bcount;
1381                                         MICROTIME(hdr.time);
1382                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1383                                 }
1384                         }
1385                         else
1386                         {
1387                                 if (chan->bprot != BPROT_NONE)
1388                                         cmd |= HSCX_CMDR_XME;
1389                                 i4b_Bfreembuf(chan->out_mbuf_head);
1390                                 chan->out_mbuf_head = NULL;
1391                         }
1392                 }
1393         }
1394         /* write what we have from the scratch buf to the HSCX fifo */
1395         if (len != 0)
1396                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1397         return(cmd);
1398 }
1399
1400 /*---------------------------------------------------------------------------*
1401  *      ifpi - ISAC interrupt routine
1402  *---------------------------------------------------------------------------*/
1403 static void
1404 ifpi_isac_intr(struct l1_softc *sc)
1405 {
1406         u_char isac_irq_stat;
1407
1408         for(;;)
1409         {
1410                 /* get isac irq status */
1411                 isac_irq_stat = ISAC_READ(I_ISTA);
1412
1413                 if(isac_irq_stat)
1414                         ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1415                 else
1416                         break;
1417         }
1418
1419         ISAC_WRITE(I_MASK, 0xff);
1420
1421         DELAY(100);
1422
1423         ISAC_WRITE(I_MASK, ISAC_IMASK);
1424 }
1425
1426 /*---------------------------------------------------------------------------*
1427  *      ifpi_recover - try to recover from irq lockup
1428  *---------------------------------------------------------------------------*/
1429 void
1430 ifpi_recover(struct l1_softc *sc)
1431 {
1432         u_char byte;
1433
1434         /* get isac irq status */
1435
1436         byte = ISAC_READ(I_ISTA);
1437
1438         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1439
1440         if(byte & ISAC_ISTA_EXI)
1441                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1442
1443         if(byte & ISAC_ISTA_CISQ)
1444         {
1445                 byte = ISAC_READ(I_CIRR);
1446
1447                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1448
1449                 if(byte & ISAC_CIRR_SQC)
1450                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1451         }
1452
1453         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1454
1455         ISAC_WRITE(I_MASK, 0xff);
1456         DELAY(100);
1457         ISAC_WRITE(I_MASK, ISAC_IMASK);
1458 }
1459
1460
1461 #endif /* NIFPI > 0 */