2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.19 2003/12/20 05:52:26 dillon Exp $
33 #include <machine/smptests.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <sys/malloc.h>
43 #include <sys/memrange.h>
45 #include <sys/dkstat.h>
47 #include <sys/cons.h> /* cngetc() */
50 #include <vm/vm_param.h>
52 #include <vm/vm_kern.h>
53 #include <vm/vm_extern.h>
55 #include <vm/vm_map.h>
61 #include <machine/smp.h>
62 #include <machine/apic.h>
63 #include <machine/atomic.h>
64 #include <machine/cpufunc.h>
65 #include <machine/mpapic.h>
66 #include <machine/psl.h>
67 #include <machine/segments.h>
68 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
69 #include <machine/tss.h>
70 #include <machine/specialreg.h>
71 #include <machine/globaldata.h>
74 #include <machine/md_var.h> /* setidt() */
75 #include <i386/isa/icu.h> /* IPIs */
76 #include <i386/isa/intr_machdep.h> /* IPIs */
79 #if defined(TEST_DEFAULT_CONFIG)
80 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
82 #define MPFPS_MPFB1 mpfps->mpfb1
83 #endif /* TEST_DEFAULT_CONFIG */
85 #define WARMBOOT_TARGET 0
86 #define WARMBOOT_OFF (KERNBASE + 0x0467)
87 #define WARMBOOT_SEG (KERNBASE + 0x0469)
90 #define BIOS_BASE (0xe8000)
91 #define BIOS_SIZE (0x18000)
93 #define BIOS_BASE (0xf0000)
94 #define BIOS_SIZE (0x10000)
96 #define BIOS_COUNT (BIOS_SIZE/4)
98 #define CMOS_REG (0x70)
99 #define CMOS_DATA (0x71)
100 #define BIOS_RESET (0x0f)
101 #define BIOS_WARM (0x0a)
103 #define PROCENTRY_FLAG_EN 0x01
104 #define PROCENTRY_FLAG_BP 0x02
105 #define IOAPICENTRY_FLAG_EN 0x01
108 /* MP Floating Pointer Structure */
109 typedef struct MPFPS {
122 /* MP Configuration Table Header */
123 typedef struct MPCTH {
125 u_short base_table_length;
129 u_char product_id[12];
130 void *oem_table_pointer;
131 u_short oem_table_size;
134 u_short extended_table_length;
135 u_char extended_table_checksum;
140 typedef struct PROCENTRY {
145 u_long cpu_signature;
146 u_long feature_flags;
151 typedef struct BUSENTRY {
157 typedef struct IOAPICENTRY {
163 } *io_apic_entry_ptr;
165 typedef struct INTENTRY {
175 /* descriptions of MP basetable entries */
176 typedef struct BASETABLE_ENTRY {
183 * this code MUST be enabled here and in mpboot.s.
184 * it follows the very early stages of AP boot by placing values in CMOS ram.
185 * it NORMALLY will never be needed and thus the primitive method for enabling.
188 #if defined(CHECK_POINTS) && !defined(PC98)
189 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
190 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
192 #define CHECK_INIT(D); \
193 CHECK_WRITE(0x34, (D)); \
194 CHECK_WRITE(0x35, (D)); \
195 CHECK_WRITE(0x36, (D)); \
196 CHECK_WRITE(0x37, (D)); \
197 CHECK_WRITE(0x38, (D)); \
198 CHECK_WRITE(0x39, (D));
200 #define CHECK_PRINT(S); \
201 printf("%s: %d, %d, %d, %d, %d, %d\n", \
210 #else /* CHECK_POINTS */
212 #define CHECK_INIT(D)
213 #define CHECK_PRINT(S)
215 #endif /* CHECK_POINTS */
218 * Values to send to the POST hardware.
220 #define MP_BOOTADDRESS_POST 0x10
221 #define MP_PROBE_POST 0x11
222 #define MPTABLE_PASS1_POST 0x12
224 #define MP_START_POST 0x13
225 #define MP_ENABLE_POST 0x14
226 #define MPTABLE_PASS2_POST 0x15
228 #define START_ALL_APS_POST 0x16
229 #define INSTALL_AP_TRAMP_POST 0x17
230 #define START_AP_POST 0x18
232 #define MP_ANNOUNCE_POST 0x19
235 static int need_hyperthreading_fixup;
236 static u_int logical_cpus;
239 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
240 int current_postcode;
242 /** XXX FIXME: what system files declare these??? */
243 extern struct region_descriptor r_gdt, r_idt;
245 int bsp_apic_ready = 0; /* flags useability of BSP apic */
246 int mp_naps; /* # of Applications processors */
247 int mp_nbusses; /* # of busses */
248 int mp_napics; /* # of IO APICs */
249 int boot_cpu_id; /* designated BSP */
250 vm_offset_t cpu_apic_address;
251 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
254 u_int32_t cpu_apic_versions[MAXCPU];
255 u_int32_t *io_apic_versions;
257 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
259 #ifdef APIC_INTR_REORDER
261 volatile int *location;
263 } apic_isrbit_location[32];
268 * APIC ID logical/physical mapping structures.
269 * We oversize these to simplify boot-time config.
271 int cpu_num_to_apic_id[NAPICID];
272 int io_num_to_apic_id[NAPICID];
273 int apic_id_to_logical[NAPICID];
276 /* Bitmap of all available CPUs */
279 /* AP uses this during bootstrap. Do not staticize. */
283 /* Hotwire a 0->4MB V==P mapping */
284 extern pt_entry_t *KPTphys;
286 /* SMP page table page */
287 extern pt_entry_t *SMPpt;
289 struct pcb stoppcbs[MAXCPU];
291 int smp_started; /* has the system started? */
294 * Local data and functions.
297 static int mp_capable;
298 static u_int boot_address;
299 static u_int base_memory;
301 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
302 static mpfps_t mpfps;
303 static int search_for_sig(u_int32_t target, int count);
304 static void mp_enable(u_int boot_addr);
307 static void mptable_hyperthread_fixup(u_int id_mask);
309 static void mptable_pass1(void);
310 static int mptable_pass2(void);
311 static void default_mp_table(int type);
312 static void fix_mp_table(void);
313 static void setup_apic_irq_mapping(void);
314 static int start_all_aps(u_int boot_addr);
315 static void install_ap_tramp(u_int boot_addr);
316 static int start_ap(int logicalCpu, u_int boot_addr);
317 static int apic_int_is_bus_type(int intr, int bus_type);
320 * Calculate usable address in base memory for AP trampoline code.
323 mp_bootaddress(u_int basemem)
325 POSTCODE(MP_BOOTADDRESS_POST);
327 base_memory = basemem * 1024; /* convert to bytes */
329 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
330 if ((base_memory - boot_address) < bootMP_size)
331 boot_address -= 4096; /* not enough, lower by 4k */
338 * Look for an Intel MP spec table (ie, SMP capable hardware).
347 POSTCODE(MP_PROBE_POST);
349 /* see if EBDA exists */
350 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
351 /* search first 1K of EBDA */
352 target = (u_int32_t) (segment << 4);
353 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
356 /* last 1K of base memory, effective 'top of base' passed in */
357 target = (u_int32_t) (base_memory - 0x400);
358 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
362 /* search the BIOS */
363 target = (u_int32_t) BIOS_BASE;
364 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
373 /* calculate needed resources */
377 /* flag fact that we are running multiple processors */
384 * Startup the SMP processors.
389 POSTCODE(MP_START_POST);
391 /* look for MP capable motherboard */
393 mp_enable(boot_address);
395 panic("MP hardware not found!");
400 * Print various information about the SMP system hardware and setup.
407 POSTCODE(MP_ANNOUNCE_POST);
409 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
410 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
411 printf(", version: 0x%08x", cpu_apic_versions[0]);
412 printf(", at 0x%08x\n", cpu_apic_address);
413 for (x = 1; x <= mp_naps; ++x) {
414 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
415 printf(", version: 0x%08x", cpu_apic_versions[x]);
416 printf(", at 0x%08x\n", cpu_apic_address);
420 for (x = 0; x < mp_napics; ++x) {
421 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
422 printf(", version: 0x%08x", io_apic_versions[x]);
423 printf(", at 0x%08x\n", io_apic_address[x]);
426 printf(" Warning: APIC I/O disabled\n");
431 * AP cpu's call this to sync up protected mode.
437 int x, myid = bootAP;
439 struct mdglobaldata *md;
441 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[myid];
442 gdt_segs[GPROC0_SEL].ssd_base =
443 (int) &CPU_prvspace[myid].mdglobaldata.gd_common_tss;
444 CPU_prvspace[myid].mdglobaldata.mi.gd_prvspace = &CPU_prvspace[myid];
446 for (x = 0; x < NGDT; x++) {
447 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
450 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
451 r_gdt.rd_base = (int) &gdt[myid * NGDT];
452 lgdt(&r_gdt); /* does magic intra-segment return */
457 mdcpu->gd_currentldt = _default_ldt;
459 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
460 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
464 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
465 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
466 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
467 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
468 md->gd_common_tssd = *md->gd_tss_gdt;
472 * Set to a known state:
473 * Set by mpboot.s: CR0_PG, CR0_PE
474 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
477 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
486 * Final configuration of the BSP's local APIC:
487 * - disable 'pic mode'.
488 * - disable 'virtual wire mode'.
492 bsp_apic_configure(void)
497 /* leave 'pic mode' if necessary */
499 outb(0x22, 0x70); /* select IMCR */
500 byte = inb(0x23); /* current contents */
501 byte |= 0x01; /* mask external INTR */
502 outb(0x23, byte); /* disconnect 8259s/NMI */
505 /* mask lint0 (the 8259 'virtual wire' connection) */
506 temp = lapic.lvt_lint0;
507 temp |= APIC_LVT_M; /* set the mask */
508 lapic.lvt_lint0 = temp;
510 /* setup lint1 to handle NMI */
511 temp = lapic.lvt_lint1;
512 temp &= ~APIC_LVT_M; /* clear the mask */
513 lapic.lvt_lint1 = temp;
516 apic_dump("bsp_apic_configure()");
521 /*******************************************************************
522 * local functions and data
526 * start the SMP system
529 mp_enable(u_int boot_addr)
537 POSTCODE(MP_ENABLE_POST);
539 /* turn on 4MB of V == P addressing so we can get to MP table */
540 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
543 /* examine the MP table for needed info, uses physical addresses */
549 /* can't process default configs till the CPU APIC is pmapped */
553 /* post scan cleanup */
555 setup_apic_irq_mapping();
559 /* fill the LOGICAL io_apic_versions table */
560 for (apic = 0; apic < mp_napics; ++apic) {
561 ux = io_apic_read(apic, IOAPIC_VER);
562 io_apic_versions[apic] = ux;
563 io_apic_set_id(apic, IO_TO_ID(apic));
566 /* program each IO APIC in the system */
567 for (apic = 0; apic < mp_napics; ++apic)
568 if (io_apic_setup(apic) < 0)
569 panic("IO APIC setup failure");
571 /* install a 'Spurious INTerrupt' vector */
572 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
575 /* install an inter-CPU IPI for TLB invalidation */
576 setidt(XINVLTLB_OFFSET, Xinvltlb,
577 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
581 /* install an inter-CPU IPI for reading processor state */
582 setidt(XCPUCHECKSTATE_OFFSET, Xcpucheckstate,
583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
587 /* install an inter-CPU IPI for IPIQ messaging */
588 setidt(XIPIQ_OFFSET, Xipiq,
589 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
591 /* install an inter-CPU IPI for all-CPU rendezvous */
592 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
593 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596 /* install an inter-CPU IPI for forcing an additional software trap */
597 setidt(XCPUAST_OFFSET, Xcpuast,
598 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
600 /* install an inter-CPU IPI for interrupt forwarding */
601 setidt(XFORWARD_IRQ_OFFSET, Xforward_irq,
602 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
605 /* install an inter-CPU IPI for CPU stop/restart */
606 setidt(XCPUSTOP_OFFSET, Xcpustop,
607 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
609 #if defined(TEST_TEST1)
610 /* install a "fake hardware INTerrupt" vector */
611 setidt(XTEST1_OFFSET, Xtest1,
612 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
613 #endif /** TEST_TEST1 */
617 /* start each Application Processor */
618 start_all_aps(boot_addr);
623 * look for the MP spec signature
626 /* string defined by the Intel MP Spec as identifying the MP table */
627 #define MP_SIG 0x5f504d5f /* _MP_ */
628 #define NEXT(X) ((X) += 4)
630 search_for_sig(u_int32_t target, int count)
633 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
635 for (x = 0; x < count; NEXT(x))
636 if (addr[x] == MP_SIG)
637 /* make array index a byte index */
638 return (target + (x * sizeof(u_int32_t)));
644 static basetable_entry basetable_entry_types[] =
646 {0, 20, "Processor"},
653 typedef struct BUSDATA {
655 enum busTypes bus_type;
658 typedef struct INTDATA {
668 typedef struct BUSTYPENAME {
673 static bus_type_name bus_type_table[] =
679 {UNKNOWN_BUSTYPE, "---"},
682 {UNKNOWN_BUSTYPE, "---"},
683 {UNKNOWN_BUSTYPE, "---"},
684 {UNKNOWN_BUSTYPE, "---"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"}
695 /* from MP spec v1.4, table 5-1 */
696 static int default_data[7][5] =
698 /* nbus, id0, type0, id1, type1 */
699 {1, 0, ISA, 255, 255},
700 {1, 0, EISA, 255, 255},
701 {1, 0, EISA, 255, 255},
702 {1, 0, MCA, 255, 255},
704 {2, 0, EISA, 1, PCI},
710 static bus_datum *bus_data;
712 /* the IO INT data, one entry per possible APIC INTerrupt */
713 static io_int *io_apic_ints;
717 static int processor_entry (proc_entry_ptr entry, int cpu);
718 static int bus_entry (bus_entry_ptr entry, int bus);
719 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
720 static int int_entry (int_entry_ptr entry, int intr);
721 static int lookup_bus_type (char *name);
725 * 1st pass on motherboard's Intel MP specification table.
731 * cpu_apic_address (common to all CPUs)
751 POSTCODE(MPTABLE_PASS1_POST);
753 /* clear various tables */
754 for (x = 0; x < NAPICID; ++x) {
755 io_apic_address[x] = ~0; /* IO APIC address table */
758 /* init everything to empty */
767 /* check for use of 'default' configuration */
768 if (MPFPS_MPFB1 != 0) {
769 /* use default addresses */
770 cpu_apic_address = DEFAULT_APIC_BASE;
771 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
773 /* fill in with defaults */
774 mp_naps = 2; /* includes BSP */
775 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
782 if ((cth = mpfps->pap) == 0)
783 panic("MP Configuration Table Header MISSING!");
785 cpu_apic_address = (vm_offset_t) cth->apic_address;
787 /* walk the table, recording info of interest */
788 totalSize = cth->base_table_length - sizeof(struct MPCTH);
789 position = (u_char *) cth + sizeof(struct MPCTH);
790 count = cth->entry_count;
793 switch (type = *(u_char *) position) {
794 case 0: /* processor_entry */
795 if (((proc_entry_ptr)position)->cpu_flags
796 & PROCENTRY_FLAG_EN) {
800 ((proc_entry_ptr)position)->apic_id;
804 case 1: /* bus_entry */
807 case 2: /* io_apic_entry */
808 if (((io_apic_entry_ptr)position)->apic_flags
809 & IOAPICENTRY_FLAG_EN)
810 io_apic_address[mp_napics++] =
811 (vm_offset_t)((io_apic_entry_ptr)
812 position)->apic_address;
814 case 3: /* int_entry */
817 case 4: /* int_entry */
820 panic("mpfps Base Table HOSED!");
824 totalSize -= basetable_entry_types[type].length;
825 (u_char*)position += basetable_entry_types[type].length;
829 /* qualify the numbers */
830 if (mp_naps > MAXCPU) {
831 printf("Warning: only using %d of %d available CPUs!\n",
837 /* See if we need to fixup HT logical CPUs. */
838 mptable_hyperthread_fixup(id_mask);
843 * This is also used as a counter while starting the APs.
847 --mp_naps; /* subtract the BSP */
852 * 2nd pass on motherboard's Intel MP specification table.
856 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
857 * CPU_TO_ID(N), logical CPU to APIC ID table
858 * IO_TO_ID(N), logical IO to APIC ID table
866 struct PROCENTRY proc;
874 int apic, bus, cpu, intr;
878 POSTCODE(MPTABLE_PASS2_POST);
881 /* Initialize fake proc entry for use with HT fixup. */
882 bzero(&proc, sizeof(proc));
884 proc.cpu_flags = PROCENTRY_FLAG_EN;
887 pgeflag = 0; /* XXX - Not used under SMP yet. */
889 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
891 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
893 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
895 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
898 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
900 for (i = 0; i < mp_napics; i++) {
901 for (j = 0; j < mp_napics; j++) {
902 /* same page frame as a previous IO apic? */
903 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
904 (io_apic_address[i] & PG_FRAME)) {
905 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
906 + (NPTEPG-2-j) * PAGE_SIZE
907 + (io_apic_address[i] & PAGE_MASK));
910 /* use this slot if available */
911 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
912 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
913 pgeflag | (io_apic_address[i] & PG_FRAME));
914 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
915 + (NPTEPG-2-j) * PAGE_SIZE
916 + (io_apic_address[i] & PAGE_MASK));
922 /* clear various tables */
923 for (x = 0; x < NAPICID; ++x) {
924 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
925 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
926 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
929 /* clear bus data table */
930 for (x = 0; x < mp_nbusses; ++x)
931 bus_data[x].bus_id = 0xff;
933 /* clear IO APIC INT table */
934 for (x = 0; x < (nintrs + 1); ++x) {
935 io_apic_ints[x].int_type = 0xff;
936 io_apic_ints[x].int_vector = 0xff;
939 /* setup the cpu/apic mapping arrays */
942 /* record whether PIC or virtual-wire mode */
943 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
945 /* check for use of 'default' configuration */
946 if (MPFPS_MPFB1 != 0)
947 return MPFPS_MPFB1; /* return default configuration type */
949 if ((cth = mpfps->pap) == 0)
950 panic("MP Configuration Table Header MISSING!");
952 /* walk the table, recording info of interest */
953 totalSize = cth->base_table_length - sizeof(struct MPCTH);
954 position = (u_char *) cth + sizeof(struct MPCTH);
955 count = cth->entry_count;
956 apic = bus = intr = 0;
957 cpu = 1; /* pre-count the BSP */
960 switch (type = *(u_char *) position) {
962 if (processor_entry(position, cpu))
966 if (need_hyperthreading_fixup) {
968 * Create fake mptable processor entries
969 * and feed them to processor_entry() to
970 * enumerate the logical CPUs.
972 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
973 for (i = 1; i < logical_cpus; i++) {
975 (void)processor_entry(&proc, cpu);
982 if (bus_entry(position, bus))
986 if (io_apic_entry(position, apic))
990 if (int_entry(position, intr))
994 /* int_entry(position); */
997 panic("mpfps Base Table HOSED!");
1001 totalSize -= basetable_entry_types[type].length;
1002 (u_char *) position += basetable_entry_types[type].length;
1005 if (boot_cpu_id == -1)
1006 panic("NO BSP found!");
1008 /* report fact that its NOT a default configuration */
1014 * Check if we should perform a hyperthreading "fix-up" to
1015 * enumerate any logical CPU's that aren't already listed
1018 * XXX: We assume that all of the physical CPUs in the
1019 * system have the same number of logical CPUs.
1021 * XXX: We assume that APIC ID's are allocated such that
1022 * the APIC ID's for a physical processor are aligned
1023 * with the number of logical CPU's in the processor.
1026 mptable_hyperthread_fixup(u_int id_mask)
1030 /* Nothing to do if there is no HTT support. */
1031 if ((cpu_feature & CPUID_HTT) == 0)
1033 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1034 if (logical_cpus <= 1)
1038 * For each APIC ID of a CPU that is set in the mask,
1039 * scan the other candidate APIC ID's for this
1040 * physical processor. If any of those ID's are
1041 * already in the table, then kill the fixup.
1043 for (id = 0; id <= MAXCPU; id++) {
1044 if ((id_mask & 1 << id) == 0)
1046 /* First, make sure we are on a logical_cpus boundary. */
1047 if (id % logical_cpus != 0)
1049 for (i = id + 1; i < id + logical_cpus; i++)
1050 if ((id_mask & 1 << i) != 0)
1055 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1056 * mp_naps right now.
1058 need_hyperthreading_fixup = 1;
1059 mp_naps *= logical_cpus;
1064 assign_apic_irq(int apic, int intpin, int irq)
1068 if (int_to_apicintpin[irq].ioapic != -1)
1069 panic("assign_apic_irq: inconsistent table");
1071 int_to_apicintpin[irq].ioapic = apic;
1072 int_to_apicintpin[irq].int_pin = intpin;
1073 int_to_apicintpin[irq].apic_address = ioapic[apic];
1074 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1076 for (x = 0; x < nintrs; x++) {
1077 if ((io_apic_ints[x].int_type == 0 ||
1078 io_apic_ints[x].int_type == 3) &&
1079 io_apic_ints[x].int_vector == 0xff &&
1080 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1081 io_apic_ints[x].dst_apic_int == intpin)
1082 io_apic_ints[x].int_vector = irq;
1087 revoke_apic_irq(int irq)
1093 if (int_to_apicintpin[irq].ioapic == -1)
1094 panic("revoke_apic_irq: inconsistent table");
1096 oldapic = int_to_apicintpin[irq].ioapic;
1097 oldintpin = int_to_apicintpin[irq].int_pin;
1099 int_to_apicintpin[irq].ioapic = -1;
1100 int_to_apicintpin[irq].int_pin = 0;
1101 int_to_apicintpin[irq].apic_address = NULL;
1102 int_to_apicintpin[irq].redirindex = 0;
1104 for (x = 0; x < nintrs; x++) {
1105 if ((io_apic_ints[x].int_type == 0 ||
1106 io_apic_ints[x].int_type == 3) &&
1107 io_apic_ints[x].int_vector != 0xff &&
1108 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1109 io_apic_ints[x].dst_apic_int == oldintpin)
1110 io_apic_ints[x].int_vector = 0xff;
1116 allocate_apic_irq(int intr)
1122 if (io_apic_ints[intr].int_vector != 0xff)
1123 return; /* Interrupt handler already assigned */
1125 if (io_apic_ints[intr].int_type != 0 &&
1126 (io_apic_ints[intr].int_type != 3 ||
1127 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1128 io_apic_ints[intr].dst_apic_int == 0)))
1129 return; /* Not INT or ExtInt on != (0, 0) */
1132 while (irq < APIC_INTMAPSIZE &&
1133 int_to_apicintpin[irq].ioapic != -1)
1136 if (irq >= APIC_INTMAPSIZE)
1137 return; /* No free interrupt handlers */
1139 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1140 intpin = io_apic_ints[intr].dst_apic_int;
1142 assign_apic_irq(apic, intpin, irq);
1143 io_apic_setup_intpin(apic, intpin);
1148 swap_apic_id(int apic, int oldid, int newid)
1155 return; /* Nothing to do */
1157 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1158 apic, oldid, newid);
1160 /* Swap physical APIC IDs in interrupt entries */
1161 for (x = 0; x < nintrs; x++) {
1162 if (io_apic_ints[x].dst_apic_id == oldid)
1163 io_apic_ints[x].dst_apic_id = newid;
1164 else if (io_apic_ints[x].dst_apic_id == newid)
1165 io_apic_ints[x].dst_apic_id = oldid;
1168 /* Swap physical APIC IDs in IO_TO_ID mappings */
1169 for (oapic = 0; oapic < mp_napics; oapic++)
1170 if (IO_TO_ID(oapic) == newid)
1173 if (oapic < mp_napics) {
1174 printf("Changing APIC ID for IO APIC #%d from "
1175 "%d to %d in MP table\n",
1176 oapic, newid, oldid);
1177 IO_TO_ID(oapic) = oldid;
1179 IO_TO_ID(apic) = newid;
1184 fix_id_to_io_mapping(void)
1188 for (x = 0; x < NAPICID; x++)
1191 for (x = 0; x <= mp_naps; x++)
1192 if (CPU_TO_ID(x) < NAPICID)
1193 ID_TO_IO(CPU_TO_ID(x)) = x;
1195 for (x = 0; x < mp_napics; x++)
1196 if (IO_TO_ID(x) < NAPICID)
1197 ID_TO_IO(IO_TO_ID(x)) = x;
1202 first_free_apic_id(void)
1206 for (freeid = 0; freeid < NAPICID; freeid++) {
1207 for (x = 0; x <= mp_naps; x++)
1208 if (CPU_TO_ID(x) == freeid)
1212 for (x = 0; x < mp_napics; x++)
1213 if (IO_TO_ID(x) == freeid)
1224 io_apic_id_acceptable(int apic, int id)
1226 int cpu; /* Logical CPU number */
1227 int oapic; /* Logical IO APIC number for other IO APIC */
1230 return 0; /* Out of range */
1232 for (cpu = 0; cpu <= mp_naps; cpu++)
1233 if (CPU_TO_ID(cpu) == id)
1234 return 0; /* Conflict with CPU */
1236 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1237 if (IO_TO_ID(oapic) == id)
1238 return 0; /* Conflict with other APIC */
1240 return 1; /* ID is acceptable for IO APIC */
1245 * parse an Intel MP specification table
1252 int bus_0 = 0; /* Stop GCC warning */
1253 int bus_pci = 0; /* Stop GCC warning */
1255 int apic; /* IO APIC unit number */
1256 int freeid; /* Free physical APIC ID */
1257 int physid; /* Current physical IO APIC ID */
1260 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1261 * did it wrong. The MP spec says that when more than 1 PCI bus
1262 * exists the BIOS must begin with bus entries for the PCI bus and use
1263 * actual PCI bus numbering. This implies that when only 1 PCI bus
1264 * exists the BIOS can choose to ignore this ordering, and indeed many
1265 * MP motherboards do ignore it. This causes a problem when the PCI
1266 * sub-system makes requests of the MP sub-system based on PCI bus
1267 * numbers. So here we look for the situation and renumber the
1268 * busses and associated INTs in an effort to "make it right".
1271 /* find bus 0, PCI bus, count the number of PCI busses */
1272 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1273 if (bus_data[x].bus_id == 0) {
1276 if (bus_data[x].bus_type == PCI) {
1282 * bus_0 == slot of bus with ID of 0
1283 * bus_pci == slot of last PCI bus encountered
1286 /* check the 1 PCI bus case for sanity */
1287 /* if it is number 0 all is well */
1288 if (num_pci_bus == 1 &&
1289 bus_data[bus_pci].bus_id != 0) {
1291 /* mis-numbered, swap with whichever bus uses slot 0 */
1293 /* swap the bus entry types */
1294 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1295 bus_data[bus_0].bus_type = PCI;
1297 /* swap each relavant INTerrupt entry */
1298 id = bus_data[bus_pci].bus_id;
1299 for (x = 0; x < nintrs; ++x) {
1300 if (io_apic_ints[x].src_bus_id == id) {
1301 io_apic_ints[x].src_bus_id = 0;
1303 else if (io_apic_ints[x].src_bus_id == 0) {
1304 io_apic_ints[x].src_bus_id = id;
1309 /* Assign IO APIC IDs.
1311 * First try the existing ID. If a conflict is detected, try
1312 * the ID in the MP table. If a conflict is still detected, find
1315 * We cannot use the ID_TO_IO table before all conflicts has been
1316 * resolved and the table has been corrected.
1318 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1320 /* First try to use the value set by the BIOS */
1321 physid = io_apic_get_id(apic);
1322 if (io_apic_id_acceptable(apic, physid)) {
1323 if (IO_TO_ID(apic) != physid)
1324 swap_apic_id(apic, IO_TO_ID(apic), physid);
1328 /* Then check if the value in the MP table is acceptable */
1329 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1332 /* Last resort, find a free APIC ID and use it */
1333 freeid = first_free_apic_id();
1334 if (freeid >= NAPICID)
1335 panic("No free physical APIC IDs found");
1337 if (io_apic_id_acceptable(apic, freeid)) {
1338 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1341 panic("Free physical APIC ID not usable");
1343 fix_id_to_io_mapping();
1345 /* detect and fix broken Compaq MP table */
1346 if (apic_int_type(0, 0) == -1) {
1347 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1348 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1349 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1350 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1351 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1352 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1358 /* Assign low level interrupt handlers */
1360 setup_apic_irq_mapping(void)
1366 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1367 int_to_apicintpin[x].ioapic = -1;
1368 int_to_apicintpin[x].int_pin = 0;
1369 int_to_apicintpin[x].apic_address = NULL;
1370 int_to_apicintpin[x].redirindex = 0;
1373 /* First assign ISA/EISA interrupts */
1374 for (x = 0; x < nintrs; x++) {
1375 int_vector = io_apic_ints[x].src_bus_irq;
1376 if (int_vector < APIC_INTMAPSIZE &&
1377 io_apic_ints[x].int_vector == 0xff &&
1378 int_to_apicintpin[int_vector].ioapic == -1 &&
1379 (apic_int_is_bus_type(x, ISA) ||
1380 apic_int_is_bus_type(x, EISA)) &&
1381 io_apic_ints[x].int_type == 0) {
1382 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1383 io_apic_ints[x].dst_apic_int,
1388 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1389 for (x = 0; x < nintrs; x++) {
1390 if (io_apic_ints[x].dst_apic_int == 0 &&
1391 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1392 io_apic_ints[x].int_vector == 0xff &&
1393 int_to_apicintpin[0].ioapic == -1 &&
1394 io_apic_ints[x].int_type == 3) {
1395 assign_apic_irq(0, 0, 0);
1399 /* PCI interrupt assignment is deferred */
1404 processor_entry(proc_entry_ptr entry, int cpu)
1406 /* check for usability */
1407 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1410 if(entry->apic_id >= NAPICID)
1411 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1412 /* check for BSP flag */
1413 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1414 boot_cpu_id = entry->apic_id;
1415 CPU_TO_ID(0) = entry->apic_id;
1416 ID_TO_CPU(entry->apic_id) = 0;
1417 return 0; /* its already been counted */
1420 /* add another AP to list, if less than max number of CPUs */
1421 else if (cpu < MAXCPU) {
1422 CPU_TO_ID(cpu) = entry->apic_id;
1423 ID_TO_CPU(entry->apic_id) = cpu;
1432 bus_entry(bus_entry_ptr entry, int bus)
1437 /* encode the name into an index */
1438 for (x = 0; x < 6; ++x) {
1439 if ((c = entry->bus_type[x]) == ' ')
1445 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1446 panic("unknown bus type: '%s'", name);
1448 bus_data[bus].bus_id = entry->bus_id;
1449 bus_data[bus].bus_type = x;
1456 io_apic_entry(io_apic_entry_ptr entry, int apic)
1458 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1461 IO_TO_ID(apic) = entry->apic_id;
1462 if (entry->apic_id < NAPICID)
1463 ID_TO_IO(entry->apic_id) = apic;
1470 lookup_bus_type(char *name)
1474 for (x = 0; x < MAX_BUSTYPE; ++x)
1475 if (strcmp(bus_type_table[x].name, name) == 0)
1476 return bus_type_table[x].type;
1478 return UNKNOWN_BUSTYPE;
1483 int_entry(int_entry_ptr entry, int intr)
1487 io_apic_ints[intr].int_type = entry->int_type;
1488 io_apic_ints[intr].int_flags = entry->int_flags;
1489 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1490 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1491 if (entry->dst_apic_id == 255) {
1492 /* This signal goes to all IO APICS. Select an IO APIC
1493 with sufficient number of interrupt pins */
1494 for (apic = 0; apic < mp_napics; apic++)
1495 if (((io_apic_read(apic, IOAPIC_VER) &
1496 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1497 entry->dst_apic_int)
1499 if (apic < mp_napics)
1500 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1502 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1504 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1505 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1512 apic_int_is_bus_type(int intr, int bus_type)
1516 for (bus = 0; bus < mp_nbusses; ++bus)
1517 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1518 && ((int) bus_data[bus].bus_type == bus_type))
1526 * Given a traditional ISA INT mask, return an APIC mask.
1529 isa_apic_mask(u_int isa_mask)
1534 #if defined(SKIP_IRQ15_REDIRECT)
1535 if (isa_mask == (1 << 15)) {
1536 printf("skipping ISA IRQ15 redirect\n");
1539 #endif /* SKIP_IRQ15_REDIRECT */
1541 isa_irq = ffs(isa_mask); /* find its bit position */
1542 if (isa_irq == 0) /* doesn't exist */
1544 --isa_irq; /* make it zero based */
1546 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1550 return (1 << apic_pin); /* convert pin# to a mask */
1555 * Determine which APIC pin an ISA/EISA INT is attached to.
1557 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1558 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1559 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1560 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1562 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1564 isa_apic_irq(int isa_irq)
1568 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1569 if (INTTYPE(intr) == 0) { /* standard INT */
1570 if (SRCBUSIRQ(intr) == isa_irq) {
1571 if (apic_int_is_bus_type(intr, ISA) ||
1572 apic_int_is_bus_type(intr, EISA)) {
1573 if (INTIRQ(intr) == 0xff)
1574 return -1; /* unassigned */
1575 return INTIRQ(intr); /* found */
1580 return -1; /* NOT found */
1585 * Determine which APIC pin a PCI INT is attached to.
1587 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1588 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1589 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1591 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1595 --pciInt; /* zero based */
1597 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1598 if ((INTTYPE(intr) == 0) /* standard INT */
1599 && (SRCBUSID(intr) == pciBus)
1600 && (SRCBUSDEVICE(intr) == pciDevice)
1601 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1602 if (apic_int_is_bus_type(intr, PCI)) {
1603 if (INTIRQ(intr) == 0xff)
1604 allocate_apic_irq(intr);
1605 if (INTIRQ(intr) == 0xff)
1606 return -1; /* unassigned */
1607 return INTIRQ(intr); /* exact match */
1610 return -1; /* NOT found */
1614 next_apic_irq(int irq)
1621 for (intr = 0; intr < nintrs; intr++) {
1622 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1624 bus = SRCBUSID(intr);
1625 bustype = apic_bus_type(bus);
1626 if (bustype != ISA &&
1632 if (intr >= nintrs) {
1635 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1636 if (INTTYPE(ointr) != 0)
1638 if (bus != SRCBUSID(ointr))
1640 if (bustype == PCI) {
1641 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1643 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1646 if (bustype == ISA || bustype == EISA) {
1647 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1650 if (INTPIN(intr) == INTPIN(ointr))
1654 if (ointr >= nintrs) {
1657 return INTIRQ(ointr);
1671 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1674 * Exactly what this means is unclear at this point. It is a solution
1675 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1676 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1677 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1681 undirect_isa_irq(int rirq)
1685 printf("Freeing redirected ISA irq %d.\n", rirq);
1686 /** FIXME: tickle the MB redirector chip */
1690 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1697 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1700 undirect_pci_irq(int rirq)
1704 printf("Freeing redirected PCI irq %d.\n", rirq);
1706 /** FIXME: tickle the MB redirector chip */
1710 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1718 * given a bus ID, return:
1719 * the bus type if found
1723 apic_bus_type(int id)
1727 for (x = 0; x < mp_nbusses; ++x)
1728 if (bus_data[x].bus_id == id)
1729 return bus_data[x].bus_type;
1736 * given a LOGICAL APIC# and pin#, return:
1737 * the associated src bus ID if found
1741 apic_src_bus_id(int apic, int pin)
1745 /* search each of the possible INTerrupt sources */
1746 for (x = 0; x < nintrs; ++x)
1747 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1748 (pin == io_apic_ints[x].dst_apic_int))
1749 return (io_apic_ints[x].src_bus_id);
1751 return -1; /* NOT found */
1756 * given a LOGICAL APIC# and pin#, return:
1757 * the associated src bus IRQ if found
1761 apic_src_bus_irq(int apic, int pin)
1765 for (x = 0; x < nintrs; x++)
1766 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1767 (pin == io_apic_ints[x].dst_apic_int))
1768 return (io_apic_ints[x].src_bus_irq);
1770 return -1; /* NOT found */
1775 * given a LOGICAL APIC# and pin#, return:
1776 * the associated INTerrupt type if found
1780 apic_int_type(int apic, int pin)
1784 /* search each of the possible INTerrupt sources */
1785 for (x = 0; x < nintrs; ++x)
1786 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1787 (pin == io_apic_ints[x].dst_apic_int))
1788 return (io_apic_ints[x].int_type);
1790 return -1; /* NOT found */
1794 apic_irq(int apic, int pin)
1799 for (x = 0; x < nintrs; ++x)
1800 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1801 (pin == io_apic_ints[x].dst_apic_int)) {
1802 res = io_apic_ints[x].int_vector;
1805 if (apic != int_to_apicintpin[res].ioapic)
1806 panic("apic_irq: inconsistent table");
1807 if (pin != int_to_apicintpin[res].int_pin)
1808 panic("apic_irq inconsistent table (2)");
1816 * given a LOGICAL APIC# and pin#, return:
1817 * the associated trigger mode if found
1821 apic_trigger(int apic, int pin)
1825 /* search each of the possible INTerrupt sources */
1826 for (x = 0; x < nintrs; ++x)
1827 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1828 (pin == io_apic_ints[x].dst_apic_int))
1829 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1831 return -1; /* NOT found */
1836 * given a LOGICAL APIC# and pin#, return:
1837 * the associated 'active' level if found
1841 apic_polarity(int apic, int pin)
1845 /* search each of the possible INTerrupt sources */
1846 for (x = 0; x < nintrs; ++x)
1847 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1848 (pin == io_apic_ints[x].dst_apic_int))
1849 return (io_apic_ints[x].int_flags & 0x03);
1851 return -1; /* NOT found */
1856 * set data according to MP defaults
1857 * FIXME: probably not complete yet...
1860 default_mp_table(int type)
1863 #if defined(APIC_IO)
1866 #endif /* APIC_IO */
1869 printf(" MP default config type: %d\n", type);
1872 printf(" bus: ISA, APIC: 82489DX\n");
1875 printf(" bus: EISA, APIC: 82489DX\n");
1878 printf(" bus: EISA, APIC: 82489DX\n");
1881 printf(" bus: MCA, APIC: 82489DX\n");
1884 printf(" bus: ISA+PCI, APIC: Integrated\n");
1887 printf(" bus: EISA+PCI, APIC: Integrated\n");
1890 printf(" bus: MCA+PCI, APIC: Integrated\n");
1893 printf(" future type\n");
1899 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1900 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1903 CPU_TO_ID(0) = boot_cpu_id;
1904 ID_TO_CPU(boot_cpu_id) = 0;
1906 /* one and only AP */
1907 CPU_TO_ID(1) = ap_cpu_id;
1908 ID_TO_CPU(ap_cpu_id) = 1;
1910 #if defined(APIC_IO)
1911 /* one and only IO APIC */
1912 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1915 * sanity check, refer to MP spec section 3.6.6, last paragraph
1916 * necessary as some hardware isn't properly setting up the IO APIC
1918 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1919 if (io_apic_id != 2) {
1921 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1922 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1923 io_apic_set_id(0, 2);
1926 IO_TO_ID(0) = io_apic_id;
1927 ID_TO_IO(io_apic_id) = 0;
1928 #endif /* APIC_IO */
1930 /* fill out bus entries */
1939 bus_data[0].bus_id = default_data[type - 1][1];
1940 bus_data[0].bus_type = default_data[type - 1][2];
1941 bus_data[1].bus_id = default_data[type - 1][3];
1942 bus_data[1].bus_type = default_data[type - 1][4];
1945 /* case 4: case 7: MCA NOT supported */
1946 default: /* illegal/reserved */
1947 panic("BAD default MP config: %d", type);
1951 #if defined(APIC_IO)
1952 /* general cases from MP v1.4, table 5-2 */
1953 for (pin = 0; pin < 16; ++pin) {
1954 io_apic_ints[pin].int_type = 0;
1955 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1956 io_apic_ints[pin].src_bus_id = 0;
1957 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1958 io_apic_ints[pin].dst_apic_id = io_apic_id;
1959 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1962 /* special cases from MP v1.4, table 5-2 */
1964 io_apic_ints[2].int_type = 0xff; /* N/C */
1965 io_apic_ints[13].int_type = 0xff; /* N/C */
1966 #if !defined(APIC_MIXED_MODE)
1968 panic("sorry, can't support type 2 default yet");
1969 #endif /* APIC_MIXED_MODE */
1972 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1975 io_apic_ints[0].int_type = 0xff; /* N/C */
1977 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1978 #endif /* APIC_IO */
1982 * start each AP in our list
1985 start_all_aps(u_int boot_addr)
1988 u_char mpbiosreason;
1989 u_long mpbioswarmvec;
1990 struct mdglobaldata *gd;
1994 POSTCODE(START_ALL_APS_POST);
1996 /* initialize BSP's local APIC */
2000 /* install the AP 1st level boot code */
2001 install_ap_tramp(boot_addr);
2004 /* save the current value of the warm-start vector */
2005 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2007 outb(CMOS_REG, BIOS_RESET);
2008 mpbiosreason = inb(CMOS_DATA);
2011 /* record BSP in CPU map */
2014 /* set up temporary P==V mapping for AP boot */
2015 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2016 kptbase = (uintptr_t)(void *)KPTphys;
2017 for (x = 0; x < NKPT; x++)
2018 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2019 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2023 for (x = 1; x <= mp_naps; ++x) {
2025 /* This is a bit verbose, it will go away soon. */
2027 /* first page of AP's private space */
2028 pg = x * i386_btop(sizeof(struct privatespace));
2030 /* allocate a new private data page */
2031 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2033 /* wire it into the private page table page */
2034 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
2036 /* allocate and set up an idle stack data page */
2037 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2038 for (i = 0; i < UPAGES; i++) {
2039 SMPpt[pg + 5 + i] = (pt_entry_t)
2040 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2043 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2044 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2045 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2046 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2048 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2049 bzero(gd, sizeof(*gd));
2050 gd->mi.gd_prvspace = &CPU_prvspace[x];
2052 /* prime data page for it to use */
2053 mi_gdinit(&gd->mi, x);
2055 gd->gd_cpu_lockid = x << 24;
2056 gd->gd_CMAP1 = &SMPpt[pg + 1];
2057 gd->gd_CMAP2 = &SMPpt[pg + 2];
2058 gd->gd_CMAP3 = &SMPpt[pg + 3];
2059 gd->gd_PMAP1 = &SMPpt[pg + 4];
2060 gd->gd_CADDR1 = CPU_prvspace[x].CPAGE1;
2061 gd->gd_CADDR2 = CPU_prvspace[x].CPAGE2;
2062 gd->gd_CADDR3 = CPU_prvspace[x].CPAGE3;
2063 gd->gd_PADDR1 = (unsigned *)CPU_prvspace[x].PPAGE1;
2064 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2065 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2067 /* setup a vector to our boot code */
2068 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2069 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2071 outb(CMOS_REG, BIOS_RESET);
2072 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2076 * Setup the AP boot stack
2078 bootSTK = &CPU_prvspace[x].idlestack[UPAGES*PAGE_SIZE/2];
2081 /* attempt to start the Application Processor */
2082 CHECK_INIT(99); /* setup checkpoints */
2083 if (!start_ap(x, boot_addr)) {
2084 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2085 CHECK_PRINT("trace"); /* show checkpoints */
2086 /* better panic as the AP may be running loose */
2087 printf("panic y/n? [y] ");
2088 if (cngetc() != 'n')
2091 CHECK_PRINT("trace"); /* show checkpoints */
2093 /* record its version info */
2094 cpu_apic_versions[x] = cpu_apic_versions[0];
2096 all_cpus |= (1 << x); /* record AP in CPU map */
2099 /* build our map of 'other' CPUs */
2100 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
2101 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2102 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2104 /* fill in our (BSP) APIC version */
2105 cpu_apic_versions[0] = lapic.version;
2107 /* restore the warmstart vector */
2108 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2110 outb(CMOS_REG, BIOS_RESET);
2111 outb(CMOS_DATA, mpbiosreason);
2115 * NOTE! The idlestack for the BSP was setup by locore. Finish
2116 * up, clean out the P==V mapping we did earlier.
2118 for (x = 0; x < NKPT; x++)
2122 /* number of APs actually started */
2128 * load the 1st level AP boot code into base memory.
2131 /* targets for relocation */
2132 extern void bigJump(void);
2133 extern void bootCodeSeg(void);
2134 extern void bootDataSeg(void);
2135 extern void MPentry(void);
2136 extern u_int MP_GDT;
2137 extern u_int mp_gdtbase;
2140 install_ap_tramp(u_int boot_addr)
2143 int size = *(int *) ((u_long) & bootMP_size);
2144 u_char *src = (u_char *) ((u_long) bootMP);
2145 u_char *dst = (u_char *) boot_addr + KERNBASE;
2146 u_int boot_base = (u_int) bootMP;
2151 POSTCODE(INSTALL_AP_TRAMP_POST);
2153 for (x = 0; x < size; ++x)
2157 * modify addresses in code we just moved to basemem. unfortunately we
2158 * need fairly detailed info about mpboot.s for this to work. changes
2159 * to mpboot.s might require changes here.
2162 /* boot code is located in KERNEL space */
2163 dst = (u_char *) boot_addr + KERNBASE;
2165 /* modify the lgdt arg */
2166 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2167 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2169 /* modify the ljmp target for MPentry() */
2170 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2171 *dst32 = ((u_int) MPentry - KERNBASE);
2173 /* modify the target for boot code segment */
2174 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2175 dst8 = (u_int8_t *) (dst16 + 1);
2176 *dst16 = (u_int) boot_addr & 0xffff;
2177 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2179 /* modify the target for boot data segment */
2180 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2181 dst8 = (u_int8_t *) (dst16 + 1);
2182 *dst16 = (u_int) boot_addr & 0xffff;
2183 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2188 * this function starts the AP (application processor) identified
2189 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2190 * to accomplish this. This is necessary because of the nuances
2191 * of the different hardware we might encounter. It ain't pretty,
2192 * but it seems to work.
2194 * NOTE: eventually an AP gets to ap_init(), which is called just
2195 * before the AP goes into the LWKT scheduler's idle loop.
2198 start_ap(int logical_cpu, u_int boot_addr)
2203 u_long icr_lo, icr_hi;
2205 POSTCODE(START_AP_POST);
2207 /* get the PHYSICAL APIC ID# */
2208 physical_cpu = CPU_TO_ID(logical_cpu);
2210 /* calculate the vector */
2211 vector = (boot_addr >> 12) & 0xff;
2213 /* used as a watchpoint to signal AP startup */
2216 /* Make sure the target cpu sees everything */
2220 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2221 * and running the target CPU. OR this INIT IPI might be latched (P5
2222 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2226 /* setup the address for the target AP */
2227 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2228 icr_hi |= (physical_cpu << 24);
2229 lapic.icr_hi = icr_hi;
2231 /* do an INIT IPI: assert RESET */
2232 icr_lo = lapic.icr_lo & 0xfff00000;
2233 lapic.icr_lo = icr_lo | 0x0000c500;
2235 /* wait for pending status end */
2236 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2239 /* do an INIT IPI: deassert RESET */
2240 lapic.icr_lo = icr_lo | 0x00008500;
2242 /* wait for pending status end */
2243 u_sleep(10000); /* wait ~10mS */
2244 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2248 * next we do a STARTUP IPI: the previous INIT IPI might still be
2249 * latched, (P5 bug) this 1st STARTUP would then terminate
2250 * immediately, and the previously started INIT IPI would continue. OR
2251 * the previous INIT IPI has already run. and this STARTUP IPI will
2252 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2256 /* do a STARTUP IPI */
2257 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2258 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2260 u_sleep(200); /* wait ~200uS */
2263 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2264 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2265 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2266 * recognized after hardware RESET or INIT IPI.
2269 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2270 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2272 u_sleep(200); /* wait ~200uS */
2274 /* wait for it to start, see ap_init() */
2275 set_apic_timer(5000000);/* == 5 seconds */
2276 while (read_apic_timer()) {
2278 return 1; /* return SUCCESS */
2280 return 0; /* return FAILURE */
2285 * Flush the TLB on all other CPU's
2287 * XXX: Needs to handshake and wait for completion before proceding.
2292 #if defined(APIC_IO)
2293 if (smp_started && invltlb_ok)
2294 all_but_self_ipi(XINVLTLB_OFFSET);
2295 #endif /* APIC_IO */
2299 * When called the executing CPU will send an IPI to all other CPUs
2300 * requesting that they halt execution.
2302 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2304 * - Signals all CPUs in map to stop.
2305 * - Waits for each to stop.
2312 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2313 * from executing at same time.
2316 stop_cpus(u_int map)
2321 /* send the Xcpustop IPI to all CPUs in map */
2322 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2324 while ((stopped_cpus & map) != map)
2332 * Called by a CPU to restart stopped CPUs.
2334 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2336 * - Signals all CPUs in map to restart.
2337 * - Waits for each to restart.
2345 restart_cpus(u_int map)
2350 started_cpus = map; /* signal other cpus to restart */
2352 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2358 int smp_active = 0; /* are the APs allowed to run? */
2359 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, "");
2361 /* XXX maybe should be hw.ncpu */
2362 static int smp_cpus = 1; /* how many cpu's running */
2363 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, "");
2365 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */
2366 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, "");
2368 /* Warning: Do not staticize. Used from swtch.s */
2369 int do_page_zero_idle = 1; /* bzero pages for fun and profit in idleloop */
2370 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW,
2371 &do_page_zero_idle, 0, "");
2373 /* Is forwarding of a interrupt to the CPU holding the ISR lock enabled ? */
2374 int forward_irq_enabled = 1;
2375 SYSCTL_INT(_machdep, OID_AUTO, forward_irq_enabled, CTLFLAG_RW,
2376 &forward_irq_enabled, 0, "");
2378 /* Enable forwarding of a signal to a process running on a different CPU */
2379 static int forward_signal_enabled = 1;
2380 SYSCTL_INT(_machdep, OID_AUTO, forward_signal_enabled, CTLFLAG_RW,
2381 &forward_signal_enabled, 0, "");
2383 /* Enable forwarding of roundrobin to all other cpus */
2384 static int forward_roundrobin_enabled = 1;
2385 SYSCTL_INT(_machdep, OID_AUTO, forward_roundrobin_enabled, CTLFLAG_RW,
2386 &forward_roundrobin_enabled, 0, "");
2389 * This is called once the mpboot code has gotten us properly relocated
2390 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2391 * and when it returns the scheduler will call the real cpu_idle() main
2392 * loop for the idlethread. Interrupts are disabled on entry and should
2393 * remain disabled at return.
2402 * Signal the BSP that we have started up successfully by incrementing
2403 * ncpus. Note that we do not hold the BGL yet. The BSP is waiting
2409 * Get the MP lock so we can finish initializing. Note: we are
2410 * in a critical section. td_mpcount must always be bumped prior
2411 * to obtaining the actual lock.
2413 ++curthread->td_mpcount;
2414 while (cpu_try_mplock() == 0)
2417 /* BSP may have changed PTD while we're waiting for the lock */
2420 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2424 /* Build our map of 'other' CPUs. */
2425 mycpu->gd_other_cpus = all_cpus & ~(1 << mycpu->gd_cpuid);
2427 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2429 /* set up CPU registers and state */
2432 /* set up FPU state on the AP */
2433 npxinit(__INITIAL_NPXCW__);
2435 /* set up SSE registers */
2438 /* A quick check from sanity claus */
2439 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2440 if (mycpu->gd_cpuid != apic_id) {
2441 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2442 printf("SMP: apic_id = %d\n", apic_id);
2443 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2444 panic("cpuid mismatch! boom!!");
2447 /* Init local apic for irq's */
2450 /* Set memory range attributes for this CPU to match the BSP */
2451 mem_range_AP_init();
2454 * Since we have the BGL if smp_cpus matches ncpus then we are
2455 * the last AP to get to this point and we can enable IPI's,
2456 * tlb shootdowns, freezes, and so forth.
2459 if (smp_cpus == ncpus) {
2461 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */
2462 smp_active = 1; /* historic */
2466 * AP helper function for kernel memory support. This will create
2467 * a memory reserve for the AP that is necessary to avoid certain
2468 * memory deadlock situations, such as when the kernel_map needs
2469 * a vm_map_entry and zalloc has no free entries and tries to allocate
2470 * a new one from the ... kernel_map :-)
2475 * Startup helper thread(s) one per cpu.
2477 sched_thread_init();
2480 * The idle loop doesn't expect the BGL to be held and while
2481 * lwkt_switch() normally cleans things up this is a special case
2482 * because we returning almost directly into the idle loop.
2484 KKASSERT(curthread->td_mpcount == 1);
2490 #define CHECKSTATE_USER 0
2491 #define CHECKSTATE_SYS 1
2492 #define CHECKSTATE_INTR 2
2494 /* Do not staticize. Used from apic_vector.s */
2495 struct thread *checkstate_curtd[MAXCPU];
2496 int checkstate_cpustate[MAXCPU];
2497 u_long checkstate_pc[MAXCPU];
2499 #define PC_TO_INDEX(pc, prof) \
2500 ((int)(((u_quad_t)((pc) - (prof)->pr_off) * \
2501 (u_quad_t)((prof)->pr_scale)) >> 16) & ~1)
2505 addupc_intr_forwarded(struct proc *p, int id, int *astmap)
2511 pc = checkstate_pc[id];
2512 prof = &p->p_stats->p_prof;
2513 if (pc >= prof->pr_off &&
2514 (i = PC_TO_INDEX(pc, prof)) < prof->pr_size) {
2515 if ((p->p_flag & P_OWEUPC) == 0) {
2518 p->p_flag |= P_OWEUPC;
2520 *astmap |= (1 << id);
2526 forwarded_statclock(int id, int pscnt, int *astmap)
2529 struct pstats *pstats;
2536 register struct gmonparam *g;
2540 t = checkstate_curtd[id];
2541 cpustate = checkstate_cpustate[id];
2544 case CHECKSTATE_USER:
2545 if (td->td_proc && td->td_proc->p_flag & P_PROFIL)
2546 addupc_intr_forwarded(td->td_proc, id, astmap);
2550 if (p->p_nice > NZERO)
2555 case CHECKSTATE_SYS:
2558 * Kernel statistics are just like addupc_intr, only easier.
2561 if (g->state == GMON_PROF_ON) {
2562 i = checkstate_pc[id] - g->lowpc;
2563 if (i < g->textsize) {
2564 i /= HISTFRACTION * sizeof(*g->kcount);
2579 case CHECKSTATE_INTR:
2583 * Kernel statistics are just like addupc_intr, only easier.
2586 if (g->state == GMON_PROF_ON) {
2587 i = checkstate_pc[id] - g->lowpc;
2588 if (i < g->textsize) {
2589 i /= HISTFRACTION * sizeof(*g->kcount);
2603 /* Update resource usage integrals and maximums. */
2604 if ((pstats = p->p_stats) != NULL &&
2605 (ru = &pstats->p_ru) != NULL &&
2606 (vm = p->p_vmspace) != NULL) {
2607 ru->ru_ixrss += pgtok(vm->vm_tsize);
2608 ru->ru_idrss += pgtok(vm->vm_dsize);
2609 ru->ru_isrss += pgtok(vm->vm_ssize);
2610 rss = pgtok(vmspace_resident_count(vm));
2611 if (ru->ru_maxrss < rss)
2612 ru->ru_maxrss = rss;
2619 forward_statclock(int pscnt)
2625 /* Kludge. We don't yet have separate locks for the interrupts
2626 * and the kernel. This means that we cannot let the other processors
2627 * handle complex interrupts while inhibiting them from entering
2628 * the kernel in a non-interrupt context.
2630 * What we can do, without changing the locking mechanisms yet,
2631 * is letting the other processors handle a very simple interrupt
2632 * (wich determines the processor states), and do the main
2636 if (!smp_started || !invltlb_ok || cold || panicstr)
2639 printf("forward_statclock\n");
2640 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle ) */
2642 map = mycpu->gd_other_cpus & ~stopped_cpus ;
2643 checkstate_probed_cpus = 0;
2645 selected_apic_ipi(map,
2646 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2649 while (checkstate_probed_cpus != map) {
2653 #ifdef BETTER_CLOCK_DIAGNOSTIC
2654 printf("forward_statclock: checkstate %x\n",
2655 checkstate_probed_cpus);
2662 * Step 2: walk through other processors processes, update ticks and
2667 for (id = 0; id < ncpus; id++) {
2668 if (id == mycpu->gd_cpuid)
2670 if (((1 << id) & checkstate_probed_cpus) == 0)
2672 forwarded_statclock(id, pscnt, &map);
2679 forward_hardclock(int pscnt)
2685 struct pstats *pstats;
2689 /* Kludge. We don't yet have separate locks for the interrupts
2690 * and the kernel. This means that we cannot let the other processors
2691 * handle complex interrupts while inhibiting them from entering
2692 * the kernel in a non-interrupt context.
2694 * What we can do, without changing the locking mechanisms yet,
2695 * is letting the other processors handle a very simple interrupt
2696 * (wich determines the processor states), and do the main
2700 if (!smp_started || !invltlb_ok || cold || panicstr)
2703 /* Step 1: Probe state (user, cpu, interrupt, spinlock, idle) */
2705 map = mycpu->gd_other_cpus & ~stopped_cpus ;
2706 checkstate_probed_cpus = 0;
2708 selected_apic_ipi(map,
2709 XCPUCHECKSTATE_OFFSET, APIC_DELMODE_FIXED);
2712 while (checkstate_probed_cpus != map) {
2716 #ifdef BETTER_CLOCK_DIAGNOSTIC
2717 printf("forward_hardclock: checkstate %x\n",
2718 checkstate_probed_cpus);
2725 * Step 2: walk through other processors processes, update virtual
2726 * timer and profiling timer. If stathz == 0, also update ticks and
2731 for (id = 0; id < ncpus; id++) {
2732 if (id == mycpu->gd_cpuid)
2734 if (((1 << id) & checkstate_probed_cpus) == 0)
2736 printf("forward_hardclock\n");
2738 p = checkstate_curproc[id];
2740 pstats = p->p_stats;
2741 if (checkstate_cpustate[id] == CHECKSTATE_USER &&
2742 timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value) &&
2743 itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL], tick) == 0) {
2744 psignal(p, SIGVTALRM);
2747 if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value) &&
2748 itimerdecr(&pstats->p_timer[ITIMER_PROF], tick) == 0) {
2749 psignal(p, SIGPROF);
2754 forwarded_statclock( id, pscnt, &map);
2762 #endif /* BETTER_CLOCK */
2764 #ifdef APIC_INTR_REORDER
2766 * Maintain mapping from softintr vector to isr bit in local apic.
2769 set_lapic_isrloc(int intr, int vector)
2771 if (intr < 0 || intr > 32)
2772 panic("set_apic_isrloc: bad intr argument: %d",intr);
2773 if (vector < ICU_OFFSET || vector > 255)
2774 panic("set_apic_isrloc: bad vector argument: %d",vector);
2775 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2776 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2781 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2782 * (if specified), rendezvous, execute the action function (if specified),
2783 * rendezvous again, execute the teardown function (if specified), and then
2786 * Note that the supplied external functions _must_ be reentrant and aware
2787 * that they are running in parallel and in an unknown lock context.
2789 static void (*smp_rv_setup_func)(void *arg);
2790 static void (*smp_rv_action_func)(void *arg);
2791 static void (*smp_rv_teardown_func)(void *arg);
2792 static void *smp_rv_func_arg;
2793 static volatile int smp_rv_waiters[2];
2796 smp_rendezvous_action(void)
2798 /* setup function */
2799 if (smp_rv_setup_func != NULL)
2800 smp_rv_setup_func(smp_rv_func_arg);
2801 /* spin on entry rendezvous */
2802 atomic_add_int(&smp_rv_waiters[0], 1);
2803 while (smp_rv_waiters[0] < ncpus)
2805 /* action function */
2806 if (smp_rv_action_func != NULL)
2807 smp_rv_action_func(smp_rv_func_arg);
2808 /* spin on exit rendezvous */
2809 atomic_add_int(&smp_rv_waiters[1], 1);
2810 while (smp_rv_waiters[1] < ncpus)
2812 /* teardown function */
2813 if (smp_rv_teardown_func != NULL)
2814 smp_rv_teardown_func(smp_rv_func_arg);
2818 smp_rendezvous(void (* setup_func)(void *),
2819 void (* action_func)(void *),
2820 void (* teardown_func)(void *),
2823 /* obtain rendezvous lock. This disables interrupts */
2824 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
2826 /* set static function pointers */
2827 smp_rv_setup_func = setup_func;
2828 smp_rv_action_func = action_func;
2829 smp_rv_teardown_func = teardown_func;
2830 smp_rv_func_arg = arg;
2831 smp_rv_waiters[0] = 0;
2832 smp_rv_waiters[1] = 0;
2834 /* signal other processors, which will enter the IPI with interrupts off */
2835 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2837 /* call executor function */
2838 smp_rendezvous_action();
2841 spin_unlock(&smp_rv_spinlock);
2845 cpu_send_ipiq(int dcpu)
2847 selected_apic_ipi(1 << dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);