2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.21 2005/02/21 03:37:44 joerg Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/linker_set.h>
51 #include <sys/module.h>
53 #include <net/ethernet.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
58 #include <netinet/in.h>
59 #include <netinet/if_ether.h>
61 #include <bus/isa/i386/isa_device.h>
62 #include <i386/isa/icu.h>
69 typedef u_short le_mcbits_t;
70 #define LE_MC_NBPW_LOG2 4
71 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
76 int (*bd_probe)(struct le_softc *sc, const struct le_board *bd, int *msize);
79 #if !defined(LE_NOLEMAC)
81 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
83 * Start of DEC EtherWORKS III (LEMAC) dependent structures
86 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
88 DECLARE_DUMMY_MODULE(if_le);
90 static int lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
92 struct le_lemac_info {
93 u_int lemac__lastpage; /* last 2K page */
94 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
95 u_int lemac__membase; /* Physical address of start of RAM */
96 u_int lemac__txctl; /* Transmit Control Byte */
97 u_int lemac__txmax; /* Maximum # of outstanding transmits */
98 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
99 /* local copy of multicast table */
100 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
101 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
102 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
103 #define lemac_memmode le_un.un_lemac.lemac__memmode
104 #define lemac_membase le_un.un_lemac.lemac__membase
105 #define lemac_txctl le_un.un_lemac.lemac__txctl
106 #define lemac_txmax le_un.un_lemac.lemac__txmax
107 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
108 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
109 #define lemac_prodname le_un.un_lemac.lemac__prodname
111 #endif /* !defined(LE_NOLEMAC) */
113 #if !defined(LE_NOLANCE)
115 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
117 * Start of DEC EtherWORKS II (LANCE) dependent structures
121 #include <i386/isa/ic/am7990.h>
127 static int depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
129 typedef struct lance_descinfo lance_descinfo_t;
130 typedef struct lance_ring lance_ring_t;
132 typedef unsigned lance_addr_t;
134 struct lance_descinfo {
135 caddr_t di_addr; /* address of descriptor */
136 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
137 unsigned di_buflen; /* size of buffer owned by descriptor */
138 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
142 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
143 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
144 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
145 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
146 unsigned ri_max; /* Size of Ring - 1 */
147 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
148 lance_addr_t ri_heap; /* Start of RAM for this ring */
149 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
150 lance_addr_t ri_outptr; /* Pointer to first output byte */
151 unsigned ri_outsize; /* Space remaining for output */
154 struct le_lance_info {
155 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
156 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
157 unsigned lance__csr3; /* Copy of CSR3 */
158 unsigned lance__rap; /* IO Port Offset of RAP */
159 unsigned lance__rdp; /* IO Port Offset of RDP */
160 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
161 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
162 unsigned lance__rxbufsize; /* Size of a receive buffer */
163 ln_initb_t lance__initb; /* local copy of LANCE initblock */
164 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
165 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
166 lance_ring_t lance__rxinfo; /* Receive ring information */
167 lance_ring_t lance__txinfo; /* Transmit ring information */
168 #define lance_csr1 le_un.un_lance.lance__csr1
169 #define lance_csr2 le_un.un_lance.lance__csr2
170 #define lance_csr3 le_un.un_lance.lance__csr3
171 #define lance_rap le_un.un_lance.lance__rap
172 #define lance_rdp le_un.un_lance.lance__rdp
173 #define lance_ramoffset le_un.un_lance.lance__ramoffset
174 #define lance_ramsize le_un.un_lance.lance__ramsize
175 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
176 #define lance_initb le_un.un_lance.lance__initb
177 #define lance_raminitb le_un.un_lance.lance__raminitb
178 #define lance_ramdesc le_un.un_lance.lance__ramdesc
179 #define lance_rxinfo le_un.un_lance.lance__rxinfo
180 #define lance_txinfo le_un.un_lance.lance__txinfo
182 #endif /* !defined(LE_NOLANCE) */
185 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
187 * Start of Common Code
191 static void (*le_intrvec[NLE])(struct le_softc *sc);
194 * Ethernet status, per interface.
197 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
198 void (*if_init) (void *);/* Interface init routine */
199 void (*if_reset) (struct le_softc*);/* Interface reset routine */
200 caddr_t le_membase; /* Starting memory address (virtual) */
201 unsigned le_iobase; /* Starting I/O base address */
202 unsigned le_irq; /* Interrupt Request Value */
203 unsigned le_flags; /* local copy of if_flags */
204 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
205 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
206 le_mcbits_t *le_mctbl; /* pointer to multicast table */
207 const char *le_prodname; /* product name DE20x-xx */
208 u_char le_hwaddr[6]; /* local copy of hwaddr */
210 #if !defined(LE_NOLEMAC)
211 struct le_lemac_info un_lemac; /* LEMAC specific information */
213 #if !defined(LE_NOLANCE)
214 struct le_lance_info un_lance; /* Am7990 specific information */
218 #define le_if le_ac.ac_if
221 static int le_probe(struct isa_device *dvp);
222 static int le_attach(struct isa_device *dvp);
223 static ointhand2_t le_intr;
224 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
226 static void le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
227 size_t len2, caddr_t seg2);
228 static void le_multi_filter(struct le_softc *sc);
229 static void le_multi_op(struct le_softc *sc, const u_char *mca, int oper_flg);
230 static int le_read_macaddr(struct le_softc *sc, int ioreg, int skippat);
232 static struct le_softc le_softc[NLE];
234 static const struct le_board le_boards[] = {
235 #if !defined(LE_NOLEMAC)
236 { lemac_probe }, /* DE20[345] */
238 #if !defined(LE_NOLANCE)
239 { depca_probe }, /* DE{20[012],422} */
241 { NULL } /* Must Be Last! */
245 * This tells the autoconf code how to set us up.
247 struct isa_driver ledriver = {
248 le_probe, le_attach, "le",
251 static unsigned le_intrs[NLE];
253 #define LE_INL(sc, reg) inl((sc)->le_iobase + (reg))
254 #define LE_OUTL(sc, reg, data) outl((sc)->le_iobase + (reg), data)
255 #define LE_INW(sc, reg) inw((sc)->le_iobase + (reg))
256 #define LE_OUTW(sc, reg, data) outw((sc)->le_iobase + (reg), data)
257 #define LE_INB(sc, reg) inb((sc)->le_iobase + (reg))
258 #define LE_OUTB(sc, reg, data) outb((sc)->le_iobase + (reg), data)
261 le_probe(struct isa_device *dvp)
263 struct le_softc *sc = &le_softc[dvp->id_unit];
264 const struct le_board *bd;
267 if (dvp->id_unit >= NLE) {
268 printf("%s%d not configured -- too many devices\n",
269 ledriver.name, dvp->id_unit);
273 sc->le_iobase = dvp->id_iobase;
274 sc->le_membase = (u_char *) dvp->id_maddr;
275 sc->le_irq = dvp->id_irq;
276 if_initname(&(sc->le_if), ledriver.name, dvp->id_unit);
279 * Find and Initialize board..
282 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
284 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
285 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
294 le_attach(struct isa_device *dvp)
296 struct le_softc *sc = &le_softc[dvp->id_unit];
297 struct ifnet *ifp = &sc->le_if;
299 dvp->id_ointr = le_intr;
301 ifp->if_mtu = ETHERMTU;
303 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
304 ifp->if_ioctl = le_ioctl;
305 ifp->if_type = IFT_ETHER;
308 ifp->if_init = sc->if_init;
310 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
321 (*le_intrvec[unit])(&le_softc[unit]);
329 le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
330 size_t len1, caddr_t seg2)
332 struct ether_header eh;
335 if (total_len - sizeof(eh) > ETHERMTU
336 || total_len - sizeof(eh) < ETHERMIN) {
337 sc->le_if.if_ierrors++;
340 bcopy(seg1, &eh, ETHER_HDR_LEN);
342 seg1 += ETHER_HDR_LEN;
343 total_len -= ETHER_HDR_LEN;
344 len1 -= ETHER_HDR_LEN;
346 MGETHDR(m, MB_DONTWAIT, MT_DATA);
348 sc->le_if.if_ierrors++;
351 m->m_pkthdr.len = total_len;
352 m->m_pkthdr.rcvif = &sc->le_if;
353 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
354 MCLGET(m, MB_DONTWAIT);
355 if ((m->m_flags & M_EXT) == 0) {
357 sc->le_if.if_ierrors++;
360 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
361 MGET(m->m_next, MB_DONTWAIT, MT_DATA);
362 if (m->m_next == NULL) {
364 sc->le_if.if_ierrors++;
367 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
368 len1 = total_len = MHLEN - LE_XTRA;
369 bcopy(&seg1[MHLEN-LE_XTRA], mtod(m->m_next, caddr_t), m->m_next->m_len);
370 } else if (total_len + LE_XTRA > MHLEN) {
371 panic("le_input: pkt of unknown length");
373 m->m_data += LE_XTRA;
374 m->m_len = total_len;
375 bcopy(seg1, mtod(m, caddr_t), len1);
377 bcopy(seg2, mtod(m, caddr_t) + len1, total_len - len1);
378 ether_input(&sc->le_if, &eh, m);
382 le_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
384 struct le_softc *sc = ifp->if_softc;
387 if ((sc->le_flags & IFF_UP) == 0)
396 error = ether_ioctl(ifp, cmd, data);
407 * Update multicast listeners
423 * This is the standard method of reading the DEC Address ROMS.
424 * I don't understand it but it does work.
427 le_read_macaddr(struct le_softc *sc, int ioreg, int skippat)
429 int cksum, rom_cksum;
432 int idx, idx2, found, octet;
433 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
436 for (idx = 0; idx < 32; idx++) {
437 octet = LE_INB(sc, ioreg);
439 if (octet == testpat[idx2]) {
440 if (++idx2 == sizeof testpat) {
454 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
455 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
457 cksum = *(u_short *) &sc->le_hwaddr[0];
459 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
460 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
462 if (cksum > 65535) cksum -= 65535;
463 cksum += *(u_short *) &sc->le_hwaddr[2];
464 if (cksum > 65535) cksum -= 65535;
466 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
467 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
469 if (cksum > 65535) cksum -= 65535;
470 cksum += *(u_short *) &sc->le_hwaddr[4];
471 if (cksum >= 65535) cksum -= 65535;
473 rom_cksum = LE_INB(sc, ioreg);
474 rom_cksum |= LE_INB(sc, ioreg) << 8;
476 if (cksum != rom_cksum)
482 le_multi_filter(struct le_softc *sc)
484 struct ifnet *ifp = &sc->le_ac.ac_if;
485 struct ifmultiaddr *ifma;
487 bzero(sc->le_mctbl, (sc->le_mcmask + 1) / 8);
489 if (sc->le_if.if_flags & IFF_ALLMULTI) {
490 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
493 sc->le_flags &= ~IFF_MULTICAST;
494 /* if (interface has had an address assigned) { */
495 le_multi_op(sc, ifp->if_broadcastaddr, TRUE);
496 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
499 sc->le_flags |= IFF_MULTICAST;
501 for (ifma = ifp->if_multiaddrs.lh_first; ifma;
502 ifma = ifma->ifma_link.le_next) {
503 if (ifma->ifma_addr->sa_family != AF_LINK)
506 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
507 sc->le_flags &= ~LE_BRDCSTONLY;
512 le_multi_op(struct le_softc *sc, const u_char *mca, int enable)
514 uint32_t bit, idx, crc;
516 crc = ether_crc32_le(mca, ETHER_ADDR_LEN);
519 * The following two line convert the N bit index into a longword index
520 * and a longword mask.
522 crc &= sc->le_mcmask;
523 bit = 1 << (crc & (LE_MC_NBPW -1));
524 idx = crc >> (LE_MC_NBPW_LOG2);
527 * Set or clear hash filter bit in our table.
530 sc->le_mctbl[idx] |= bit; /* Set Bit */
532 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
536 #if !defined(LE_NOLEMAC)
538 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
540 * Start of DEC EtherWORKS III (LEMAC) dependent code
544 #define LEMAC_INTR_ENABLE(sc) \
545 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
547 #define LEMAC_INTR_DISABLE(sc) \
548 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
550 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
551 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
552 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
554 static void lemac_init(void *xsc);
555 static void lemac_start(struct ifnet *ifp);
556 static void lemac_reset(struct le_softc *sc);
557 static void lemac_intr(struct le_softc *sc);
558 static void lemac_rne_intr(struct le_softc *sc);
559 static void lemac_tne_intr(struct le_softc *sc);
560 static void lemac_txd_intr(struct le_softc *sc, unsigned cs_value);
561 static void lemac_rxd_intr(struct le_softc *sc, unsigned cs_value);
562 static int lemac_read_eeprom(struct le_softc *sc);
563 static void lemac_init_adapmem(struct le_softc *sc);
565 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
567 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
568 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
569 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
570 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
571 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
574 * An IRQ mapping table. Less space than switch statement.
576 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
579 * Some tuning/monitoring variables.
581 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
582 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
584 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
585 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
586 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
587 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
590 lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
594 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
595 DELAY(LEMAC_EEP_DELAY);
598 * Read Ethernet address if card is present.
600 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
603 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
605 * Clear interrupts and set IRQ.
608 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
609 irq = lemac_irqs[portval >> 5];
610 LE_OUTB(sc, LEMAC_REG_IC, portval);
613 * Make sure settings match.
616 if (irq != sc->le_irq) {
617 if_printf(&sc->le_if, "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
623 * Try to reset the unit
625 sc->if_init = lemac_init;
626 sc->le_if.if_start = lemac_start;
627 sc->if_reset = lemac_reset;
628 sc->lemac_memmode = 2;
630 if ((sc->le_flags & IFF_UP) == 0)
634 * Check for correct memory base configuration.
636 if (vtophys(sc->le_membase) != sc->lemac_membase) {
637 if_printf(&sc->le_if, "lemac configuration error: expected iomem 0x%llx actual 0x%x\n",
638 vtophys(sc->le_membase), sc->lemac_membase);
642 sc->le_prodname = sc->lemac_prodname;
643 sc->le_mctbl = sc->lemac_mctbl;
644 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
645 sc->lemac_txmax = lemac_deftxmax;
647 le_intrvec[sc->le_if.if_dunit] = lemac_intr;
649 return LEMAC_IOSPACE;
653 * Do a hard reset of the board;
656 lemac_reset(struct le_softc *sc)
658 struct ifnet *ifp = &sc->le_if;
665 sc->le_flags &= IFF_UP;
666 ifp->if_flags &= ~IFF_OACTIVE;
667 LEMAC_INTR_DISABLE(sc);
669 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
670 DELAY(LEMAC_EEP_DELAY);
672 /* Disable Interrupts */
673 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
676 * Read EEPROM information. NOTE - the placement of this function
677 * is important because functions hereafter may rely on information
678 * read from the EEPROM.
680 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
681 if_printf(ifp, "reset: EEPROM checksum failed (0x%x)\n", cksum);
686 * Force to 2K mode if not already configured.
689 portval = LE_INB(sc, LEMAC_REG_MBR);
690 if (!LEMAC_2K_MODE(portval)) {
691 if (LEMAC_64K_MODE(portval)) {
692 portval = (((portval * 2) & 0xF) << 4);
693 sc->lemac_memmode = 64;
694 } else if (LEMAC_32K_MODE(portval)) {
695 portval = ((portval & 0xF) << 4);
696 sc->lemac_memmode = 32;
698 LE_OUTB(sc, LEMAC_REG_MBR, portval);
700 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
703 * Initialize Free Memory Queue, Init mcast table with broadcast.
706 lemac_init_adapmem(sc);
707 sc->le_flags |= IFF_UP;
711 lemac_init(void *xsc)
713 struct le_softc *sc = (struct le_softc *)xsc;
716 if ((sc->le_flags & IFF_UP) == 0)
722 * If the interface has the up flag
724 if (sc->le_if.if_flags & IFF_UP) {
725 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
726 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
727 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
728 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
729 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
730 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
731 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
732 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
734 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
736 if (sc->le_if.if_flags & IFF_PROMISC) {
737 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
739 LEMAC_INTR_DISABLE(sc);
741 LE_OUTB(sc, LEMAC_REG_MPN, 0);
742 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
743 bcopy(lemac_allmulti_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(lemac_allmulti_mctbl));
745 bcopy(sc->lemac_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(sc->lemac_mctbl));
747 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
750 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
752 LEMAC_INTR_ENABLE(sc);
753 sc->le_if.if_flags |= IFF_RUNNING;
755 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
757 LEMAC_INTR_DISABLE(sc);
758 sc->le_if.if_flags &= ~IFF_RUNNING;
764 * What to do upon receipt of an interrupt.
767 lemac_intr(struct le_softc *sc)
771 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
774 * Determine cause of interrupt. Receive events take
775 * priority over Transmit.
778 cs_value = LE_INB(sc, LEMAC_REG_CS);
781 * Check for Receive Queue not being empty.
782 * Check for Transmit Done Queue not being empty.
785 if (cs_value & LEMAC_CS_RNE)
787 if (cs_value & LEMAC_CS_TNE)
791 * Check for Transmitter Disabled.
792 * Check for Receiver Disabled.
795 if (cs_value & LEMAC_CS_TXD)
796 lemac_txd_intr(sc, cs_value);
797 if (cs_value & LEMAC_CS_RXD)
798 lemac_rxd_intr(sc, cs_value);
801 * Toggle LED and unmask interrupts.
804 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
805 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
809 lemac_rne_intr(struct le_softc *sc)
811 int rxcount, rxlen, rxpg;
815 rxcount = LE_INB(sc, LEMAC_REG_RQC);
817 rxpg = LE_INB(sc, LEMAC_REG_RQ);
818 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
820 rxptr = sc->le_membase;
821 sc->le_if.if_ipackets++;
822 if (*rxptr & LEMAC_RX_OK) {
825 * Get receive length - subtract out checksum.
828 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
829 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
830 } else { /* end if (*rxptr & LEMAC_RX_OK) */
831 sc->le_if.if_ierrors++;
833 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
834 } /* end while (recv_count--) */
838 lemac_rxd_intr(struct le_softc *sc, unsigned cs_value)
841 * Handle CS_RXD (Receiver disabled) here.
843 * Check Free Memory Queue Count. If not equal to zero
844 * then just turn Receiver back on. If it is equal to
845 * zero then check to see if transmitter is disabled.
846 * Process transmit TXD loop once more. If all else
847 * fails then do software init (0xC0 to EEPROM Init)
848 * and rebuild Free Memory Queue.
854 * Re-enable Receiver.
857 cs_value &= ~LEMAC_CS_RXD;
858 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
860 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
863 if (cs_value & LEMAC_CS_TXD)
864 lemac_txd_intr(sc, cs_value);
866 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
869 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
872 if (sc->le_flags & IFF_UP) {
878 * Error during initializion. Mark card as disabled.
880 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
884 lemac_start(struct ifnet *ifp)
886 struct le_softc *sc = (struct le_softc *) ifp;
888 if ((ifp->if_flags & IFF_RUNNING) == 0)
891 LEMAC_INTR_DISABLE(sc);
893 while (!IF_QEMPTY(&ifp->if_snd)) {
898 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
899 ifp->if_flags |= IFF_OACTIVE;
903 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
905 * Check for good transmit page.
907 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
909 ifp->if_flags |= IFF_OACTIVE;
913 IF_DEQUEUE(&ifp->if_snd, m);
914 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
917 * The first four bytes of each transmit buffer are for
918 * control information. The first byte is the control
919 * byte, then the length (why not word aligned?), then
920 * the off to the buffer.
923 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
924 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
925 *(u_int *) sc->le_membase = txhdr;
928 * Copy the packet to the board
931 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
933 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
937 m_freem(m); /* free the mbuf */
939 LEMAC_INTR_ENABLE(sc);
943 lemac_tne_intr(struct le_softc *sc)
945 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
949 txsts = LE_INB(sc, LEMAC_REG_TDQ);
950 sc->le_if.if_opackets++; /* another one done */
951 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
952 sc->le_if.if_collisions++;
954 sc->le_if.if_flags &= ~IFF_OACTIVE;
955 lemac_start(&sc->le_if);
959 lemac_txd_intr(struct le_softc *sc, unsigned cs_value)
962 * Read transmit status, remove transmit buffer from
963 * transmit queue and place on free memory queue,
964 * then reset transmitter.
965 * Increment appropriate counters.
969 sc->le_if.if_oerrors++;
970 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
971 sc->le_if.if_collisions++;
972 sc->le_if.if_flags &= ~IFF_OACTIVE;
974 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
975 /* Get Page number and write it back out */
977 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
978 /* Turn back on transmitter */
982 lemac_read_eeprom(struct le_softc *sc)
989 ep = sc->lemac_eeprom;
990 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
991 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
992 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
994 DELAY(LEMAC_EEP_DELAY);
996 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
997 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1001 * Set up Transmit Control Byte for use later during transmit.
1004 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1006 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1007 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1009 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1010 sc->lemac_txctl |= LEMAC_TX_LAB;
1012 bcopy(&sc->lemac_eeprom[LEMAC_EEP_PRDNM], sc->lemac_prodname, LEMAC_EEP_PRDNMSZ);
1013 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1019 lemac_init_adapmem(struct le_softc *sc)
1023 conf = LE_INB(sc, LEMAC_REG_CNF);
1025 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1026 sc->lemac_lastpage = 63;
1027 conf &= ~LEMAC_CNF_DRAM;
1029 sc->lemac_lastpage = 127;
1030 conf |= LEMAC_CNF_DRAM;
1033 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1035 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1036 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1040 #endif /* !defined(LE_NOLEMAC) */
1042 #if !defined(LE_NOLANCE)
1044 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1046 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1049 static void depca_intr(struct le_softc *sc);
1050 static int lance_init_adapmem(struct le_softc *sc);
1051 static int lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1052 unsigned ndescs, unsigned bufoffset,
1053 unsigned descoffset);
1054 static void lance_init(void *xsc);
1055 static void lance_reset(struct le_softc *sc);
1056 static void lance_intr(struct le_softc *sc);
1057 static int lance_rx_intr(struct le_softc *sc);
1058 static void lance_start(struct ifnet *ifp);
1059 static int lance_tx_intr(struct le_softc *sc);
1061 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1062 #define LN_TXDESC_RATIO 2048
1063 #define LN_DESC_MAX 128
1067 unsigned lance_rx_misses;
1068 unsigned lance_rx_badcrc;
1069 unsigned lance_rx_badalign;
1070 unsigned lance_rx_badframe;
1071 unsigned lance_rx_buferror;
1072 unsigned lance_tx_deferred;
1073 unsigned lance_tx_single_collisions;
1074 unsigned lance_tx_multiple_collisions;
1075 unsigned lance_tx_excessive_collisions;
1076 unsigned lance_tx_late_collisions;
1078 unsigned lance_memory_errors;
1079 unsigned lance_inits;
1080 unsigned lance_tx_intrs;
1081 unsigned lance_tx_nospc[2];
1082 unsigned lance_tx_drains[2];
1083 unsigned lance_tx_orphaned;
1084 unsigned lance_tx_adoptions;
1085 unsigned lance_tx_emptied;
1086 unsigned lance_tx_deftxint;
1087 unsigned lance_tx_buferror;
1088 unsigned lance_high_txoutptr;
1089 unsigned lance_low_txheapsize;
1090 unsigned lance_low_txfree;
1091 unsigned lance_tx_intr_hidescs;
1092 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1094 unsigned lance_rx_intrs;
1095 unsigned lance_rx_badsop;
1096 unsigned lance_rx_contig;
1097 unsigned lance_rx_noncontig;
1098 unsigned lance_rx_intr_hidescs;
1099 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1100 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1103 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1104 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1105 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1108 #define LN_STAT(stat) 0
1109 #define LN_MINSTAT(stat, val) 0
1110 #define LN_MAXSTAT(stat, val) 0
1113 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1114 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1116 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1117 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1120 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1121 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1123 #define LN_SETFLAG(sc, vaddr, val) \
1124 (((volatile u_char *) vaddr)[3] = (val))
1126 #define LN_PUTDESC(sc, desc, vaddr) \
1127 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1128 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1129 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1132 * Only get the descriptor flags and length/status. All else
1135 #define LN_GETDESC(sc, desc, vaddr) \
1136 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1137 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1140 * These definitions are specific to the DEC "DEPCA-style" NICs.
1141 * (DEPCA, DE10x, DE20[012], DE422)
1144 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1145 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1146 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1147 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1148 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1150 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1151 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1152 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1153 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1154 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1155 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1156 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1157 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1158 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1160 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1161 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1163 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1165 #define DEPCA_REG_EISAID 0x80
1166 #define DEPCA_EISAID_MASK 0xf0ffffff
1167 #define DEPCA_EISAID_DE422 0x2042A310
1171 DEPCA_DE100, DEPCA_DE101,
1173 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1178 static const char *depca_signatures[] = {
1182 "DE200", "DE201", "DE202",
1188 depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
1190 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1193 * Find out how memory we are dealing with. Adjust
1194 * the ID string offset approriately if we are at
1195 * 32K. Make sure the ROM is enabled.
1197 nicsr = DEPCA_RDNICSR(sc);
1198 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1200 if (nicsr & DEPCA_NICSR_32KRAM) {
1202 * Make we are going to read the upper
1203 * 32K so we do read the ROM.
1205 sc->lance_ramsize = 32 * 1024;
1206 nicsr &= ~DEPCA_NICSR_LOW32K;
1207 sc->lance_ramoffset = 32 * 1024;
1208 idstr_offset -= sc->lance_ramsize;
1210 sc->lance_ramsize = 64 * 1024;
1211 sc->lance_ramoffset = 0;
1213 DEPCA_WRNICSR(sc, nicsr);
1215 sc->le_prodname = NULL;
1216 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1217 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1218 sc->le_prodname = depca_signatures[idx];
1223 if (sc->le_prodname == NULL) {
1225 * Try to get the EISA device if it's a DE422.
1227 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1228 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1229 == DEPCA_EISAID_DE422) {
1230 sc->le_prodname = "DE422";
1235 if (idx == DEPCA_CLASSIC)
1236 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1239 * Try to read the address ROM.
1240 * Stop the LANCE, reset the Address ROM Counter (AAC),
1241 * read the NICSR to "clock" in the reset, and then
1242 * re-enable the Address ROM Counter. Now read the
1245 sc->lance_rdp = DEPCA_REG_RDP;
1246 sc->lance_rap = DEPCA_REG_RAP;
1247 sc->lance_csr3 = LN_CSR3_ALE;
1248 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1249 sc->le_mcmask = LN_MC_MASK;
1250 LN_SELCSR(sc, LN_CSR0);
1251 LN_WRCSR(sc, LN_CSR0_STOP);
1253 if (idx < DEPCA_DE200) {
1254 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1255 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1258 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1261 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
1263 * Renable shared RAM.
1265 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1267 le_intrvec[sc->le_if.if_dunit] = depca_intr;
1268 if (!lance_init_adapmem(sc))
1271 sc->if_reset = lance_reset;
1272 sc->if_init = lance_init;
1273 sc->le_if.if_start = lance_start;
1274 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1277 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1278 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1279 *msize = sc->lance_ramsize;
1280 return DEPCA_IOSPACE;
1284 depca_intr(struct le_softc *sc)
1286 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1291 * Here's as good a place to describe our paritioning of the
1292 * LANCE shared RAM space. (NOTE: this driver does not yet support
1293 * the concept of a LANCE being able to DMA).
1295 * First is the 24 (00:23) bytes for LANCE Initialization Block
1296 * Next are the recieve descriptors. The number is calculated from
1297 * how many LN_BUFSIZE buffers we can allocate (this number must
1298 * be a power of 2). Next are the transmit descriptors. The amount
1299 * of transmit descriptors is derived from the size of the RAM
1300 * divided by 1K. Now come the receive buffers (one for each receive
1301 * descriptor). Finally is the transmit heap. (no fixed buffers are
1302 * allocated so as to make the most use of the limited space).
1305 lance_init_adapmem(struct le_softc *sc)
1307 lance_addr_t rxbufoffset;
1308 lance_addr_t rxdescoffset, txdescoffset;
1309 unsigned rxdescs, txdescs;
1312 * First calculate how many descriptors we heap.
1313 * Note this assumes the ramsize is a power of two.
1315 sc->lance_rxbufsize = LN_BUFSIZE;
1317 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1320 if (rxdescs > LN_DESC_MAX) {
1321 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1322 rxdescs = LN_DESC_MAX;
1324 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1325 if (txdescs > LN_DESC_MAX)
1326 txdescs = LN_DESC_MAX;
1329 * Now calculate where everything goes in memory
1331 rxdescoffset = sizeof(ln_initb_t);
1332 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1333 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1335 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1337 * Remember these for debugging.
1339 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1340 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1343 * Initialize the rings.
1345 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1346 rxdescs, rxbufoffset, rxdescoffset))
1348 sc->lance_rxinfo.ri_heap = rxbufoffset;
1349 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1351 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1352 txdescs, 0, txdescoffset))
1354 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1355 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1358 * Set CSR1 and CSR2 to the address of the init block (which
1359 * for us is always 0.
1361 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1362 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1367 lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1368 unsigned ndescs, lance_addr_t bufoffset, lance_addr_t descoffset)
1370 lance_descinfo_t *di;
1373 * Initialize the ring pointer in the LANCE InitBlock
1375 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1376 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1377 rp->r_log2_size = ffs(ndescs) - 1;
1380 * Allocate the ring entry descriptors and initialize
1381 * our ring information data structure. All these are
1382 * our copies and do not live in the LANCE RAM.
1384 ri->ri_first = malloc(ndescs * sizeof(*di), M_DEVBUF, M_WAITOK);
1385 ri->ri_free = ri->ri_max = ndescs;
1386 ri->ri_last = ri->ri_first + ri->ri_max;
1387 for (di = ri->ri_first; di < ri->ri_last; di++) {
1388 di->di_addr = sc->le_membase + descoffset;
1391 di->di_bufaddr = bufoffset;
1392 di->di_buflen = sc->lance_rxbufsize;
1393 bufoffset += sc->lance_rxbufsize;
1395 descoffset += sizeof(ln_desc_t);
1401 lance_dumpcsrs(struct le_softc *sc, const char *id)
1403 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1404 LN_SELCSR(sc, LN_CSR0);
1405 printf(" csr0=%04x", LN_RDCSR(sc));
1406 LN_SELCSR(sc, LN_CSR1);
1407 printf(" csr1=%04x", LN_RDCSR(sc));
1408 LN_SELCSR(sc, LN_CSR2);
1409 printf(" csr2=%04x", LN_RDCSR(sc));
1410 LN_SELCSR(sc, LN_CSR3);
1411 printf(" csr3=%04x\n", LN_RDCSR(sc));
1412 LN_SELCSR(sc, LN_CSR0);
1416 lance_reset(struct le_softc *sc)
1420 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1422 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1423 LN_WRCSR(sc, LN_CSR0_STOP);
1426 sc->le_flags &= ~IFF_UP;
1427 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1429 le_multi_filter(sc); /* initialize the multicast table */
1430 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1431 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1432 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1433 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1434 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1436 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1437 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1438 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1439 if (sc->le_if.if_flags & IFF_PROMISC) {
1440 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1442 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1445 * We force the init block to be at the start
1446 * of the LANCE's RAM buffer.
1448 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1449 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1450 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1451 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1453 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1456 * clear INITDONE and INIT the chip
1458 LN_SELCSR(sc, LN_CSR0);
1459 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1464 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1469 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1470 lance_dumpcsrs(sc, "lance_reset: reset failure");
1472 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1473 sc->le_if.if_flags |= IFF_UP;
1474 sc->le_flags |= IFF_UP;
1479 lance_init(void *xsc)
1481 struct le_softc *sc = (struct le_softc *)xsc;
1483 lance_descinfo_t *di;
1487 if (sc->le_if.if_flags & IFF_RUNNING) {
1491 * If we were running, requeue any pending transmits.
1493 ri = &sc->lance_txinfo;
1494 di = ri->ri_nextout;
1495 while (ri->ri_free < ri->ri_max) {
1496 if (--di == ri->ri_first)
1497 di = ri->ri_nextout - 1;
1498 if (di->di_mbuf == NULL)
1500 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1509 * Reset the transmit ring. Make sure we own all the buffers.
1510 * Also reset the transmit heap.
1512 sc->le_if.if_flags &= ~IFF_OACTIVE;
1513 ri = &sc->lance_txinfo;
1514 for (di = ri->ri_first; di < ri->ri_last; di++) {
1515 if (di->di_mbuf != NULL) {
1516 m_freem(di->di_mbuf);
1520 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1521 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1523 LN_PUTDESC(sc, &desc, di->di_addr);
1525 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1526 ri->ri_free = ri->ri_max;
1527 ri->ri_outptr = ri->ri_heap;
1528 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1530 ri = &sc->lance_rxinfo;
1531 desc.d_flag = LN_DFLAG_OWNER;
1532 desc.d_buflen = 0 - sc->lance_rxbufsize;
1533 for (di = ri->ri_first; di < ri->ri_last; di++) {
1534 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1535 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1536 LN_PUTDESC(sc, &desc, di->di_addr);
1538 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1539 ri->ri_outptr = ri->ri_heap;
1540 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1543 if (sc->le_if.if_flags & IFF_UP) {
1544 sc->le_if.if_flags |= IFF_RUNNING;
1545 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1546 /* lance_dumpcsrs(sc, "lance_init: up"); */
1547 lance_start(&sc->le_if);
1549 /* lance_dumpcsrs(sc, "lance_init: down"); */
1550 sc->le_if.if_flags &= ~IFF_RUNNING;
1555 lance_intr(struct le_softc *sc)
1559 oldcsr = LN_RDCSR(sc);
1560 oldcsr &= ~LN_CSR0_ENABINTR;
1561 LN_WRCSR(sc, oldcsr);
1562 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1564 if (oldcsr & LN_CSR0_ERRSUM) {
1565 if (oldcsr & LN_CSR0_MISS) {
1567 * LN_CSR0_MISS is signaled when the LANCE receiver
1568 * loses a packet because it doesn't own a receive
1569 * descriptor. Rev. D LANCE chips, which are no
1570 * longer used, require a chip reset as described
1573 LN_STAT(rx_misses++);
1575 if (oldcsr & LN_CSR0_MEMERROR) {
1576 LN_STAT(memory_errors++);
1577 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1584 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1589 if (oldcsr & LN_CSR0_TXINT) {
1590 if (lance_tx_intr(sc))
1591 lance_start(&sc->le_if);
1594 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1595 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1599 lance_rx_intr(struct le_softc *sc)
1601 lance_ring_t *ri = &sc->lance_rxinfo;
1602 lance_descinfo_t *eop;
1604 int ndescs, total_len, rxdescs;
1606 LN_STAT(rx_intrs++);
1608 for (rxdescs = 0;;) {
1610 * Now to try to find the end of this packet chain.
1612 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1614 * If we don't own this descriptor, the packet ain't
1615 * all here so return because we are done.
1617 LN_GETDESC(sc, &desc, eop->di_addr);
1618 if (desc.d_flag & LN_DFLAG_OWNER)
1621 * In case we have missed a packet and gotten the
1622 * LANCE confused, make sure we are pointing at the
1623 * start of a packet. If we aren't, something is really
1624 * strange so reinit the LANCE.
1626 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1627 LN_STAT(rx_buferror++);
1630 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1631 LN_STAT(rx_badsop++);
1634 if (desc.d_flag & LN_DFLAG_EOP)
1636 if (++eop == ri->ri_last)
1640 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1641 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1643 * Valid Packet -- If the SOP is less than or equal to the EOP
1644 * or the length is less than the receive buffer size, then the
1645 * packet is contiguous in memory and can be copied in one shot.
1646 * Otherwise we need to copy two segments to get the entire
1649 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1650 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1651 total_len, total_len, NULL);
1652 LN_STAT(rx_contig++);
1654 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1656 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1657 sc->le_membase + ri->ri_first->di_bufaddr);
1658 LN_STAT(rx_noncontig++);
1662 * If the packet is bad, increment the
1665 sc->le_if.if_ierrors++;
1666 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1667 LN_STAT(rx_badcrc++);
1668 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1669 LN_STAT(rx_badalign++);
1670 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1671 LN_STAT(rx_badframe++);
1673 sc->le_if.if_ipackets++;
1674 LN_STAT(rx_ndescs[ndescs-1]++);
1676 while (ndescs-- > 0) {
1677 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1678 if (++ri->ri_nextin == ri->ri_last)
1679 ri->ri_nextin = ri->ri_first;
1682 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1683 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1689 lance_start(struct ifnet *ifp)
1691 struct le_softc *sc = (struct le_softc *) ifp;
1692 lance_ring_t *ri = &sc->lance_txinfo;
1693 lance_descinfo_t *di;
1696 struct mbuf *m, *m0;
1699 if ((ifp->if_flags & IFF_RUNNING) == 0)
1703 IF_DEQUEUE(&ifp->if_snd, m);
1708 * Make the packet meets the minimum size for Ethernet.
1709 * The slop is so that we also use an even number of longwards.
1711 len = ETHERMIN + sizeof(struct ether_header);
1712 if (m->m_pkthdr.len > len)
1713 len = m->m_pkthdr.len;
1715 slop = (8 - len) & 3;
1717 * If there are no free ring entries (there must be always
1718 * one owned by the host), or there's not enough space for
1719 * this packet, or this packet would wrap around the end
1720 * of LANCE RAM then wait for the transmits to empty for
1721 * space and ring entries to become available.
1723 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1725 * Try to see if we can free up anything off the transit ring.
1727 if (lance_tx_intr(sc) > 0) {
1728 LN_STAT(tx_drains[0]++);
1729 IF_PREPEND(&ifp->if_snd, m);
1732 LN_STAT(tx_nospc[0]++);
1736 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1738 * Since the packet won't fit in the end of the transmit
1739 * heap, see if there is space at the beginning of the transmit
1740 * heap. If not, try again when there is space.
1742 LN_STAT(tx_orphaned++);
1743 slop += ri->ri_heapend - ri->ri_outptr;
1744 if (len + slop > ri->ri_outsize) {
1745 LN_STAT(tx_nospc[1]++);
1749 * Point to the beginning of the heap
1751 ri->ri_outptr = ri->ri_heap;
1752 LN_STAT(tx_adoptions++);
1756 * Initialize the descriptor (saving the buffer address,
1757 * buffer length, and mbuf) and write the packet out
1760 di = ri->ri_nextout;
1761 di->di_bufaddr = ri->ri_outptr;
1762 di->di_buflen = len + slop;
1764 bp = sc->le_membase + di->di_bufaddr;
1765 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1766 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1770 * Zero out the remainder if needed (< ETHERMIN).
1772 if (m->m_pkthdr.len < len)
1773 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1776 * Finally, copy out the descriptor and tell the
1777 * LANCE to transmit!.
1779 desc.d_buflen = 0 - len;
1780 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1781 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1782 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1783 LN_PUTDESC(sc, &desc, di->di_addr);
1784 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1787 * Do our bookkeeping with our transmit heap.
1788 * (if we wrap, point back to the beginning).
1790 ri->ri_outptr += di->di_buflen;
1791 ri->ri_outsize -= di->di_buflen;
1792 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1793 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1795 if (ri->ri_outptr == ri->ri_heapend)
1796 ri->ri_outptr = ri->ri_heap;
1799 if (++ri->ri_nextout == ri->ri_last)
1800 ri->ri_nextout = ri->ri_first;
1801 LN_MINSTAT(low_txfree, ri->ri_free);
1804 ifp->if_flags |= IFF_OACTIVE;
1805 IF_PREPEND(&ifp->if_snd, m);
1810 lance_tx_intr(struct le_softc *sc)
1812 lance_ring_t *ri = &sc->lance_txinfo;
1815 LN_STAT(tx_intrs++);
1816 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1819 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1820 if (desc.d_flag & LN_DFLAG_OWNER)
1823 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1824 sc->le_if.if_collisions++;
1825 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1826 LN_STAT(tx_deferred++);
1827 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1828 LN_STAT(tx_single_collisions++);
1829 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1830 LN_STAT(tx_multiple_collisions++);
1832 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1833 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1834 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1835 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1837 LN_STAT(tx_excessive_collisions++);
1838 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1840 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1841 tdr, (tdr*99)/1000, (tdr*117)/1000);
1844 if (desc.d_status & LN_DSTS_TxBUFERROR)
1845 LN_STAT(tx_buferror++);
1846 sc->le_if.if_oerrors++;
1847 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1851 LN_STAT(tx_late_collisions++);
1855 m_freem(ri->ri_nextin->di_mbuf);
1856 ri->ri_nextin->di_mbuf = NULL;
1857 sc->le_if.if_opackets++;
1859 ri->ri_outsize += ri->ri_nextin->di_buflen;
1860 if (++ri->ri_nextin == ri->ri_last)
1861 ri->ri_nextin = ri->ri_first;
1862 sc->le_if.if_flags &= ~IFF_OACTIVE;
1865 if (ri->ri_free == ri->ri_max)
1866 LN_STAT(tx_emptied++);
1867 /* LN_STAT(tx_intr_descs[xmits]++); */
1868 LN_MAXSTAT(tx_intr_hidescs, xmits);
1871 #endif /* !defined(LE_NOLANCE) */