1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.9 2004/03/23 22:19:04 hsu Exp $ */
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
38 * $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $
42 * Driver for 3c990 (Typhoon) Ethernet ASIC
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/kernel.h>
51 #include <sys/socket.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #include <netinet/if_ether.h>
65 #include <sys/in_cksum.h>
67 #include <net/if_media.h>
71 #include <vm/vm.h> /* for vtophys */
72 #include <vm/pmap.h> /* for vtophys */
73 #include <machine/clock.h> /* for DELAY */
74 #include <machine/bus_pio.h>
75 #include <machine/bus_memio.h>
76 #include <machine/bus.h>
77 #include <machine/resource.h>
81 #include "../mii_layer/mii.h"
82 #include "../mii_layer/miivar.h"
83 #include <bus/pci/pcireg.h>
84 #include <bus/pci/pcivar.h>
86 #define TXP_USEIOSPACE
87 #define __STRICT_ALIGNMENT
89 #include "if_txpreg.h"
93 * Various supported device vendors/types and their names.
95 static struct txp_type txp_devs[] = {
96 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
97 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
99 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
101 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
103 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
105 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
107 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
111 static int txp_probe (device_t);
112 static int txp_attach (device_t);
113 static int txp_detach (device_t);
114 static void txp_intr (void *);
115 static void txp_tick (void *);
116 static int txp_shutdown (device_t);
117 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
118 static void txp_start (struct ifnet *);
119 static void txp_stop (struct txp_softc *);
120 static void txp_init (void *);
121 static void txp_watchdog (struct ifnet *);
123 static void txp_release_resources (struct txp_softc *);
124 static int txp_chip_init (struct txp_softc *);
125 static int txp_reset_adapter (struct txp_softc *);
126 static int txp_download_fw (struct txp_softc *);
127 static int txp_download_fw_wait (struct txp_softc *);
128 static int txp_download_fw_section (struct txp_softc *,
129 struct txp_fw_section_header *, int);
130 static int txp_alloc_rings (struct txp_softc *);
131 static int txp_rxring_fill (struct txp_softc *);
132 static void txp_rxring_empty (struct txp_softc *);
133 static void txp_set_filter (struct txp_softc *);
135 static int txp_cmd_desc_numfree (struct txp_softc *);
136 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
137 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
138 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
139 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
140 struct txp_rsp_desc **, int);
141 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
142 struct txp_rsp_desc **);
143 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
144 struct txp_rsp_desc *);
145 static void txp_capabilities (struct txp_softc *);
147 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
148 static int txp_ifmedia_upd (struct ifnet *);
150 static void txp_show_descriptor (void *);
152 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
153 static void txp_rxbuf_reclaim (struct txp_softc *);
154 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
156 #ifdef TXP_USEIOSPACE
157 #define TXP_RES SYS_RES_IOPORT
158 #define TXP_RID TXP_PCI_LOIO
160 #define TXP_RES SYS_RES_MEMORY
161 #define TXP_RID TXP_PCI_LOMEM
164 static device_method_t txp_methods[] = {
165 /* Device interface */
166 DEVMETHOD(device_probe, txp_probe),
167 DEVMETHOD(device_attach, txp_attach),
168 DEVMETHOD(device_detach, txp_detach),
169 DEVMETHOD(device_shutdown, txp_shutdown),
173 static driver_t txp_driver = {
176 sizeof(struct txp_softc)
179 static devclass_t txp_devclass;
181 DECLARE_DUMMY_MODULE(if_txp);
182 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
192 while(t->txp_name != NULL) {
193 if ((pci_get_vendor(dev) == t->txp_vid) &&
194 (pci_get_device(dev) == t->txp_did)) {
195 device_set_desc(dev, t->txp_name);
208 struct txp_softc *sc;
213 int unit, error = 0, rid;
215 sc = device_get_softc(dev);
216 unit = device_get_unit(dev);
221 * Map control/status registers.
223 command = pci_read_config(dev, PCIR_COMMAND, 4);
224 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
225 pci_write_config(dev, PCIR_COMMAND, command, 4);
226 command = pci_read_config(dev, PCIR_COMMAND, 4);
228 #ifdef TXP_USEIOSPACE
229 if (!(command & PCIM_CMD_PORTEN)) {
230 device_printf(dev, "failed to enable I/O ports!\n");
235 if (!(command & PCIM_CMD_MEMEN)) {
236 device_printf(dev, "failed to enable memory mapping!\n");
243 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid,
244 0, ~0, 1, RF_ACTIVE);
246 if (sc->sc_res == NULL) {
247 device_printf(dev, "couldn't map ports/memory\n");
252 sc->sc_bt = rman_get_bustag(sc->sc_res);
253 sc->sc_bh = rman_get_bushandle(sc->sc_res);
255 /* Allocate interrupt */
257 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
258 RF_SHAREABLE | RF_ACTIVE);
260 if (sc->sc_irq == NULL) {
261 device_printf(dev, "couldn't map interrupt\n");
262 txp_release_resources(sc);
267 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
268 txp_intr, sc, &sc->sc_intrhand);
271 txp_release_resources(sc);
272 device_printf(dev, "couldn't set up irq\n");
276 if (txp_chip_init(sc)) {
277 txp_release_resources(sc);
281 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
282 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
283 error = txp_download_fw(sc);
284 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
288 txp_release_resources(sc);
292 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
293 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
294 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
296 if (txp_alloc_rings(sc)) {
297 txp_release_resources(sc);
301 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
302 NULL, NULL, NULL, 1)) {
303 txp_release_resources(sc);
307 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
308 &p1, &p2, NULL, 1)) {
309 txp_release_resources(sc);
315 sc->sc_arpcom.ac_enaddr[0] = ((uint8_t *)&p1)[1];
316 sc->sc_arpcom.ac_enaddr[1] = ((uint8_t *)&p1)[0];
317 sc->sc_arpcom.ac_enaddr[2] = ((uint8_t *)&p2)[3];
318 sc->sc_arpcom.ac_enaddr[3] = ((uint8_t *)&p2)[2];
319 sc->sc_arpcom.ac_enaddr[4] = ((uint8_t *)&p2)[1];
320 sc->sc_arpcom.ac_enaddr[5] = ((uint8_t *)&p2)[0];
322 printf("txp%d: Ethernet address %6D\n", unit,
323 sc->sc_arpcom.ac_enaddr, ":");
327 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
328 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
329 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
330 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
331 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
332 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
333 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
334 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
336 sc->sc_xcvr = TXP_XCVR_AUTO;
337 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
338 NULL, NULL, NULL, 0);
339 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
341 ifp = &sc->sc_arpcom.ac_if;
343 if_initname(ifp, "txp", unit);
344 ifp->if_mtu = ETHERMTU;
345 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
346 ifp->if_ioctl = txp_ioctl;
347 ifp->if_output = ether_output;
348 ifp->if_start = txp_start;
349 ifp->if_watchdog = txp_watchdog;
350 ifp->if_init = txp_init;
351 ifp->if_baudrate = 100000000;
352 ifp->if_snd.ifq_maxlen = TX_ENTRIES;
353 ifp->if_hwassist = 0;
354 txp_capabilities(sc);
357 * Attach us everywhere
359 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr);
360 callout_handle_init(&sc->sc_tick);
364 txp_release_resources(sc);
372 struct txp_softc *sc;
376 sc = device_get_softc(dev);
377 ifp = &sc->sc_arpcom.ac_if;
382 ifmedia_removeall(&sc->sc_ifmedia);
385 for (i = 0; i < RXBUF_ENTRIES; i++)
386 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
388 txp_release_resources(sc);
394 txp_release_resources(sc)
395 struct txp_softc *sc;
401 if (sc->sc_intrhand != NULL)
402 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
404 if (sc->sc_irq != NULL)
405 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
407 if (sc->sc_res != NULL)
408 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
410 if (sc->sc_ldata != NULL)
411 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
418 struct txp_softc *sc;
420 /* disable interrupts */
421 WRITE_REG(sc, TXP_IER, 0);
422 WRITE_REG(sc, TXP_IMR,
423 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
424 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
427 /* ack all interrupts */
428 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
429 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
430 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
431 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
432 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
434 if (txp_reset_adapter(sc))
437 /* disable interrupts */
438 WRITE_REG(sc, TXP_IER, 0);
439 WRITE_REG(sc, TXP_IMR,
440 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
441 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
444 /* ack all interrupts */
445 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
446 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
447 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
448 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
449 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
455 txp_reset_adapter(sc)
456 struct txp_softc *sc;
461 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
463 WRITE_REG(sc, TXP_SRR, 0);
465 /* Should wait max 6 seconds */
466 for (i = 0; i < 6000; i++) {
467 r = READ_REG(sc, TXP_A2H_0);
468 if (r == STAT_WAITING_FOR_HOST_REQUEST)
473 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
474 device_printf(sc->sc_dev, "reset hung\n");
483 struct txp_softc *sc;
485 struct txp_fw_file_header *fileheader;
486 struct txp_fw_section_header *secthead;
488 u_int32_t r, i, ier, imr;
490 ier = READ_REG(sc, TXP_IER);
491 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
493 imr = READ_REG(sc, TXP_IMR);
494 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
496 for (i = 0; i < 10000; i++) {
497 r = READ_REG(sc, TXP_A2H_0);
498 if (r == STAT_WAITING_FOR_HOST_REQUEST)
502 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
503 device_printf(sc->sc_dev, "not waiting for host request\n");
508 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
510 fileheader = (struct txp_fw_file_header *)tc990image;
511 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
512 device_printf(sc->sc_dev, "fw invalid magic\n");
516 /* Tell boot firmware to get ready for image */
517 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
518 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
520 if (txp_download_fw_wait(sc)) {
521 device_printf(sc->sc_dev, "fw wait failed, initial\n");
525 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
526 sizeof(struct txp_fw_file_header));
528 for (sect = 0; sect < fileheader->nsections; sect++) {
529 if (txp_download_fw_section(sc, secthead, sect))
531 secthead = (struct txp_fw_section_header *)
532 (((u_int8_t *)secthead) + secthead->nbytes +
536 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
538 for (i = 0; i < 10000; i++) {
539 r = READ_REG(sc, TXP_A2H_0);
540 if (r == STAT_WAITING_FOR_BOOT)
544 if (r != STAT_WAITING_FOR_BOOT) {
545 device_printf(sc->sc_dev, "not waiting for boot\n");
549 WRITE_REG(sc, TXP_IER, ier);
550 WRITE_REG(sc, TXP_IMR, imr);
556 txp_download_fw_wait(sc)
557 struct txp_softc *sc;
561 for (i = 0; i < 10000; i++) {
562 r = READ_REG(sc, TXP_ISR);
563 if (r & TXP_INT_A2H_0)
568 if (!(r & TXP_INT_A2H_0)) {
569 device_printf(sc->sc_dev, "fw wait failed comm0\n");
573 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
575 r = READ_REG(sc, TXP_A2H_0);
576 if (r != STAT_WAITING_FOR_SEGMENT) {
577 device_printf(sc->sc_dev, "fw not waiting for segment\n");
584 txp_download_fw_section(sc, sect, sectnum)
585 struct txp_softc *sc;
586 struct txp_fw_section_header *sect;
594 /* Skip zero length sections */
595 if (sect->nbytes == 0)
598 /* Make sure we aren't past the end of the image */
599 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
600 if (rseg >= sizeof(tc990image)) {
601 device_printf(sc->sc_dev, "fw invalid section address, "
602 "section %d\n", sectnum);
606 /* Make sure this section doesn't go past the end */
607 rseg += sect->nbytes;
608 if (rseg >= sizeof(tc990image)) {
609 device_printf(sc->sc_dev, "fw truncated section %d\n",
614 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
615 dma = vtophys(sc->sc_fwbuf);
618 * dummy up mbuf and verify section checksum
621 m.m_next = m.m_nextpkt = NULL;
622 m.m_len = sect->nbytes;
623 m.m_data = sc->sc_fwbuf;
625 csum = in_cksum(&m, sect->nbytes);
626 if (csum != sect->cksum) {
627 device_printf(sc->sc_dev, "fw section %d, bad "
628 "cksum (expected 0x%x got 0x%x)\n",
629 sectnum, sect->cksum, csum);
634 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
635 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
636 WRITE_REG(sc, TXP_H2A_3, sect->addr);
637 WRITE_REG(sc, TXP_H2A_4, 0);
638 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
639 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
641 if (txp_download_fw_wait(sc)) {
642 device_printf(sc->sc_dev, "fw wait failed, "
643 "section %d\n", sectnum);
655 struct txp_softc *sc = vsc;
656 struct txp_hostvar *hv = sc->sc_hostvar;
659 /* mask all interrupts */
660 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
661 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
662 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
663 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
664 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
666 isr = READ_REG(sc, TXP_ISR);
668 WRITE_REG(sc, TXP_ISR, isr);
670 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
671 txp_rx_reclaim(sc, &sc->sc_rxhir);
672 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
673 txp_rx_reclaim(sc, &sc->sc_rxlor);
675 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
676 txp_rxbuf_reclaim(sc);
678 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
679 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
680 txp_tx_reclaim(sc, &sc->sc_txhir);
682 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
683 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
684 txp_tx_reclaim(sc, &sc->sc_txlor);
686 isr = READ_REG(sc, TXP_ISR);
689 /* unmask all interrupts */
690 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
692 txp_start(&sc->sc_arpcom.ac_if);
698 txp_rx_reclaim(sc, r)
699 struct txp_softc *sc;
700 struct txp_rx_ring *r;
702 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
703 struct txp_rx_desc *rxd;
705 struct txp_swdesc *sd = NULL;
706 u_int32_t roff, woff;
707 struct ether_header *eh = NULL;
711 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
713 while (roff != woff) {
715 if (rxd->rx_flags & RX_FLAGS_ERROR) {
716 device_printf(sc->sc_dev, "error 0x%x\n",
722 /* retrieve stashed pointer */
728 m->m_pkthdr.len = m->m_len = rxd->rx_len;
730 #ifdef __STRICT_ALIGNMENT
733 * XXX Nice chip, except it won't accept "off by 2"
734 * buffers, so we're force to copy. Supposedly
735 * this will be fixed in a newer firmware rev
736 * and this will be temporary.
740 MGETHDR(mnew, M_DONTWAIT, MT_DATA);
745 if (m->m_len > (MHLEN - 2)) {
746 MCLGET(mnew, M_DONTWAIT);
747 if (!(mnew->m_flags & M_EXT)) {
753 mnew->m_pkthdr.rcvif = ifp;
755 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
756 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
762 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
763 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
764 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
765 m->m_pkthdr.csum_flags |=
766 CSUM_IP_CHECKED|CSUM_IP_VALID;
768 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
769 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
770 m->m_pkthdr.csum_flags |=
771 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
772 m->m_pkthdr.csum_data = 0xffff;
775 eh = mtod(m, struct ether_header *);
776 /* Remove header from mbuf and pass it on. */
777 m_adj(m, sizeof(struct ether_header));
779 if (rxd->rx_stat & RX_STAT_VLAN) {
780 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16));
784 ether_input(ifp, eh, m);
788 roff += sizeof(struct txp_rx_desc);
789 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
803 txp_rxbuf_reclaim(sc)
804 struct txp_softc *sc;
806 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
807 struct txp_hostvar *hv = sc->sc_hostvar;
808 struct txp_rxbuf_desc *rbd;
809 struct txp_swdesc *sd;
812 if (!(ifp->if_flags & IFF_RUNNING))
815 i = sc->sc_rxbufprod;
816 rbd = sc->sc_rxbufs + i;
820 if (sd->sd_mbuf != NULL)
823 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA);
824 if (sd->sd_mbuf == NULL)
827 MCLGET(sd->sd_mbuf, M_DONTWAIT);
828 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
830 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
831 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
833 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
837 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
839 if (++i == RXBUF_ENTRIES) {
846 sc->sc_rxbufprod = i;
851 m_freem(sd->sd_mbuf);
857 * Reclaim mbufs and entries from a transmit ring.
860 txp_tx_reclaim(sc, r)
861 struct txp_softc *sc;
862 struct txp_tx_ring *r;
864 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
865 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
866 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
867 struct txp_tx_desc *txd = r->r_desc + cons;
868 struct txp_swdesc *sd = sc->sc_txd + cons;
871 while (cons != idx) {
875 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
876 TX_FLAGS_TYPE_DATA) {
885 ifp->if_flags &= ~IFF_OACTIVE;
887 if (++cons == TX_ENTRIES) {
909 struct txp_softc *sc;
911 sc = device_get_softc(dev);
913 /* mask all interrupts */
914 WRITE_REG(sc, TXP_IMR,
915 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
916 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
919 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
920 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
921 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
928 struct txp_softc *sc;
930 struct txp_boot_record *boot;
931 struct txp_ldata *ld;
936 boot = &ld->txp_boot;
942 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
943 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
944 boot->br_hostvar_hi = 0;
945 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
947 /* hi priority tx ring */
948 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
949 boot->br_txhipri_hi = 0;
950 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
951 sc->sc_txhir.r_reg = TXP_H2A_1;
952 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
953 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
954 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
956 /* lo priority tx ring */
957 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
958 boot->br_txlopri_hi = 0;
959 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
960 sc->sc_txlor.r_reg = TXP_H2A_3;
961 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
962 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
963 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
965 /* high priority rx ring */
966 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
967 boot->br_rxhipri_hi = 0;
968 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
969 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
970 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
971 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
973 /* low priority rx ring */
974 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
975 boot->br_rxlopri_hi = 0;
976 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
977 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
978 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
979 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
982 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
983 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
985 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
986 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
987 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
988 sc->sc_cmdring.lastwrite = 0;
991 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
992 boot->br_resp_lo = vtophys(&ld->txp_rspring);
993 boot->br_resp_hi = 0;
994 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
995 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
996 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
997 sc->sc_rspring.lastwrite = 0;
999 /* receive buffer ring */
1000 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
1001 boot->br_rxbuf_hi = 0;
1002 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
1003 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
1005 for (i = 0; i < RXBUF_ENTRIES; i++) {
1006 struct txp_swdesc *sd;
1007 if (sc->sc_rxbufs[i].rb_sd != NULL)
1009 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
1010 M_DEVBUF, M_NOWAIT);
1011 if (sc->sc_rxbufs[i].rb_sd == NULL)
1013 sd = sc->sc_rxbufs[i].rb_sd;
1016 sc->sc_rxbufprod = 0;
1019 bzero(&ld->txp_zero, sizeof(u_int32_t));
1020 boot->br_zero_lo = vtophys(&ld->txp_zero);
1021 boot->br_zero_hi = 0;
1023 /* See if it's waiting for boot, and try to boot it */
1024 for (i = 0; i < 10000; i++) {
1025 r = READ_REG(sc, TXP_A2H_0);
1026 if (r == STAT_WAITING_FOR_BOOT)
1031 if (r != STAT_WAITING_FOR_BOOT) {
1032 device_printf(sc->sc_dev, "not waiting for boot\n");
1036 WRITE_REG(sc, TXP_H2A_2, 0);
1037 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
1038 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
1040 /* See if it booted */
1041 for (i = 0; i < 10000; i++) {
1042 r = READ_REG(sc, TXP_A2H_0);
1043 if (r == STAT_RUNNING)
1047 if (r != STAT_RUNNING) {
1048 device_printf(sc->sc_dev, "fw not running\n");
1052 /* Clear TX and CMD ring write registers */
1053 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1054 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1055 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1056 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1062 txp_ioctl(ifp, command, data, cr)
1068 struct txp_softc *sc = ifp->if_softc;
1069 struct ifreq *ifr = (struct ifreq *)data;
1074 if ((error = ether_ioctl(ifp, command, data)) > 0) {
1083 error = ether_ioctl(ifp, command, data);
1086 if (ifp->if_flags & IFF_UP) {
1089 if (ifp->if_flags & IFF_RUNNING)
1096 * Multicast list has changed; set the hardware
1097 * filter accordingly.
1104 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1118 struct txp_softc *sc;
1122 struct txp_swdesc *sd;
1124 ifp = &sc->sc_arpcom.ac_if;
1126 for (i = 0; i < RXBUF_ENTRIES; i++) {
1127 sd = sc->sc_rxbufs[i].rb_sd;
1128 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA);
1129 if (sd->sd_mbuf == NULL)
1132 MCLGET(sd->sd_mbuf, M_DONTWAIT);
1133 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1134 m_freem(sd->sd_mbuf);
1137 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1138 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1140 sc->sc_rxbufs[i].rb_paddrlo =
1141 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1142 sc->sc_rxbufs[i].rb_paddrhi = 0;
1145 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1146 sizeof(struct txp_rxbuf_desc);
1152 txp_rxring_empty(sc)
1153 struct txp_softc *sc;
1156 struct txp_swdesc *sd;
1158 if (sc->sc_rxbufs == NULL)
1161 for (i = 0; i < RXBUF_ENTRIES; i++) {
1162 if (&sc->sc_rxbufs[i] == NULL)
1164 sd = sc->sc_rxbufs[i].rb_sd;
1167 if (sd->sd_mbuf != NULL) {
1168 m_freem(sd->sd_mbuf);
1180 struct txp_softc *sc;
1187 ifp = &sc->sc_arpcom.ac_if;
1189 if (ifp->if_flags & IFF_RUNNING)
1196 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1197 NULL, NULL, NULL, 1);
1199 /* Set station address. */
1200 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1201 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1202 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1203 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1204 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1205 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1206 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1207 NULL, NULL, NULL, 1);
1211 txp_rxring_fill(sc);
1213 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1214 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1216 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1217 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1218 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1219 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1220 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1221 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1223 ifp->if_flags |= IFF_RUNNING;
1224 ifp->if_flags &= ~IFF_OACTIVE;
1227 sc->sc_tick = timeout(txp_tick, sc, hz);
1236 struct txp_softc *sc = vsc;
1237 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1238 struct txp_rsp_desc *rsp = NULL;
1239 struct txp_ext_desc *ext;
1243 txp_rxbuf_reclaim(sc);
1245 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1248 if (rsp->rsp_numdesc != 6)
1250 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1251 NULL, NULL, NULL, 1))
1253 ext = (struct txp_ext_desc *)(rsp + 1);
1255 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1256 ext[4].ext_1 + ext[4].ext_4;
1257 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1259 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1261 ifp->if_opackets += rsp->rsp_par2;
1262 ifp->if_ipackets += ext[2].ext_3;
1266 free(rsp, M_DEVBUF);
1269 sc->sc_tick = timeout(txp_tick, sc, hz);
1278 struct txp_softc *sc = ifp->if_softc;
1279 struct txp_tx_ring *r = &sc->sc_txhir;
1280 struct txp_tx_desc *txd;
1281 struct txp_frag_desc *fxd;
1282 struct mbuf *m, *m0;
1283 struct txp_swdesc *sd;
1284 u_int32_t firstprod, firstcnt, prod, cnt;
1287 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1294 IF_DEQUEUE(&ifp->if_snd, m);
1301 sd = sc->sc_txd + prod;
1304 if ((TX_ENTRIES - cnt) < 4)
1307 txd = r->r_desc + prod;
1309 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1310 txd->tx_numdesc = 0;
1316 if (++prod == TX_ENTRIES)
1319 if (++cnt >= (TX_ENTRIES - 4))
1322 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1323 m->m_pkthdr.rcvif != NULL) {
1324 ifv = m->m_pkthdr.rcvif->if_softc;
1325 txd->tx_pflags = TX_PFLAGS_VLAN |
1326 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1329 if (m->m_pkthdr.csum_flags & CSUM_IP)
1330 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1333 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1334 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1335 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1336 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1339 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1340 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1343 if (++cnt >= (TX_ENTRIES - 4))
1348 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1349 fxd->frag_rsvd1 = 0;
1350 fxd->frag_len = m0->m_len;
1351 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1352 fxd->frag_addrhi = 0;
1353 fxd->frag_rsvd2 = 0;
1355 if (++prod == TX_ENTRIES) {
1356 fxd = (struct txp_frag_desc *)r->r_desc;
1367 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1375 ifp->if_flags |= IFF_OACTIVE;
1376 r->r_prod = firstprod;
1377 r->r_cnt = firstcnt;
1378 IF_PREPEND(&ifp->if_snd, m);
1383 * Handle simple commands sent to the typhoon
1386 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1387 struct txp_softc *sc;
1388 u_int16_t id, in1, *out1;
1389 u_int32_t in2, in3, *out2, *out3;
1392 struct txp_rsp_desc *rsp = NULL;
1394 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1401 *out1 = rsp->rsp_par1;
1403 *out2 = rsp->rsp_par2;
1405 *out3 = rsp->rsp_par3;
1406 free(rsp, M_DEVBUF);
1411 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1412 struct txp_softc *sc;
1415 struct txp_ext_desc *in_extp;
1417 struct txp_rsp_desc **rspp;
1420 struct txp_hostvar *hv = sc->sc_hostvar;
1421 struct txp_cmd_desc *cmd;
1422 struct txp_ext_desc *ext;
1426 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1427 device_printf(sc->sc_dev, "no free cmd descriptors\n");
1431 idx = sc->sc_cmdring.lastwrite;
1432 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1433 bzero(cmd, sizeof(*cmd));
1435 cmd->cmd_numdesc = in_extn;
1436 cmd->cmd_seq = seq = sc->sc_seq++;
1438 cmd->cmd_par1 = in1;
1439 cmd->cmd_par2 = in2;
1440 cmd->cmd_par3 = in3;
1441 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1442 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1444 idx += sizeof(struct txp_cmd_desc);
1445 if (idx == sc->sc_cmdring.size)
1448 for (i = 0; i < in_extn; i++) {
1449 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1450 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1452 idx += sizeof(struct txp_cmd_desc);
1453 if (idx == sc->sc_cmdring.size)
1457 sc->sc_cmdring.lastwrite = idx;
1459 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1464 for (i = 0; i < 10000; i++) {
1465 idx = hv->hv_resp_read_idx;
1466 if (idx != hv->hv_resp_write_idx) {
1468 if (txp_response(sc, idx, id, seq, rspp))
1475 if (i == 1000 || (*rspp) == NULL) {
1476 device_printf(sc->sc_dev, "0x%x command failed\n", id);
1484 txp_response(sc, ridx, id, seq, rspp)
1485 struct txp_softc *sc;
1489 struct txp_rsp_desc **rspp;
1491 struct txp_hostvar *hv = sc->sc_hostvar;
1492 struct txp_rsp_desc *rsp;
1494 while (ridx != hv->hv_resp_write_idx) {
1495 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1497 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1498 *rspp = (struct txp_rsp_desc *)malloc(
1499 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1500 M_DEVBUF, M_NOWAIT);
1501 if ((*rspp) == NULL)
1503 txp_rsp_fixup(sc, rsp, *rspp);
1507 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1508 device_printf(sc->sc_dev, "response error!\n");
1509 txp_rsp_fixup(sc, rsp, NULL);
1510 ridx = hv->hv_resp_read_idx;
1514 switch (rsp->rsp_id) {
1515 case TXP_CMD_CYCLE_STATISTICS:
1516 case TXP_CMD_MEDIA_STATUS_READ:
1518 case TXP_CMD_HELLO_RESPONSE:
1519 device_printf(sc->sc_dev, "hello\n");
1522 device_printf(sc->sc_dev, "unknown id(0x%x)\n",
1526 txp_rsp_fixup(sc, rsp, NULL);
1527 ridx = hv->hv_resp_read_idx;
1528 hv->hv_resp_read_idx = ridx;
1535 txp_rsp_fixup(sc, rsp, dst)
1536 struct txp_softc *sc;
1537 struct txp_rsp_desc *rsp, *dst;
1539 struct txp_rsp_desc *src = rsp;
1540 struct txp_hostvar *hv = sc->sc_hostvar;
1543 ridx = hv->hv_resp_read_idx;
1545 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1547 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1548 ridx += sizeof(struct txp_rsp_desc);
1549 if (ridx == sc->sc_rspring.size) {
1550 src = sc->sc_rspring.base;
1554 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1557 hv->hv_resp_read_idx = ridx;
1561 txp_cmd_desc_numfree(sc)
1562 struct txp_softc *sc;
1564 struct txp_hostvar *hv = sc->sc_hostvar;
1565 struct txp_boot_record *br = sc->sc_boot;
1566 u_int32_t widx, ridx, nfree;
1568 widx = sc->sc_cmdring.lastwrite;
1569 ridx = hv->hv_cmd_read_idx;
1572 /* Ring is completely free */
1573 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1576 nfree = br->br_cmd_siz -
1577 (widx - ridx + sizeof(struct txp_cmd_desc));
1579 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1582 return (nfree / sizeof(struct txp_cmd_desc));
1587 struct txp_softc *sc;
1591 ifp = &sc->sc_arpcom.ac_if;
1593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1595 untimeout(txp_tick, sc, sc->sc_tick);
1597 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1598 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1600 txp_rxring_empty(sc);
1613 txp_ifmedia_upd(ifp)
1616 struct txp_softc *sc = ifp->if_softc;
1617 struct ifmedia *ifm = &sc->sc_ifmedia;
1620 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1623 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1624 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1625 new_xcvr = TXP_XCVR_10_FDX;
1627 new_xcvr = TXP_XCVR_10_HDX;
1628 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1629 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1630 new_xcvr = TXP_XCVR_100_FDX;
1632 new_xcvr = TXP_XCVR_100_HDX;
1633 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1634 new_xcvr = TXP_XCVR_AUTO;
1639 if (sc->sc_xcvr == new_xcvr)
1642 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1643 NULL, NULL, NULL, 0);
1644 sc->sc_xcvr = new_xcvr;
1650 txp_ifmedia_sts(ifp, ifmr)
1652 struct ifmediareq *ifmr;
1654 struct txp_softc *sc = ifp->if_softc;
1655 struct ifmedia *ifm = &sc->sc_ifmedia;
1656 u_int16_t bmsr, bmcr, anlpar;
1658 ifmr->ifm_status = IFM_AVALID;
1659 ifmr->ifm_active = IFM_ETHER;
1661 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1662 &bmsr, NULL, NULL, 1))
1664 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1665 &bmsr, NULL, NULL, 1))
1668 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1669 &bmcr, NULL, NULL, 1))
1672 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1673 &anlpar, NULL, NULL, 1))
1676 if (bmsr & BMSR_LINK)
1677 ifmr->ifm_status |= IFM_ACTIVE;
1679 if (bmcr & BMCR_ISO) {
1680 ifmr->ifm_active |= IFM_NONE;
1681 ifmr->ifm_status = 0;
1685 if (bmcr & BMCR_LOOP)
1686 ifmr->ifm_active |= IFM_LOOP;
1688 if (bmcr & BMCR_AUTOEN) {
1689 if ((bmsr & BMSR_ACOMP) == 0) {
1690 ifmr->ifm_active |= IFM_NONE;
1694 if (anlpar & ANLPAR_T4)
1695 ifmr->ifm_active |= IFM_100_T4;
1696 else if (anlpar & ANLPAR_TX_FD)
1697 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1698 else if (anlpar & ANLPAR_TX)
1699 ifmr->ifm_active |= IFM_100_TX;
1700 else if (anlpar & ANLPAR_10_FD)
1701 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1702 else if (anlpar & ANLPAR_10)
1703 ifmr->ifm_active |= IFM_10_T;
1705 ifmr->ifm_active |= IFM_NONE;
1707 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1711 ifmr->ifm_active |= IFM_NONE;
1712 ifmr->ifm_status &= ~IFM_AVALID;
1717 txp_show_descriptor(d)
1720 struct txp_cmd_desc *cmd = d;
1721 struct txp_rsp_desc *rsp = d;
1722 struct txp_tx_desc *txd = d;
1723 struct txp_frag_desc *frgd = d;
1725 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1726 case CMD_FLAGS_TYPE_CMD:
1727 /* command descriptor */
1728 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1729 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1730 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1732 case CMD_FLAGS_TYPE_RESP:
1733 /* response descriptor */
1734 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1735 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1736 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1738 case CMD_FLAGS_TYPE_DATA:
1739 /* data header (assuming tx for now) */
1740 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1741 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1742 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1744 case CMD_FLAGS_TYPE_FRAG:
1745 /* fragment descriptor */
1746 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1747 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1748 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1751 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1752 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1753 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1754 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1762 struct txp_softc *sc;
1764 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1765 u_int32_t crc, carry, hashbit, hash[2];
1769 struct ifmultiaddr *ifma;
1772 if (ifp->if_flags & IFF_PROMISC) {
1773 filter = TXP_RXFILT_PROMISC;
1777 filter = TXP_RXFILT_DIRECT;
1779 if (ifp->if_flags & IFF_BROADCAST)
1780 filter |= TXP_RXFILT_BROADCAST;
1782 if (ifp->if_flags & IFF_ALLMULTI)
1783 filter |= TXP_RXFILT_ALLMULTI;
1785 hash[0] = hash[1] = 0;
1787 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1788 ifma = ifma->ifma_link.le_next) {
1789 if (ifma->ifma_addr->sa_family != AF_LINK)
1792 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1796 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1798 for (j = 0; j < 8; j++) {
1799 carry = ((crc & 0x80000000) ? 1 : 0) ^
1804 crc = (crc ^ TXP_POLYNOMIAL) |
1808 hashbit = (u_int16_t)(crc & (64 - 1));
1809 hash[hashbit / 32] |= (1 << hashbit % 32);
1813 filter |= TXP_RXFILT_HASHMULTI;
1814 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1815 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1821 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1822 NULL, NULL, NULL, 1);
1828 txp_capabilities(sc)
1829 struct txp_softc *sc;
1831 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1832 struct txp_rsp_desc *rsp = NULL;
1833 struct txp_ext_desc *ext;
1835 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1838 if (rsp->rsp_numdesc != 1)
1840 ext = (struct txp_ext_desc *)(rsp + 1);
1842 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1843 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1844 ifp->if_capabilities = 0;
1846 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1847 sc->sc_tx_capability |= OFFLOAD_VLAN;
1848 sc->sc_rx_capability |= OFFLOAD_VLAN;
1853 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1854 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1855 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1856 ifp->if_capabilities |= IFCAP_IPSEC;
1860 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1861 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1862 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1863 ifp->if_capabilities |= IFCAP_HWCSUM;
1864 ifp->if_hwassist |= CSUM_IP;
1867 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1869 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1871 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1872 ifp->if_capabilities |= IFCAP_HWCSUM;
1875 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1877 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1879 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1880 ifp->if_capabilities |= IFCAP_HWCSUM;
1882 ifp->if_capenable = ifp->if_capabilities;
1884 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1885 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1890 free(rsp, M_DEVBUF);