1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
102 * e1000_null_set_page - No-op function, return 0
103 * @hw: pointer to the HW structure
105 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
107 DEBUGFUNC("e1000_null_set_page");
108 return E1000_SUCCESS;
112 * e1000_null_read_reg - No-op function, return 0
113 * @hw: pointer to the HW structure
115 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
117 DEBUGFUNC("e1000_null_read_reg");
118 return E1000_SUCCESS;
122 * e1000_null_phy_generic - No-op function, return void
123 * @hw: pointer to the HW structure
125 void e1000_null_phy_generic(struct e1000_hw *hw)
127 DEBUGFUNC("e1000_null_phy_generic");
132 * e1000_null_lplu_state - No-op function, return 0
133 * @hw: pointer to the HW structure
135 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
137 DEBUGFUNC("e1000_null_lplu_state");
138 return E1000_SUCCESS;
142 * e1000_null_write_reg - No-op function, return 0
143 * @hw: pointer to the HW structure
145 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
147 DEBUGFUNC("e1000_null_write_reg");
148 return E1000_SUCCESS;
152 * e1000_check_reset_block_generic - Check if PHY reset is blocked
153 * @hw: pointer to the HW structure
155 * Read the PHY management control register and check whether a PHY reset
156 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
157 * return E1000_BLK_PHY_RESET (12).
159 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
163 DEBUGFUNC("e1000_check_reset_block");
165 manc = E1000_READ_REG(hw, E1000_MANC);
167 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
168 E1000_BLK_PHY_RESET : E1000_SUCCESS;
172 * e1000_get_phy_id - Retrieve the PHY ID and revision
173 * @hw: pointer to the HW structure
175 * Reads the PHY registers and stores the PHY ID and possibly the PHY
176 * revision in the hardware structure.
178 s32 e1000_get_phy_id(struct e1000_hw *hw)
180 struct e1000_phy_info *phy = &hw->phy;
181 s32 ret_val = E1000_SUCCESS;
185 DEBUGFUNC("e1000_get_phy_id");
187 if (!(phy->ops.read_reg))
190 while (retry_count < 2) {
191 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
195 phy->id = (u32)(phy_id << 16);
197 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
201 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
202 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
204 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
214 * e1000_phy_reset_dsp_generic - Reset PHY DSP
215 * @hw: pointer to the HW structure
217 * Reset the digital signal processor.
219 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
221 s32 ret_val = E1000_SUCCESS;
223 DEBUGFUNC("e1000_phy_reset_dsp_generic");
225 if (!(hw->phy.ops.write_reg))
228 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
232 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
239 * e1000_read_phy_reg_mdic - Read MDI control register
240 * @hw: pointer to the HW structure
241 * @offset: register offset to be read
242 * @data: pointer to the read data
244 * Reads the MDI control register in the PHY at offset and stores the
245 * information read to data.
247 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
249 struct e1000_phy_info *phy = &hw->phy;
251 s32 ret_val = E1000_SUCCESS;
253 DEBUGFUNC("e1000_read_phy_reg_mdic");
255 if (offset > MAX_PHY_REG_ADDRESS) {
256 DEBUGOUT1("PHY Address %d is out of range\n", offset);
257 return -E1000_ERR_PARAM;
261 * Set up Op-code, Phy Address, and register offset in the MDI
262 * Control register. The MAC will take care of interfacing with the
263 * PHY to retrieve the desired data.
265 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
266 (phy->addr << E1000_MDIC_PHY_SHIFT) |
267 (E1000_MDIC_OP_READ));
269 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
272 * Poll the ready bit to see if the MDI read completed
273 * Increasing the time out as testing showed failures with
276 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
278 mdic = E1000_READ_REG(hw, E1000_MDIC);
279 if (mdic & E1000_MDIC_READY)
282 if (!(mdic & E1000_MDIC_READY)) {
283 DEBUGOUT("MDI Read did not complete\n");
284 ret_val = -E1000_ERR_PHY;
287 if (mdic & E1000_MDIC_ERROR) {
288 DEBUGOUT("MDI Error\n");
289 ret_val = -E1000_ERR_PHY;
295 * Allow some time after each MDIC transaction to avoid
296 * reading duplicate data in the next MDIC transaction.
298 if (hw->mac.type == e1000_pch2lan)
306 * e1000_write_phy_reg_mdic - Write MDI control register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to write to
309 * @data: data to write to register at offset
311 * Writes data to MDI control register in the PHY at offset.
313 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
315 struct e1000_phy_info *phy = &hw->phy;
317 s32 ret_val = E1000_SUCCESS;
319 DEBUGFUNC("e1000_write_phy_reg_mdic");
321 if (offset > MAX_PHY_REG_ADDRESS) {
322 DEBUGOUT1("PHY Address %d is out of range\n", offset);
323 return -E1000_ERR_PARAM;
327 * Set up Op-code, Phy Address, and register offset in the MDI
328 * Control register. The MAC will take care of interfacing with the
329 * PHY to retrieve the desired data.
331 mdic = (((u32)data) |
332 (offset << E1000_MDIC_REG_SHIFT) |
333 (phy->addr << E1000_MDIC_PHY_SHIFT) |
334 (E1000_MDIC_OP_WRITE));
336 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
339 * Poll the ready bit to see if the MDI read completed
340 * Increasing the time out as testing showed failures with
343 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
345 mdic = E1000_READ_REG(hw, E1000_MDIC);
346 if (mdic & E1000_MDIC_READY)
349 if (!(mdic & E1000_MDIC_READY)) {
350 DEBUGOUT("MDI Write did not complete\n");
351 ret_val = -E1000_ERR_PHY;
354 if (mdic & E1000_MDIC_ERROR) {
355 DEBUGOUT("MDI Error\n");
356 ret_val = -E1000_ERR_PHY;
361 * Allow some time after each MDIC transaction to avoid
362 * reading duplicate data in the next MDIC transaction.
364 if (hw->mac.type == e1000_pch2lan)
372 * e1000_read_phy_reg_i2c - Read PHY register using i2c
373 * @hw: pointer to the HW structure
374 * @offset: register offset to be read
375 * @data: pointer to the read data
377 * Reads the PHY register at offset using the i2c interface and stores the
378 * retrieved information in data.
380 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
382 struct e1000_phy_info *phy = &hw->phy;
385 DEBUGFUNC("e1000_read_phy_reg_i2c");
388 * Set up Op-code, Phy Address, and register address in the I2CCMD
389 * register. The MAC will take care of interfacing with the
390 * PHY to retrieve the desired data.
392 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
393 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
394 (E1000_I2CCMD_OPCODE_READ));
396 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
398 /* Poll the ready bit to see if the I2C read completed */
399 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
401 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
402 if (i2ccmd & E1000_I2CCMD_READY)
405 if (!(i2ccmd & E1000_I2CCMD_READY)) {
406 DEBUGOUT("I2CCMD Read did not complete\n");
407 return -E1000_ERR_PHY;
409 if (i2ccmd & E1000_I2CCMD_ERROR) {
410 DEBUGOUT("I2CCMD Error bit set\n");
411 return -E1000_ERR_PHY;
414 /* Need to byte-swap the 16-bit value. */
415 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
417 return E1000_SUCCESS;
421 * e1000_write_phy_reg_i2c - Write PHY register using i2c
422 * @hw: pointer to the HW structure
423 * @offset: register offset to write to
424 * @data: data to write at register offset
426 * Writes the data to PHY register at the offset using the i2c interface.
428 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
430 struct e1000_phy_info *phy = &hw->phy;
432 u16 phy_data_swapped;
434 DEBUGFUNC("e1000_write_phy_reg_i2c");
436 /* Swap the data bytes for the I2C interface */
437 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
440 * Set up Op-code, Phy Address, and register address in the I2CCMD
441 * register. The MAC will take care of interfacing with the
442 * PHY to retrieve the desired data.
444 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
445 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
446 E1000_I2CCMD_OPCODE_WRITE |
449 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
451 /* Poll the ready bit to see if the I2C read completed */
452 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
454 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
455 if (i2ccmd & E1000_I2CCMD_READY)
458 if (!(i2ccmd & E1000_I2CCMD_READY)) {
459 DEBUGOUT("I2CCMD Write did not complete\n");
460 return -E1000_ERR_PHY;
462 if (i2ccmd & E1000_I2CCMD_ERROR) {
463 DEBUGOUT("I2CCMD Error bit set\n");
464 return -E1000_ERR_PHY;
467 return E1000_SUCCESS;
471 * e1000_read_phy_reg_m88 - Read m88 PHY register
472 * @hw: pointer to the HW structure
473 * @offset: register offset to be read
474 * @data: pointer to the read data
476 * Acquires semaphore, if necessary, then reads the PHY register at offset
477 * and storing the retrieved information in data. Release any acquired
478 * semaphores before exiting.
480 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
482 s32 ret_val = E1000_SUCCESS;
484 DEBUGFUNC("e1000_read_phy_reg_m88");
486 if (!(hw->phy.ops.acquire))
489 ret_val = hw->phy.ops.acquire(hw);
493 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
496 hw->phy.ops.release(hw);
503 * e1000_write_phy_reg_m88 - Write m88 PHY register
504 * @hw: pointer to the HW structure
505 * @offset: register offset to write to
506 * @data: data to write at register offset
508 * Acquires semaphore, if necessary, then writes the data to PHY register
509 * at the offset. Release any acquired semaphores before exiting.
511 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
513 s32 ret_val = E1000_SUCCESS;
515 DEBUGFUNC("e1000_write_phy_reg_m88");
517 if (!(hw->phy.ops.acquire))
520 ret_val = hw->phy.ops.acquire(hw);
524 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
527 hw->phy.ops.release(hw);
534 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
535 * @hw: pointer to the HW structure
536 * @page: page to set (shifted left when necessary)
538 * Sets PHY page required for PHY register access. Assumes semaphore is
539 * already acquired. Note, this function sets phy.addr to 1 so the caller
540 * must set it appropriately (if necessary) after this function returns.
542 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
544 DEBUGFUNC("e1000_set_page_igp");
546 DEBUGOUT1("Setting page 0x%x\n", page);
550 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
554 * __e1000_read_phy_reg_igp - Read igp PHY register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to be read
557 * @data: pointer to the read data
558 * @locked: semaphore has already been acquired or not
560 * Acquires semaphore, if necessary, then reads the PHY register at offset
561 * and stores the retrieved information in data. Release any acquired
562 * semaphores before exiting.
564 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
567 s32 ret_val = E1000_SUCCESS;
569 DEBUGFUNC("__e1000_read_phy_reg_igp");
572 if (!(hw->phy.ops.acquire))
575 ret_val = hw->phy.ops.acquire(hw);
580 if (offset > MAX_PHY_MULTI_PAGE_REG) {
581 ret_val = e1000_write_phy_reg_mdic(hw,
582 IGP01E1000_PHY_PAGE_SELECT,
588 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
593 hw->phy.ops.release(hw);
599 * e1000_read_phy_reg_igp - Read igp PHY register
600 * @hw: pointer to the HW structure
601 * @offset: register offset to be read
602 * @data: pointer to the read data
604 * Acquires semaphore then reads the PHY register at offset and stores the
605 * retrieved information in data.
606 * Release the acquired semaphore before exiting.
608 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
610 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
614 * e1000_read_phy_reg_igp_locked - Read igp PHY register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to be read
617 * @data: pointer to the read data
619 * Reads the PHY register at offset and stores the retrieved information
620 * in data. Assumes semaphore already acquired.
622 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
624 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
628 * e1000_write_phy_reg_igp - Write igp PHY register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
632 * @locked: semaphore has already been acquired or not
634 * Acquires semaphore, if necessary, then writes the data to PHY register
635 * at the offset. Release any acquired semaphores before exiting.
637 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
640 s32 ret_val = E1000_SUCCESS;
642 DEBUGFUNC("e1000_write_phy_reg_igp");
645 if (!(hw->phy.ops.acquire))
648 ret_val = hw->phy.ops.acquire(hw);
653 if (offset > MAX_PHY_MULTI_PAGE_REG) {
654 ret_val = e1000_write_phy_reg_mdic(hw,
655 IGP01E1000_PHY_PAGE_SELECT,
661 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
666 hw->phy.ops.release(hw);
673 * e1000_write_phy_reg_igp - Write igp PHY register
674 * @hw: pointer to the HW structure
675 * @offset: register offset to write to
676 * @data: data to write at register offset
678 * Acquires semaphore then writes the data to PHY register
679 * at the offset. Release any acquired semaphores before exiting.
681 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
683 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
687 * e1000_write_phy_reg_igp_locked - Write igp PHY register
688 * @hw: pointer to the HW structure
689 * @offset: register offset to write to
690 * @data: data to write at register offset
692 * Writes the data to PHY register at the offset.
693 * Assumes semaphore already acquired.
695 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
697 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
701 * __e1000_read_kmrn_reg - Read kumeran register
702 * @hw: pointer to the HW structure
703 * @offset: register offset to be read
704 * @data: pointer to the read data
705 * @locked: semaphore has already been acquired or not
707 * Acquires semaphore, if necessary. Then reads the PHY register at offset
708 * using the kumeran interface. The information retrieved is stored in data.
709 * Release any acquired semaphores before exiting.
711 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
715 s32 ret_val = E1000_SUCCESS;
717 DEBUGFUNC("__e1000_read_kmrn_reg");
720 if (!(hw->phy.ops.acquire))
723 ret_val = hw->phy.ops.acquire(hw);
728 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
729 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
730 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
734 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
735 *data = (u16)kmrnctrlsta;
738 hw->phy.ops.release(hw);
745 * e1000_read_kmrn_reg_generic - Read kumeran register
746 * @hw: pointer to the HW structure
747 * @offset: register offset to be read
748 * @data: pointer to the read data
750 * Acquires semaphore then reads the PHY register at offset using the
751 * kumeran interface. The information retrieved is stored in data.
752 * Release the acquired semaphore before exiting.
754 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
756 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
760 * e1000_read_kmrn_reg_locked - Read kumeran register
761 * @hw: pointer to the HW structure
762 * @offset: register offset to be read
763 * @data: pointer to the read data
765 * Reads the PHY register at offset using the kumeran interface. The
766 * information retrieved is stored in data.
767 * Assumes semaphore already acquired.
769 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
771 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
775 * __e1000_write_kmrn_reg - Write kumeran register
776 * @hw: pointer to the HW structure
777 * @offset: register offset to write to
778 * @data: data to write at register offset
779 * @locked: semaphore has already been acquired or not
781 * Acquires semaphore, if necessary. Then write the data to PHY register
782 * at the offset using the kumeran interface. Release any acquired semaphores
785 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
789 s32 ret_val = E1000_SUCCESS;
791 DEBUGFUNC("e1000_write_kmrn_reg_generic");
794 if (!(hw->phy.ops.acquire))
797 ret_val = hw->phy.ops.acquire(hw);
802 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
803 E1000_KMRNCTRLSTA_OFFSET) | data;
804 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
809 hw->phy.ops.release(hw);
816 * e1000_write_kmrn_reg_generic - Write kumeran register
817 * @hw: pointer to the HW structure
818 * @offset: register offset to write to
819 * @data: data to write at register offset
821 * Acquires semaphore then writes the data to the PHY register at the offset
822 * using the kumeran interface. Release the acquired semaphore before exiting.
824 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
826 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
830 * e1000_write_kmrn_reg_locked - Write kumeran register
831 * @hw: pointer to the HW structure
832 * @offset: register offset to write to
833 * @data: data to write at register offset
835 * Write the data to PHY register at the offset using the kumeran interface.
836 * Assumes semaphore already acquired.
838 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
840 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
844 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
845 * @hw: pointer to the HW structure
847 * Sets up Carrier-sense on Transmit and downshift values.
849 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
854 DEBUGFUNC("e1000_copper_link_setup_82577");
856 if (hw->phy.reset_disable) {
857 ret_val = E1000_SUCCESS;
861 if (hw->phy.type == e1000_phy_82580) {
862 ret_val = hw->phy.ops.reset(hw);
864 DEBUGOUT("Error resetting the PHY.\n");
869 /* Enable CRS on Tx. This must be set for half-duplex operation. */
870 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
874 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
876 /* Enable downshift */
877 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
879 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
886 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
887 * @hw: pointer to the HW structure
889 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
890 * and downshift values are set also.
892 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
894 struct e1000_phy_info *phy = &hw->phy;
898 DEBUGFUNC("e1000_copper_link_setup_m88");
900 if (phy->reset_disable) {
901 ret_val = E1000_SUCCESS;
905 /* Enable CRS on Tx. This must be set for half-duplex operation. */
906 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
910 /* For BM PHY this bit is downshift enable */
911 if (phy->type != e1000_phy_bm)
912 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
916 * MDI/MDI-X = 0 (default)
917 * 0 - Auto for all speeds
920 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
922 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
926 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
929 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
932 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
936 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
942 * disable_polarity_correction = 0 (default)
943 * Automatic Correction for Reversed Cable Polarity
947 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
948 if (phy->disable_polarity_correction == 1)
949 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
951 /* Enable downshift on BM (disabled by default) */
952 if (phy->type == e1000_phy_bm)
953 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
955 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
959 if ((phy->type == e1000_phy_m88) &&
960 (phy->revision < E1000_REVISION_4) &&
961 (phy->id != BME1000_E_PHY_ID_R2)) {
963 * Force TX_CLK in the Extended PHY Specific Control Register
966 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
971 phy_data |= M88E1000_EPSCR_TX_CLK_25;
973 if ((phy->revision == E1000_REVISION_2) &&
974 (phy->id == M88E1111_I_PHY_ID)) {
975 /* 82573L PHY - set the downshift counter to 5x. */
976 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
977 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
979 /* Configure Master and Slave downshift values */
980 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
981 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
982 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
983 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
985 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
991 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
992 /* Set PHY page 0, register 29 to 0x0003 */
993 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
997 /* Set PHY page 0, register 30 to 0x0000 */
998 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1003 /* Commit the changes. */
1004 ret_val = phy->ops.commit(hw);
1006 DEBUGOUT("Error committing the PHY changes\n");
1010 if (phy->type == e1000_phy_82578) {
1011 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1016 /* 82578 PHY - set the downshift count to 1x. */
1017 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1018 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1019 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1030 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1031 * @hw: pointer to the HW structure
1033 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1034 * Also enables and sets the downshift parameters.
1036 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1038 struct e1000_phy_info *phy = &hw->phy;
1042 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1044 if (phy->reset_disable) {
1045 ret_val = E1000_SUCCESS;
1049 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1050 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1056 * MDI/MDI-X = 0 (default)
1057 * 0 - Auto for all speeds
1060 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1062 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1064 switch (phy->mdix) {
1066 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1069 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1072 /* M88E1112 does not support this mode) */
1073 if (phy->id != M88E1112_E_PHY_ID) {
1074 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1079 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1085 * disable_polarity_correction = 0 (default)
1086 * Automatic Correction for Reversed Cable Polarity
1090 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1091 if (phy->disable_polarity_correction == 1)
1092 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1094 /* Enable downshift and setting it to X6 */
1095 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1096 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1097 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1099 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1103 /* Commit the changes. */
1104 ret_val = phy->ops.commit(hw);
1106 DEBUGOUT("Error committing the PHY changes\n");
1115 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1116 * @hw: pointer to the HW structure
1118 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1121 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1123 struct e1000_phy_info *phy = &hw->phy;
1127 DEBUGFUNC("e1000_copper_link_setup_igp");
1129 if (phy->reset_disable) {
1130 ret_val = E1000_SUCCESS;
1134 ret_val = hw->phy.ops.reset(hw);
1136 DEBUGOUT("Error resetting the PHY.\n");
1141 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1142 * timeout issues when LFS is enabled.
1147 * The NVM settings will configure LPLU in D3 for
1150 if (phy->type == e1000_phy_igp) {
1151 /* disable lplu d3 during driver init */
1152 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1154 DEBUGOUT("Error Disabling LPLU D3\n");
1159 /* disable lplu d0 during driver init */
1160 if (hw->phy.ops.set_d0_lplu_state) {
1161 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1163 DEBUGOUT("Error Disabling LPLU D0\n");
1167 /* Configure mdi-mdix settings */
1168 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1172 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1174 switch (phy->mdix) {
1176 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1179 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1183 data |= IGP01E1000_PSCR_AUTO_MDIX;
1186 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1190 /* set auto-master slave resolution settings */
1191 if (hw->mac.autoneg) {
1193 * when autonegotiation advertisement is only 1000Mbps then we
1194 * should disable SmartSpeed and enable Auto MasterSlave
1195 * resolution as hardware default.
1197 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1198 /* Disable SmartSpeed */
1199 ret_val = phy->ops.read_reg(hw,
1200 IGP01E1000_PHY_PORT_CONFIG,
1205 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1206 ret_val = phy->ops.write_reg(hw,
1207 IGP01E1000_PHY_PORT_CONFIG,
1212 /* Set auto Master/Slave resolution process */
1213 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1217 data &= ~CR_1000T_MS_ENABLE;
1218 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1223 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1227 /* load defaults for future use */
1228 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1229 ((data & CR_1000T_MS_VALUE) ?
1230 e1000_ms_force_master :
1231 e1000_ms_force_slave) :
1234 switch (phy->ms_type) {
1235 case e1000_ms_force_master:
1236 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1238 case e1000_ms_force_slave:
1239 data |= CR_1000T_MS_ENABLE;
1240 data &= ~(CR_1000T_MS_VALUE);
1243 data &= ~CR_1000T_MS_ENABLE;
1247 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1257 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1258 * @hw: pointer to the HW structure
1260 * Performs initial bounds checking on autoneg advertisement parameter, then
1261 * configure to advertise the full capability. Setup the PHY to autoneg
1262 * and restart the negotiation process between the link partner. If
1263 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1265 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1267 struct e1000_phy_info *phy = &hw->phy;
1271 DEBUGFUNC("e1000_copper_link_autoneg");
1274 * Perform some bounds checking on the autoneg advertisement
1277 phy->autoneg_advertised &= phy->autoneg_mask;
1280 * If autoneg_advertised is zero, we assume it was not defaulted
1281 * by the calling code so we set to advertise full capability.
1283 if (phy->autoneg_advertised == 0)
1284 phy->autoneg_advertised = phy->autoneg_mask;
1286 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1287 ret_val = e1000_phy_setup_autoneg(hw);
1289 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1292 DEBUGOUT("Restarting Auto-Neg\n");
1295 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1296 * the Auto Neg Restart bit in the PHY control register.
1298 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1302 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1303 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1308 * Does the user want to wait for Auto-Neg to complete here, or
1309 * check at a later time (for example, callback routine).
1311 if (phy->autoneg_wait_to_complete) {
1312 ret_val = hw->mac.ops.wait_autoneg(hw);
1314 DEBUGOUT("Error while waiting for "
1315 "autoneg to complete\n");
1320 hw->mac.get_link_status = TRUE;
1327 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1328 * @hw: pointer to the HW structure
1330 * Reads the MII auto-neg advertisement register and/or the 1000T control
1331 * register and if the PHY is already setup for auto-negotiation, then
1332 * return successful. Otherwise, setup advertisement and flow control to
1333 * the appropriate values for the wanted auto-negotiation.
1335 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1337 struct e1000_phy_info *phy = &hw->phy;
1339 u16 mii_autoneg_adv_reg;
1340 u16 mii_1000t_ctrl_reg = 0;
1342 DEBUGFUNC("e1000_phy_setup_autoneg");
1344 phy->autoneg_advertised &= phy->autoneg_mask;
1346 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1347 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1351 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1352 /* Read the MII 1000Base-T Control Register (Address 9). */
1353 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1354 &mii_1000t_ctrl_reg);
1360 * Need to parse both autoneg_advertised and fc and set up
1361 * the appropriate PHY registers. First we will parse for
1362 * autoneg_advertised software override. Since we can advertise
1363 * a plethora of combinations, we need to check each bit
1368 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1369 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1370 * the 1000Base-T Control Register (Address 9).
1372 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1373 NWAY_AR_100TX_HD_CAPS |
1374 NWAY_AR_10T_FD_CAPS |
1375 NWAY_AR_10T_HD_CAPS);
1376 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1378 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1380 /* Do we want to advertise 10 Mb Half Duplex? */
1381 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1382 DEBUGOUT("Advertise 10mb Half duplex\n");
1383 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1386 /* Do we want to advertise 10 Mb Full Duplex? */
1387 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1388 DEBUGOUT("Advertise 10mb Full duplex\n");
1389 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1392 /* Do we want to advertise 100 Mb Half Duplex? */
1393 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1394 DEBUGOUT("Advertise 100mb Half duplex\n");
1395 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1398 /* Do we want to advertise 100 Mb Full Duplex? */
1399 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1400 DEBUGOUT("Advertise 100mb Full duplex\n");
1401 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1404 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1405 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1406 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1408 /* Do we want to advertise 1000 Mb Full Duplex? */
1409 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1410 DEBUGOUT("Advertise 1000mb Full duplex\n");
1411 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1415 * Check for a software override of the flow control settings, and
1416 * setup the PHY advertisement registers accordingly. If
1417 * auto-negotiation is enabled, then software will have to set the
1418 * "PAUSE" bits to the correct value in the Auto-Negotiation
1419 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1422 * The possible values of the "fc" parameter are:
1423 * 0: Flow control is completely disabled
1424 * 1: Rx flow control is enabled (we can receive pause frames
1425 * but not send pause frames).
1426 * 2: Tx flow control is enabled (we can send pause frames
1427 * but we do not support receiving pause frames).
1428 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1429 * other: No software override. The flow control configuration
1430 * in the EEPROM is used.
1432 switch (hw->fc.current_mode) {
1435 * Flow control (Rx & Tx) is completely disabled by a
1436 * software over-ride.
1438 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1440 case e1000_fc_rx_pause:
1442 * Rx Flow control is enabled, and Tx Flow control is
1443 * disabled, by a software over-ride.
1445 * Since there really isn't a way to advertise that we are
1446 * capable of Rx Pause ONLY, we will advertise that we
1447 * support both symmetric and asymmetric Rx PAUSE. Later
1448 * (in e1000_config_fc_after_link_up) we will disable the
1449 * hw's ability to send PAUSE frames.
1451 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1453 case e1000_fc_tx_pause:
1455 * Tx Flow control is enabled, and Rx Flow control is
1456 * disabled, by a software over-ride.
1458 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1459 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1463 * Flow control (both Rx and Tx) is enabled by a software
1466 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1469 DEBUGOUT("Flow control param set incorrectly\n");
1470 ret_val = -E1000_ERR_CONFIG;
1474 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1478 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1480 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1481 ret_val = phy->ops.write_reg(hw,
1483 mii_1000t_ctrl_reg);
1493 * e1000_setup_copper_link_generic - Configure copper link settings
1494 * @hw: pointer to the HW structure
1496 * Calls the appropriate function to configure the link for auto-neg or forced
1497 * speed and duplex. Then we check for link, once link is established calls
1498 * to configure collision distance and flow control are called. If link is
1499 * not established, we return -E1000_ERR_PHY (-2).
1501 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1506 DEBUGFUNC("e1000_setup_copper_link_generic");
1508 if (hw->mac.autoneg) {
1510 * Setup autoneg and flow control advertisement and perform
1513 ret_val = e1000_copper_link_autoneg(hw);
1518 * PHY will be set to 10H, 10F, 100H or 100F
1519 * depending on user settings.
1521 DEBUGOUT("Forcing Speed and Duplex\n");
1522 ret_val = hw->phy.ops.force_speed_duplex(hw);
1524 DEBUGOUT("Error Forcing Speed and Duplex\n");
1530 * Check link status. Wait up to 100 microseconds for link to become
1533 ret_val = e1000_phy_has_link_generic(hw,
1534 COPPER_LINK_UP_LIMIT,
1541 DEBUGOUT("Valid link established!!!\n");
1542 e1000_config_collision_dist_generic(hw);
1543 ret_val = e1000_config_fc_after_link_up_generic(hw);
1545 DEBUGOUT("Unable to establish link!!!\n");
1553 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1554 * @hw: pointer to the HW structure
1556 * Calls the PHY setup function to force speed and duplex. Clears the
1557 * auto-crossover to force MDI manually. Waits for link and returns
1558 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1560 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1562 struct e1000_phy_info *phy = &hw->phy;
1567 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1569 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1573 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1575 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1580 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1581 * forced whenever speed and duplex are forced.
1583 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1587 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1588 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1590 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1594 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1598 if (phy->autoneg_wait_to_complete) {
1599 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1601 ret_val = e1000_phy_has_link_generic(hw,
1609 DEBUGOUT("Link taking longer than expected.\n");
1612 ret_val = e1000_phy_has_link_generic(hw,
1625 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1626 * @hw: pointer to the HW structure
1628 * Calls the PHY setup function to force speed and duplex. Clears the
1629 * auto-crossover to force MDI manually. Resets the PHY to commit the
1630 * changes. If time expires while waiting for link up, we reset the DSP.
1631 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1632 * successful completion, else return corresponding error code.
1634 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1636 struct e1000_phy_info *phy = &hw->phy;
1641 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1644 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1645 * forced whenever speed and duplex are forced.
1647 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1651 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1652 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1656 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1658 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1662 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1664 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1668 /* Reset the phy to commit changes. */
1669 ret_val = hw->phy.ops.commit(hw);
1673 if (phy->autoneg_wait_to_complete) {
1674 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1676 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1682 if (hw->phy.type != e1000_phy_m88 ||
1683 hw->phy.id == I347AT4_E_PHY_ID ||
1684 hw->phy.id == M88E1340M_E_PHY_ID ||
1685 hw->phy.id == M88E1112_E_PHY_ID) {
1686 DEBUGOUT("Link taking longer than expected.\n");
1689 * We didn't get link.
1690 * Reset the DSP and cross our fingers.
1692 ret_val = phy->ops.write_reg(hw,
1693 M88E1000_PHY_PAGE_SELECT,
1697 ret_val = e1000_phy_reset_dsp_generic(hw);
1704 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1710 if (hw->phy.type != e1000_phy_m88 ||
1711 hw->phy.id == I347AT4_E_PHY_ID ||
1712 hw->phy.id == M88E1340M_E_PHY_ID ||
1713 hw->phy.id == M88E1112_E_PHY_ID)
1716 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1721 * Resetting the phy means we need to re-force TX_CLK in the
1722 * Extended PHY Specific Control Register to 25MHz clock from
1723 * the reset value of 2.5MHz.
1725 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1726 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1731 * In addition, we must re-enable CRS on Tx for both half and full
1734 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1738 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1739 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1746 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1747 * @hw: pointer to the HW structure
1749 * Forces the speed and duplex settings of the PHY.
1750 * This is a function pointer entry point only called by
1751 * PHY setup routines.
1753 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1755 struct e1000_phy_info *phy = &hw->phy;
1760 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1762 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1766 e1000_phy_force_speed_duplex_setup(hw, &data);
1768 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1772 /* Disable MDI-X support for 10/100 */
1773 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1777 data &= ~IFE_PMC_AUTO_MDIX;
1778 data &= ~IFE_PMC_FORCE_MDIX;
1780 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1784 DEBUGOUT1("IFE PMC: %X\n", data);
1788 if (phy->autoneg_wait_to_complete) {
1789 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1791 ret_val = e1000_phy_has_link_generic(hw,
1799 DEBUGOUT("Link taking longer than expected.\n");
1802 ret_val = e1000_phy_has_link_generic(hw,
1815 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1816 * @hw: pointer to the HW structure
1817 * @phy_ctrl: pointer to current value of PHY_CONTROL
1819 * Forces speed and duplex on the PHY by doing the following: disable flow
1820 * control, force speed/duplex on the MAC, disable auto speed detection,
1821 * disable auto-negotiation, configure duplex, configure speed, configure
1822 * the collision distance, write configuration to CTRL register. The
1823 * caller must write to the PHY_CONTROL register for these settings to
1826 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1828 struct e1000_mac_info *mac = &hw->mac;
1831 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1833 /* Turn off flow control when forcing speed/duplex */
1834 hw->fc.current_mode = e1000_fc_none;
1836 /* Force speed/duplex on the mac */
1837 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1838 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1839 ctrl &= ~E1000_CTRL_SPD_SEL;
1841 /* Disable Auto Speed Detection */
1842 ctrl &= ~E1000_CTRL_ASDE;
1844 /* Disable autoneg on the phy */
1845 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1847 /* Forcing Full or Half Duplex? */
1848 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1849 ctrl &= ~E1000_CTRL_FD;
1850 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1851 DEBUGOUT("Half Duplex\n");
1853 ctrl |= E1000_CTRL_FD;
1854 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1855 DEBUGOUT("Full Duplex\n");
1858 /* Forcing 10mb or 100mb? */
1859 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1860 ctrl |= E1000_CTRL_SPD_100;
1861 *phy_ctrl |= MII_CR_SPEED_100;
1862 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1863 DEBUGOUT("Forcing 100mb\n");
1865 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1866 *phy_ctrl |= MII_CR_SPEED_10;
1867 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1868 DEBUGOUT("Forcing 10mb\n");
1871 e1000_config_collision_dist_generic(hw);
1873 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1877 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1878 * @hw: pointer to the HW structure
1879 * @active: boolean used to enable/disable lplu
1881 * Success returns 0, Failure returns 1
1883 * The low power link up (lplu) state is set to the power management level D3
1884 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1885 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1886 * is used during Dx states where the power conservation is most important.
1887 * During driver activity, SmartSpeed should be enabled so performance is
1890 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1892 struct e1000_phy_info *phy = &hw->phy;
1893 s32 ret_val = E1000_SUCCESS;
1896 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1898 if (!(hw->phy.ops.read_reg))
1901 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1906 data &= ~IGP02E1000_PM_D3_LPLU;
1907 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1912 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1913 * during Dx states where the power conservation is most
1914 * important. During driver activity we should enable
1915 * SmartSpeed, so performance is maintained.
1917 if (phy->smart_speed == e1000_smart_speed_on) {
1918 ret_val = phy->ops.read_reg(hw,
1919 IGP01E1000_PHY_PORT_CONFIG,
1924 data |= IGP01E1000_PSCFR_SMART_SPEED;
1925 ret_val = phy->ops.write_reg(hw,
1926 IGP01E1000_PHY_PORT_CONFIG,
1930 } else if (phy->smart_speed == e1000_smart_speed_off) {
1931 ret_val = phy->ops.read_reg(hw,
1932 IGP01E1000_PHY_PORT_CONFIG,
1937 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1938 ret_val = phy->ops.write_reg(hw,
1939 IGP01E1000_PHY_PORT_CONFIG,
1944 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1945 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1946 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1947 data |= IGP02E1000_PM_D3_LPLU;
1948 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1953 /* When LPLU is enabled, we should disable SmartSpeed */
1954 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1959 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1960 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1969 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1970 * @hw: pointer to the HW structure
1972 * Success returns 0, Failure returns 1
1974 * A downshift is detected by querying the PHY link health.
1976 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1978 struct e1000_phy_info *phy = &hw->phy;
1980 u16 phy_data, offset, mask;
1982 DEBUGFUNC("e1000_check_downshift_generic");
1984 switch (phy->type) {
1986 case e1000_phy_gg82563:
1988 case e1000_phy_82578:
1989 offset = M88E1000_PHY_SPEC_STATUS;
1990 mask = M88E1000_PSSR_DOWNSHIFT;
1993 case e1000_phy_igp_2:
1994 case e1000_phy_igp_3:
1995 offset = IGP01E1000_PHY_LINK_HEALTH;
1996 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1999 /* speed downshift not supported */
2000 phy->speed_downgraded = FALSE;
2001 ret_val = E1000_SUCCESS;
2005 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2008 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
2015 * e1000_check_polarity_m88 - Checks the polarity.
2016 * @hw: pointer to the HW structure
2018 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2020 * Polarity is determined based on the PHY specific status register.
2022 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2024 struct e1000_phy_info *phy = &hw->phy;
2028 DEBUGFUNC("e1000_check_polarity_m88");
2030 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2033 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2034 ? e1000_rev_polarity_reversed
2035 : e1000_rev_polarity_normal;
2041 * e1000_check_polarity_igp - Checks the polarity.
2042 * @hw: pointer to the HW structure
2044 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2046 * Polarity is determined based on the PHY port status register, and the
2047 * current speed (since there is no polarity at 100Mbps).
2049 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2051 struct e1000_phy_info *phy = &hw->phy;
2053 u16 data, offset, mask;
2055 DEBUGFUNC("e1000_check_polarity_igp");
2058 * Polarity is determined based on the speed of
2061 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2065 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2066 IGP01E1000_PSSR_SPEED_1000MBPS) {
2067 offset = IGP01E1000_PHY_PCS_INIT_REG;
2068 mask = IGP01E1000_PHY_POLARITY_MASK;
2071 * This really only applies to 10Mbps since
2072 * there is no polarity for 100Mbps (always 0).
2074 offset = IGP01E1000_PHY_PORT_STATUS;
2075 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2078 ret_val = phy->ops.read_reg(hw, offset, &data);
2081 phy->cable_polarity = (data & mask)
2082 ? e1000_rev_polarity_reversed
2083 : e1000_rev_polarity_normal;
2090 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2091 * @hw: pointer to the HW structure
2093 * Polarity is determined on the polarity reversal feature being enabled.
2095 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2097 struct e1000_phy_info *phy = &hw->phy;
2099 u16 phy_data, offset, mask;
2101 DEBUGFUNC("e1000_check_polarity_ife");
2104 * Polarity is determined based on the reversal feature being enabled.
2106 if (phy->polarity_correction) {
2107 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2108 mask = IFE_PESC_POLARITY_REVERSED;
2110 offset = IFE_PHY_SPECIAL_CONTROL;
2111 mask = IFE_PSC_FORCE_POLARITY;
2114 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2117 phy->cable_polarity = (phy_data & mask)
2118 ? e1000_rev_polarity_reversed
2119 : e1000_rev_polarity_normal;
2125 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2126 * @hw: pointer to the HW structure
2128 * Waits for auto-negotiation to complete or for the auto-negotiation time
2129 * limit to expire, which ever happens first.
2131 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2133 s32 ret_val = E1000_SUCCESS;
2136 DEBUGFUNC("e1000_wait_autoneg_generic");
2138 if (!(hw->phy.ops.read_reg))
2139 return E1000_SUCCESS;
2141 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2142 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2143 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2146 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2149 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2155 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2162 * e1000_phy_has_link_generic - Polls PHY for link
2163 * @hw: pointer to the HW structure
2164 * @iterations: number of times to poll for link
2165 * @usec_interval: delay between polling attempts
2166 * @success: pointer to whether polling was successful or not
2168 * Polls the PHY status register for link, 'iterations' number of times.
2170 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2171 u32 usec_interval, bool *success)
2173 s32 ret_val = E1000_SUCCESS;
2176 DEBUGFUNC("e1000_phy_has_link_generic");
2178 if (!(hw->phy.ops.read_reg))
2179 return E1000_SUCCESS;
2181 for (i = 0; i < iterations; i++) {
2183 * Some PHYs require the PHY_STATUS register to be read
2184 * twice due to the link bit being sticky. No harm doing
2185 * it across the board.
2187 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2190 * If the first read fails, another entity may have
2191 * ownership of the resources, wait and try again to
2192 * see if they have relinquished the resources yet.
2194 usec_delay(usec_interval);
2195 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2198 if (phy_status & MII_SR_LINK_STATUS)
2200 if (usec_interval >= 1000)
2201 msec_delay_irq(usec_interval/1000);
2203 usec_delay(usec_interval);
2206 *success = (i < iterations) ? TRUE : FALSE;
2212 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2213 * @hw: pointer to the HW structure
2215 * Reads the PHY specific status register to retrieve the cable length
2216 * information. The cable length is determined by averaging the minimum and
2217 * maximum values to get the "average" cable length. The m88 PHY has four
2218 * possible cable length values, which are:
2219 * Register Value Cable Length
2223 * 3 110 - 140 meters
2226 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2228 struct e1000_phy_info *phy = &hw->phy;
2230 u16 phy_data, index;
2232 DEBUGFUNC("e1000_get_cable_length_m88");
2234 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2238 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2239 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2240 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2241 ret_val = -E1000_ERR_PHY;
2245 phy->min_cable_length = e1000_m88_cable_length_table[index];
2246 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2248 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2254 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2256 struct e1000_phy_info *phy = &hw->phy;
2258 u16 phy_data, phy_data2, index, default_page, is_cm;
2260 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2262 switch (hw->phy.id) {
2263 case M88E1340M_E_PHY_ID:
2264 case I347AT4_E_PHY_ID:
2265 /* Remember the original page select and set it to 7 */
2266 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2271 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2275 /* Get cable length from PHY Cable Diagnostics Control Reg */
2276 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2281 /* Check if the unit of cable length is meters or cm */
2282 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2286 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2288 /* Populate the phy structure with cable length in meters */
2289 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2290 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2291 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2293 /* Reset the page selec to its original value */
2294 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2299 case M88E1112_E_PHY_ID:
2300 /* Remember the original page select and set it to 5 */
2301 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2306 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2310 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2315 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2316 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2317 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2318 ret_val = -E1000_ERR_PHY;
2322 phy->min_cable_length = e1000_m88_cable_length_table[index];
2323 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2325 phy->cable_length = (phy->min_cable_length +
2326 phy->max_cable_length) / 2;
2328 /* Reset the page select to its original value */
2329 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2336 ret_val = -E1000_ERR_PHY;
2345 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2346 * @hw: pointer to the HW structure
2348 * The automatic gain control (agc) normalizes the amplitude of the
2349 * received signal, adjusting for the attenuation produced by the
2350 * cable. By reading the AGC registers, which represent the
2351 * combination of coarse and fine gain value, the value can be put
2352 * into a lookup table to obtain the approximate cable length
2355 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2357 struct e1000_phy_info *phy = &hw->phy;
2358 s32 ret_val = E1000_SUCCESS;
2359 u16 phy_data, i, agc_value = 0;
2360 u16 cur_agc_index, max_agc_index = 0;
2361 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2362 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2363 IGP02E1000_PHY_AGC_A,
2364 IGP02E1000_PHY_AGC_B,
2365 IGP02E1000_PHY_AGC_C,
2366 IGP02E1000_PHY_AGC_D
2369 DEBUGFUNC("e1000_get_cable_length_igp_2");
2371 /* Read the AGC registers for all channels */
2372 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2373 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2378 * Getting bits 15:9, which represent the combination of
2379 * coarse and fine gain values. The result is a number
2380 * that can be put into the lookup table to obtain the
2381 * approximate cable length.
2383 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2384 IGP02E1000_AGC_LENGTH_MASK;
2386 /* Array index bound check. */
2387 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2388 (cur_agc_index == 0)) {
2389 ret_val = -E1000_ERR_PHY;
2393 /* Remove min & max AGC values from calculation. */
2394 if (e1000_igp_2_cable_length_table[min_agc_index] >
2395 e1000_igp_2_cable_length_table[cur_agc_index])
2396 min_agc_index = cur_agc_index;
2397 if (e1000_igp_2_cable_length_table[max_agc_index] <
2398 e1000_igp_2_cable_length_table[cur_agc_index])
2399 max_agc_index = cur_agc_index;
2401 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2404 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2405 e1000_igp_2_cable_length_table[max_agc_index]);
2406 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2408 /* Calculate cable length with the error range of +/- 10 meters. */
2409 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2410 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2411 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2413 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2420 * e1000_get_phy_info_m88 - Retrieve PHY information
2421 * @hw: pointer to the HW structure
2423 * Valid for only copper links. Read the PHY status register (sticky read)
2424 * to verify that link is up. Read the PHY special control register to
2425 * determine the polarity and 10base-T extended distance. Read the PHY
2426 * special status register to determine MDI/MDIx and current speed. If
2427 * speed is 1000, then determine cable length, local and remote receiver.
2429 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2431 struct e1000_phy_info *phy = &hw->phy;
2436 DEBUGFUNC("e1000_get_phy_info_m88");
2438 if (phy->media_type != e1000_media_type_copper) {
2439 DEBUGOUT("Phy info is only valid for copper media\n");
2440 ret_val = -E1000_ERR_CONFIG;
2444 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2449 DEBUGOUT("Phy info is only valid if link is up\n");
2450 ret_val = -E1000_ERR_CONFIG;
2454 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2458 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2461 ret_val = e1000_check_polarity_m88(hw);
2465 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2469 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2471 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2472 ret_val = hw->phy.ops.get_cable_length(hw);
2476 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2480 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2481 ? e1000_1000t_rx_status_ok
2482 : e1000_1000t_rx_status_not_ok;
2484 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2485 ? e1000_1000t_rx_status_ok
2486 : e1000_1000t_rx_status_not_ok;
2488 /* Set values to "undefined" */
2489 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2490 phy->local_rx = e1000_1000t_rx_status_undefined;
2491 phy->remote_rx = e1000_1000t_rx_status_undefined;
2499 * e1000_get_phy_info_igp - Retrieve igp PHY information
2500 * @hw: pointer to the HW structure
2502 * Read PHY status to determine if link is up. If link is up, then
2503 * set/determine 10base-T extended distance and polarity correction. Read
2504 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2505 * determine on the cable length, local and remote receiver.
2507 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2509 struct e1000_phy_info *phy = &hw->phy;
2514 DEBUGFUNC("e1000_get_phy_info_igp");
2516 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2521 DEBUGOUT("Phy info is only valid if link is up\n");
2522 ret_val = -E1000_ERR_CONFIG;
2526 phy->polarity_correction = TRUE;
2528 ret_val = e1000_check_polarity_igp(hw);
2532 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2536 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2538 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2539 IGP01E1000_PSSR_SPEED_1000MBPS) {
2540 ret_val = phy->ops.get_cable_length(hw);
2544 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2548 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2549 ? e1000_1000t_rx_status_ok
2550 : e1000_1000t_rx_status_not_ok;
2552 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2553 ? e1000_1000t_rx_status_ok
2554 : e1000_1000t_rx_status_not_ok;
2556 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2557 phy->local_rx = e1000_1000t_rx_status_undefined;
2558 phy->remote_rx = e1000_1000t_rx_status_undefined;
2566 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2567 * @hw: pointer to the HW structure
2569 * Populates "phy" structure with various feature states.
2571 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2573 struct e1000_phy_info *phy = &hw->phy;
2578 DEBUGFUNC("e1000_get_phy_info_ife");
2580 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2585 DEBUGOUT("Phy info is only valid if link is up\n");
2586 ret_val = -E1000_ERR_CONFIG;
2590 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2593 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2596 if (phy->polarity_correction) {
2597 ret_val = e1000_check_polarity_ife(hw);
2601 /* Polarity is forced */
2602 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2603 ? e1000_rev_polarity_reversed
2604 : e1000_rev_polarity_normal;
2607 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2611 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2613 /* The following parameters are undefined for 10/100 operation. */
2614 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2615 phy->local_rx = e1000_1000t_rx_status_undefined;
2616 phy->remote_rx = e1000_1000t_rx_status_undefined;
2623 * e1000_phy_sw_reset_generic - PHY software reset
2624 * @hw: pointer to the HW structure
2626 * Does a software reset of the PHY by reading the PHY control register and
2627 * setting/write the control register reset bit to the PHY.
2629 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2631 s32 ret_val = E1000_SUCCESS;
2634 DEBUGFUNC("e1000_phy_sw_reset_generic");
2636 if (!(hw->phy.ops.read_reg))
2639 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2643 phy_ctrl |= MII_CR_RESET;
2644 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2655 * e1000_phy_hw_reset_generic - PHY hardware reset
2656 * @hw: pointer to the HW structure
2658 * Verify the reset block is not blocking us from resetting. Acquire
2659 * semaphore (if necessary) and read/set/write the device control reset
2660 * bit in the PHY. Wait the appropriate delay time for the device to
2661 * reset and release the semaphore (if necessary).
2663 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2665 struct e1000_phy_info *phy = &hw->phy;
2666 s32 ret_val = E1000_SUCCESS;
2669 DEBUGFUNC("e1000_phy_hw_reset_generic");
2671 ret_val = phy->ops.check_reset_block(hw);
2673 ret_val = E1000_SUCCESS;
2677 ret_val = phy->ops.acquire(hw);
2681 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2682 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2683 E1000_WRITE_FLUSH(hw);
2685 usec_delay(phy->reset_delay_us);
2687 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2688 E1000_WRITE_FLUSH(hw);
2692 phy->ops.release(hw);
2694 ret_val = phy->ops.get_cfg_done(hw);
2701 * e1000_get_cfg_done_generic - Generic configuration done
2702 * @hw: pointer to the HW structure
2704 * Generic function to wait 10 milli-seconds for configuration to complete
2705 * and return success.
2707 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2709 DEBUGFUNC("e1000_get_cfg_done_generic");
2713 return E1000_SUCCESS;
2717 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2718 * @hw: pointer to the HW structure
2720 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2722 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2724 DEBUGOUT("Running IGP 3 PHY init script\n");
2726 /* PHY init IGP 3 */
2727 /* Enable rise/fall, 10-mode work in class-A */
2728 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2729 /* Remove all caps from Replica path filter */
2730 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2731 /* Bias trimming for ADC, AFE and Driver (Default) */
2732 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2733 /* Increase Hybrid poly bias */
2734 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2735 /* Add 4% to Tx amplitude in Gig mode */
2736 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2737 /* Disable trimming (TTT) */
2738 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2739 /* Poly DC correction to 94.6% + 2% for all channels */
2740 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2741 /* ABS DC correction to 95.9% */
2742 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2743 /* BG temp curve trim */
2744 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2745 /* Increasing ADC OPAMP stage 1 currents to max */
2746 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2747 /* Force 1000 ( required for enabling PHY regs configuration) */
2748 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2749 /* Set upd_freq to 6 */
2750 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2752 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2753 /* Disable adaptive fixed FFE (Default) */
2754 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2755 /* Enable FFE hysteresis */
2756 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2757 /* Fixed FFE for short cable lengths */
2758 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2759 /* Fixed FFE for medium cable lengths */
2760 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2761 /* Fixed FFE for long cable lengths */
2762 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2763 /* Enable Adaptive Clip Threshold */
2764 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2765 /* AHT reset limit to 1 */
2766 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2767 /* Set AHT master delay to 127 msec */
2768 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2769 /* Set scan bits for AHT */
2770 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2771 /* Set AHT Preset bits */
2772 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2773 /* Change integ_factor of channel A to 3 */
2774 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2775 /* Change prop_factor of channels BCD to 8 */
2776 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2777 /* Change cg_icount + enable integbp for channels BCD */
2778 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2780 * Change cg_icount + enable integbp + change prop_factor_master
2781 * to 8 for channel A
2783 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2784 /* Disable AHT in Slave mode on channel A */
2785 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2787 * Enable LPLU and disable AN to 1000 in non-D0a states,
2790 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2791 /* Enable restart AN on an1000_dis change */
2792 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2793 /* Enable wh_fifo read clock in 10/100 modes */
2794 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2795 /* Restart AN, Speed selection is 1000 */
2796 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2798 return E1000_SUCCESS;
2802 * e1000_get_phy_type_from_id - Get PHY type from id
2803 * @phy_id: phy_id read from the phy
2805 * Returns the phy type from the id.
2807 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2809 enum e1000_phy_type phy_type = e1000_phy_unknown;
2812 case M88E1000_I_PHY_ID:
2813 case M88E1000_E_PHY_ID:
2814 case M88E1111_I_PHY_ID:
2815 case M88E1011_I_PHY_ID:
2816 case I347AT4_E_PHY_ID:
2817 case M88E1112_E_PHY_ID:
2818 case M88E1340M_E_PHY_ID:
2819 phy_type = e1000_phy_m88;
2821 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2822 phy_type = e1000_phy_igp_2;
2824 case GG82563_E_PHY_ID:
2825 phy_type = e1000_phy_gg82563;
2827 case IGP03E1000_E_PHY_ID:
2828 phy_type = e1000_phy_igp_3;
2831 case IFE_PLUS_E_PHY_ID:
2832 case IFE_C_E_PHY_ID:
2833 phy_type = e1000_phy_ife;
2835 case BME1000_E_PHY_ID:
2836 case BME1000_E_PHY_ID_R2:
2837 phy_type = e1000_phy_bm;
2839 case I82578_E_PHY_ID:
2840 phy_type = e1000_phy_82578;
2842 case I82577_E_PHY_ID:
2843 phy_type = e1000_phy_82577;
2845 case I82579_E_PHY_ID:
2846 phy_type = e1000_phy_82579;
2848 case I82580_I_PHY_ID:
2849 phy_type = e1000_phy_82580;
2852 phy_type = e1000_phy_unknown;
2859 * e1000_determine_phy_address - Determines PHY address.
2860 * @hw: pointer to the HW structure
2862 * This uses a trial and error method to loop through possible PHY
2863 * addresses. It tests each by reading the PHY ID registers and
2864 * checking for a match.
2866 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2868 s32 ret_val = -E1000_ERR_PHY_TYPE;
2871 enum e1000_phy_type phy_type = e1000_phy_unknown;
2873 hw->phy.id = phy_type;
2875 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2876 hw->phy.addr = phy_addr;
2880 e1000_get_phy_id(hw);
2881 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2884 * If phy_type is valid, break - we found our
2887 if (phy_type != e1000_phy_unknown) {
2888 ret_val = E1000_SUCCESS;
2901 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2902 * @page: page to access
2904 * Returns the phy address for the page requested.
2906 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2910 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2917 * e1000_write_phy_reg_bm - Write BM PHY register
2918 * @hw: pointer to the HW structure
2919 * @offset: register offset to write to
2920 * @data: data to write at register offset
2922 * Acquires semaphore, if necessary, then writes the data to PHY register
2923 * at the offset. Release any acquired semaphores before exiting.
2925 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2928 u32 page = offset >> IGP_PAGE_SHIFT;
2930 DEBUGFUNC("e1000_write_phy_reg_bm");
2932 ret_val = hw->phy.ops.acquire(hw);
2936 /* Page 800 works differently than the rest so it has its own func */
2937 if (page == BM_WUC_PAGE) {
2938 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2943 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2945 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2946 u32 page_shift, page_select;
2949 * Page select is register 31 for phy address 1 and 22 for
2950 * phy address 2 and 3. Page select is shifted only for
2953 if (hw->phy.addr == 1) {
2954 page_shift = IGP_PAGE_SHIFT;
2955 page_select = IGP01E1000_PHY_PAGE_SELECT;
2958 page_select = BM_PHY_PAGE_SELECT;
2961 /* Page is shifted left, PHY expects (page x 32) */
2962 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2963 (page << page_shift));
2968 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2972 hw->phy.ops.release(hw);
2977 * e1000_read_phy_reg_bm - Read BM PHY register
2978 * @hw: pointer to the HW structure
2979 * @offset: register offset to be read
2980 * @data: pointer to the read data
2982 * Acquires semaphore, if necessary, then reads the PHY register at offset
2983 * and storing the retrieved information in data. Release any acquired
2984 * semaphores before exiting.
2986 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2989 u32 page = offset >> IGP_PAGE_SHIFT;
2991 DEBUGFUNC("e1000_read_phy_reg_bm");
2993 ret_val = hw->phy.ops.acquire(hw);
2997 /* Page 800 works differently than the rest so it has its own func */
2998 if (page == BM_WUC_PAGE) {
2999 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3004 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3006 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3007 u32 page_shift, page_select;
3010 * Page select is register 31 for phy address 1 and 22 for
3011 * phy address 2 and 3. Page select is shifted only for
3014 if (hw->phy.addr == 1) {
3015 page_shift = IGP_PAGE_SHIFT;
3016 page_select = IGP01E1000_PHY_PAGE_SELECT;
3019 page_select = BM_PHY_PAGE_SELECT;
3022 /* Page is shifted left, PHY expects (page x 32) */
3023 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3024 (page << page_shift));
3029 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3032 hw->phy.ops.release(hw);
3037 * e1000_read_phy_reg_bm2 - Read BM PHY register
3038 * @hw: pointer to the HW structure
3039 * @offset: register offset to be read
3040 * @data: pointer to the read data
3042 * Acquires semaphore, if necessary, then reads the PHY register at offset
3043 * and storing the retrieved information in data. Release any acquired
3044 * semaphores before exiting.
3046 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3049 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3051 DEBUGFUNC("e1000_read_phy_reg_bm2");
3053 ret_val = hw->phy.ops.acquire(hw);
3057 /* Page 800 works differently than the rest so it has its own func */
3058 if (page == BM_WUC_PAGE) {
3059 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3066 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3068 /* Page is shifted left, PHY expects (page x 32) */
3069 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3076 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3079 hw->phy.ops.release(hw);
3084 * e1000_write_phy_reg_bm2 - Write BM PHY register
3085 * @hw: pointer to the HW structure
3086 * @offset: register offset to write to
3087 * @data: data to write at register offset
3089 * Acquires semaphore, if necessary, then writes the data to PHY register
3090 * at the offset. Release any acquired semaphores before exiting.
3092 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3095 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3097 DEBUGFUNC("e1000_write_phy_reg_bm2");
3099 ret_val = hw->phy.ops.acquire(hw);
3103 /* Page 800 works differently than the rest so it has its own func */
3104 if (page == BM_WUC_PAGE) {
3105 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3112 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3113 /* Page is shifted left, PHY expects (page x 32) */
3114 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3121 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3125 hw->phy.ops.release(hw);
3130 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3131 * @hw: pointer to the HW structure
3132 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3134 * Assumes semaphore already acquired and phy_reg points to a valid memory
3135 * address to store contents of the BM_WUC_ENABLE_REG register.
3137 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3142 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3145 ret_val = -E1000_ERR_PARAM;
3149 /* All page select, port ctrl and wakeup registers use phy address 1 */
3152 /* Select Port Control Registers page */
3153 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3155 DEBUGOUT("Could not set Port Control page\n");
3159 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3161 DEBUGOUT2("Could not read PHY register %d.%d\n",
3162 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3167 * Enable both PHY wakeup mode and Wakeup register page writes.
3168 * Prevent a power state change by disabling ME and Host PHY wakeup.
3171 temp |= BM_WUC_ENABLE_BIT;
3172 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3174 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3176 DEBUGOUT2("Could not write PHY register %d.%d\n",
3177 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3181 /* Select Host Wakeup Registers page */
3182 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3184 /* caller now able to write registers on the Wakeup registers page */
3190 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3191 * @hw: pointer to the HW structure
3192 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3194 * Restore BM_WUC_ENABLE_REG to its original value.
3196 * Assumes semaphore already acquired and *phy_reg is the contents of the
3197 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3200 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3202 s32 ret_val = E1000_SUCCESS;
3204 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3207 return -E1000_ERR_PARAM;
3209 /* Select Port Control Registers page */
3210 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3212 DEBUGOUT("Could not set Port Control page\n");
3216 /* Restore 769.17 to its original value */
3217 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3219 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3220 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3226 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3227 * @hw: pointer to the HW structure
3228 * @offset: register offset to be read or written
3229 * @data: pointer to the data to read or write
3230 * @read: determines if operation is read or write
3231 * @page_set: BM_WUC_PAGE already set and access enabled
3233 * Read the PHY register at offset and store the retrieved information in
3234 * data, or write data to PHY register at offset. Note the procedure to
3235 * access the PHY wakeup registers is different than reading the other PHY
3236 * registers. It works as such:
3237 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3238 * 2) Set page to 800 for host (801 if we were manageability)
3239 * 3) Write the address using the address opcode (0x11)
3240 * 4) Read or write the data using the data opcode (0x12)
3241 * 5) Restore 769.17.2 to its original value
3243 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3244 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3246 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3247 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3248 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3250 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3251 u16 *data, bool read, bool page_set)
3254 u16 reg = BM_PHY_REG_NUM(offset);
3257 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3259 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3260 if ((hw->mac.type == e1000_pchlan) &&
3261 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3262 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3266 /* Enable access to PHY wakeup registers */
3267 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3269 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3274 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3276 /* Write the Wakeup register page offset value using opcode 0x11 */
3277 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3279 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3284 /* Read the Wakeup register page value using opcode 0x12 */
3285 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3288 /* Write the Wakeup register page value using opcode 0x12 */
3289 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3294 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3299 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3306 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3307 * @hw: pointer to the HW structure
3309 * In the case of a PHY power down to save power, or to turn off link during a
3310 * driver unload, or wake on lan is not enabled, restore the link to previous
3313 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3317 /* The PHY will retain its settings across a power down/up cycle */
3318 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3319 mii_reg &= ~MII_CR_POWER_DOWN;
3320 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3324 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3325 * @hw: pointer to the HW structure
3327 * In the case of a PHY power down to save power, or to turn off link during a
3328 * driver unload, or wake on lan is not enabled, restore the link to previous
3331 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3335 /* The PHY will retain its settings across a power down/up cycle */
3336 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3337 mii_reg |= MII_CR_POWER_DOWN;
3338 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3343 * __e1000_read_phy_reg_hv - Read HV PHY register
3344 * @hw: pointer to the HW structure
3345 * @offset: register offset to be read
3346 * @data: pointer to the read data
3347 * @locked: semaphore has already been acquired or not
3349 * Acquires semaphore, if necessary, then reads the PHY register at offset
3350 * and stores the retrieved information in data. Release any acquired
3351 * semaphore before exiting.
3353 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3354 bool locked, bool page_set)
3357 u16 page = BM_PHY_REG_PAGE(offset);
3358 u16 reg = BM_PHY_REG_NUM(offset);
3359 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3361 DEBUGFUNC("__e1000_read_phy_reg_hv");
3364 ret_val = hw->phy.ops.acquire(hw);
3369 /* Page 800 works differently than the rest so it has its own func */
3370 if (page == BM_WUC_PAGE) {
3371 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3376 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3377 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3383 if (page == HV_INTC_FC_PAGE_START)
3386 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3387 /* Page is shifted left, PHY expects (page x 32) */
3388 ret_val = e1000_set_page_igp(hw,
3389 (page << IGP_PAGE_SHIFT));
3391 hw->phy.addr = phy_addr;
3398 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3399 page << IGP_PAGE_SHIFT, reg);
3401 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3405 hw->phy.ops.release(hw);
3411 * e1000_read_phy_reg_hv - Read HV PHY register
3412 * @hw: pointer to the HW structure
3413 * @offset: register offset to be read
3414 * @data: pointer to the read data
3416 * Acquires semaphore then reads the PHY register at offset and stores
3417 * the retrieved information in data. Release the acquired semaphore
3420 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3422 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3426 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3427 * @hw: pointer to the HW structure
3428 * @offset: register offset to be read
3429 * @data: pointer to the read data
3431 * Reads the PHY register at offset and stores the retrieved information
3432 * in data. Assumes semaphore already acquired.
3434 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3436 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3440 * e1000_read_phy_reg_page_hv - Read HV PHY register
3441 * @hw: pointer to the HW structure
3442 * @offset: register offset to write to
3443 * @data: data to write at register offset
3445 * Reads the PHY register at offset and stores the retrieved information
3446 * in data. Assumes semaphore already acquired and page already set.
3448 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3450 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE);
3454 * __e1000_write_phy_reg_hv - Write HV PHY register
3455 * @hw: pointer to the HW structure
3456 * @offset: register offset to write to
3457 * @data: data to write at register offset
3458 * @locked: semaphore has already been acquired or not
3460 * Acquires semaphore, if necessary, then writes the data to PHY register
3461 * at the offset. Release any acquired semaphores before exiting.
3463 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3464 bool locked, bool page_set)
3467 u16 page = BM_PHY_REG_PAGE(offset);
3468 u16 reg = BM_PHY_REG_NUM(offset);
3469 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3471 DEBUGFUNC("__e1000_write_phy_reg_hv");
3474 ret_val = hw->phy.ops.acquire(hw);
3479 /* Page 800 works differently than the rest so it has its own func */
3480 if (page == BM_WUC_PAGE) {
3481 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3486 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3487 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3493 if (page == HV_INTC_FC_PAGE_START)
3497 * Workaround MDIO accesses being disabled after entering IEEE
3498 * Power Down (when bit 11 of the PHY Control register is set)
3500 if ((hw->phy.type == e1000_phy_82578) &&
3501 (hw->phy.revision >= 1) &&
3502 (hw->phy.addr == 2) &&
3503 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3504 (data & (1 << 11))) {
3506 ret_val = e1000_access_phy_debug_regs_hv(hw,
3513 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3514 /* Page is shifted left, PHY expects (page x 32) */
3515 ret_val = e1000_set_page_igp(hw,
3516 (page << IGP_PAGE_SHIFT));
3518 hw->phy.addr = phy_addr;
3525 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3526 page << IGP_PAGE_SHIFT, reg);
3528 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3533 hw->phy.ops.release(hw);
3539 * e1000_write_phy_reg_hv - Write HV PHY register
3540 * @hw: pointer to the HW structure
3541 * @offset: register offset to write to
3542 * @data: data to write at register offset
3544 * Acquires semaphore then writes the data to PHY register at the offset.
3545 * Release the acquired semaphores before exiting.
3547 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3549 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3553 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3554 * @hw: pointer to the HW structure
3555 * @offset: register offset to write to
3556 * @data: data to write at register offset
3558 * Writes the data to PHY register at the offset. Assumes semaphore
3561 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3563 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3567 * e1000_write_phy_reg_page_hv - Write HV PHY register
3568 * @hw: pointer to the HW structure
3569 * @offset: register offset to write to
3570 * @data: data to write at register offset
3572 * Writes the data to PHY register at the offset. Assumes semaphore
3573 * already acquired and page already set.
3575 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3577 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE);
3581 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3582 * @page: page to be accessed
3584 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3588 if (page >= HV_INTC_FC_PAGE_START)
3595 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3596 * @hw: pointer to the HW structure
3597 * @offset: register offset to be read or written
3598 * @data: pointer to the data to be read or written
3599 * @read: determines if operation is read or write
3601 * Reads the PHY register at offset and stores the retreived information
3602 * in data. Assumes semaphore already acquired. Note that the procedure
3603 * to access these regs uses the address port and data port to read/write.
3604 * These accesses done with PHY address 2 and without using pages.
3606 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3607 u16 *data, bool read)
3613 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3615 /* This takes care of the difference with desktop vs mobile phy */
3616 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3617 I82578_ADDR_REG : I82577_ADDR_REG;
3618 data_reg = addr_reg + 1;
3620 /* All operations in this function are phy address 2 */
3623 /* masking with 0x3F to remove the page from offset */
3624 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3626 DEBUGOUT("Could not write the Address Offset port register\n");
3630 /* Read or write the data value next */
3632 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3634 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3637 DEBUGOUT("Could not access the Data port register\n");
3646 * e1000_link_stall_workaround_hv - Si workaround
3647 * @hw: pointer to the HW structure
3649 * This function works around a Si bug where the link partner can get
3650 * a link up indication before the PHY does. If small packets are sent
3651 * by the link partner they can be placed in the packet buffer without
3652 * being properly accounted for by the PHY and will stall preventing
3653 * further packets from being received. The workaround is to clear the
3654 * packet buffer after the PHY detects link up.
3656 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3658 s32 ret_val = E1000_SUCCESS;
3661 DEBUGFUNC("e1000_link_stall_workaround_hv");
3663 if (hw->phy.type != e1000_phy_82578)
3666 /* Do not apply workaround if in PHY loopback bit 14 set */
3667 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3668 if (data & PHY_CONTROL_LB)
3671 /* check if link is up and at 1Gbps */
3672 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3676 data &= BM_CS_STATUS_LINK_UP |
3677 BM_CS_STATUS_RESOLVED |
3678 BM_CS_STATUS_SPEED_MASK;
3680 if (data != (BM_CS_STATUS_LINK_UP |
3681 BM_CS_STATUS_RESOLVED |
3682 BM_CS_STATUS_SPEED_1000))
3687 /* flush the packets in the fifo buffer */
3688 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3689 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3690 HV_MUX_DATA_CTRL_FORCE_SPEED);
3694 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3695 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3702 * e1000_check_polarity_82577 - Checks the polarity.
3703 * @hw: pointer to the HW structure
3705 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3707 * Polarity is determined based on the PHY specific status register.
3709 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3711 struct e1000_phy_info *phy = &hw->phy;
3715 DEBUGFUNC("e1000_check_polarity_82577");
3717 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3720 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3721 ? e1000_rev_polarity_reversed
3722 : e1000_rev_polarity_normal;
3728 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3729 * @hw: pointer to the HW structure
3731 * Calls the PHY setup function to force speed and duplex.
3733 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3735 struct e1000_phy_info *phy = &hw->phy;
3740 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3742 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3746 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3748 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3754 if (phy->autoneg_wait_to_complete) {
3755 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3757 ret_val = e1000_phy_has_link_generic(hw,
3765 DEBUGOUT("Link taking longer than expected.\n");
3768 ret_val = e1000_phy_has_link_generic(hw,
3781 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3782 * @hw: pointer to the HW structure
3784 * Read PHY status to determine if link is up. If link is up, then
3785 * set/determine 10base-T extended distance and polarity correction. Read
3786 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3787 * determine on the cable length, local and remote receiver.
3789 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3791 struct e1000_phy_info *phy = &hw->phy;
3796 DEBUGFUNC("e1000_get_phy_info_82577");
3798 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3803 DEBUGOUT("Phy info is only valid if link is up\n");
3804 ret_val = -E1000_ERR_CONFIG;
3808 phy->polarity_correction = TRUE;
3810 ret_val = e1000_check_polarity_82577(hw);
3814 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3818 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3820 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3821 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3822 ret_val = hw->phy.ops.get_cable_length(hw);
3826 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3830 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3831 ? e1000_1000t_rx_status_ok
3832 : e1000_1000t_rx_status_not_ok;
3834 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3835 ? e1000_1000t_rx_status_ok
3836 : e1000_1000t_rx_status_not_ok;
3838 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3839 phy->local_rx = e1000_1000t_rx_status_undefined;
3840 phy->remote_rx = e1000_1000t_rx_status_undefined;
3848 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3849 * @hw: pointer to the HW structure
3851 * Reads the diagnostic status register and verifies result is valid before
3852 * placing it in the phy_cable_length field.
3854 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3856 struct e1000_phy_info *phy = &hw->phy;
3858 u16 phy_data, length;
3860 DEBUGFUNC("e1000_get_cable_length_82577");
3862 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3866 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3867 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3869 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3870 ret_val = -E1000_ERR_PHY;
3872 phy->cable_length = length;