2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * without modification.
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15 * substantially similar to the "NO WARRANTY" disclaimer below
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17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
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20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
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40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.seq,v 1.16 2004/05/11 20:46:05 gibbs Exp $
41 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.seq,v 1.7 2007/07/06 02:23:31 pavalos Exp $
44 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $"
45 PATCH_ARG_LIST = "struct ahd_softc *ahd"
48 #include "aic79xx.reg"
49 #include "scsi_message.h"
52 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
53 test SEQINTCODE, 0xFF jz idle_loop;
54 SET_SEQINTCODE(NO_SEQINT)
59 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
61 * Convert ERROR status into a sequencer
62 * interrupt to handle the case of an
63 * interrupt collision on the hardware
66 test ERROR, 0xFF jz no_error_set;
67 SET_SEQINTCODE(SAW_HWERR)
70 SET_MODE(M_SCSI, M_SCSI)
71 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
72 test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
74 * If the kernel has caught up with us, thaw the queue.
76 mov A, KERNEL_QFREEZE_COUNT;
77 cmp QFREEZE_COUNT, A jne check_frozen_completions;
78 mov A, KERNEL_QFREEZE_COUNT[1];
79 cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
80 and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
81 jmp check_waiting_list;
82 check_frozen_completions:
83 test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
86 * If we have completions stalled waiting for the qfreeze
87 * to take effect, move them over to the complete_scb list
88 * now that no selections are pending.
90 cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
92 * Find the end of the qfreeze list. The first element has
93 * to be treated specially.
95 bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
96 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
98 * Now the normal loop.
100 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
101 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
103 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
104 bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
105 mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
106 jmp idle_loop_checkbus;
108 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
110 * ENSELO is cleared by a SELDO, so we must test for SELDO
113 test SSTAT0, SELDO jnz select_out;
115 call start_selection;
118 test SSTAT0, SELDO jnz select_out;
120 test SSTAT0, SELDI jnz select_in;
121 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
122 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
123 call unexpected_nonpkt_phase_find_ctxt;
124 idle_loop_check_nonpackreq:
125 test SSTAT2, NONPACKREQ jz . + 2;
126 call unexpected_nonpkt_phase_find_ctxt;
127 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
129 * On Rev A. hardware, the busy LED is only
130 * turned on automaically during selections
131 * and re-selections. Make the LED status
132 * more useful by forcing it to be on so
133 * long as one of our data FIFOs is active.
135 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
136 cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
137 and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
139 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
141 call idle_loop_gsfifo_in_scsi_mode;
142 call idle_loop_service_fifos;
143 call idle_loop_cchan;
147 SET_MODE(M_SCSI, M_SCSI)
149 idle_loop_gsfifo_in_scsi_mode:
150 test LQISTAT2, LQIGSAVAIL jz return;
152 * We have received good status for this transaction. There may
153 * still be data in our FIFOs draining to the host. Complete
154 * the SCB only if all data has transferred to the host.
157 bmov SCBPTR, GSFIFO, 2;
160 * If a command completed before an attempted task management
161 * function completed, notify the host after disabling any
162 * pending select-outs.
164 test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
165 test SSTAT0, SELDO|SELINGO jnz . + 2;
166 and SCSISEQ0, ~ENSELO;
167 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
168 gsfifo_complete_normally:
169 or SCB_CONTROL, STATUS_RCVD;
172 * Since this status did not consume a FIFO, we have to
173 * be a bit more dilligent in how we check for FIFOs pertaining
174 * to this transaction. There are two states that a FIFO still
175 * transferring data may be in.
177 * 1) Configured and draining to the host, with a FIFO handler.
178 * 2) Pending cfg4data, fifo not empty.
180 * Case 1 can be detected by noticing a non-zero FIFO active
181 * count in the SCB. In this case, we allow the routine servicing
182 * the FIFO to complete the SCB.
184 * Case 2 implies either a pending or yet to occur save data
185 * pointers for this same context in the other FIFO. So, if
186 * we detect case 1, we will properly defer the post of the SCB
187 * and achieve the desired result. The pending cfg4data will
188 * notice that status has been received and complete the SCB.
190 test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
193 jmp idle_loop_gsfifo_in_scsi_mode;
195 idle_loop_service_fifos:
196 SET_MODE(M_DFF0, M_DFF0)
198 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
202 SET_MODE(M_DFF1, M_DFF1)
204 test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
210 SET_MODE(M_CCHAN, M_CCHAN)
211 test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
212 or QOFF_CTLSTA, HS_MAILBOX_ACT;
213 mov LOCAL_HS_MAILBOX, HS_MAILBOX;
216 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
217 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
218 test CCSCBCTL, CCSCBDONE jz return;
221 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
223 * An SCB has been succesfully uploaded to the host.
224 * If the SCB was uploaded for some reason other than
225 * bad SCSI status (currently only for underruns), we
226 * queue the SCB for normal completion. Otherwise, we
227 * wait until any select-out activity has halted, and
228 * then queue the completion.
230 and CCSCBCTL, ~(CCARREN|CCSCBEN);
231 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
232 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
233 mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
234 test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
235 bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
236 bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
237 scbdma_queue_completion:
238 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
239 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
240 fill_qoutfifo_dmadone:
241 and CCSCBCTL, ~(CCARREN|CCSCBEN);
242 call qoutfifo_updated;
243 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
244 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
245 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
246 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
247 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
252 * If there are more commands waiting to be dma'ed
253 * to the host, always coalesce. Otherwise honor the
256 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
257 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
258 test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
261 * If we have relatively few commands outstanding, don't
262 * bother waiting for another command to complete.
264 test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
265 /* Add -1 so that jnc means <= not just < */
266 add A, -1, INT_COALESCING_MINCMDS;
267 add NONE, A, CMDS_PENDING;
271 * If coalescing, only coalesce up to the limit
272 * provided by the host driver.
275 mov A, INT_COALESCING_MAXCMDS;
276 add NONE, A, INT_COALESCING_CMDCOUNT;
279 * If the timer is not currently active,
282 test INTCTL, SWTMINTMASK jz return;
283 bmov SWTIMER, INT_COALESCING_TIMER, 2;
284 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
285 or INTCTL, SWTMINTEN|SWTIMER_START;
286 and INTCTL, ~SWTMINTMASK ret;
289 mvi INTSTAT, CMDCMPLT;
290 clr INT_COALESCING_CMDCOUNT;
291 or INTCTL, SWTMINTMASK ret;
294 fetch_new_scb_inprog:
295 test CCSCBCTL, ARRDONE jz return;
297 and CCSCBCTL, ~(CCARREN|CCSCBEN);
298 bmov REG0, SCBPTR, 2;
301 adc CMDS_PENDING[1], A;
302 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
304 * "Short Luns" are not placed into outgoing LQ
305 * packets in the correct byte order. Use a full
306 * sized lun field instead and fill it with the
307 * one byte of lun information we support.
309 mov SCB_PKT_LUN[6], SCB_LUN;
312 * The FIFO use count field is shared with the
313 * tag set by the host so that our SCB dma engine
314 * knows the correct location to store the SCB.
315 * Set it to zero before processing the SCB.
317 clr SCB_FIFO_USE_COUNT;
318 /* Update the next SCB address to download. */
319 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
320 mvi SCB_NEXT[1], SCB_LIST_NULL;
321 mvi SCB_NEXT2[1], SCB_LIST_NULL;
322 /* Increment our position in the QINFIFO. */
323 mov NONE, SNSCB_QOFF;
325 * SCBs that want to send messages are always
326 * queued independently. This ensures that they
327 * are at the head of the SCB list to select out
328 * to a target and we will see the MK_MESSAGE flag.
330 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
331 shr SINDEX, 3, SCB_SCSIID;
333 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
334 bmov DINDEX, SINDEX, 2;
335 bmov SCBPTR, SINDIR, 2;
336 bmov DINDIR, REG0, 2;
337 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
338 bmov SCB_NEXT, REG0, 2 ret;
339 first_new_target_scb:
340 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
341 bmov SCBPTR, WAITING_TID_TAIL, 2;
342 bmov SCB_NEXT2, REG0, 2;
343 bmov WAITING_TID_TAIL, REG0, 2 ret;
345 bmov WAITING_TID_HEAD, REG0, 2;
346 bmov WAITING_TID_TAIL, REG0, 2 ret;
351 * Give precedence to downloading new SCBs to execute
352 * unless select-outs are currently frozen.
354 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
356 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
357 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
358 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
362 * Keep track of the SCBs we are dmaing just
363 * in case the DMA fails or is aborted.
365 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
366 mvi CCSCBCTL, CCSCBRESET;
367 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
368 mov A, QOUTFIFO_NEXT_ADDR;
369 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
371 bmov CCSCBRAM, SCBPTR, 2;
372 mov CCSCBRAM, SCB_SGPTR[0];
373 mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
374 mov NONE, SDSCB_QOFF;
375 inc INT_COALESCING_CMDCOUNT;
376 add CMDS_PENDING, -1;
377 adc CMDS_PENDING[1], -1;
378 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
379 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
380 test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
382 * Don't cross an ADB or Cachline boundary when DMA'ing
383 * completion entries. In PCI mode, at least in 32/33
384 * configurations, the SCB DMA engine may lose its place
385 * in the data-stream should the target force a retry on
386 * something other than an 8byte aligned boundary. In
387 * PCI-X mode, we do this to avoid split transactions since
388 * many chipsets seem to be unable to format proper split
389 * completions to continue the data transfer.
391 add SINDEX, A, CCSCBADDR;
392 test SINDEX, CACHELINE_MASK jz fill_qoutfifo_done;
393 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
394 jmp fill_qoutfifo_loop;
396 mov SCBHCNT, CCSCBADDR;
397 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
398 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
399 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
402 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
403 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
405 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
406 bmov SCBHADDR, SCB_BUSADDR, 4;
407 mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
410 * Either post or fetch an SCB from host memory. The caller
411 * is responsible for polling for transfer completion.
413 * Prerequisits: Mode == M_CCHAN
414 * SINDEX contains CCSCBCTL flags
415 * SCBHADDR set to Host SCB address
416 * SCBPTR set to SCB src location on "push" operations
418 SET_SRC_MODE M_CCHAN;
419 SET_DST_MODE M_CCHAN;
421 mvi SCBHCNT, SCB_TRANSFER_SIZE;
422 mov CCSCBCTL, SINDEX ret;
426 * At least on the A, a return in the same
427 * instruction as the bmov results in a return
428 * to the caller, not to the new address at the
429 * top of the stack. Since we want the latter
430 * (we use setjmp to register a handler from an
431 * interrupt context but not invoke that handler
432 * until we return to our idle loop), use a
433 * separate ret instruction.
435 bmov LONGJMP_ADDR, STACK, 2;
438 bmov LONGJMP_ADDR, STACK, 2;
440 bmov STACK, LONGJMP_ADDR, 2 ret;
443 /*************************** Chip Bug Work Arounds ****************************/
445 * Must disable interrupts when setting the mode pointer
446 * register as an interrupt occurring mid update will
447 * fail to store the new mode value for restoration on
450 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
451 set_mode_work_around:
452 mvi SEQINTCTL, INTVEC1DSL;
453 mov MODE_PTR, SINDEX;
458 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
459 set_seqint_work_around:
460 mov SEQINTCODE, SINDEX;
461 mvi SEQINTCODE, NO_SEQINT ret;
464 /************************ Packetized LongJmp Routines *************************/
469 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
472 * Rev A hardware fails to update LAST/CURR/NEXTSCB
473 * correctly after a packetized selection in several
476 * 1) If only one command existed in the queue, the
477 * LAST/CURR/NEXTSCB are unchanged.
479 * 2) In a non QAS, protocol allowed phase change,
480 * the queue is shifted 1 too far. LASTSCB is
481 * the last SCB that was correctly processed.
483 * 3) In the QAS case, if the full list of commands
484 * was successfully sent, NEXTSCB is NULL and neither
485 * CURRSCB nor LASTSCB can be trusted. We must
486 * manually walk the list counting MAXCMDCNT elements
487 * to find the last SCB that was sent correctly.
489 * To simplify the workaround for this bug in SELDO
490 * handling, we initialize LASTSCB prior to enabling
491 * selection so we can rely on it even for case #1 above.
493 bmov LASTSCB, WAITING_TID_HEAD, 2;
495 bmov CURRSCB, WAITING_TID_HEAD, 2;
496 bmov SCBPTR, WAITING_TID_HEAD, 2;
497 shr SELOID, 4, SCB_SCSIID;
499 * If we want to send a message to the device, ensure
500 * we are selecting with atn irregardless of our packetized
501 * agreement. Since SPI4 only allows target reset or PPR
502 * messages if this is a packetized connection, the change
503 * to our negotiation table entry for this selection will
504 * be cleared when the message is acted on.
506 test SCB_CONTROL, MK_MESSAGE jz . + 3;
507 mov NEGOADDR, SELOID;
508 or NEGCONOPTS, ENAUTOATNO;
509 or SCSISEQ0, ENSELO ret;
513 * Allocate a FIFO for a non-packetized transaction.
514 * In RevA hardware, both FIFOs must be free before we
515 * can allocate a FIFO for a non-packetized transaction.
519 * Do whatever work is required to free a FIFO.
521 call idle_loop_service_fifos;
522 SET_MODE(M_SCSI, M_SCSI)
524 if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
525 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
526 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
528 test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
529 test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
530 mvi DFFSTAT, B_CURRFIFO_0;
531 SET_MODE(M_DFF0, M_DFF0)
532 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
537 mvi DFFSTAT, CURRFIFO_1;
538 SET_MODE(M_DFF1, M_DFF1)
539 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
542 * We have been reselected as an initiator
543 * or selected as a target.
548 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
550 * On Rev A. hardware, the busy LED is only
551 * turned on automaically during selections
552 * and re-selections. Make the LED status
553 * more useful by forcing it to be on from
554 * the point of selection until our idle
555 * loop determines that neither of our FIFOs
556 * are busy. This handles the non-packetized
557 * case nicely as we will not return to the
558 * idle loop until the busfree at the end of
561 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
563 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
565 * Test to ensure that the bus has not
566 * already gone free prior to clearing
567 * any stale busfree status. This avoids
568 * a window whereby a busfree just after
569 * a selection could be missed.
571 test SCSISIGI, BSYI jz . + 2;
572 mvi CLRSINT1,CLRBUSFREE;
573 or SIMODE1, ENBUSFREE;
576 and SAVED_SCSIID, SELID_MASK, SELID;
579 mvi CLRSINT0, CLRSELDI;
583 * We have successfully selected out.
586 * Dequeue all SCBs sent from the waiting queue
587 * Requeue all SCBs *not* sent to the tail of the waiting queue
588 * Take Razor #494 into account for above.
590 * In Packetized Mode:
591 * Return to the idle loop. Our interrupt handler will take
592 * care of any incoming L_Qs.
594 * In Non-Packetize Mode:
595 * Continue to our normal state machine.
601 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
603 * On Rev A. hardware, the busy LED is only
604 * turned on automaically during selections
605 * and re-selections. Make the LED status
606 * more useful by forcing it to be on from
607 * the point of re-selection until our idle
608 * loop determines that neither of our FIFOs
609 * are busy. This handles the non-packetized
610 * case nicely as we will not return to the
611 * idle loop until the busfree at the end of
614 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
616 /* Clear out all SCBs that have been successfully sent. */
617 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
619 * For packetized, the LQO manager clears ENSELO on
620 * the assertion of SELDO. If we are non-packetized,
621 * LASTSCB and CURRSCB are accurate.
623 test SCSISEQ0, ENSELO jnz use_lastscb;
626 * The update is correct for LQOSTAT1 errors. All
627 * but LQOBUSFREE are handled by kernel interrupts.
628 * If we see LQOBUSFREE, return to the idle loop.
629 * Once we are out of the select_out critical section,
630 * the kernel will cleanup the LQOBUSFREE and we will
631 * eventually restart the selection if appropriate.
633 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
636 * On a phase change oustside of packet boundaries,
637 * LASTSCB points to the currently active SCB context
640 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
643 * If the hardware has traversed the whole list, NEXTSCB
644 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
645 * but MAXCMDCNT is accurate. If we stop part way through
646 * the list or only had one command to issue, NEXTSCB[1] is
647 * not NULL and LASTSCB is the last command to go out.
649 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
654 bmov SCBPTR, WAITING_TID_HEAD, 2;
655 mvi SEQINTCTL, INTVEC1DSL;
656 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
658 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
662 test A, 0xFF jz found_last_sent_scb;
663 bmov SCBPTR, SCB_NEXT, 2;
664 jmp find_lastscb_loop;
666 bmov SCBPTR, LASTSCB, 2;
668 bmov CURRSCB, SCBPTR, 2;
671 bmov SCBPTR, CURRSCB, 2;
675 * Requeue any SCBs not sent, to the tail of the waiting Q.
677 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
680 * We know that neither the per-TID list nor the list of
681 * TIDs is empty. Use this knowledge to our advantage.
683 bmov REG0, SCB_NEXT, 2;
684 bmov SCBPTR, WAITING_TID_TAIL, 2;
685 bmov SCB_NEXT2, REG0, 2;
686 bmov WAITING_TID_TAIL, REG0, 2;
687 jmp select_out_inc_tid_q;
689 select_out_list_done:
691 * The whole list made it. Just clear our TID's tail pointer
692 * unless we were queued independently due to our need to
695 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
696 shr DINDEX, 3, SCB_SCSIID;
697 or DINDEX, 1; /* Want only the second byte */
698 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
699 mvi DINDIR, SCB_LIST_NULL;
700 select_out_inc_tid_q:
701 bmov SCBPTR, WAITING_TID_HEAD, 2;
702 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
703 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
704 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
705 bmov SCBPTR, CURRSCB, 2;
706 mvi CLRSINT0, CLRSELDO;
707 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
708 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
711 * If this is a packetized connection, return to our
712 * idle_loop and let our interrupt handler deal with
713 * any connection setup/teardown issues. The only
714 * exceptions are the case of MK_MESSAGE and task management
717 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
719 * In the A, the LQO manager transitions to LQOSTOP0 even if
720 * we have selected out with ATN asserted and the target
721 * REQs in a non-packet phase.
723 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
724 test SCSISIGO, ATNO jnz select_out_non_packetized;
725 select_out_no_message:
727 test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
728 test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
729 SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
732 select_out_non_packetized:
733 /* Non packetized request. */
734 and SCSISEQ0, ~ENSELO;
735 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
737 * Test to ensure that the bus has not
738 * already gone free prior to clearing
739 * any stale busfree status. This avoids
740 * a window whereby a busfree just after
741 * a selection could be missed.
743 test SCSISIGI, BSYI jz . + 2;
744 mvi CLRSINT1,CLRBUSFREE;
745 or SIMODE1, ENBUSFREE;
747 mov SAVED_SCSIID, SCB_SCSIID;
748 mov SAVED_LUN, SCB_LUN;
749 mvi SEQ_FLAGS, NO_CDB_SENT;
754 * As soon as we get a successful selection, the target
755 * should go into the message out phase since we have ATN
758 mvi MSG_OUT, MSG_IDENTIFYFLAG;
761 * Main loop for information transfer phases. Wait for the
762 * target to assert REQ before checking MSG, C/D and I/O for
771 test A, ~P_DATAIN_DT jz p_data;
772 cmp A,P_COMMAND je p_command;
773 cmp A,P_MESGOUT je p_mesgout;
774 cmp A,P_STATUS je p_status;
775 cmp A,P_MESGIN je p_mesgin;
777 SET_SEQINTCODE(BAD_PHASE)
778 jmp ITloop; /* Try reading the bus again. */
781 * Command phase. Set up the DMA registers and let 'er rip.
784 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
785 SET_SEQINTCODE(PROTO_VIOLATION)
787 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
788 jnz p_command_allocate_fifo;
790 * Command retry. Free our current FIFO and
791 * re-allocate a FIFO so transfer state is
796 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
797 SET_MODE(M_SCSI, M_SCSI)
798 p_command_allocate_fifo:
799 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
803 add NONE, -17, SCB_CDB_LEN;
804 jnc p_command_embedded;
806 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
807 mvi SG_CACHE_PRE, LAST_SEG;
808 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
811 bmov SHCNT[0], SCB_CDB_LEN, 1;
812 bmov DFDAT, SCB_CDB_STORE, 16;
815 and SEQ_FLAGS, ~NO_CDB_SENT;
816 if ((ahd->features & AHD_FAST_CDB_DELIVERY) != 0) {
818 * To speed up CDB delivery in Rev B, all CDB acks
819 * are "released" to the output sync as soon as the
820 * command phase starts. There is only one problem
821 * with this approach. If the target changes phase
822 * before all data are sent, we have left over acks
823 * that can go out on the bus in a data phase. Due
824 * to other chip contraints, this only happens if
825 * the target goes to data-in, but if the acks go
826 * out before we can test SDONE, we'll think that
827 * the transfer has completed successfully. Work
828 * around this by taking advantage of the 400ns or
829 * 800ns dead time between command phase and the REQ
830 * of the new phase. If the transfer has completed
831 * successfully, SCSIEN should fall *long* before we
832 * see a phase change. We thus treat any phasemiss
833 * that occurs before SCSIEN falls as an incomplete
836 test SSTAT1, PHASEMIS jnz p_command_xfer_failed;
837 test DFCNTRL, SCSIEN jnz . - 1;
839 test DFCNTRL, SCSIEN jnz .;
842 * DMA Channel automatically disabled.
843 * Don't allow a data phase if the command
844 * was not fully transferred.
846 test SSTAT2, SDONE jnz ITloop;
847 p_command_xfer_failed:
848 or SEQ_FLAGS, NO_CDB_SENT;
853 * Status phase. Wait for the data byte to appear, then read it
854 * and store it into the SCB.
859 test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
861 mov SCB_SCSI_STATUS, SCSIDAT;
862 or SCB_CONTROL, STATUS_RCVD;
866 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
867 * indentify message sequence and send it to the target. The host may
868 * override this behavior by setting the MK_MESSAGE bit in the SCB
869 * control byte. This will cause us to interrupt the host and allow
870 * it to handle the message phase completely on its own. If the bit
871 * associated with this target is set, we will also interrupt the host,
872 * thereby allowing it to send a message on the next selection regardless
873 * of the transaction being sent.
875 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
876 * This is done to allow the host to send messages outside of an identify
877 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
878 * on an SCB that might not be for the current nexus. (For example, a
879 * BDR message in responce to a bad reselection would leave us pointed to
880 * an SCB that doesn't have anything to do with the current target).
882 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
885 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
886 * in case the target decides to put us in this phase for some strange
890 /* Turn on ATN for the retry */
894 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
895 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
897 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
898 test SCB_CONTROL, DISCENB jnz . + 2;
899 and SINDEX, ~DISCENB;
901 * Send a tag message if TAG_ENB is set in the SCB control block.
902 * Use SCB_NONPACKET_TAG as the tag value.
905 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
906 mov SCSIDAT, SINDEX; /* Send the identify message */
908 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
909 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
911 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
912 mov SCBPTR jmp p_mesgout_onebyte;
914 * Interrupt the driver, and allow it to handle this message
915 * phase and any required retries.
918 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
919 jmp host_message_loop;
922 mvi CLRSINT1, CLRATNO;
926 * If the next bus phase after ATN drops is message out, it means
927 * that the target is requesting that the last message(s) be resent.
930 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
933 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
934 mov LAST_MSG, MSG_OUT;
935 mvi MSG_OUT, MSG_NOOP; /* No message left */
939 * Message in phase. Bytes are read using Automatic PIO mode.
942 /* read the 1st message byte */
943 mvi ACCUM call inb_first;
945 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
946 cmp A,MSG_DISCONNECT je mesgin_disconnect;
947 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
948 cmp ALLZEROS,A je mesgin_complete;
949 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
950 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
951 cmp A,MSG_NOOP je mesgin_done;
954 * Pushed message loop to allow the kernel to
955 * run it's own message state engine. To avoid an
956 * extra nop instruction after signaling the kernel,
957 * we perform the phase_lock before checking to see
958 * if we should exit the loop and skip the phase_lock
959 * in the ITloop. Performing back to back phase_locks
960 * shouldn't hurt, but why do it twice...
963 call phase_lock; /* Benign the first time through. */
964 SET_SEQINTCODE(HOST_MSG_LOOP)
965 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
966 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
967 mov SCSIDAT, RETURN_2;
968 jmp host_message_loop;
969 /* Must be CONT_MSG_LOOP_READ */
970 mov NONE, SCSIDAT; /* ACK Byte */
971 jmp host_message_loop;
973 mesgin_ign_wide_residue:
974 mov SAVED_MODE, MODE_PTR;
975 SET_MODE(M_SCSI, M_SCSI)
976 shr NEGOADDR, 4, SAVED_SCSIID;
978 RESTORE_MODE(SAVED_MODE)
979 test A, WIDEXFER jz mesgin_reject;
980 /* Pull the residue byte */
981 mvi REG0 call inb_next;
982 cmp REG0, 0x01 jne mesgin_reject;
983 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
984 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
985 SET_SEQINTCODE(IGN_WIDE_RES)
988 mesgin_proto_violation:
989 SET_SEQINTCODE(PROTO_VIOLATION)
992 mvi MSG_MESSAGE_REJECT call mk_mesg;
994 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
997 #define INDEX_DISC_LIST(scsiid, lun) \
998 and A, 0xC0, scsiid; \
1001 and SINDEX, 0x30, scsiid; \
1002 shr SINDEX, 3; /* Multiply by 2 */ \
1003 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
1004 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
1008 * Determine whether a target is using tagged or non-tagged
1009 * transactions by first looking at the transaction stored in
1010 * the per-device, disconnected array. If there is no untagged
1011 * transaction for this target, this must be a tagged transaction.
1013 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1014 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1015 bmov DINDEX, SINDEX, 2;
1016 bmov REG0, SINDIR, 2;
1017 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
1018 /* Untagged. Clear the busy table entry and setup the SCB. */
1019 bmov DINDIR, ALLONES, 2;
1020 bmov SCBPTR, REG0, 2;
1024 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1025 * If we get one, we use the tag returned to find the proper
1026 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
1030 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1033 mov NONE, SCSIDAT; /* ACK Identify MSG */
1035 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1038 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
1039 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1042 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
1045 mvi SCBPTR call inb_next; /* tag value */
1047 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
1048 mov A, SAVED_SCSIID;
1049 cmp SCB_SCSIID, A jne verify_other_scb;
1051 cmp SCB_LUN, A je setup_SCB_disconnected;
1054 test SCBPTR[1], 0xFF jnz verify_scb;
1058 * Ensure that the SCB the tag points to is for
1059 * an SCB transaction to the reconnecting target.
1062 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1065 test SCB_CONTROL,DISCONNECTED jz not_found;
1066 setup_SCB_disconnected:
1067 and SCB_CONTROL,~DISCONNECTED;
1068 clr SEQ_FLAGS; /* make note of IDENTIFY */
1069 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
1070 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
1072 /* See if the host wants to send a message upon reconnection */
1073 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1074 mvi HOST_MSG call mk_mesg;
1078 SET_SEQINTCODE(NO_MATCH)
1082 SET_SEQINTCODE(NO_MATCH)
1086 * We received a "command complete" message. Put the SCB on the complete
1087 * queue and trigger a completion interrupt via the idle loop. Before doing
1088 * so, check to see if there is a residual or the status byte is something
1089 * other than STATUS_GOOD (0). In either of these conditions, we upload the
1090 * SCB back to the host so it can process this information.
1095 * If ATN is raised, we still want to give the target a message.
1096 * Perhaps there was a parity error on this last message byte.
1097 * Either way, the target should take us to message out phase
1098 * and then attempt to complete the command again. We should use a
1099 * critical section here to guard against a timeout triggering
1100 * for this command and setting ATN while we are still processing
1102 test SCSISIGI, ATNI jnz mesgin_done;
1106 * If we are identified and have successfully sent the CDB,
1107 * any status will do. Optimize this fast path.
1109 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1110 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1113 * If the target never sent an identify message but instead went
1114 * to mesgin to give an invalid message, let the host abort us.
1116 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1119 * If we recevied good status but never successfully sent the
1120 * cdb, abort the command.
1122 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1123 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1127 * See if we attempted to deliver a message but the target ingnored us.
1129 test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1130 SET_SEQINTCODE(MKMSG_FAILED)
1132 call queue_scb_completion;
1137 /* Cancel any pending select-out. */
1138 test SSTAT0, SELDO|SELINGO jnz . + 2;
1139 and SCSISEQ0, ~ENSELO;
1142 add QFREEZE_COUNT, 1;
1143 adc QFREEZE_COUNT[1], A;
1144 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1145 mov A, ACCUM_SAVE ret;
1149 * Complete the current FIFO's SCB if data for this same
1150 * SCB is not transferring in the other FIFO.
1152 SET_SRC_MODE M_DFF1;
1153 SET_DST_MODE M_DFF1;
1154 pkt_complete_scb_if_fifos_idle:
1155 bmov ARG_1, SCBPTR, 2;
1156 mvi DFFSXFRCTL, CLRCHN;
1157 SET_MODE(M_SCSI, M_SCSI)
1158 bmov SCBPTR, ARG_1, 2;
1159 test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1160 queue_scb_completion:
1161 test SCB_SCSI_STATUS,0xff jnz bad_status;
1163 * Check for residuals
1165 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1166 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1167 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1170 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1171 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1174 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1178 * Restore SCB TAG since we reuse this field
1179 * in the sequencer. We don't want to corrupt
1182 bmov SCB_TAG, SCBPTR, 2;
1184 or SCB_SGPTR, SG_STATUS_VALID;
1185 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
1186 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
1187 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1188 bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
1190 bmov REG0, SCBPTR, 2;
1191 bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
1192 bmov SCB_NEXT_COMPLETE, REG0, 2;
1193 bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
1197 * Is it a disconnect message? Set a flag in the SCB to remind us
1198 * and await the bus going free. If this is an untagged transaction
1199 * store the SCB id for it in our untagged target table for lookup on
1204 * If ATN is raised, we still want to give the target a message.
1205 * Perhaps there was a parity error on this last message byte
1206 * or we want to abort this command. Either way, the target
1207 * should take us to message out phase and then attempt to
1209 * XXX - Wait for more testing.
1210 test SCSISIGI, ATNI jnz mesgin_done;
1212 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1213 jnz mesgin_proto_violation;
1214 or SCB_CONTROL,DISCONNECTED;
1215 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1217 bmov REG0, SCBPTR, 2;
1218 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1219 bmov DINDEX, SINDEX, 2;
1220 bmov DINDIR, REG0, 2;
1221 bmov SCBPTR, REG0, 2;
1224 and SIMODE1, ~ENBUSFREE;
1225 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1227 * In the BUSFREEREV_BUG case, the
1228 * busfree status was cleared at the
1229 * beginning of the connection.
1231 mvi CLRSINT1,CLRBUSFREE;
1233 mov NONE, SCSIDAT; /* Ack the last byte */
1234 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1235 jnz await_busfree_not_m_dff;
1236 SET_SRC_MODE M_DFF1;
1237 SET_DST_MODE M_DFF1;
1238 await_busfree_clrchn:
1239 mvi DFFSXFRCTL, CLRCHN;
1240 await_busfree_not_m_dff:
1241 /* clear target specific flags */
1242 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
1243 test SSTAT1,REQINIT|BUSFREE jz .;
1245 * We only set BUSFREE status once either a new
1246 * phase has been detected or we are really
1247 * BUSFREE. This allows the driver to know
1248 * that we are active on the bus even though
1249 * no identified transaction exists should a
1250 * timeout occur while awaiting busfree.
1252 mvi LASTPHASE, P_BUSFREE;
1253 test SSTAT1, BUSFREE jnz idle_loop;
1254 SET_SEQINTCODE(MISSED_BUSFREE)
1258 * Save data pointers message:
1259 * Copying RAM values back to SCB, for Save Data Pointers message, but
1260 * only if we've actually been into a data phase to change them. This
1261 * protects against bogus data in scratch ram and the residual counts
1262 * since they are only initialized when we go into data_in or data_out.
1263 * Ack the message as soon as possible.
1265 SET_SRC_MODE M_DFF1;
1266 SET_DST_MODE M_DFF1;
1268 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1269 test SEQ_FLAGS, DPHASE jz ITloop;
1275 * If we are asked to save our position at the end of the
1276 * transfer, just mark us at the end rather than perform a
1279 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1280 or SCB_SGPTR, SG_LIST_NULL ret;
1284 * The SCB_DATAPTR becomes the current SHADDR.
1285 * All other information comes directly from our residual
1288 bmov SCB_DATAPTR, SHADDR, 8;
1289 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1292 * Restore pointers message? Data pointers are recopied from the
1293 * SCB anytime we enter a data phase for the first time, so all
1294 * we need to do is clear the DPHASE flag and let the data phase
1295 * code do the rest. We also reset/reallocate the FIFO to make
1296 * sure we have a clean start for the next data or command phase.
1299 and SEQ_FLAGS, ~DPHASE;
1300 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1301 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1302 SET_MODE(M_SCSI, M_SCSI)
1303 msgin_rdptrs_get_fifo:
1308 if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1310 * Don't ignore persistent REQ assertions just because
1311 * they were asserted within the bus settle delay window.
1312 * This allows us to tolerate devices like the GEM318
1313 * that violate the SCSI spec. We are careful not to
1314 * count REQ while we are waiting for it to fall during
1315 * an async phase due to our asserted ACK. Each
1316 * sequencer instruction takes ~25ns, so the REQ must
1317 * last at least 100ns in order to be counted as a true
1320 test SCSIPHASE, 0xFF jnz phase_locked;
1321 test SCSISIGI, ACKI jnz phase_lock;
1322 test SCSISIGI, REQI jz phase_lock;
1323 test SCSIPHASE, 0xFF jnz phase_locked;
1324 test SCSISIGI, ACKI jnz phase_lock;
1325 test SCSISIGI, REQI jz phase_lock;
1328 test SCSIPHASE, 0xFF jz .;
1330 test SSTAT1, SCSIPERR jnz phase_lock;
1331 phase_lock_latch_phase:
1332 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1335 * Functions to read data in Automatic PIO mode.
1337 * An ACK is not sent on input from the target until SCSIDATL is read from.
1338 * So we wait until SCSIDATL is latched (the usual way), then read the data
1339 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1340 * line, or we just want to acknowledge the byte, then we do a dummy read
1341 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1342 * data byte on the bus until we send our ACK.
1344 * The assumption here is that these are called in a particular sequence,
1345 * and that REQ is already set when inb_first is called. inb_{first,next}
1346 * use the same calling convention as inb.
1349 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1352 * If there is a parity error, wait for the kernel to
1353 * see the interrupt and prepare our message response
1354 * before continuing.
1356 test SCSIPHASE, 0xFF jz .;
1357 test SSTAT1, SCSIPERR jnz inb_next_wait;
1358 inb_next_check_phase:
1359 and LASTPHASE, PHASE_MASK, SCSISIGI;
1360 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1364 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1366 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1370 mov MSG_OUT,SINDEX ret;
1372 SET_SRC_MODE M_DFF1;
1373 SET_DST_MODE M_DFF1;
1375 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1377 disable_ccsgen_fetch_done:
1382 * Do we have any prefetch left???
1384 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1387 * Can this FIFO have access to the S/G cache yet?
1389 test CCSGCTL, SG_CACHE_AVAIL jz return;
1391 /* Did we just finish fetching segs? */
1392 test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1394 /* Are we actively fetching segments? */
1395 test CCSGCTL, CCSGENACK jnz return;
1398 * Should the other FIFO get the S/G cache first? If
1399 * both FIFOs have been allocated since we last checked
1400 * any FIFO, it is important that we service a FIFO
1401 * that is not actively on the bus first. This guarantees
1402 * that a FIFO will be freed to handle snapshot requests for
1403 * any FIFO that is still on the bus. Chips with RTI do not
1404 * perform snapshots, so don't bother with this test there.
1406 if ((ahd->features & AHD_RTI) == 0) {
1408 * If we're not still receiving SCSI data,
1409 * it is safe to allocate the S/G cache to
1412 test DFCNTRL, SCSIEN jz idle_sgfetch_start;
1415 * Switch to the other FIFO. Non-RTI chips
1416 * also have the "set mode" bug, so we must
1417 * disable interrupts during the switch.
1419 mvi SEQINTCTL, INTVEC1DSL;
1420 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1423 * If the other FIFO needs loading, then it
1424 * must not have claimed the S/G cache yet
1425 * (SG_CACHE_AVAIL would have been cleared in
1426 * the orginal FIFO mode and we test this above).
1427 * Return to the idle loop so we can process the
1428 * FIFO not currently on the bus first.
1430 test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
1433 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1439 * We fetch a "cacheline aligned" and sized amount of data
1440 * so we don't end up referencing a non-existant page.
1441 * Cacheline aligned is in quotes because the kernel will
1442 * set the prefetch amount to a reasonable level if the
1443 * cacheline size is unknown.
1445 bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1446 mvi SGHCNT, SG_PREFETCH_CNT;
1447 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1449 * Need two instructions between "touches" of SGHADDR.
1453 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1454 mvi CCSGCTL, CCSGEN|CCSGRESET;
1455 or SG_STATE, FETCH_INPROG ret;
1456 idle_sgfetch_complete:
1458 * Guard against SG_CACHE_AVAIL activating during sg fetch
1459 * request in the other FIFO.
1461 test SG_STATE, FETCH_INPROG jz return;
1463 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1464 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1466 /* Does the hardware have space for another SG entry? */
1467 test DFSTATUS, PRELOAD_AVAIL jz return;
1469 * On the A, preloading a segment before HDMAENACK
1470 * comes true can clobber the shaddow address of the
1471 * first segment in the S/G FIFO. Wait until it is
1474 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1475 test DFCNTRL, HDMAENACK jz return;
1477 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1478 bmov HADDR, CCSGRAM, 8;
1480 bmov HADDR, CCSGRAM, 4;
1482 bmov HCNT, CCSGRAM, 3;
1483 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1484 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1485 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1487 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1488 /* Skip 4 bytes of pad. */
1492 clr A; /* add sizeof(struct scatter) */
1493 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1494 adc SCB_RESIDUAL_SGPTR[1],A;
1495 adc SCB_RESIDUAL_SGPTR[2],A;
1496 adc SCB_RESIDUAL_SGPTR[3],A;
1497 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1498 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1499 or SINDEX, LAST_SEG;
1501 mov SG_CACHE_PRE, SINDEX;
1502 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1504 * Use SCSIENWRDIS so that SCSIEN is never
1505 * modified by this operation.
1507 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1509 or DFCNTRL, PRELOADEN|HDMAEN;
1512 * Do we have another segment in the cache?
1514 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1516 and SG_STATE, ~SEGS_AVAIL ret;
1519 * Initialize the DMA address and counter from the SCB.
1522 bmov HADDR, SCB_DATAPTR, 11;
1523 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1524 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1525 or REG_ISR, LAST_SEG;
1526 mov SG_CACHE_PRE, REG_ISR;
1527 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1529 * Since we've are entering a data phase, we will
1530 * rely on the SCB_RESID* fields. Initialize the
1531 * residual and clear the full residual flag.
1533 and SCB_SGPTR[0], ~SG_FULL_RESID;
1534 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1535 /* If we need more S/G elements, tell the idle loop */
1536 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1537 mvi SG_STATE, LOADING_NEEDED ret;
1542 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1543 p_data_clear_handler:
1544 or LONGJMP_ADDR[1], INVALID_ADDR ret;
1547 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1548 SET_SEQINTCODE(PROTO_VIOLATION)
1551 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1554 * If we re-enter the data phase after going through another
1555 * phase, our transfer location has almost certainly been
1556 * corrupted by the interveining, non-data, transfers. Ask
1557 * the host driver to fix us up based on the transfer residual
1558 * unless we already know that we should be bitbucketing.
1560 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1561 SET_SEQINTCODE(PDATA_REINIT)
1562 jmp data_phase_inbounds;
1566 * Turn on `Bit Bucket' mode, wait until the target takes
1567 * us to another phase, and then notify the host.
1569 mov SAVED_MODE, MODE_PTR;
1570 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1571 jnz bitbucket_not_m_dff;
1573 * Ensure that any FIFO contents are cleared out and the
1574 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1575 * doesn't discard data already in the FIFO.
1577 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1578 SET_MODE(M_SCSI, M_SCSI)
1579 bitbucket_not_m_dff:
1580 or SXFRCTL1,BITBUCKET;
1581 /* Wait for non-data phase. */
1582 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1583 and SXFRCTL1, ~BITBUCKET;
1584 RESTORE_MODE(SAVED_MODE)
1585 SET_SRC_MODE M_DFF1;
1586 SET_DST_MODE M_DFF1;
1587 SET_SEQINTCODE(DATA_OVERRUN)
1590 data_phase_initialize:
1591 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1592 call load_first_seg;
1593 data_phase_inbounds:
1594 /* We have seen a data phase at least once. */
1595 or SEQ_FLAGS, DPHASE;
1596 mov SAVED_MODE, MODE_PTR;
1597 test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1598 call p_data_handle_xfer;
1599 data_group_dma_loop:
1601 * The transfer is complete if either the last segment
1602 * completes or the target changes phase. Both conditions
1603 * will clear SCSIEN.
1605 call idle_loop_service_fifos;
1606 call idle_loop_cchan;
1607 call idle_loop_gsfifo;
1608 RESTORE_MODE(SAVED_MODE)
1609 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1611 data_group_dmafinish:
1613 * The transfer has terminated either due to a phase
1614 * change, and/or the completion of the last segment.
1615 * We have two goals here. Do as much other work
1616 * as possible while the data fifo drains on a read
1617 * and respond as quickly as possible to the standard
1618 * messages (save data pointers/disconnect and command
1619 * complete) that usually follow a data phase.
1624 * Go ahead and shut down the DMA engine now.
1626 test DFCNTRL, DIRECTION jnz data_phase_finish;
1627 data_group_fifoflush:
1628 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1629 or DFCNTRL, FIFOFLUSH;
1632 * We have enabled the auto-ack feature. This means
1633 * that the controller may have already transferred
1634 * some overrun bytes into the data FIFO and acked them
1635 * on the bus. The only way to detect this situation is
1636 * to wait for LAST_SEG_DONE to come true on a completed
1637 * transfer and then test to see if the data FIFO is
1638 * non-empty. We know there is more data yet to transfer
1639 * if SG_LIST_NULL is not yet set, thus there cannot be
1642 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1643 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1644 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1649 * If the target has left us in data phase, loop through
1650 * the dma code again. We will only loop if there is a
1653 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1654 test SSTAT0, TARGET jnz data_phase_done;
1656 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1657 test SSTAT1, REQINIT jz .;
1658 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1662 /* Kill off any pending prefetch */
1663 call disable_ccsgen;
1664 or LONGJMP_ADDR[1], INVALID_ADDR;
1666 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1667 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1669 and SEQ_FLAGS, ~DPHASE_PENDING;
1670 * For data-in phases, wait for any pending acks from the
1671 * initiator before changing phase. We only need to
1672 * send Ignore Wide Residue messages for data-in phases.
1673 test DFCNTRL, DIRECTION jz target_ITloop;
1674 test SSTAT1, REQINIT jnz .;
1675 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1676 SET_MODE(M_SCSI, M_SCSI)
1677 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1680 * Issue an Ignore Wide Residue Message.
1681 mvi P_MESGIN|BSYO call change_phase;
1682 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1683 mvi 1 call target_outb;
1691 * We assume that, even though data may still be
1692 * transferring to the host, that the SCSI side of
1693 * the DMA engine is now in a static state. This
1694 * allows us to update our notion of where we are
1697 * If, by chance, we stopped before being able
1698 * to fetch additional segments for this transfer,
1699 * yet the last S/G was completely exhausted,
1700 * call our idle loop until it is able to load
1701 * another segment. This will allow us to immediately
1702 * pickup on the next segment on the next data phase.
1704 * If we happened to stop on the last segment, then
1705 * our residual information is still correct from
1706 * the idle loop and there is no need to perform
1709 residual_before_last_seg:
1710 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1712 * Can never happen from an interrupt as the packetized
1713 * hardware will only interrupt us once SHVALID or
1716 call idle_loop_service_fifos;
1717 RESTORE_MODE(SAVED_MODE)
1720 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1721 /* Record if we've consumed all S/G entries */
1722 test MDFFSTAT, SHVALID jz . + 2;
1723 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1724 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1728 * Fixup the residual next S/G pointer. The S/G preload
1729 * feature of the chip allows us to load two elements
1730 * in addition to the currently active element. We
1731 * store the bottom byte of the next S/G pointer in
1732 * the SG_CACHE_PTR register so we can restore the
1733 * correct value when the DMA completes. If the next
1734 * sg ptr value has advanced to the point where higher
1735 * bytes in the address have been affected, fix them
1738 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1739 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1740 add SCB_RESIDUAL_SGPTR[1], -1;
1741 adc SCB_RESIDUAL_SGPTR[2], -1;
1742 adc SCB_RESIDUAL_SGPTR[3], -1;
1744 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1745 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1746 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1749 call issue_cmdcmplt;
1750 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1751 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1753 * In H2A4, the mode pointer is not saved
1754 * for intvec2, but is restored on iret.
1755 * This can lead to the restoration of a
1756 * bogus mode ptr. Manually clear the
1757 * intmask bits and do a normal return
1760 and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1762 or SEQINTCTL, IRET ret;
1766 if ((ahd->features & AHD_RTI) == 0) {
1768 * On RevA Silicon, if the target returns us to data-out
1769 * after we have already trained for data-out, it is
1770 * possible for us to transition the free running clock to
1771 * data-valid before the required 100ns P1 setup time (8 P1
1772 * assertions in fast-160 mode). This will only happen if
1773 * this L-Q is a continuation of a data transfer for which
1774 * we have already prefetched data into our FIFO (LQ/Data
1775 * followed by LQ/Data for the same write transaction).
1776 * This can cause some target implementations to miss the
1777 * first few data transfers on the bus. We detect this
1778 * situation by noticing that this is the first data transfer
1779 * after an LQ (LQIWORKONLQ true), that the data transfer is
1780 * a continuation of a transfer already setup in our FIFO
1781 * (SAVEPTRS interrupt), and that the transaction is a write
1782 * (DIRECTION set in DFCNTRL). The delay is performed by
1783 * disabling SCSIEN until we see the first REQ from the
1786 * First instruction in an ISR cannot be a branch on
1787 * Rev A. Snapshot LQISTAT2 so the status is not missed
1788 * and deffer the test by one instruction.
1790 mov REG_ISR, LQISTAT2;
1791 test REG_ISR, LQIWORKONLQ jz main_isr;
1792 test SEQINTSRC, SAVEPTRS jz main_isr;
1793 test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1795 * Switch to the active FIFO after clearing the snapshot
1796 * savepointer in the current FIFO. We do this so that
1797 * a pending CTXTDONE or SAVEPTR is visible in the active
1798 * FIFO. This status is the only way we can detect if we
1799 * have lost the race (e.g. host paused us) and our attempts
1800 * to disable the channel occurred after all REQs were
1801 * already seen and acked (REQINIT never comes true).
1803 mvi DFFSXFRCTL, CLRCHN;
1804 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1805 test DFCNTRL, DIRECTION jz interrupt_return;
1806 and DFCNTRL, ~SCSIEN;
1807 snapshot_wait_data_valid:
1808 test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
1809 test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1810 snapshot_data_valid:
1812 or SEQINTCTL, IRET ret;
1814 mvi DFFSXFRCTL, CLRCHN;
1815 or SEQINTCTL, IRET ret;
1818 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1819 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1820 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1821 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1822 SET_SEQINTCODE(INVALID_SEQINT)
1825 * There are two types of save pointers interrupts:
1826 * The first is a snapshot save pointers where the current FIFO is not
1827 * active and contains a snapshot of the current poniter information.
1828 * This happens between packets in a stream for a single L_Q. Since we
1829 * are not performing a pointer save, we can safely clear the channel
1830 * so it can be used for other transactions. On RTI capable controllers,
1831 * where snapshots can, and are, disabled, the code to handle this type
1832 * of snapshot is not active.
1834 * The second case is a save pointers on an active FIFO which occurs
1835 * if the target changes to a new L_Q or busfrees/QASes and the transfer
1836 * has a residual. This should occur coincident with a ctxtdone. We
1837 * disable the interrupt and allow our active routine to handle the
1841 if ((ahd->features & AHD_RTI) == 0) {
1842 test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1844 saveptr_active_fifo:
1845 and SEQIMODE, ~ENSAVEPTRS;
1846 or SEQINTCTL, IRET ret;
1849 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1850 call load_first_seg;
1851 call pkt_handle_xfer;
1852 inc SCB_FIFO_USE_COUNT;
1854 or SEQINTCTL, IRET ret;
1858 add NONE, -13, SCB_CDB_LEN;
1859 jnc cfg4istat_have_sense_addr;
1860 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1862 * Host sets up address/count and enables transfer.
1864 SET_SEQINTCODE(CFG4ISTAT_INTR)
1865 jmp cfg4istat_setup_handler;
1866 cfg4istat_have_sense_addr:
1867 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1868 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1869 mvi SG_CACHE_PRE, LAST_SEG;
1870 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1871 cfg4istat_setup_handler:
1873 * Status pkt is transferring to host.
1874 * Wait in idle loop for transfer to complete.
1875 * If a command completed before an attempted
1876 * task management function completed, notify the host.
1878 test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1879 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1880 cfg4istat_no_taskmgmt_func:
1881 call pkt_handle_status;
1882 or SEQINTCTL, IRET ret;
1886 * In the case of DMAing a CDB from the host, the normal
1887 * CDB buffer is formatted with an 8 byte address followed
1888 * by a 1 byte count.
1890 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1891 mvi SG_CACHE_PRE, LAST_SEG;
1892 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1893 call pkt_handle_cdb;
1894 or SEQINTCTL, IRET ret;
1897 * See if the target has gone on in this context creating an
1898 * overrun condition. For the write case, the hardware cannot
1899 * ack bytes until data are provided. So, if the target begins
1900 * another packet without changing contexts, implying we are
1901 * not sitting on a packet boundary, we are in an overrun
1902 * situation. For the read case, the hardware will continue to
1903 * ack bytes into the FIFO, and may even ack the last overrun packet
1904 * into the FIFO. If the FIFO should become non-empty, we are in
1905 * a read overrun case.
1907 #define check_overrun \
1908 /* Not on a packet boundary. */ \
1909 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1910 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1913 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1915 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1916 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1917 test SCSISIGO, ATNO jnz . + 2;
1918 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1920 * Defer handling of this NONPACKREQ until we
1921 * can be sure it pertains to this FIFO. SAVEPTRS
1922 * will not be asserted if the NONPACKREQ is for us,
1923 * so we must simulate it if shaddow is valid. If
1924 * shaddow is not valid, keep running this FIFO until we
1925 * have satisfied the transfer by loading segments and
1926 * waiting for either shaddow valid or last_seg_done.
1928 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1930 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1933 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1934 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
1935 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1936 test SCSISIGO, ATNO jnz . + 2;
1937 test SSTAT2, NONPACKREQ jz return;
1938 test MDFFSTAT, SHVALID jz return;
1942 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1943 * or we have a pending NONPACKREQ for this FIFO. We differentiate
1944 * between the two by capturing the state of the SAVEPTRS interrupt
1945 * prior to clearing this status and executing the common code for
1950 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1951 or DFCNTRL, FIFOFLUSH;
1953 mov REG0, SEQINTSRC;
1956 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1957 call disable_ccsgen;
1958 or SEQIMODE, ENSAVEPTRS;
1959 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1960 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1962 * Keep a handler around for this FIFO until it drains
1963 * to the host to guarantee that we don't complete the
1964 * command to the host before the data arrives.
1966 pkt_saveptrs_wait_fifoemp:
1968 test DFSTATUS, FIFOEMP jz return;
1969 pkt_saveptrs_check_status:
1970 or LONGJMP_ADDR[1], INVALID_ADDR;
1971 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1972 dec SCB_FIFO_USE_COUNT;
1973 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1974 mvi DFFSXFRCTL, CLRCHN ret;
1977 * LAST_SEG_DONE status has been seen in the current FIFO.
1978 * This indicates that all of the allowed data for this
1979 * command has transferred across the SCSI and host buses.
1980 * Check for overrun and see if we can complete this command.
1984 * Mark transfer as completed.
1986 or SCB_SGPTR, SG_LIST_NULL;
1989 * Wait for the current context to finish to verify that
1990 * no overrun condition has occurred.
1992 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1994 pkt_wait_ctxt_done_loop:
1995 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1997 * A sufficiently large overrun or a NONPACKREQ may
1998 * prevent CTXTDONE from ever asserting, so we must
1999 * poll for these statuses too.
2002 test SSTAT2, NONPACKREQ jz return;
2003 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2008 or LONGJMP_ADDR[1], INVALID_ADDR;
2010 * If status has been received, it is safe to skip
2011 * the check to see if another FIFO is active because
2012 * LAST_SEG_DONE has been observed. However, we check
2013 * the FIFO anyway since it costs us only one extra
2014 * instruction to leverage common code to perform the
2017 dec SCB_FIFO_USE_COUNT;
2018 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2019 mvi DFFSXFRCTL, CLRCHN ret;
2023 * Must wait until CDB xfer is over before issuing the
2028 test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
2029 or LONGJMP_ADDR[1], INVALID_ADDR;
2030 mvi DFFSXFRCTL, CLRCHN ret;
2033 * Watch over the status transfer. Our host sense buffer is
2034 * large enough to take the maximum allowed status packet.
2035 * None-the-less, we must still catch and report overruns to
2036 * the host. Additionally, properly catch unexpected non-packet
2037 * phases that are typically caused by CRC errors in status packet
2042 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2043 test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
2044 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2046 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
2047 or DFCNTRL, FIFOFLUSH;
2049 test DFSTATUS, FIFOEMP jz return;
2051 or LONGJMP_ADDR[1], INVALID_ADDR;
2052 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
2053 or SCB_CONTROL, STATUS_RCVD;
2054 jmp pkt_complete_scb_if_fifos_idle;
2056 pkt_status_check_overrun:
2058 * Status PKT overruns are uncerimoniously recovered with a
2059 * bus reset. If we've overrun, let the host know so that
2060 * recovery can be performed.
2062 * LAST_SEG_DONE has been observed. If either CTXTDONE or
2063 * a NONPACKREQ phase change have occurred and the FIFO is
2064 * empty, there is no overrun.
2066 test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
2067 test SEQINTSRC, CTXTDONE jz . + 2;
2068 test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
2069 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2070 test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
2071 pkt_status_report_overrun:
2072 SET_SEQINTCODE(STATUS_OVERRUN)
2073 /* SEQUENCER RESTARTED */
2074 pkt_status_check_nonpackreq:
2076 * CTXTDONE may be held off if a NONPACKREQ is associated with
2077 * the current context. If a NONPACKREQ is observed, decide
2078 * if it is for the current context. If it is for the current
2079 * context, we must defer NONPACKREQ processing until all data
2080 * has transferred to the host.
2082 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2083 test SCSISIGO, ATNO jnz . + 2;
2084 test SSTAT2, NONPACKREQ jz return;
2085 test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
2086 test DFSTATUS, FIFOEMP jz return;
2088 * The unexpected nonpkt phase handler assumes that any
2089 * data channel use will have a FIFO reference count. It
2090 * turns out that the status handler doesn't need a refernce
2091 * count since the status received flag, and thus completion
2092 * processing, cannot be set until the handler is finished.
2093 * We increment the count here to make the nonpkt handler
2096 inc SCB_FIFO_USE_COUNT;
2100 * Nonpackreq is a polled status. It can come true in three situations:
2101 * we have received an L_Q, we have sent one or more L_Qs, or there is no
2102 * L_Q context associated with this REQ (REQ occurs immediately after a
2103 * (re)selection). Routines that know that the context responsible for this
2104 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
2105 * top level idle loop, we exhaust all active contexts prior to determining that
2106 * we simply do not have the full I_T_L_Q for this phase.
2108 unexpected_nonpkt_phase_find_ctxt:
2110 * This nonpackreq is most likely associated with one of the tags
2111 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
2112 * nonpackreq if we've cleared out the FIFOs and handled any
2115 SET_SRC_MODE M_SCSI;
2116 SET_DST_MODE M_SCSI;
2117 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
2118 cmp A, FIFO1FREE|FIFO0FREE jne return;
2119 test SSTAT0, SELDO jnz return;
2120 mvi SCBPTR[1], SCB_LIST_NULL;
2121 unexpected_nonpkt_phase:
2122 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
2123 jnz unexpected_nonpkt_mode_cleared;
2124 SET_SRC_MODE M_DFF0;
2125 SET_DST_MODE M_DFF0;
2126 or LONGJMP_ADDR[1], INVALID_ADDR;
2127 dec SCB_FIFO_USE_COUNT;
2128 mvi DFFSXFRCTL, CLRCHN;
2129 unexpected_nonpkt_mode_cleared:
2130 mvi CLRSINT2, CLRNONPACKREQ;
2131 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
2132 SET_SEQINTCODE(ENTERING_NONPACK)
2136 SET_SEQINTCODE(ILLEGAL_PHASE)
2140 * We have entered an overrun situation. If we have working
2141 * BITBUCKET, flip that on and let the hardware eat any overrun
2142 * data. Otherwise use an overrun buffer in the host to simulate
2145 pkt_handle_overrun_inc_use_count:
2146 inc SCB_FIFO_USE_COUNT;
2148 SET_SEQINTCODE(CFG4OVERRUN)
2150 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
2151 or DFFSXFRCTL, DFFBITBUCKET;
2152 SET_SRC_MODE M_DFF1;
2153 SET_DST_MODE M_DFF1;
2155 call load_overrun_buf;
2156 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2159 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2160 test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
2161 call load_overrun_buf;
2162 or DFCNTRL, PRELOADEN;
2164 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2166 test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2168 test SSTAT2, NONPACKREQ jz return;
2170 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2171 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2172 dec SCB_FIFO_USE_COUNT;
2173 or LONGJMP_ADDR[1], INVALID_ADDR;
2174 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2175 mvi DFFSXFRCTL, CLRCHN ret;
2177 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2180 * Load a dummy segment if preload space is available.
2182 mov HADDR[0], SHARED_DATA_ADDR;
2183 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2186 adc HADDR[2], A, SHARED_DATA_ADDR[2];
2187 adc HADDR[3], A, SHARED_DATA_ADDR[3];
2189 bmov HADDR[4], ALLZEROS, 4;
2190 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2192 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);
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