2 * Inline routines shareable across OS platforms.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#57 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_inline.h,v 1.15 2004/05/11 20:46:05 gibbs Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx_inline.h,v 1.7 2007/07/06 02:23:31 pavalos Exp $
46 #ifndef _AIC79XX_INLINE_H_
47 #define _AIC79XX_INLINE_H_
49 /******************************** Debugging ***********************************/
50 static __inline char *ahd_name(struct ahd_softc *ahd);
52 static __inline char *
53 ahd_name(struct ahd_softc *ahd)
58 /************************ Sequencer Execution Control *************************/
59 static __inline void ahd_known_modes(struct ahd_softc *ahd,
60 ahd_mode src, ahd_mode dst);
61 static __inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *ahd,
64 static __inline void ahd_extract_mode_state(struct ahd_softc *ahd,
66 ahd_mode *src, ahd_mode *dst);
67 static __inline void ahd_set_modes(struct ahd_softc *ahd, ahd_mode src,
69 static __inline void ahd_update_modes(struct ahd_softc *ahd);
70 static __inline void ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
71 ahd_mode dstmode, const char *file,
73 static __inline ahd_mode_state ahd_save_modes(struct ahd_softc *ahd);
74 static __inline void ahd_restore_modes(struct ahd_softc *ahd,
75 ahd_mode_state state);
76 static __inline int ahd_is_paused(struct ahd_softc *ahd);
77 static __inline void ahd_pause(struct ahd_softc *ahd);
78 static __inline void ahd_unpause(struct ahd_softc *ahd);
81 ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
85 ahd->saved_src_mode = src;
86 ahd->saved_dst_mode = dst;
89 static __inline ahd_mode_state
90 ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
92 return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT));
96 ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state,
97 ahd_mode *src, ahd_mode *dst)
99 *src = (state & SRC_MODE) >> SRC_MODE_SHIFT;
100 *dst = (state & DST_MODE) >> DST_MODE_SHIFT;
104 ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
106 if (ahd->src_mode == src && ahd->dst_mode == dst)
109 if (ahd->src_mode == AHD_MODE_UNKNOWN
110 || ahd->dst_mode == AHD_MODE_UNKNOWN)
111 panic("Setting mode prior to saving it.\n");
112 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
113 kprintf("%s: Setting mode 0x%x\n", ahd_name(ahd),
114 ahd_build_mode_state(ahd, src, dst));
116 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
122 ahd_update_modes(struct ahd_softc *ahd)
124 ahd_mode_state mode_ptr;
128 mode_ptr = ahd_inb(ahd, MODE_PTR);
130 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
131 kprintf("Reading mode 0x%x\n", mode_ptr);
133 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
134 ahd_known_modes(ahd, src, dst);
138 ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
139 ahd_mode dstmode, const char *file, int line)
142 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
143 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
144 panic("%s:%s:%d: Mode assertion failed.\n",
145 ahd_name(ahd), file, line);
150 static __inline ahd_mode_state
151 ahd_save_modes(struct ahd_softc *ahd)
153 if (ahd->src_mode == AHD_MODE_UNKNOWN
154 || ahd->dst_mode == AHD_MODE_UNKNOWN)
155 ahd_update_modes(ahd);
157 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
161 ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
166 ahd_extract_mode_state(ahd, state, &src, &dst);
167 ahd_set_modes(ahd, src, dst);
170 #define AHD_ASSERT_MODES(ahd, source, dest) \
171 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__);
174 * Determine whether the sequencer has halted code execution.
175 * Returns non-zero status if the sequencer is stopped.
178 ahd_is_paused(struct ahd_softc *ahd)
180 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
184 * Request that the sequencer stop and wait, indefinitely, for it
185 * to stop. The sequencer will only acknowledge that it is paused
186 * once it has reached an instruction boundary and PAUSEDIS is
187 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
188 * for critical sections.
191 ahd_pause(struct ahd_softc *ahd)
193 ahd_outb(ahd, HCNTRL, ahd->pause);
196 * Since the sequencer can disable pausing in a critical section, we
197 * must loop until it actually stops.
199 while (ahd_is_paused(ahd) == 0)
204 * Allow the sequencer to continue program execution.
205 * We check here to ensure that no additional interrupt
206 * sources that would cause the sequencer to halt have been
207 * asserted. If, for example, a SCSI bus reset is detected
208 * while we are fielding a different, pausing, interrupt type,
209 * we don't want to release the sequencer before going back
210 * into our interrupt handler and dealing with this new
214 ahd_unpause(struct ahd_softc *ahd)
217 * Automatically restore our modes to those saved
218 * prior to the first change of the mode.
220 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
221 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) {
222 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0)
223 ahd_reset_cmds_pending(ahd);
224 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
227 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0)
228 ahd_outb(ahd, HCNTRL, ahd->unpause);
230 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
233 /*********************** Scatter Gather List Handling *************************/
234 static __inline void *ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
235 void *sgptr, bus_addr_t addr,
236 bus_size_t len, int last);
237 static __inline void ahd_setup_scb_common(struct ahd_softc *ahd,
239 static __inline void ahd_setup_data_scb(struct ahd_softc *ahd,
241 static __inline void ahd_setup_noxfer_scb(struct ahd_softc *ahd,
244 static __inline void *
245 ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
246 void *sgptr, bus_addr_t addr, bus_size_t len, int last)
249 if (sizeof(bus_addr_t) > 4
250 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
251 struct ahd_dma64_seg *sg;
253 sg = (struct ahd_dma64_seg *)sgptr;
254 sg->addr = aic_htole64(addr);
255 sg->len = aic_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
258 struct ahd_dma_seg *sg;
260 sg = (struct ahd_dma_seg *)sgptr;
261 sg->addr = aic_htole32(addr & 0xFFFFFFFF);
262 sg->len = aic_htole32(len | ((addr >> 8) & 0x7F000000)
263 | (last ? AHD_DMA_LAST_SEG : 0));
269 ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
271 /* XXX Handle target mode SCBs. */
272 scb->crc_retry_count = 0;
273 if ((scb->flags & SCB_PACKETIZED) != 0) {
274 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
275 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
277 if (aic_get_transfer_length(scb) & 0x01)
278 scb->hscb->task_attribute = SCB_XFERLEN_ODD;
280 scb->hscb->task_attribute = 0;
283 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
284 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
285 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
286 aic_htole32(scb->sense_busaddr);
290 ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
293 * Copy the first SG into the "current" data ponter area.
295 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
296 struct ahd_dma64_seg *sg;
298 sg = (struct ahd_dma64_seg *)scb->sg_list;
299 scb->hscb->dataptr = sg->addr;
300 scb->hscb->datacnt = sg->len;
302 struct ahd_dma_seg *sg;
303 uint32_t *dataptr_words;
305 sg = (struct ahd_dma_seg *)scb->sg_list;
306 dataptr_words = (uint32_t*)&scb->hscb->dataptr;
307 dataptr_words[0] = sg->addr;
308 dataptr_words[1] = 0;
309 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
312 high_addr = aic_le32toh(sg->len) & 0x7F000000;
313 scb->hscb->dataptr |= aic_htole64(high_addr << 8);
315 scb->hscb->datacnt = sg->len;
318 * Note where to find the SG entries in bus space.
319 * We also set the full residual flag which the
320 * sequencer will clear as soon as a data transfer
323 scb->hscb->sgptr = aic_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
327 ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
329 scb->hscb->sgptr = aic_htole32(SG_LIST_NULL);
330 scb->hscb->dataptr = 0;
331 scb->hscb->datacnt = 0;
334 /************************** Memory mapping routines ***************************/
335 static __inline size_t ahd_sg_size(struct ahd_softc *ahd);
336 static __inline void *
337 ahd_sg_bus_to_virt(struct ahd_softc *ahd,
339 uint32_t sg_busaddr);
340 static __inline uint32_t
341 ahd_sg_virt_to_bus(struct ahd_softc *ahd,
344 static __inline void ahd_sync_scb(struct ahd_softc *ahd,
345 struct scb *scb, int op);
346 static __inline void ahd_sync_sglist(struct ahd_softc *ahd,
347 struct scb *scb, int op);
348 static __inline void ahd_sync_sense(struct ahd_softc *ahd,
349 struct scb *scb, int op);
350 static __inline uint32_t
351 ahd_targetcmd_offset(struct ahd_softc *ahd,
354 static __inline size_t
355 ahd_sg_size(struct ahd_softc *ahd)
357 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
358 return (sizeof(struct ahd_dma64_seg));
359 return (sizeof(struct ahd_dma_seg));
362 static __inline void *
363 ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
365 bus_addr_t sg_offset;
367 /* sg_list_phys points to entry 1, not 0 */
368 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
369 return ((uint8_t *)scb->sg_list + sg_offset);
372 static __inline uint32_t
373 ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
375 bus_addr_t sg_offset;
377 /* sg_list_phys points to entry 1, not 0 */
378 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
381 return (scb->sg_list_busaddr + sg_offset);
385 ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
387 aic_dmamap_sync(ahd, ahd->scb_data.hscb_dmat,
388 scb->hscb_map->dmamap,
389 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
390 /*len*/sizeof(*scb->hscb), op);
394 ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
396 if (scb->sg_count == 0)
399 aic_dmamap_sync(ahd, ahd->scb_data.sg_dmat,
401 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
402 /*len*/ahd_sg_size(ahd) * scb->sg_count, op);
406 ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
408 aic_dmamap_sync(ahd, ahd->scb_data.sense_dmat,
409 scb->sense_map->dmamap,
410 /*offset*/scb->sense_busaddr,
411 /*len*/AHD_SENSE_BUFSIZE, op);
414 static __inline uint32_t
415 ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
417 return (((uint8_t *)&ahd->targetcmds[index])
418 - (uint8_t *)ahd->qoutfifo);
421 /*********************** Miscelaneous Support Functions ***********************/
422 static __inline void ahd_complete_scb(struct ahd_softc *ahd,
424 static __inline void ahd_update_residual(struct ahd_softc *ahd,
426 static __inline struct ahd_initiator_tinfo *
427 ahd_fetch_transinfo(struct ahd_softc *ahd,
428 char channel, u_int our_id,
430 struct ahd_tmode_tstate **tstate);
431 static __inline uint16_t
432 ahd_inw(struct ahd_softc *ahd, u_int port);
433 static __inline void ahd_outw(struct ahd_softc *ahd, u_int port,
435 static __inline uint32_t
436 ahd_inl(struct ahd_softc *ahd, u_int port);
437 static __inline void ahd_outl(struct ahd_softc *ahd, u_int port,
439 static __inline uint64_t
440 ahd_inq(struct ahd_softc *ahd, u_int port);
441 static __inline void ahd_outq(struct ahd_softc *ahd, u_int port,
443 static __inline u_int ahd_get_scbptr(struct ahd_softc *ahd);
444 static __inline void ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr);
445 static __inline u_int ahd_get_hnscb_qoff(struct ahd_softc *ahd);
446 static __inline void ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value);
447 static __inline u_int ahd_get_hescb_qoff(struct ahd_softc *ahd);
448 static __inline void ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value);
449 static __inline u_int ahd_get_snscb_qoff(struct ahd_softc *ahd);
450 static __inline void ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value);
451 static __inline u_int ahd_get_sescb_qoff(struct ahd_softc *ahd);
452 static __inline void ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value);
453 static __inline u_int ahd_get_sdscb_qoff(struct ahd_softc *ahd);
454 static __inline void ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value);
455 static __inline u_int ahd_inb_scbram(struct ahd_softc *ahd, u_int offset);
456 static __inline u_int ahd_inw_scbram(struct ahd_softc *ahd, u_int offset);
457 static __inline uint32_t
458 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset);
459 static __inline uint64_t
460 ahd_inq_scbram(struct ahd_softc *ahd, u_int offset);
461 static __inline void ahd_swap_with_next_hscb(struct ahd_softc *ahd,
463 static __inline void ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb);
464 static __inline uint8_t *
465 ahd_get_sense_buf(struct ahd_softc *ahd,
467 static __inline uint32_t
468 ahd_get_sense_bufaddr(struct ahd_softc *ahd,
472 ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb)
476 sgptr = aic_le32toh(scb->hscb->sgptr);
477 if ((sgptr & SG_STATUS_VALID) != 0)
478 ahd_handle_scb_status(ahd, scb);
484 * Determine whether the sequencer reported a residual
485 * for this SCB/transaction.
488 ahd_update_residual(struct ahd_softc *ahd, struct scb *scb)
492 sgptr = aic_le32toh(scb->hscb->sgptr);
493 if ((sgptr & SG_STATUS_VALID) != 0)
494 ahd_calc_residual(ahd, scb);
498 * Return pointers to the transfer negotiation information
499 * for the specified our_id/remote_id pair.
501 static __inline struct ahd_initiator_tinfo *
502 ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
503 u_int remote_id, struct ahd_tmode_tstate **tstate)
506 * Transfer data structures are stored from the perspective
507 * of the target role. Since the parameters for a connection
508 * in the initiator role to a given target are the same as
509 * when the roles are reversed, we pretend we are the target.
513 *tstate = ahd->enabled_targets[our_id];
514 return (&(*tstate)->transinfo[remote_id]);
517 #define AHD_COPY_COL_IDX(dst, src) \
519 dst->hscb->scsiid = src->hscb->scsiid; \
520 dst->hscb->lun = src->hscb->lun; \
523 static __inline uint16_t
524 ahd_inw(struct ahd_softc *ahd, u_int port)
527 * Read high byte first as some registers increment
528 * or have other side effects when the low byte is
531 return ((ahd_inb(ahd, port+1) << 8) | ahd_inb(ahd, port));
535 ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
538 * Write low byte first to accomodate registers
539 * such as PRGMCNT where the order maters.
541 ahd_outb(ahd, port, value & 0xFF);
542 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
545 static __inline uint32_t
546 ahd_inl(struct ahd_softc *ahd, u_int port)
548 return ((ahd_inb(ahd, port))
549 | (ahd_inb(ahd, port+1) << 8)
550 | (ahd_inb(ahd, port+2) << 16)
551 | (ahd_inb(ahd, port+3) << 24));
555 ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
557 ahd_outb(ahd, port, (value) & 0xFF);
558 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
559 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
560 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
563 static __inline uint64_t
564 ahd_inq(struct ahd_softc *ahd, u_int port)
566 return ((ahd_inb(ahd, port))
567 | (ahd_inb(ahd, port+1) << 8)
568 | (ahd_inb(ahd, port+2) << 16)
569 | (ahd_inb(ahd, port+3) << 24)
570 | (((uint64_t)ahd_inb(ahd, port+4)) << 32)
571 | (((uint64_t)ahd_inb(ahd, port+5)) << 40)
572 | (((uint64_t)ahd_inb(ahd, port+6)) << 48)
573 | (((uint64_t)ahd_inb(ahd, port+7)) << 56));
577 ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
579 ahd_outb(ahd, port, value & 0xFF);
580 ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
581 ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
582 ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
583 ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
584 ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
585 ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
586 ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
589 static __inline u_int
590 ahd_get_scbptr(struct ahd_softc *ahd)
592 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
593 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
594 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
598 ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
600 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
601 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
602 ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
603 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
606 static __inline u_int
607 ahd_get_hnscb_qoff(struct ahd_softc *ahd)
609 return (ahd_inw_atomic(ahd, HNSCB_QOFF));
613 ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
615 ahd_outw_atomic(ahd, HNSCB_QOFF, value);
618 static __inline u_int
619 ahd_get_hescb_qoff(struct ahd_softc *ahd)
621 return (ahd_inb(ahd, HESCB_QOFF));
625 ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
627 ahd_outb(ahd, HESCB_QOFF, value);
630 static __inline u_int
631 ahd_get_snscb_qoff(struct ahd_softc *ahd)
635 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
636 oldvalue = ahd_inw(ahd, SNSCB_QOFF);
637 ahd_outw(ahd, SNSCB_QOFF, oldvalue);
642 ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
644 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
645 ahd_outw(ahd, SNSCB_QOFF, value);
648 static __inline u_int
649 ahd_get_sescb_qoff(struct ahd_softc *ahd)
651 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
652 return (ahd_inb(ahd, SESCB_QOFF));
656 ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
658 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
659 ahd_outb(ahd, SESCB_QOFF, value);
662 static __inline u_int
663 ahd_get_sdscb_qoff(struct ahd_softc *ahd)
665 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
666 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
670 ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
672 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
673 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
674 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
677 static __inline u_int
678 ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
683 * Workaround PCI-X Rev A. hardware bug.
684 * After a host read of SCB memory, the chip
685 * may become confused into thinking prefetch
686 * was required. This starts the discard timer
687 * running and can cause an unexpected discard
688 * timer interrupt. The work around is to read
689 * a normal register prior to the exhaustion of
690 * the discard timer. The mode pointer register
691 * has no side effects and so serves well for
696 value = ahd_inb(ahd, offset);
697 if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0)
698 ahd_inb(ahd, MODE_PTR);
702 static __inline u_int
703 ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
705 return (ahd_inb_scbram(ahd, offset)
706 | (ahd_inb_scbram(ahd, offset+1) << 8));
709 static __inline uint32_t
710 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
712 return (ahd_inw_scbram(ahd, offset)
713 | (ahd_inw_scbram(ahd, offset+2) << 16));
716 static __inline uint64_t
717 ahd_inq_scbram(struct ahd_softc *ahd, u_int offset)
719 return (ahd_inl_scbram(ahd, offset)
720 | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32);
723 static __inline struct scb *
724 ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
728 if (tag >= AHD_SCB_MAX)
730 scb = ahd->scb_data.scbindex[tag];
732 ahd_sync_scb(ahd, scb,
733 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
738 ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
740 struct hardware_scb *q_hscb;
741 struct map_node *q_hscb_map;
742 uint32_t saved_hscb_busaddr;
745 * Our queuing method is a bit tricky. The card
746 * knows in advance which HSCB (by address) to download,
747 * and we can't disappoint it. To achieve this, the next
748 * HSCB to download is saved off in ahd->next_queued_hscb.
749 * When we are called to queue "an arbitrary scb",
750 * we copy the contents of the incoming HSCB to the one
751 * the sequencer knows about, swap HSCB pointers and
752 * finally assign the SCB to the tag indexed location
753 * in the scb_array. This makes sure that we can still
754 * locate the correct SCB by SCB_TAG.
756 q_hscb = ahd->next_queued_hscb;
757 q_hscb_map = ahd->next_queued_hscb_map;
758 saved_hscb_busaddr = q_hscb->hscb_busaddr;
759 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
760 q_hscb->hscb_busaddr = saved_hscb_busaddr;
761 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
763 /* Now swap HSCB pointers. */
764 ahd->next_queued_hscb = scb->hscb;
765 ahd->next_queued_hscb_map = scb->hscb_map;
767 scb->hscb_map = q_hscb_map;
769 /* Now define the mapping from tag to SCB in the scbindex */
770 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
774 * Tell the sequencer about a new transaction to execute.
777 ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
779 ahd_swap_with_next_hscb(ahd, scb);
781 if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
782 panic("Attempt to queue invalid SCB tag %x\n",
786 * Keep a history of SCBs we've downloaded in the qinfifo.
788 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
791 if (scb->sg_count != 0)
792 ahd_setup_data_scb(ahd, scb);
794 ahd_setup_noxfer_scb(ahd, scb);
795 ahd_setup_scb_common(ahd, scb);
798 * Make sure our data is consistent from the
799 * perspective of the adapter.
801 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
804 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
805 uint64_t host_dataptr;
807 host_dataptr = aic_le64toh(scb->hscb->dataptr);
808 kprintf("%s: Queueing SCB 0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
810 SCB_GET_TAG(scb), aic_le32toh(scb->hscb->hscb_busaddr),
811 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF),
812 (u_int)(host_dataptr & 0xFFFFFFFF),
813 aic_le32toh(scb->hscb->datacnt));
816 /* Tell the adapter about the newly queued SCB */
817 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
820 static __inline uint8_t *
821 ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb)
823 return (scb->sense_data);
826 static __inline uint32_t
827 ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb)
829 return (scb->sense_busaddr);
832 /************************** Interrupt Processing ******************************/
833 static __inline void ahd_sync_qoutfifo(struct ahd_softc *ahd, int op);
834 static __inline void ahd_sync_tqinfifo(struct ahd_softc *ahd, int op);
835 static __inline u_int ahd_check_cmdcmpltqueues(struct ahd_softc *ahd);
836 static __inline int ahd_intr(struct ahd_softc *ahd);
839 ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
841 aic_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
843 /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
847 ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
849 #ifdef AHD_TARGET_MODE
850 if ((ahd->flags & AHD_TARGETROLE) != 0) {
851 aic_dmamap_sync(ahd, ahd->shared_data_dmat,
852 ahd->shared_data_map.dmamap,
853 ahd_targetcmd_offset(ahd, 0),
854 sizeof(struct target_cmd) * AHD_TMODE_CMDS,
861 * See if the firmware has posted any completed commands
862 * into our in-core command complete fifos.
864 #define AHD_RUN_QOUTFIFO 0x1
865 #define AHD_RUN_TQINFIFO 0x2
866 static __inline u_int
867 ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
872 aic_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
873 /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
874 /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
875 if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
876 == ahd->qoutfifonext_valid_tag)
877 retval |= AHD_RUN_QOUTFIFO;
878 #ifdef AHD_TARGET_MODE
879 if ((ahd->flags & AHD_TARGETROLE) != 0
880 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
881 aic_dmamap_sync(ahd, ahd->shared_data_dmat,
882 ahd->shared_data_map.dmamap,
883 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
884 /*len*/sizeof(struct target_cmd),
885 BUS_DMASYNC_POSTREAD);
886 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
887 retval |= AHD_RUN_TQINFIFO;
894 * Catch an interrupt from the adapter
897 ahd_intr(struct ahd_softc *ahd)
901 if ((ahd->pause & INTEN) == 0) {
903 * Our interrupt is not enabled on the chip
904 * and may be disabled for re-entrancy reasons,
905 * so just return. This is likely just a shared
912 * Instead of directly reading the interrupt status register,
913 * infer the cause of the interrupt by checking our in-core
914 * completion queues. This avoids a costly PCI bus read in
917 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
918 && (ahd_check_cmdcmpltqueues(ahd) != 0))
921 intstat = ahd_inb(ahd, INTSTAT);
923 if ((intstat & INT_PEND) == 0)
926 if (intstat & CMDCMPLT) {
927 ahd_outb(ahd, CLRINT, CLRCMDINT);
930 * Ensure that the chip sees that we've cleared
931 * this interrupt before we walk the output fifo.
932 * Otherwise, we may, due to posted bus writes,
933 * clear the interrupt after we finish the scan,
934 * and after the sequencer has added new entries
935 * and asserted the interrupt again.
937 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
938 if (ahd_is_paused(ahd)) {
940 * Potentially lost SEQINT.
941 * If SEQINTCODE is non-zero,
942 * simulate the SEQINT.
944 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT)
948 ahd_flush_device_writes(ahd);
950 ahd_run_qoutfifo(ahd);
951 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++;
952 ahd->cmdcmplt_total++;
953 #ifdef AHD_TARGET_MODE
954 if ((ahd->flags & AHD_TARGETROLE) != 0)
955 ahd_run_tqinfifo(ahd, /*paused*/FALSE);
960 * Handle statuses that may invalidate our cached
961 * copy of INTSTAT separately.
963 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) {
964 /* Hot eject. Do nothing */
965 } else if (intstat & HWERRINT) {
966 ahd_handle_hwerrint(ahd);
967 } else if ((intstat & (PCIINT|SPLTINT)) != 0) {
971 if ((intstat & SEQINT) != 0)
972 ahd_handle_seqint(ahd, intstat);
974 if ((intstat & SCSIINT) != 0)
975 ahd_handle_scsiint(ahd, intstat);
980 #endif /* _AIC79XX_INLINE_H_ */