2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <machine/psl.h>
51 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
67 #include <machine/lock.h> /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
87 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
91 static __inline u_long
96 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
100 static __inline u_long
105 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
109 static __inline u_int
114 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
118 static __inline u_long
123 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
128 do_cpuid(u_int ax, u_int *p)
130 __asm __volatile("cpuid"
131 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
136 cpuid_count(u_int ax, u_int cx, u_int *p)
138 __asm __volatile("cpuid"
139 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
140 : "0" (ax), "c" (cx));
143 #ifndef _CPU_DISABLE_INTR_DEFINED
146 cpu_disable_intr(void)
148 __asm __volatile("cli" : : : "memory");
153 #ifndef _CPU_ENABLE_INTR_DEFINED
156 cpu_enable_intr(void)
158 __asm __volatile("sti");
164 * Cpu and compiler memory ordering fence. mfence ensures strong read and
167 * A serializing or fence instruction is required here. A locked bus
168 * cycle on data for which we already own cache mastership is the most
175 __asm __volatile("mfence" : : : "memory");
177 __asm __volatile("" : : : "memory");
182 * cpu_lfence() ensures strong read ordering for reads issued prior
183 * to the instruction verses reads issued afterwords.
185 * A serializing or fence instruction is required here. A locked bus
186 * cycle on data for which we already own cache mastership is the most
193 __asm __volatile("lfence" : : : "memory");
195 __asm __volatile("" : : : "memory");
200 * cpu_sfence() ensures strong write ordering for writes issued prior
201 * to the instruction verses writes issued afterwords. Writes are
202 * ordered on intel cpus so we do not actually have to do anything.
209 * Don't use 'sfence' here, as it will create a lot of
210 * unnecessary stalls.
212 __asm __volatile("" : : : "memory");
216 * cpu_ccfence() prevents the compiler from reordering instructions, in
217 * particular stores, relative to the current cpu. Use cpu_sfence() if
218 * you need to guarentee ordering by both the compiler and by the cpu.
220 * This also prevents the compiler from caching memory loads into local
221 * variables across the routine.
226 __asm __volatile("" : : : "memory");
230 * This is a horrible, horrible hack that might have to be put at the
231 * end of certain procedures (on a case by case basis), just before it
232 * returns to avoid what we believe to be an unreported AMD cpu bug.
233 * Found to occur on both a Phenom II X4 820 (two of them), as well
234 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
235 * The problem does not appear to occur w/Intel cpus.
237 * The bug is likely related to either a write combining issue or the
238 * Return Address Stack (RAS) hardware cache.
240 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
241 * which due to its deep recursion and stack flow appears to be able to
242 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
243 * end of the routine just before it returns works around the bug.
245 * The bug appears to be extremely sensitive to %rip and %rsp values, to
246 * the point where even just inserting an instruction in an unrelated
247 * procedure (shifting the entire code base being run) effects the outcome.
248 * DragonFly is probably able to more readily reproduce the bug due to
249 * the stackgap randomization code. We would expect OpenBSD (where we got
250 * the stackgap randomization code from) to also be able to reproduce the
251 * issue. To date we have only reproduced the issue in DragonFly.
253 #define __AMDCPUBUG_DFLY01_AVAILABLE__
256 cpu_amdcpubug_dfly01(void)
258 __asm __volatile("nop" : : : "memory");
263 #define HAVE_INLINE_FFS
270 * Note that gcc-2's builtin ffs would be used if we didn't declare
271 * this inline or turn off the builtin. The builtin is faster but
272 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
275 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
277 /* Actually, the above is way out of date. The builtins use cmov etc */
278 return (__builtin_ffs(mask));
282 #define HAVE_INLINE_FFSL
287 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
290 #define HAVE_INLINE_FLS
295 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
298 #define HAVE_INLINE_FLSL
303 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
311 __asm __volatile("hlt");
315 * The following complications are to get around gcc not having a
316 * constraint letter for the range 0..255. We still put "d" in the
317 * constraint because "i" isn't a valid constraint when the port
318 * isn't constant. This only matters for -O0 because otherwise
319 * the non-working version gets optimized away.
321 * Use an expression-statement instead of a conditional expression
322 * because gcc-2.6.0 would promote the operands of the conditional
323 * and produce poor code for "if ((inb(var) & const1) == const2)".
325 * The unnecessary test `(port) < 0x10000' is to generate a warning if
326 * the `port' has type u_short or smaller. Such types are pessimal.
327 * This actually only works for signed types. The range check is
328 * careful to avoid generating warnings.
330 #define inb(port) __extension__ ({ \
332 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
333 && (port) < 0x10000) \
334 _data = inbc(port); \
336 _data = inbv(port); \
339 #define outb(port, data) ( \
340 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
341 && (port) < 0x10000 \
342 ? outbc(port, data) : outbv(port, data))
344 static __inline u_char
349 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
354 outbc(u_int port, u_char data)
356 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
359 static __inline u_char
364 * We use %%dx and not %1 here because i/o is done at %dx and not at
365 * %edx, while gcc generates inferior code (movw instead of movl)
366 * if we tell it to load (u_short) port.
368 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
372 static __inline u_int
377 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
382 insb(u_int port, void *addr, size_t cnt)
384 __asm __volatile("cld; rep; insb"
385 : "+D" (addr), "+c" (cnt)
391 insw(u_int port, void *addr, size_t cnt)
393 __asm __volatile("cld; rep; insw"
394 : "+D" (addr), "+c" (cnt)
400 insl(u_int port, void *addr, size_t cnt)
402 __asm __volatile("cld; rep; insl"
403 : "+D" (addr), "+c" (cnt)
411 __asm __volatile("invd");
417 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
418 * will cause the invl*() functions to be equivalent to the cpu_invl*()
422 void smp_invltlb(void);
423 void smp_invltlb_intr(void);
425 #define smp_invltlb()
428 #ifndef _CPU_INVLPG_DEFINED
431 * Invalidate a patricular VA on this cpu only
434 cpu_invlpg(void *addr)
436 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
444 __asm __volatile("rep; nop");
449 static __inline u_short
454 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
458 static __inline u_int
459 loadandclear(volatile u_int *addr)
463 __asm __volatile("xorl %0,%0; xchgl %1,%0"
464 : "=&r" (result) : "m" (*addr));
469 outbv(u_int port, u_char data)
473 * Use an unnecessary assignment to help gcc's register allocator.
474 * This make a large difference for gcc-1.40 and a tiny difference
475 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
476 * best results. gcc-2.6.0 can't handle this.
479 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
483 outl(u_int port, u_int data)
486 * outl() and outw() aren't used much so we haven't looked at
487 * possible micro-optimizations such as the unnecessary
488 * assignment for them.
490 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
494 outsb(u_int port, const void *addr, size_t cnt)
496 __asm __volatile("cld; rep; outsb"
497 : "+S" (addr), "+c" (cnt)
502 outsw(u_int port, const void *addr, size_t cnt)
504 __asm __volatile("cld; rep; outsw"
505 : "+S" (addr), "+c" (cnt)
510 outsl(u_int port, const void *addr, size_t cnt)
512 __asm __volatile("cld; rep; outsl"
513 : "+S" (addr), "+c" (cnt)
518 outw(u_int port, u_short data)
520 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
526 __asm __volatile("pause");
529 static __inline u_long
534 __asm __volatile("pushfq; popq %0" : "=r" (rf));
538 static __inline u_int64_t
543 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
544 return (low | ((u_int64_t)high << 32));
547 static __inline u_int64_t
552 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
553 return (low | ((u_int64_t)high << 32));
556 #define _RDTSC_SUPPORTED_
558 static __inline u_int64_t
563 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
564 return (low | ((u_int64_t)high << 32));
570 __asm __volatile("wbinvd");
574 write_rflags(u_long rf)
576 __asm __volatile("pushq %0; popfq" : : "r" (rf));
580 wrmsr(u_int msr, u_int64_t newval)
586 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
590 load_cr0(u_long data)
593 __asm __volatile("movq %0,%%cr0" : : "r" (data));
596 static __inline u_long
601 __asm __volatile("movq %%cr0,%0" : "=r" (data));
605 static __inline u_long
610 __asm __volatile("movq %%cr2,%0" : "=r" (data));
615 load_cr3(u_long data)
618 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
621 static __inline u_long
626 __asm __volatile("movq %%cr3,%0" : "=r" (data));
631 load_cr4(u_long data)
633 __asm __volatile("movq %0,%%cr4" : : "r" (data));
636 static __inline u_long
641 __asm __volatile("movq %%cr4,%0" : "=r" (data));
645 #ifndef _CPU_INVLTLB_DEFINED
648 * Invalidate the TLB on this cpu only
654 #if defined(SWTCH_OPTIM_STATS)
662 * TLB flush for an individual page (even if it has PG_G).
663 * Only works on 486+ CPUs (i386 does not have PG_G).
669 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
672 static __inline u_short
676 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
680 static __inline u_short
684 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
691 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
697 __asm __volatile("movw %0,%%es" : : "rm" (sel));
701 /* This is defined in <machine/specialreg.h> but is too painful to get to */
703 #define MSR_FSBASE 0xc0000100
708 /* Preserve the fsbase value across the selector load */
709 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
710 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
714 #define MSR_GSBASE 0xc0000101
720 * Preserve the gsbase value across the selector load.
721 * Note that we have to disable interrupts because the gsbase
722 * being trashed happens to be the kernel gsbase at the time.
724 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
725 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
728 /* Usable by userland */
732 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
738 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
742 /* void lidt(struct region_descriptor *addr); */
744 lidt(struct region_descriptor *addr)
746 __asm __volatile("lidt (%0)" : : "r" (addr));
749 /* void lldt(u_short sel); */
753 __asm __volatile("lldt %0" : : "r" (sel));
756 /* void ltr(u_short sel); */
760 __asm __volatile("ltr %0" : : "r" (sel));
763 static __inline u_int64_t
767 __asm __volatile("movq %%dr0,%0" : "=r" (data));
772 load_dr0(u_int64_t dr0)
774 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
777 static __inline u_int64_t
781 __asm __volatile("movq %%dr1,%0" : "=r" (data));
786 load_dr1(u_int64_t dr1)
788 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
791 static __inline u_int64_t
795 __asm __volatile("movq %%dr2,%0" : "=r" (data));
800 load_dr2(u_int64_t dr2)
802 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
805 static __inline u_int64_t
809 __asm __volatile("movq %%dr3,%0" : "=r" (data));
814 load_dr3(u_int64_t dr3)
816 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
819 static __inline u_int64_t
823 __asm __volatile("movq %%dr4,%0" : "=r" (data));
828 load_dr4(u_int64_t dr4)
830 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
833 static __inline u_int64_t
837 __asm __volatile("movq %%dr5,%0" : "=r" (data));
842 load_dr5(u_int64_t dr5)
844 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
847 static __inline u_int64_t
851 __asm __volatile("movq %%dr6,%0" : "=r" (data));
856 load_dr6(u_int64_t dr6)
858 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
861 static __inline u_int64_t
865 __asm __volatile("movq %%dr7,%0" : "=r" (data));
870 load_dr7(u_int64_t dr7)
872 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
875 static __inline register_t
880 rflags = read_rflags();
886 intr_restore(register_t rflags)
888 write_rflags(rflags);
891 #else /* !__GNUC__ */
893 int breakpoint(void);
894 void cpu_pause(void);
895 u_int bsfl(u_int mask);
896 u_int bsrl(u_int mask);
897 void cpu_disable_intr(void);
898 void cpu_enable_intr(void);
899 void cpu_invlpg(u_long addr);
900 void cpu_invlpg_range(u_long start, u_long end);
901 void do_cpuid(u_int ax, u_int *p);
903 u_char inb(u_int port);
904 u_int inl(u_int port);
905 void insb(u_int port, void *addr, size_t cnt);
906 void insl(u_int port, void *addr, size_t cnt);
907 void insw(u_int port, void *addr, size_t cnt);
909 void invlpg(u_int addr);
910 void invlpg_range(u_int start, u_int end);
911 void cpu_invltlb(void);
912 u_short inw(u_int port);
913 void load_cr0(u_int cr0);
914 void load_cr3(u_int cr3);
915 void load_cr4(u_int cr4);
916 void load_fs(u_int sel);
917 void load_gs(u_int sel);
918 struct region_descriptor;
919 void lidt(struct region_descriptor *addr);
920 void lldt(u_short sel);
921 void ltr(u_short sel);
922 void outb(u_int port, u_char data);
923 void outl(u_int port, u_int data);
924 void outsb(u_int port, void *addr, size_t cnt);
925 void outsl(u_int port, void *addr, size_t cnt);
926 void outsw(u_int port, void *addr, size_t cnt);
927 void outw(u_int port, u_short data);
928 void ia32_pause(void);
935 u_int64_t rdmsr(u_int msr);
936 u_int64_t rdpmc(u_int pmc);
937 u_int64_t rdtsc(void);
938 u_int read_rflags(void);
940 void write_rflags(u_int rf);
941 void wrmsr(u_int msr, u_int64_t newval);
942 u_int64_t rdr0(void);
943 void load_dr0(u_int64_t dr0);
944 u_int64_t rdr1(void);
945 void load_dr1(u_int64_t dr1);
946 u_int64_t rdr2(void);
947 void load_dr2(u_int64_t dr2);
948 u_int64_t rdr3(void);
949 void load_dr3(u_int64_t dr3);
950 u_int64_t rdr4(void);
951 void load_dr4(u_int64_t dr4);
952 u_int64_t rdr5(void);
953 void load_dr5(u_int64_t dr5);
954 u_int64_t rdr6(void);
955 void load_dr6(u_int64_t dr6);
956 u_int64_t rdr7(void);
957 void load_dr7(u_int64_t dr7);
958 register_t intr_disable(void);
959 void intr_restore(register_t rf);
961 #endif /* __GNUC__ */
963 int rdmsr_safe(u_int msr, uint64_t *val);
964 void reset_dbregs(void);
968 #endif /* !_CPU_CPUFUNC_H_ */