2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.55 2008/09/06 21:18:39 hasso Exp $
34 #include "opt_compat_oldpci.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/types.h>
45 #include <sys/sysctl.h>
50 #include <vm/vm_extern.h>
54 #include <machine/smp.h>
55 #include "pci_cfgreg.h"
57 #include <sys/pciio.h>
60 #include "pci_private.h"
64 devclass_t pci_devclass;
65 const char *pcib_owner;
67 static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
68 static int pcie_slotimpl(const pcicfgregs *);
71 u_int32_t devid; /* Vendor/device of the card */
73 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
78 struct pci_quirk pci_quirks[] = {
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 /* map register information */
91 #define PCI_MAPMEM 0x01 /* memory map */
92 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93 #define PCI_MAPPORT 0x04 /* port map */
95 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96 u_int32_t pci_numdevs = 0;
97 static u_int32_t pci_generation = 0;
99 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "pci parameters");
100 static int pci_do_power_nodriver = 0;
101 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
102 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
103 &pci_do_power_nodriver, 0,
104 "Place a function into D3 state when no driver attaches to it. 0 means\n\
105 disable. 1 means conservatively place devices into D3 state. 2 means\n\
106 agressively place devices into D3 state. 3 means put absolutely everything\n\
110 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
112 struct pci_devinfo *dinfo;
114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
115 if ((dinfo->cfg.bus == bus) &&
116 (dinfo->cfg.slot == slot) &&
117 (dinfo->cfg.func == func)) {
118 return (dinfo->cfg.dev);
126 pci_find_device(u_int16_t vendor, u_int16_t device)
128 struct pci_devinfo *dinfo;
130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
131 if ((dinfo->cfg.vendor == vendor) &&
132 (dinfo->cfg.device == device)) {
133 return (dinfo->cfg.dev);
141 pcie_slot_implemented(device_t dev)
143 struct pci_devinfo *dinfo = device_get_ivars(dev);
145 return pcie_slotimpl(&dinfo->cfg);
148 /* return base address of memory or port map */
151 pci_mapbase(unsigned mapreg)
154 if ((mapreg & 0x01) == 0)
156 return (mapreg & ~mask);
159 /* return map type of memory or port map */
162 pci_maptype(unsigned mapreg)
164 static u_int8_t maptype[0x10] = {
165 PCI_MAPMEM, PCI_MAPPORT,
167 PCI_MAPMEM, PCI_MAPPORT,
169 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
170 PCI_MAPMEM|PCI_MAPMEMP, 0,
171 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
175 return maptype[mapreg & 0x0f];
178 /* return log2 of map size decoded for memory or port map */
181 pci_mapsize(unsigned testval)
185 testval = pci_mapbase(testval);
188 while ((testval & 1) == 0)
197 /* return log2 of address range supported by map register */
200 pci_maprange(unsigned mapreg)
203 switch (mapreg & 0x07) {
219 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
222 pci_fixancient(pcicfgregs *cfg)
224 if (cfg->hdrtype != 0)
227 /* PCI to PCI bridges use header type 1 */
228 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
232 /* read config data specific to header type 1 device (PCI to PCI bridge) */
235 pci_readppb(device_t pcib, int b, int s, int f)
239 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
241 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
242 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
244 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
246 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
248 PCIB_READ_CONFIG(pcib, b, s, f,
250 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIB_READ_CONFIG(pcib, b, s, f,
253 PCIR_IOLIMITL_1, 1));
255 p->membase = PCI_PPBMEMBASE (0,
256 PCIB_READ_CONFIG(pcib, b, s, f,
258 p->memlimit = PCI_PPBMEMLIMIT (0,
259 PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIR_MEMLIMIT_1, 2));
262 p->pmembase = PCI_PPBMEMBASE (
263 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
264 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
266 p->pmemlimit = PCI_PPBMEMLIMIT (
267 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
269 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
274 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
277 pci_readpcb(device_t pcib, int b, int s, int f)
281 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
283 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
284 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
286 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
288 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
289 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
290 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
291 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
293 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
294 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
295 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
296 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
298 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
302 /* extract header type specific config data */
305 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
307 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
308 switch (cfg->hdrtype) {
310 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
311 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
312 cfg->nummaps = PCI_MAXMAPS_0;
315 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
316 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
317 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
318 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
319 cfg->nummaps = PCI_MAXMAPS_1;
320 cfg->hdrspec = pci_readppb(pcib, b, s, f);
323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
325 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
326 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
327 cfg->nummaps = PCI_MAXMAPS_2;
328 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
334 /* read configuration header into pcicfgrect structure */
337 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
339 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
341 pcicfgregs *cfg = NULL;
342 struct pci_devinfo *devlist_entry;
343 struct devlist *devlist_head;
345 devlist_head = &pci_devq;
347 devlist_entry = NULL;
349 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
351 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
353 cfg = &devlist_entry->cfg;
358 cfg->vendor = REG(PCIR_VENDOR, 2);
359 cfg->device = REG(PCIR_DEVICE, 2);
360 cfg->cmdreg = REG(PCIR_COMMAND, 2);
361 cfg->statreg = REG(PCIR_STATUS, 2);
362 cfg->baseclass = REG(PCIR_CLASS, 1);
363 cfg->subclass = REG(PCIR_SUBCLASS, 1);
364 cfg->progif = REG(PCIR_PROGIF, 1);
365 cfg->revid = REG(PCIR_REVID, 1);
366 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
367 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
368 cfg->lattimer = REG(PCIR_LATTIMER, 1);
369 cfg->intpin = REG(PCIR_INTPIN, 1);
370 cfg->intline = REG(PCIR_INTLINE, 1);
374 * If using the APIC the intpin is probably wrong, since it
375 * is often setup by the BIOS with the PIC in mind.
377 if (cfg->intpin != 0) {
380 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
382 /* PCI specific entry found in MP table */
383 if (airq != cfg->intline) {
384 undirect_pci_irq(cfg->intline);
389 * PCI interrupts might be redirected to the
390 * ISA bus according to some MP tables. Use the
391 * same methods as used by the ISA devices
392 * devices to find the proper IOAPIC int pin.
394 airq = isa_apic_irq(cfg->intline);
395 if ((airq >= 0) && (airq != cfg->intline)) {
396 /* XXX: undirect_pci_irq() ? */
397 undirect_isa_irq(cfg->intline);
404 cfg->mingnt = REG(PCIR_MINGNT, 1);
405 cfg->maxlat = REG(PCIR_MAXLAT, 1);
407 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
408 cfg->hdrtype &= ~PCIM_MFDEV;
411 pci_hdrtypedata(pcib, b, s, f, cfg);
412 pci_read_capabilities(pcib, cfg);
414 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
416 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
417 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
418 devlist_entry->conf.pc_sel.pc_func = cfg->func;
419 devlist_entry->conf.pc_hdr = cfg->hdrtype;
421 devlist_entry->conf.pc_subvendor = cfg->subvendor;
422 devlist_entry->conf.pc_subdevice = cfg->subdevice;
423 devlist_entry->conf.pc_vendor = cfg->vendor;
424 devlist_entry->conf.pc_device = cfg->device;
426 devlist_entry->conf.pc_class = cfg->baseclass;
427 devlist_entry->conf.pc_subclass = cfg->subclass;
428 devlist_entry->conf.pc_progif = cfg->progif;
429 devlist_entry->conf.pc_revid = cfg->revid;
434 return (devlist_entry);
439 pci_fixup_nextptr(int *nextptr0)
441 int nextptr = *nextptr0;
443 /* "Next pointer" is only one byte */
444 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
448 * PCI local bus spec 3.0:
450 * "... The bottom two bits of all pointers are reserved
451 * and must be implemented as 00b although software must
452 * mask them to allow for future uses of these bits ..."
455 kprintf("Illegal PCI extended capability "
456 "offset, fixup 0x%02x -> 0x%02x\n",
457 nextptr, nextptr & ~0x3);
463 if (nextptr < 0x40) {
465 kprintf("Illegal PCI extended capability "
466 "offset 0x%02x", nextptr);
474 pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
477 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
479 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
484 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
485 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
486 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
489 * Following way may be used to to test whether
490 * 'data' register exists:
491 * if 'data_select' register of
492 * PCIR_POWER_STATUS(bits[12,9]) is read-only
493 * then 'data' register is _not_ implemented.
501 pcie_slotimpl(const pcicfgregs *cfg)
503 const struct pcicfg_expr *expr = &cfg->expr;
507 * Only version 1 can be parsed currently
509 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
513 * - Slot implemented bit is meaningful iff current port is
514 * root port or down stream port.
515 * - Testing for root port or down stream port is meanningful
516 * iff PCI configure has type 1 header.
519 if (cfg->hdrtype != 1)
522 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
523 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
526 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
533 pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
536 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
538 struct pcicfg_expr *expr = &cfg->expr;
540 expr->expr_ptr = ptr;
541 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
544 * Only version 1 can be parsed currently
546 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
550 * Read slot capabilities. Slot capabilities exists iff
551 * current port's slot is implemented
553 if (pcie_slotimpl(cfg))
554 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
560 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
563 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
567 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
568 /* No capabilities */
572 switch (cfg->hdrtype) {
575 ptrptr = PCIR_CAP_PTR;
578 ptrptr = PCIR_CAP_PTR_2;
581 return; /* No capabilities support */
583 nextptr = REG(ptrptr, 1);
586 * Read capability entries.
588 while (pci_fixup_nextptr(&nextptr)) {
591 /* Process this entry */
592 switch (REG(ptr, 1)) {
593 case PCIY_PMG: /* PCI power management */
594 pci_read_cap_pmgt(pcib, ptr, cfg);
596 case PCIY_PCIX: /* PCI-X */
597 cfg->pcixcap_ptr = ptr;
599 case PCIY_EXPRESS: /* PCI Express */
600 pci_read_cap_expr(pcib, ptr, cfg);
606 /* Find the next entry */
607 nextptr = REG(ptr + 1, 1);
613 /* free pcicfgregs structure and all depending data structures */
616 pci_freecfg(struct pci_devinfo *dinfo)
618 struct devlist *devlist_head;
620 devlist_head = &pci_devq;
622 if (dinfo->cfg.hdrspec != NULL)
623 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
624 /* XXX this hasn't been tested */
625 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
626 kfree(dinfo, M_DEVBUF);
628 /* increment the generation count */
631 /* we're losing one device */
638 * PCI power manangement
641 pci_set_powerstate_method(device_t dev, device_t child, int state)
643 struct pci_devinfo *dinfo = device_get_ivars(child);
644 pcicfgregs *cfg = &dinfo->cfg;
646 int result, oldstate, highest, delay;
648 if (cfg->pmgt.pp_cap == 0)
652 * Optimize a no state change request away. While it would be OK to
653 * write to the hardware in theory, some devices have shown odd
654 * behavior when going from D3 -> D3.
656 oldstate = pci_get_powerstate(child);
657 if (oldstate == state)
661 * The PCI power management specification states that after a state
662 * transition between PCI power states, system software must
663 * guarantee a minimal delay before the function accesses the device.
664 * Compute the worst case delay that we need to guarantee before we
665 * access the device. Many devices will be responsive much more
666 * quickly than this delay, but there are some that don't respond
667 * instantly to state changes. Transitions to/from D3 state require
668 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
669 * is done below with DELAY rather than a sleeper function because
670 * this function can be called from contexts where we cannot sleep.
672 highest = (oldstate > state) ? oldstate : state;
673 if (highest == PCI_POWERSTATE_D3)
675 else if (highest == PCI_POWERSTATE_D2)
679 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2)
683 case PCI_POWERSTATE_D0:
684 status |= PCIM_PSTAT_D0;
686 case PCI_POWERSTATE_D1:
687 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D1SUPP) == 0)
689 status |= PCIM_PSTAT_D1;
691 case PCI_POWERSTATE_D2:
692 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D2SUPP) == 0)
694 status |= PCIM_PSTAT_D2;
696 case PCI_POWERSTATE_D3:
697 status |= PCIM_PSTAT_D3;
705 "pci%d:%d:%d: Transition from D%d to D%d\n",
706 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
709 PCI_WRITE_CONFIG(dev, child, cfg->pmgt.pp_status, status, 2);
716 pci_get_powerstate_method(device_t dev, device_t child)
718 struct pci_devinfo *dinfo = device_get_ivars(child);
719 pcicfgregs *cfg = &dinfo->cfg;
723 if (cfg->pmgt.pp_cap != 0) {
724 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2);
725 switch (status & PCIM_PSTAT_DMASK) {
727 result = PCI_POWERSTATE_D0;
730 result = PCI_POWERSTATE_D1;
733 result = PCI_POWERSTATE_D2;
736 result = PCI_POWERSTATE_D3;
739 result = PCI_POWERSTATE_UNKNOWN;
743 /* No support, device is always at D0 */
744 result = PCI_POWERSTATE_D0;
750 * Some convenience functions for PCI device drivers.
754 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
758 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
760 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
764 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
768 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
770 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
774 pci_enable_busmaster_method(device_t dev, device_t child)
776 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
781 pci_disable_busmaster_method(device_t dev, device_t child)
783 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
788 pci_enable_io_method(device_t dev, device_t child, int space)
799 bit = PCIM_CMD_PORTEN;
803 bit = PCIM_CMD_MEMEN;
809 pci_set_command_bit(dev, child, bit);
810 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
813 device_printf(child, "failed to enable %s mapping!\n", error);
818 pci_disable_io_method(device_t dev, device_t child, int space)
829 bit = PCIM_CMD_PORTEN;
833 bit = PCIM_CMD_MEMEN;
839 pci_clear_command_bit(dev, child, bit);
840 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
842 device_printf(child, "failed to disable %s mapping!\n", error);
849 * This is the user interface to PCI configuration space.
853 pci_open(struct dev_open_args *ap)
855 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
862 pci_close(struct dev_close_args *ap)
868 * Match a single pci_conf structure against an array of pci_match_conf
869 * structures. The first argument, 'matches', is an array of num_matches
870 * pci_match_conf structures. match_buf is a pointer to the pci_conf
871 * structure that will be compared to every entry in the matches array.
872 * This function returns 1 on failure, 0 on success.
875 pci_conf_match(struct pci_match_conf *matches, int num_matches,
876 struct pci_conf *match_buf)
880 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
883 for (i = 0; i < num_matches; i++) {
885 * I'm not sure why someone would do this...but...
887 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
891 * Look at each of the match flags. If it's set, do the
892 * comparison. If the comparison fails, we don't have a
893 * match, go on to the next item if there is one.
895 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
896 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
899 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
900 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
903 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
904 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
907 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
908 && (match_buf->pc_vendor != matches[i].pc_vendor))
911 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
912 && (match_buf->pc_device != matches[i].pc_device))
915 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
916 && (match_buf->pc_class != matches[i].pc_class))
919 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
920 && (match_buf->pd_unit != matches[i].pd_unit))
923 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
924 && (strncmp(matches[i].pd_name, match_buf->pd_name,
925 sizeof(match_buf->pd_name)) != 0))
935 * Locate the parent of a PCI device by scanning the PCI devlist
936 * and return the entry for the parent.
937 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
938 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
942 pci_devlist_get_parent(pcicfgregs *cfg)
944 struct devlist *devlist_head;
945 struct pci_devinfo *dinfo;
946 pcicfgregs *bridge_cfg;
949 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
951 /* If the device is on PCI bus 0, look for the host */
953 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
954 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
955 bridge_cfg = &dinfo->cfg;
956 if (bridge_cfg->baseclass == PCIC_BRIDGE
957 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
958 && bridge_cfg->bus == cfg->bus) {
964 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
966 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
967 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
968 bridge_cfg = &dinfo->cfg;
969 if (bridge_cfg->baseclass == PCIC_BRIDGE
970 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
971 && bridge_cfg->secondarybus == cfg->bus) {
981 pci_ioctl(struct dev_ioctl_args *ap)
988 if (!(ap->a_fflag & FWRITE))
994 struct pci_devinfo *dinfo;
995 struct pci_conf_io *cio;
996 struct devlist *devlist_head;
997 struct pci_match_conf *pattern_buf;
1002 cio = (struct pci_conf_io *)ap->a_data;
1008 * Hopefully the user won't pass in a null pointer, but it
1009 * can't hurt to check.
1017 * If the user specified an offset into the device list,
1018 * but the list has changed since they last called this
1019 * ioctl, tell them that the list has changed. They will
1020 * have to get the list from the beginning.
1022 if ((cio->offset != 0)
1023 && (cio->generation != pci_generation)){
1024 cio->num_matches = 0;
1025 cio->status = PCI_GETCONF_LIST_CHANGED;
1031 * Check to see whether the user has asked for an offset
1032 * past the end of our list.
1034 if (cio->offset >= pci_numdevs) {
1035 cio->num_matches = 0;
1036 cio->status = PCI_GETCONF_LAST_DEVICE;
1041 /* get the head of the device queue */
1042 devlist_head = &pci_devq;
1045 * Determine how much room we have for pci_conf structures.
1046 * Round the user's buffer size down to the nearest
1047 * multiple of sizeof(struct pci_conf) in case the user
1048 * didn't specify a multiple of that size.
1050 iolen = min(cio->match_buf_len -
1051 (cio->match_buf_len % sizeof(struct pci_conf)),
1052 pci_numdevs * sizeof(struct pci_conf));
1055 * Since we know that iolen is a multiple of the size of
1056 * the pciconf union, it's okay to do this.
1058 ionum = iolen / sizeof(struct pci_conf);
1061 * If this test is true, the user wants the pci_conf
1062 * structures returned to match the supplied entries.
1064 if ((cio->num_patterns > 0)
1065 && (cio->pat_buf_len > 0)) {
1067 * pat_buf_len needs to be:
1068 * num_patterns * sizeof(struct pci_match_conf)
1069 * While it is certainly possible the user just
1070 * allocated a large buffer, but set the number of
1071 * matches correctly, it is far more likely that
1072 * their kernel doesn't match the userland utility
1073 * they're using. It's also possible that the user
1074 * forgot to initialize some variables. Yes, this
1075 * may be overly picky, but I hazard to guess that
1076 * it's far more likely to just catch folks that
1077 * updated their kernel but not their userland.
1079 if ((cio->num_patterns *
1080 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1081 /* The user made a mistake, return an error*/
1082 cio->status = PCI_GETCONF_ERROR;
1083 kprintf("pci_ioctl: pat_buf_len %d != "
1084 "num_patterns (%d) * sizeof(struct "
1085 "pci_match_conf) (%d)\npci_ioctl: "
1086 "pat_buf_len should be = %d\n",
1087 cio->pat_buf_len, cio->num_patterns,
1088 (int)sizeof(struct pci_match_conf),
1089 (int)sizeof(struct pci_match_conf) *
1091 kprintf("pci_ioctl: do your headers match your "
1093 cio->num_matches = 0;
1099 * Check the user's buffer to make sure it's readable.
1101 if (!useracc((caddr_t)cio->patterns,
1102 cio->pat_buf_len, VM_PROT_READ)) {
1103 kprintf("pci_ioctl: pattern buffer %p, "
1104 "length %u isn't user accessible for"
1105 " READ\n", cio->patterns,
1111 * Allocate a buffer to hold the patterns.
1113 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
1115 error = copyin(cio->patterns, pattern_buf,
1119 num_patterns = cio->num_patterns;
1121 } else if ((cio->num_patterns > 0)
1122 || (cio->pat_buf_len > 0)) {
1124 * The user made a mistake, spit out an error.
1126 cio->status = PCI_GETCONF_ERROR;
1127 cio->num_matches = 0;
1128 kprintf("pci_ioctl: invalid GETCONF arguments\n");
1135 * Make sure we can write to the match buffer.
1137 if (!useracc((caddr_t)cio->matches,
1138 cio->match_buf_len, VM_PROT_WRITE)) {
1139 kprintf("pci_ioctl: match buffer %p, length %u "
1140 "isn't user accessible for WRITE\n",
1141 cio->matches, cio->match_buf_len);
1147 * Go through the list of devices and copy out the devices
1148 * that match the user's criteria.
1150 for (cio->num_matches = 0, error = 0, i = 0,
1151 dinfo = STAILQ_FIRST(devlist_head);
1152 (dinfo != NULL) && (cio->num_matches < ionum)
1153 && (error == 0) && (i < pci_numdevs);
1154 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1156 if (i < cio->offset)
1159 /* Populate pd_name and pd_unit */
1161 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1162 name = device_get_name(dinfo->cfg.dev);
1164 strncpy(dinfo->conf.pd_name, name,
1165 sizeof(dinfo->conf.pd_name));
1166 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1167 dinfo->conf.pd_unit =
1168 device_get_unit(dinfo->cfg.dev);
1171 if ((pattern_buf == NULL) ||
1172 (pci_conf_match(pattern_buf, num_patterns,
1173 &dinfo->conf) == 0)) {
1176 * If we've filled up the user's buffer,
1177 * break out at this point. Since we've
1178 * got a match here, we'll pick right back
1179 * up at the matching entry. We can also
1180 * tell the user that there are more matches
1183 if (cio->num_matches >= ionum)
1186 error = copyout(&dinfo->conf,
1187 &cio->matches[cio->num_matches],
1188 sizeof(struct pci_conf));
1194 * Set the pointer into the list, so if the user is getting
1195 * n records at a time, where n < pci_numdevs,
1200 * Set the generation, the user will need this if they make
1201 * another ioctl call with offset != 0.
1203 cio->generation = pci_generation;
1206 * If this is the last device, inform the user so he won't
1207 * bother asking for more devices. If dinfo isn't NULL, we
1208 * know that there are more matches in the list because of
1209 * the way the traversal is done.
1212 cio->status = PCI_GETCONF_LAST_DEVICE;
1214 cio->status = PCI_GETCONF_MORE_DEVS;
1216 if (pattern_buf != NULL)
1217 kfree(pattern_buf, M_TEMP);
1222 io = (struct pci_io *)ap->a_data;
1223 switch(io->pi_width) {
1228 * Assume that the user-level bus number is
1229 * actually the pciN instance number. We map
1230 * from that to the real pcib+bus combination.
1232 pci = devclass_get_device(pci_devclass,
1236 * pci is the pci device and may contain
1237 * several children (for each function code).
1238 * The governing pci bus is the parent to
1243 pcib = device_get_parent(pci);
1244 b = pcib_get_bus(pcib);
1246 PCIB_READ_CONFIG(pcib,
1264 io = (struct pci_io *)ap->a_data;
1265 switch(io->pi_width) {
1270 * Assume that the user-level bus number is
1271 * actually the pciN instance number. We map
1272 * from that to the real pcib+bus combination.
1274 pci = devclass_get_device(pci_devclass,
1278 * pci is the pci device and may contain
1279 * several children (for each function code).
1280 * The governing pci bus is the parent to
1285 pcib = device_get_parent(pci);
1286 b = pcib_get_bus(pcib);
1287 PCIB_WRITE_CONFIG(pcib,
1315 static struct dev_ops pcic_ops = {
1316 { "pci", PCI_CDEV, 0 },
1318 .d_close = pci_close,
1319 .d_ioctl = pci_ioctl,
1325 * New style pci driver. Parent device is either a pci-host-bridge or a
1326 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1329 pci_class_to_string(int baseclass)
1346 case PCIC_MULTIMEDIA:
1347 name = "MULTIMEDIA";
1355 case PCIC_SIMPLECOMM:
1356 name = "SIMPLECOMM";
1358 case PCIC_BASEPERIPH:
1359 name = "BASEPERIPH";
1367 case PCIC_PROCESSOR:
1370 case PCIC_SERIALBUS:
1379 case PCIC_SATELLITE:
1399 pci_print_verbose_expr(const pcicfgregs *cfg)
1401 const struct pcicfg_expr *expr = &cfg->expr;
1402 const char *port_name;
1408 if (expr->expr_ptr == 0) /* No PCI Express capability */
1411 kprintf("\tPCI Express ver.%d cap=0x%04x",
1412 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1413 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1416 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1418 switch (port_type) {
1419 case PCIE_END_POINT:
1420 port_name = "DEVICE";
1422 case PCIE_LEG_END_POINT:
1423 port_name = "LEGDEV";
1425 case PCIE_ROOT_PORT:
1428 case PCIE_UP_STREAM_PORT:
1429 port_name = "UPSTREAM";
1431 case PCIE_DOWN_STREAM_PORT:
1432 port_name = "DOWNSTRM";
1434 case PCIE_PCIE2PCI_BRIDGE:
1435 port_name = "PCIE2PCI";
1437 case PCIE_PCI2PCIE_BRIDGE:
1438 port_name = "PCI2PCIE";
1444 if ((port_type == PCIE_ROOT_PORT ||
1445 port_type == PCIE_DOWN_STREAM_PORT) &&
1446 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1448 if (port_name != NULL)
1449 kprintf("[%s]", port_name);
1451 if (pcie_slotimpl(cfg)) {
1452 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1453 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1454 kprintf("[HOTPLUG]");
1461 pci_print_verbose(struct pci_devinfo *dinfo)
1464 pcicfgregs *cfg = &dinfo->cfg;
1466 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1467 cfg->vendor, cfg->device, cfg->revid);
1468 kprintf("\tbus=%d, slot=%d, func=%d\n",
1469 cfg->bus, cfg->slot, cfg->func);
1470 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1471 pci_class_to_string(cfg->baseclass),
1472 cfg->baseclass, cfg->subclass, cfg->progif,
1473 cfg->hdrtype, cfg->mfdev);
1474 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1475 cfg->subordinatebus, cfg->secondarybus);
1477 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1478 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1479 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1480 cfg->lattimer, cfg->lattimer * 30,
1481 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1482 #endif /* PCI_DEBUG */
1483 if (cfg->intpin > 0)
1484 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1486 pci_print_verbose_expr(cfg);
1491 pci_porten(device_t pcib, int b, int s, int f)
1493 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1494 & PCIM_CMD_PORTEN) != 0;
1498 pci_memen(device_t pcib, int b, int s, int f)
1500 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1501 & PCIM_CMD_MEMEN) != 0;
1505 * Add a resource based on a pci map register. Return 1 if the map
1506 * register is a 32bit map register or 2 if it is a 64bit register.
1509 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1510 struct resource_list *rl)
1519 #ifdef PCI_ENABLE_IO_MODES
1524 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1526 if (map == 0 || map == 0xffffffff)
1527 return 1; /* skip invalid entry */
1529 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1530 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1531 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1533 base = pci_mapbase(map);
1534 if (pci_maptype(map) & PCI_MAPMEM)
1535 type = SYS_RES_MEMORY;
1537 type = SYS_RES_IOPORT;
1538 ln2size = pci_mapsize(testval);
1539 ln2range = pci_maprange(testval);
1540 if (ln2range == 64) {
1541 /* Read the other half of a 64bit map register */
1542 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1546 * This code theoretically does the right thing, but has
1547 * undesirable side effects in some cases where
1548 * peripherals respond oddly to having these bits
1549 * enabled. Leave them alone by default.
1551 #ifdef PCI_ENABLE_IO_MODES
1552 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1553 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1554 cmd |= PCIM_CMD_PORTEN;
1555 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1557 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1558 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1559 cmd |= PCIM_CMD_MEMEN;
1560 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1563 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1565 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1569 resource_list_add(rl, type, reg,
1570 base, base + (1 << ln2size) - 1,
1574 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1575 reg, pci_maptype(base), ln2range,
1576 (unsigned int) base, ln2size);
1579 return (ln2range == 64) ? 2 : 1;
1582 #ifdef PCI_MAP_FIXUP
1584 * For ATA devices we need to decide early on what addressing mode to use.
1585 * Legacy demands that the primary and secondary ATA ports sits on the
1586 * same addresses that old ISA hardware did. This dictates that we use
1587 * those addresses and ignore the BARs if we cannot set PCI native
1591 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1592 struct resource_list *rl)
1594 int rid, type, progif;
1596 /* if this device supports PCI native addressing use it */
1597 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1598 if ((progif &0x8a) == 0x8a) {
1599 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1600 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
1601 kprintf("Trying ATA native PCI addressing mode\n");
1602 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1607 * Because we return any preallocated resources for lazy
1608 * allocation for PCI devices in pci_alloc_resource(), we can
1609 * allocate our legacy resources here.
1611 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1612 type = SYS_RES_IOPORT;
1613 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1614 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1615 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1618 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1619 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1622 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1623 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1626 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1627 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1628 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1631 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1632 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1635 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1636 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1639 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1640 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1642 #endif /* PCI_MAP_FIXUP */
1645 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1647 struct pci_devinfo *dinfo = device_get_ivars(dev);
1648 pcicfgregs *cfg = &dinfo->cfg;
1649 struct resource_list *rl = &dinfo->resources;
1650 struct pci_quirk *q;
1652 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1659 #ifdef PCI_MAP_FIXUP
1660 /* atapci devices in legacy mode need special map treatment */
1661 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1662 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1663 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1664 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1665 !pci_read_config(dev, PCIR_BAR(2), 4))) )
1666 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1668 #endif /* PCI_MAP_FIXUP */
1669 for (i = 0; i < cfg->nummaps;) {
1670 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1673 for (q = &pci_quirks[0]; q->devid; q++) {
1674 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1675 && q->type == PCI_QUIRK_MAP_REG)
1676 pci_add_map(pcib, b, s, f, q->arg1, rl);
1679 if (cfg->intpin > 0 && cfg->intline != 255)
1680 resource_list_add(rl, SYS_RES_IRQ, 0,
1681 cfg->intline, cfg->intline, 1);
1685 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1687 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1688 device_t pcib = device_get_parent(dev);
1689 struct pci_devinfo *dinfo;
1691 int s, f, pcifunchigh;
1694 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1696 maxslots = PCIB_MAXSLOTS(pcib);
1698 for (s = 0; s <= maxslots; s++) {
1701 hdrtype = REG(PCIR_HDRTYPE, 1);
1702 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1704 if (hdrtype & PCIM_MFDEV)
1705 pcifunchigh = PCI_FUNCMAX;
1706 for (f = 0; f <= pcifunchigh; f++) {
1707 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1708 if (dinfo != NULL) {
1709 pci_add_child(dev, dinfo);
1717 * The actual PCI child that we add has a NULL driver whos parent
1718 * device will be "pci". The child contains the ivars, not the parent.
1721 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1725 pcib = device_get_parent(bus);
1726 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1727 device_set_ivars(dinfo->cfg.dev, dinfo);
1728 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1729 pci_cfg_restore(dinfo->cfg.dev, dinfo);
1730 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1731 pci_print_verbose(dinfo);
1735 * Probe the PCI bus. Note: probe code is not supposed to add children
1739 pci_probe(device_t dev)
1741 device_set_desc(dev, "PCI bus");
1743 /* Allow other subclasses to override this driver */
1748 pci_attach(device_t dev)
1751 int lunit = device_get_unit(dev);
1753 dev_ops_add(&pcic_ops, -1, lunit);
1754 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1757 * Since there can be multiple independantly numbered PCI
1758 * busses on some large alpha systems, we can't use the unit
1759 * number to decide what bus we are probing. We ask the parent
1760 * pcib what our bus number is.
1762 * pcib_get_bus() must act on the pci bus device, not on the pci
1763 * device, because it uses badly hacked nexus-based ivars to
1764 * store and retrieve the physical bus number. XXX
1766 busno = pcib_get_bus(device_get_parent(dev));
1768 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1770 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1772 return (bus_generic_attach(dev));
1776 pci_print_resources(struct resource_list *rl, const char *name, int type,
1779 struct resource_list_entry *rle;
1780 int printed, retval;
1784 /* Yes, this is kinda cheating */
1785 SLIST_FOREACH(rle, rl, link) {
1786 if (rle->type == type) {
1788 retval += kprintf(" %s ", name);
1789 else if (printed > 0)
1790 retval += kprintf(",");
1792 retval += kprintf(format, rle->start);
1793 if (rle->count > 1) {
1794 retval += kprintf("-");
1795 retval += kprintf(format, rle->start +
1804 pci_print_child(device_t dev, device_t child)
1806 struct pci_devinfo *dinfo;
1807 struct resource_list *rl;
1811 dinfo = device_get_ivars(child);
1813 rl = &dinfo->resources;
1815 retval += bus_print_child_header(dev, child);
1817 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1818 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1819 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1820 if (device_get_flags(dev))
1821 retval += kprintf(" flags %#x", device_get_flags(dev));
1823 retval += kprintf(" at device %d.%d", pci_get_slot(child),
1824 pci_get_function(child));
1826 retval += bus_print_child_footer(dev, child);
1832 pci_probe_nomatch(device_t dev, device_t child)
1834 struct pci_devinfo *dinfo;
1840 dinfo = device_get_ivars(child);
1842 desc = pci_ata_match(child);
1843 if (!desc) desc = pci_usb_match(child);
1844 if (!desc) desc = pci_vga_match(child);
1845 if (!desc) desc = pci_chip_match(child);
1847 desc = "unknown card";
1850 device_printf(dev, "<%s>", desc);
1851 if (bootverbose || unknown) {
1852 kprintf(" (vendor=0x%04x, dev=0x%04x)",
1856 kprintf(" at %d.%d",
1857 pci_get_slot(child),
1858 pci_get_function(child));
1859 if (cfg->intpin > 0 && cfg->intline != 255) {
1860 kprintf(" irq %d", cfg->intline);
1863 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
1869 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1871 struct pci_devinfo *dinfo;
1874 dinfo = device_get_ivars(child);
1878 case PCI_IVAR_SUBVENDOR:
1879 *result = cfg->subvendor;
1881 case PCI_IVAR_SUBDEVICE:
1882 *result = cfg->subdevice;
1884 case PCI_IVAR_VENDOR:
1885 *result = cfg->vendor;
1887 case PCI_IVAR_DEVICE:
1888 *result = cfg->device;
1890 case PCI_IVAR_DEVID:
1891 *result = (cfg->device << 16) | cfg->vendor;
1893 case PCI_IVAR_CLASS:
1894 *result = cfg->baseclass;
1896 case PCI_IVAR_SUBCLASS:
1897 *result = cfg->subclass;
1899 case PCI_IVAR_PROGIF:
1900 *result = cfg->progif;
1902 case PCI_IVAR_REVID:
1903 *result = cfg->revid;
1905 case PCI_IVAR_INTPIN:
1906 *result = cfg->intpin;
1909 *result = cfg->intline;
1915 *result = cfg->slot;
1917 case PCI_IVAR_FUNCTION:
1918 *result = cfg->func;
1920 case PCI_IVAR_SECONDARYBUS:
1921 *result = cfg->secondarybus;
1923 case PCI_IVAR_SUBORDINATEBUS:
1924 *result = cfg->subordinatebus;
1926 case PCI_IVAR_ETHADDR:
1928 * The generic accessor doesn't deal with failure, so
1929 * we set the return value, then return an error.
1933 case PCI_IVAR_PCIXCAP_PTR:
1934 *result = cfg->pcixcap_ptr;
1936 case PCI_IVAR_PCIECAP_PTR:
1937 *result = cfg->expr.expr_ptr;
1946 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1948 struct pci_devinfo *dinfo;
1951 dinfo = device_get_ivars(child);
1955 case PCI_IVAR_SUBVENDOR:
1956 case PCI_IVAR_SUBDEVICE:
1957 case PCI_IVAR_VENDOR:
1958 case PCI_IVAR_DEVICE:
1959 case PCI_IVAR_DEVID:
1960 case PCI_IVAR_CLASS:
1961 case PCI_IVAR_SUBCLASS:
1962 case PCI_IVAR_PROGIF:
1963 case PCI_IVAR_REVID:
1964 case PCI_IVAR_INTPIN:
1968 case PCI_IVAR_FUNCTION:
1969 case PCI_IVAR_ETHADDR:
1970 case PCI_IVAR_PCIXCAP_PTR:
1971 case PCI_IVAR_PCIECAP_PTR:
1972 return EINVAL; /* disallow for now */
1974 case PCI_IVAR_SECONDARYBUS:
1975 cfg->secondarybus = value;
1977 case PCI_IVAR_SUBORDINATEBUS:
1978 cfg->subordinatebus = value;
1986 #ifdef PCI_MAP_FIXUP
1987 static struct resource *
1988 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1989 u_long end, u_long count, u_int flags)
1991 struct pci_devinfo *dinfo = device_get_ivars(child);
1992 struct resource_list *rl = &dinfo->resources;
1993 struct resource_list_entry *rle;
1994 struct resource *res;
1995 uint32_t map, testval;
1999 * Weed out the bogons, and figure out how large the BAR/map
2000 * is. BARs that read back 0 here are bogus and unimplemented.
2002 * Note: atapci in legacy mode are special and handled elsewhere
2003 * in the code. If you have an atapci device in legacy mode and
2004 * it fails here, that other code is broken.
2007 map = pci_read_config(child, *rid, 4);
2008 pci_write_config(child, *rid, 0xffffffff, 4);
2009 testval = pci_read_config(child, *rid, 4);
2010 if (pci_mapbase(testval) == 0)
2012 if (pci_maptype(testval) & PCI_MAPMEM) {
2013 if (type != SYS_RES_MEMORY) {
2015 device_printf(dev, "child %s requested type %d"
2016 " for rid %#x, but the BAR says "
2018 device_get_nameunit(child), type,
2023 if (type != SYS_RES_IOPORT) {
2025 device_printf(dev, "child %s requested type %d"
2026 " for rid %#x, but the BAR says "
2027 "it is an ioport\n",
2028 device_get_nameunit(child), type,
2034 * For real BARs, we need to override the size that
2035 * the driver requests, because that's what the BAR
2036 * actually uses and we would otherwise have a
2037 * situation where we might allocate the excess to
2038 * another driver, which won't work.
2040 mapsize = pci_mapsize(testval);
2041 count = 1 << mapsize;
2042 if (RF_ALIGNMENT(flags) < mapsize)
2043 flags = (flags & ~RF_ALIGNMENT_MASK) |
2044 RF_ALIGNMENT_LOG2(mapsize);
2046 * Allocate enough resource, and then write back the
2047 * appropriate BAR for that resource.
2049 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2050 start, end, count, flags);
2052 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2053 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2056 resource_list_add(rl, type, *rid, start, end, count);
2057 rle = resource_list_find(rl, type, *rid);
2059 panic("pci_alloc_map: unexpectedly can't find resource.");
2061 rle->start = rman_get_start(res);
2062 rle->end = rman_get_end(res);
2065 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2066 "type %d at %#lx\n", count, *rid, type,
2067 rman_get_start(res));
2068 map = rman_get_start(res);
2070 pci_write_config(child, *rid, map, 4);
2073 #endif /* PCI_MAP_FIXUP */
2076 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2077 u_long start, u_long end, u_long count, u_int flags)
2079 struct pci_devinfo *dinfo = device_get_ivars(child);
2080 struct resource_list *rl = &dinfo->resources;
2081 #ifdef PCI_MAP_FIXUP
2082 struct resource_list_entry *rle;
2083 #endif /* PCI_MAP_FIXUP */
2084 pcicfgregs *cfg = &dinfo->cfg;
2087 * Perform lazy resource allocation
2089 if (device_get_parent(child) == dev) {
2094 * If device doesn't have an interrupt routed, and is
2095 * deserving of an interrupt, try to assign it one.
2097 if ((cfg->intline == 255 || cfg->intline == 0) &&
2098 (cfg->intpin != 0) &&
2099 (start == 0) && (end == ~0UL)) {
2100 cfg->intline = PCIB_ROUTE_INTERRUPT(
2101 device_get_parent(dev), child,
2103 if (cfg->intline != 255) {
2104 pci_write_config(child, PCIR_INTLINE,
2106 resource_list_add(rl, SYS_RES_IRQ, 0,
2107 cfg->intline, cfg->intline, 1);
2112 case SYS_RES_IOPORT:
2114 case SYS_RES_MEMORY:
2115 if (*rid < PCIR_BAR(cfg->nummaps)) {
2117 * Enable the I/O mode. We should
2118 * also be assigning resources too
2119 * when none are present. The
2120 * resource_list_alloc kind of sorta does
2123 if (PCI_ENABLE_IO(dev, child, type))
2126 #ifdef PCI_MAP_FIXUP
2127 rle = resource_list_find(rl, type, *rid);
2129 return pci_alloc_map(dev, child, type, rid,
2130 start, end, count, flags);
2131 #endif /* PCI_MAP_FIXUP */
2134 #ifdef PCI_MAP_FIXUP
2136 * If we've already allocated the resource, then
2137 * return it now. But first we may need to activate
2138 * it, since we don't allocate the resource as active
2139 * above. Normally this would be done down in the
2140 * nexus, but since we short-circuit that path we have
2141 * to do its job here. Not sure if we should free the
2142 * resource if it fails to activate.
2144 * Note: this also finds and returns resources for
2145 * atapci devices in legacy mode as allocated in
2148 rle = resource_list_find(rl, type, *rid);
2149 if (rle != NULL && rle->res != NULL) {
2151 device_printf(child, "reserved %#lx bytes for "
2152 "rid %#x type %d at %#lx\n",
2153 rman_get_size(rle->res), *rid,
2154 type, rman_get_start(rle->res));
2155 if ((flags & RF_ACTIVE) &&
2156 bus_generic_activate_resource(dev, child, type,
2157 *rid, rle->res) != 0)
2161 #endif /* PCI_MAP_FIXUP */
2163 return resource_list_alloc(rl, dev, child, type, rid,
2164 start, end, count, flags);
2168 pci_release_resource(device_t dev, device_t child, int type, int rid,
2171 struct pci_devinfo *dinfo = device_get_ivars(child);
2172 struct resource_list *rl = &dinfo->resources;
2174 return resource_list_release(rl, dev, child, type, rid, r);
2178 pci_set_resource(device_t dev, device_t child, int type, int rid,
2179 u_long start, u_long count)
2181 struct pci_devinfo *dinfo = device_get_ivars(child);
2182 struct resource_list *rl = &dinfo->resources;
2184 resource_list_add(rl, type, rid, start, start + count - 1, count);
2189 pci_get_resource(device_t dev, device_t child, int type, int rid,
2190 u_long *startp, u_long *countp)
2192 struct pci_devinfo *dinfo = device_get_ivars(child);
2193 struct resource_list *rl = &dinfo->resources;
2194 struct resource_list_entry *rle;
2196 rle = resource_list_find(rl, type, rid);
2201 *startp = rle->start;
2203 *countp = rle->count;
2209 pci_delete_resource(device_t dev, device_t child, int type, int rid)
2211 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
2214 struct resource_list *
2215 pci_get_resource_list (device_t dev, device_t child)
2217 struct pci_devinfo *dinfo = device_get_ivars(child);
2221 return (&dinfo->resources);
2225 pci_read_config_method(device_t dev, device_t child, int reg, int width)
2227 struct pci_devinfo *dinfo = device_get_ivars(child);
2228 pcicfgregs *cfg = &dinfo->cfg;
2230 return PCIB_READ_CONFIG(device_get_parent(dev),
2231 cfg->bus, cfg->slot, cfg->func,
2236 pci_write_config_method(device_t dev, device_t child, int reg,
2237 u_int32_t val, int width)
2239 struct pci_devinfo *dinfo = device_get_ivars(child);
2240 pcicfgregs *cfg = &dinfo->cfg;
2242 PCIB_WRITE_CONFIG(device_get_parent(dev),
2243 cfg->bus, cfg->slot, cfg->func,
2248 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2251 struct pci_devinfo *dinfo;
2253 dinfo = device_get_ivars(child);
2254 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
2255 pci_get_function(child));
2260 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2263 struct pci_devinfo *dinfo;
2266 dinfo = device_get_ivars(child);
2268 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
2269 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2270 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2276 pci_assign_interrupt_method(device_t dev, device_t child)
2278 struct pci_devinfo *dinfo = device_get_ivars(child);
2279 pcicfgregs *cfg = &dinfo->cfg;
2281 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2286 pci_modevent(module_t mod, int what, void *arg)
2290 STAILQ_INIT(&pci_devq);
2300 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2305 * Only do header type 0 devices. Type 1 devices are bridges,
2306 * which we know need special treatment. Type 2 devices are
2307 * cardbus bridges which also require special treatment.
2308 * Other types are unknown, and we err on the side of safety
2311 if (dinfo->cfg.hdrtype != 0)
2315 * Restore the device to full power mode. We must do this
2316 * before we restore the registers because moving from D3 to
2317 * D0 will cause the chip's BARs and some other registers to
2318 * be reset to some unknown power on reset values. Cut down
2319 * the noise on boot by doing nothing if we are already in
2322 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2323 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2325 for (i = 0; i < dinfo->cfg.nummaps; i++)
2326 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2327 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2328 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2329 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2330 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2331 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2332 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2333 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2334 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2335 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2336 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2338 /* Restore MSI and MSI-X configurations if they are present. */
2339 if (dinfo->cfg.msi.msi_location != 0)
2340 pci_resume_msi(dev);
2341 if (dinfo->cfg.msix.msix_location != 0)
2342 pci_resume_msix(dev);
2347 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2354 * Only do header type 0 devices. Type 1 devices are bridges, which
2355 * we know need special treatment. Type 2 devices are cardbus bridges
2356 * which also require special treatment. Other types are unknown, and
2357 * we err on the side of safety by ignoring them. Powering down
2358 * bridges should not be undertaken lightly.
2360 if (dinfo->cfg.hdrtype != 0)
2362 for (i = 0; i < dinfo->cfg.nummaps; i++)
2363 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2364 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2367 * Some drivers apparently write to these registers w/o updating our
2368 * cached copy. No harm happens if we update the copy, so do so here
2369 * so we can restore them. The COMMAND register is modified by the
2370 * bus w/o updating the cache. This should represent the normally
2371 * writable portion of the 'defined' part of type 0 headers. In
2372 * theory we also need to save/restore the PCI capability structures
2373 * we know about, but apart from power we don't know any that are
2376 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2377 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2378 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2379 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2380 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2381 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2382 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2383 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2384 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2385 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2386 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2387 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2388 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2389 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2390 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2393 * don't set the state for display devices, base peripherals and
2394 * memory devices since bad things happen when they are powered down.
2395 * We should (a) have drivers that can easily detach and (b) use
2396 * generic drivers for these devices so that some device actually
2397 * attaches. We need to make sure that when we implement (a) we don't
2398 * power the device down on a reattach.
2400 cls = pci_get_class(dev);
2404 switch (pci_do_power_nodriver)
2406 case 0: /* NO powerdown at all */
2408 case 1: /* Conservative about what to power down */
2409 if (cls == PCIC_STORAGE)
2412 case 2: /* Agressive about what to power down */
2413 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2414 cls == PCIC_BASEPERIPH)
2417 case 3: /* Power down everything */
2421 if (cls == PCIC_STORAGE)
2425 * PCI spec says we can only go into D3 state from D0 state.
2426 * Transition from D[12] into D0 before going to D3 state.
2428 ps = pci_get_powerstate(dev);
2429 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2430 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2431 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2432 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
2436 pci_resume(device_t dev)
2442 struct pci_devinfo *dinfo;
2445 device_get_children(dev, &children, &numdevs);
2447 for (i = 0; i < numdevs; i++) {
2448 child = children[i];
2450 dinfo = device_get_ivars(child);
2452 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2453 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2454 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2455 pci_write_config(child, PCIR_INTLINE,
2461 kfree(children, M_TEMP);
2463 return (bus_generic_resume(dev));
2467 pci_driver_added(device_t dev, driver_t *driver)
2472 struct pci_devinfo *dinfo;
2476 device_printf(dev, "driver added\n");
2477 DEVICE_IDENTIFY(driver, dev);
2478 device_get_children(dev, &devlist, &numdevs);
2479 for (i = 0; i < numdevs; i++) {
2481 if (device_get_state(child) != DS_NOTPRESENT)
2483 dinfo = device_get_ivars(child);
2484 pci_print_verbose(dinfo);
2486 kprintf("pci%d:%d:%d: reprobing on driver added\n",
2487 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
2488 pci_cfg_restore(child, dinfo);
2489 if (device_probe_and_attach(child) != 0)
2490 pci_cfg_save(child, dinfo, 1);
2492 kfree(devlist, M_TEMP);
2495 static device_method_t pci_methods[] = {
2496 /* Device interface */
2497 DEVMETHOD(device_probe, pci_probe),
2498 DEVMETHOD(device_attach, pci_attach),
2499 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2500 DEVMETHOD(device_suspend, bus_generic_suspend),
2501 DEVMETHOD(device_resume, pci_resume),
2504 DEVMETHOD(bus_print_child, pci_print_child),
2505 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2506 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2507 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2508 DEVMETHOD(bus_driver_added, pci_driver_added),
2509 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2510 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
2512 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
2513 DEVMETHOD(bus_set_resource, pci_set_resource),
2514 DEVMETHOD(bus_get_resource, pci_get_resource),
2515 DEVMETHOD(bus_delete_resource, pci_delete_resource),
2516 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2517 DEVMETHOD(bus_release_resource, pci_release_resource),
2518 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2519 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2520 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2521 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
2524 DEVMETHOD(pci_read_config, pci_read_config_method),
2525 DEVMETHOD(pci_write_config, pci_write_config_method),
2526 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2527 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2528 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2529 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2530 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2531 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
2532 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
2537 driver_t pci_driver = {
2543 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
2544 MODULE_VERSION(pci, 1);