1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
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32 ******************************************************************************/
34 #ifndef _DRAGONFLY_OS_H_
35 #define _DRAGONFLY_OS_H_
37 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
45 #define usec_delay(x) DELAY(x)
46 #define usec_delay_irq usec_delay
47 #define msec_delay(x) DELAY(1000*(x))
48 /* TODO: Should we be paranoid about delaying in interrupt context? */
49 #define msec_delay_irq(x) DELAY(1000*(x))
51 extern int e1000_debug;
53 #define DEBUGPRINT(S, args...) \
58 #define DEBUGFUNC(F) DEBUGOUT(F)
59 #define DEBUGOUT(S) DEBUGPRINT(S)
60 #define DEBUGOUT1(S,A) DEBUGPRINT(S, A)
61 #define DEBUGOUT2(S,A,B) DEBUGPRINT(S, A, B)
62 #define DEBUGOUT3(S,A,B,C) DEBUGPRINT(S, A, B, C)
63 #define DEBUGOUT7(S,A,B,C,D,E,F,G) DEBUGPRINT(S, A, B, C, D, E, F, G)
65 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
66 #define PCI_COMMAND_REGISTER PCIR_COMMAND
69 * These typedefs are necessary due to the new
70 * shared code, they are native to Linux.
86 bus_space_tag_t mem_bus_space_tag;
87 bus_space_handle_t mem_bus_space_handle;
88 bus_space_tag_t io_bus_space_tag;
89 bus_space_handle_t io_bus_space_handle;
90 bus_space_tag_t flash_bus_space_tag;
91 bus_space_handle_t flash_bus_space_handle;
95 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \
96 ? reg : e1000_translate_register_82542(reg))
98 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
100 /* Read from an absolute offset in the adapter's memory space */
101 #define E1000_READ_OFFSET(hw, offset) \
102 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
103 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset)
105 /* Write to an absolute offset in the adapter's memory space */
106 #define E1000_WRITE_OFFSET(hw, offset, value) \
107 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
108 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value)
110 /* Register READ/WRITE macros */
112 #define E1000_READ_REG(hw, reg) \
113 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
114 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
115 E1000_REGISTER(hw, reg))
117 #define E1000_READ_REG16(hw, reg) \
118 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
119 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
120 E1000_REGISTER(hw, reg))
122 #define E1000_WRITE_REG(hw, reg, value) \
123 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
124 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
125 E1000_REGISTER(hw, reg), value)
127 #define E1000_WRITE_REG16(hw, reg, value) \
128 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
129 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
130 E1000_REGISTER(hw, reg), value)
132 #define E1000_READ_REG_ARRAY(hw, reg, index) \
133 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
134 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
135 E1000_REGISTER(hw, reg) + ((index)<< 2))
137 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
138 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
139 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
140 E1000_REGISTER(hw, reg) + ((index)<< 2), value)
142 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
143 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
145 #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \
146 bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
147 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
148 E1000_REGISTER(hw, reg) + index)
150 #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
151 bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
152 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
153 E1000_REGISTER(hw, reg) + index, value)
155 #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
156 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
157 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
158 E1000_REGISTER(hw, reg) + (index << 1), value)
160 #define E1000_WRITE_REG_IO(hw, reg, value) do {\
161 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
162 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
163 (hw)->io_base, reg); \
164 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
165 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
166 (hw)->io_base + 4, value); } while (0)
168 #define E1000_READ_FLASH_REG(hw, reg) \
169 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG(hw, (reg) + 0xE000): \
170 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
171 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg))
173 #define E1000_READ_FLASH_REG16(hw, reg) \
174 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG16(hw, (reg) + 0xE000): \
175 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
176 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg))
178 #define E1000_WRITE_FLASH_REG(hw, reg, value) \
179 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG(hw, (reg) + 0xE000, value): \
180 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
181 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value))
183 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
184 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG16(hw, (reg) + 0xE000, value): \
185 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
186 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value))
188 #endif /* _DRAGONFLY_OS_H_ */