sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.34 2005/05/23 07:00:36 joerg Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83
  84 #include <net/if.h>
  85 #include <net/ifq_var.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/vlan/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99
 100 #include <vm/vm.h>              /* for vtophys */
 101 #include <vm/pmap.h>            /* for vtophys */
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/netif/mii_layer/mii.h>
 107 #include <dev/netif/mii_layer/miivar.h>
 108 #include <dev/netif/mii_layer/miidevs.h>
 109 #include <dev/netif/mii_layer/brgphyreg.h>
 110
 111 #include <bus/pci/pcidevs.h>
 112 #include <bus/pci/pcireg.h>
 113 #include <bus/pci/pcivar.h>
 114
 115 #include "if_bgereg.h"
 116
 117 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 118
 119 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 120 #include "miibus_if.h"
 121
 122 /*
 123  * Various supported device vendors/types and their names. Note: the
 124  * spec seems to indicate that the hardware still has Alteon's vendor
 125  * ID burned into it, though it will always be overriden by the vendor
 126  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 127  */
 128 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 129
 130 static struct bge_type bge_devs[] = {
 131         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 132                 "Broadcom BCM5700 Gigabit Ethernet" },
 133         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 134                 "Broadcom BCM5701 Gigabit Ethernet" },
 135         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 136                 "Broadcom BCM5700 Gigabit Ethernet" },
 137         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 138                 "Broadcom BCM5701 Gigabit Ethernet" },
 139         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 140                 "Broadcom BCM5702X Gigabit Ethernet" },
 141         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X,
 142                 "Broadcom BCM5702X Gigabit Ethernet" },
 143         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 144                 "Broadcom BCM5703X Gigabit Ethernet" },
 145         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X,
 146                 "Broadcom BCM5703X Gigabit Ethernet" },
 147         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 148                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 149         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 150                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 151         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 152                 "Broadcom BCM5705 Gigabit Ethernet" },
 153         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 154                 "Broadcom BCM5705M Gigabit Ethernet" },
 155         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT,
 156                 "Broadcom BCM5705M Gigabit Ethernet" },
 157         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 158                 "Broadcom BCM5782 Gigabit Ethernet" },
 159         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788,
 160                 "Broadcom BCM5788 Gigabit Ethernet" },
 161         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 162                 "Broadcom BCM5901 Fast Ethernet" },
 163         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 164                 "Broadcom BCM5901A2 Fast Ethernet" },
 165         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 166                 "SysKonnect Gigabit Ethernet" },
 167         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 168                 "Altima AC1000 Gigabit Ethernet" },
 169         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 170                 "Altima AC1002 Gigabit Ethernet" },
 171         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 172                 "Altima AC9100 Gigabit Ethernet" },
 173         { 0, 0, NULL }
 174 };
 175
 176 static int      bge_probe(device_t);
 177 static int      bge_attach(device_t);
 178 static int      bge_detach(device_t);
 179 static void     bge_release_resources(struct bge_softc *);
 180 static void     bge_txeof(struct bge_softc *);
 181 static void     bge_rxeof(struct bge_softc *);
 182
 183 static void     bge_tick(void *);
 184 static void     bge_stats_update(struct bge_softc *);
 185 static void     bge_stats_update_regs(struct bge_softc *);
 186 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 187
 188 static void     bge_intr(void *);
 189 static void     bge_start(struct ifnet *);
 190 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 191 static void     bge_init(void *);
 192 static void     bge_stop(struct bge_softc *);
 193 static void     bge_watchdog(struct ifnet *);
 194 static void     bge_shutdown(device_t);
 195 static int      bge_ifmedia_upd(struct ifnet *);
 196 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 197
 198 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 199 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 200
 201 static void     bge_setmulti(struct bge_softc *);
 202
 203 static void     bge_handle_events(struct bge_softc *);
 204 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 205 static void     bge_free_jumbo_mem(struct bge_softc *);
 206 static struct bge_jslot
 207                 *bge_jalloc(struct bge_softc *);
 208 static void     bge_jfree(void *);
 209 static void     bge_jref(void *);
 210 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 211 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 212 static int      bge_init_rx_ring_std(struct bge_softc *);
 213 static void     bge_free_rx_ring_std(struct bge_softc *);
 214 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 215 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 216 static void     bge_free_tx_ring(struct bge_softc *);
 217 static int      bge_init_tx_ring(struct bge_softc *);
 218
 219 static int      bge_chipinit(struct bge_softc *);
 220 static int      bge_blockinit(struct bge_softc *);
 221
 222 #ifdef notdef
 223 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 224 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 225 static void     bge_vpd_read(struct bge_softc *);
 226 #endif
 227
 228 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 229 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 230 #ifdef notdef
 231 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 232 #endif
 233 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 234
 235 static int      bge_miibus_readreg(device_t, int, int);
 236 static int      bge_miibus_writereg(device_t, int, int, int);
 237 static void     bge_miibus_statchg(device_t);
 238
 239 static void     bge_reset(struct bge_softc *);
 240
 241 static device_method_t bge_methods[] = {
 242         /* Device interface */
 243         DEVMETHOD(device_probe,         bge_probe),
 244         DEVMETHOD(device_attach,        bge_attach),
 245         DEVMETHOD(device_detach,        bge_detach),
 246         DEVMETHOD(device_shutdown,      bge_shutdown),
 247
 248         /* bus interface */
 249         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 250         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 251
 252         /* MII interface */
 253         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 254         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 255         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 256
 257         { 0, 0 }
 258 };
 259
 260 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 261 static devclass_t bge_devclass;
 262
 263 DECLARE_DUMMY_MODULE(if_bge);
 264 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 265 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 266
 267 static uint32_t
 268 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 269 {
 270         device_t dev = sc->bge_dev;
 271
 272         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 273         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 274 }
 275
 276 static void
 277 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 278 {
 279         device_t dev = sc->bge_dev;
 280
 281         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 282         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 283 }
 284
 285 #ifdef notdef
 286 static uint32_t
 287 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 288 {
 289         device_t dev = sc->bge_dev;
 290
 291         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 292         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 293 }
 294 #endif
 295
 296 static void
 297 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 298 {
 299         device_t dev = sc->bge_dev;
 300
 301         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 302         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 303 }
 304
 305 #ifdef notdef
 306 static uint8_t
 307 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 308 {
 309         device_t dev = sc->bge_dev;
 310         uint32_t val;
 311         int i;
 312
 313         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 314         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 315                 DELAY(10);
 316                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 317                         break;
 318         }
 319
 320         if (i == BGE_TIMEOUT) {
 321                 device_printf(sc->bge_dev, "VPD read timed out\n");
 322                 return(0);
 323         }
 324
 325         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 326
 327         return((val >> ((addr % 4) * 8)) & 0xFF);
 328 }
 329
 330 static void
 331 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 332 {
 333         size_t i;
 334         uint8_t *ptr;
 335
 336         ptr = (uint8_t *)res;
 337         for (i = 0; i < sizeof(struct vpd_res); i++)
 338                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 339
 340         return;
 341 }
 342
 343 static void
 344 bge_vpd_read(struct bge_softc *sc)
 345 {
 346         int pos = 0, i;
 347         struct vpd_res res;
 348
 349         if (sc->bge_vpd_prodname != NULL)
 350                 free(sc->bge_vpd_prodname, M_DEVBUF);
 351         if (sc->bge_vpd_readonly != NULL)
 352                 free(sc->bge_vpd_readonly, M_DEVBUF);
 353         sc->bge_vpd_prodname = NULL;
 354         sc->bge_vpd_readonly = NULL;
 355
 356         bge_vpd_read_res(sc, &res, pos);
 357
 358         if (res.vr_id != VPD_RES_ID) {
 359                 device_printf(sc->bge_dev,
 360                               "bad VPD resource id: expected %x got %x\n",
 361                               VPD_RES_ID, res.vr_id);
 362                 return;
 363         }
 364
 365         pos += sizeof(res);
 366         sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 367         for (i = 0; i < res.vr_len; i++)
 368                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 369         sc->bge_vpd_prodname[i] = '\0';
 370         pos += i;
 371
 372         bge_vpd_read_res(sc, &res, pos);
 373
 374         if (res.vr_id != VPD_RES_READ) {
 375                 device_printf(sc->bge_dev,
 376                               "bad VPD resource id: expected %x got %x\n",
 377                               VPD_RES_READ, res.vr_id);
 378                 return;
 379         }
 380
 381         pos += sizeof(res);
 382         sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 383         for (i = 0; i < res.vr_len + 1; i++)
 384                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 385 }
 386 #endif
 387
 388 /*
 389  * Read a byte of data stored in the EEPROM at address 'addr.' The
 390  * BCM570x supports both the traditional bitbang interface and an
 391  * auto access interface for reading the EEPROM. We use the auto
 392  * access method.
 393  */
 394 static uint8_t
 395 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 396 {
 397         int i;
 398         uint32_t byte = 0;
 399
 400         /*
 401          * Enable use of auto EEPROM access so we can avoid
 402          * having to use the bitbang method.
 403          */
 404         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 405
 406         /* Reset the EEPROM, load the clock period. */
 407         CSR_WRITE_4(sc, BGE_EE_ADDR,
 408             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 409         DELAY(20);
 410
 411         /* Issue the read EEPROM command. */
 412         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 413
 414         /* Wait for completion */
 415         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 416                 DELAY(10);
 417                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 418                         break;
 419         }
 420
 421         if (i == BGE_TIMEOUT) {
 422                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 423                 return(0);
 424         }
 425
 426         /* Get result. */
 427         byte = CSR_READ_4(sc, BGE_EE_DATA);
 428
 429         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 430
 431         return(0);
 432 }
 433
 434 /*
 435  * Read a sequence of bytes from the EEPROM.
 436  */
 437 static int
 438 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 439 {
 440         size_t i;
 441         int err;
 442         uint8_t byte;
 443
 444         for (byte = 0, err = 0, i = 0; i < len; i++) {
 445                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 446                 if (err)
 447                         break;
 448                 *(dest + i) = byte;
 449         }
 450
 451         return(err ? 1 : 0);
 452 }
 453
 454 static int
 455 bge_miibus_readreg(device_t dev, int phy, int reg)
 456 {
 457         struct bge_softc *sc;
 458         struct ifnet *ifp;
 459         uint32_t val, autopoll;
 460         int i;
 461
 462         sc = device_get_softc(dev);
 463         ifp = &sc->arpcom.ac_if;
 464
 465         /*
 466          * Broadcom's own driver always assumes the internal
 467          * PHY is at GMII address 1. On some chips, the PHY responds
 468          * to accesses at all addresses, which could cause us to
 469          * bogusly attach the PHY 32 times at probe type. Always
 470          * restricting the lookup to address 1 is simpler than
 471          * trying to figure out which chips revisions should be
 472          * special-cased.
 473          */
 474         if (phy != 1)
 475                 return(0);
 476
 477         /* Reading with autopolling on may trigger PCI errors */
 478         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 479         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 480                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 481                 DELAY(40);
 482         }
 483
 484         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 485             BGE_MIPHY(phy)|BGE_MIREG(reg));
 486
 487         for (i = 0; i < BGE_TIMEOUT; i++) {
 488                 val = CSR_READ_4(sc, BGE_MI_COMM);
 489                 if (!(val & BGE_MICOMM_BUSY))
 490                         break;
 491         }
 492
 493         if (i == BGE_TIMEOUT) {
 494                 if_printf(ifp, "PHY read timed out\n");
 495                 val = 0;
 496                 goto done;
 497         }
 498
 499         val = CSR_READ_4(sc, BGE_MI_COMM);
 500
 501 done:
 502         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 503                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 504                 DELAY(40);
 505         }
 506
 507         if (val & BGE_MICOMM_READFAIL)
 508                 return(0);
 509
 510         return(val & 0xFFFF);
 511 }
 512
 513 static int
 514 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 515 {
 516         struct bge_softc *sc;
 517         uint32_t autopoll;
 518         int i;
 519
 520         sc = device_get_softc(dev);
 521
 522         /* Reading with autopolling on may trigger PCI errors */
 523         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 524         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 525                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 526                 DELAY(40);
 527         }
 528
 529         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 530             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 531
 532         for (i = 0; i < BGE_TIMEOUT; i++) {
 533                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 534                         break;
 535         }
 536
 537         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 538                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 539                 DELAY(40);
 540         }
 541
 542         if (i == BGE_TIMEOUT) {
 543                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 544                 return(0);
 545         }
 546
 547         return(0);
 548 }
 549
 550 static void
 551 bge_miibus_statchg(device_t dev)
 552 {
 553         struct bge_softc *sc;
 554         struct mii_data *mii;
 555
 556         sc = device_get_softc(dev);
 557         mii = device_get_softc(sc->bge_miibus);
 558
 559         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 560         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 561                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 562         } else {
 563                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 564         }
 565
 566         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 567                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 568         } else {
 569                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 570         }
 571 }
 572
 573 /*
 574  * Handle events that have triggered interrupts.
 575  */
 576 static void
 577 bge_handle_events(struct bge_softc *sc)
 578 {
 579 }
 580
 581 /*
 582  * Memory management for jumbo frames.
 583  */
 584 static int
 585 bge_alloc_jumbo_mem(struct bge_softc *sc)
 586 {
 587         struct bge_jslot *entry;
 588         caddr_t ptr;
 589         int i;
 590
 591         /* Grab a big chunk o' storage. */
 592         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 593                 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 594
 595         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 596                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 597                 return(ENOBUFS);
 598         }
 599
 600         SLIST_INIT(&sc->bge_jfree_listhead);
 601
 602         /*
 603          * Now divide it up into 9K pieces and save the addresses
 604          * in an array. Note that we play an evil trick here by using
 605          * the first few bytes in the buffer to hold the the address
 606          * of the softc structure for this interface. This is because
 607          * bge_jfree() needs it, but it is called by the mbuf management
 608          * code which will not pass it to us explicitly.
 609          */
 610         ptr = sc->bge_cdata.bge_jumbo_buf;
 611         for (i = 0; i < BGE_JSLOTS; i++) {
 612                 entry = &sc->bge_cdata.bge_jslots[i];
 613                 entry->bge_sc = sc;
 614                 entry->bge_buf = ptr;
 615                 entry->bge_inuse = 0;
 616                 entry->bge_slot = i;
 617                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 618                 ptr += BGE_JLEN;
 619         }
 620
 621         return(0);
 622 }
 623
 624 static void
 625 bge_free_jumbo_mem(struct bge_softc *sc)
 626 {
 627         contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 628 }
 629
 630 /*
 631  * Allocate a jumbo buffer.
 632  */
 633 static struct bge_jslot *
 634 bge_jalloc(struct bge_softc *sc)
 635 {
 636         struct bge_jslot *entry;
 637
 638         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 639
 640         if (entry == NULL) {
 641                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 642                 return(NULL);
 643         }
 644
 645         SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 646         entry->bge_inuse = 1;
 647         return(entry);
 648 }
 649
 650 /*
 651  * Adjust usage count on a jumbo buffer.
 652  */
 653 static void
 654 bge_jref(void *arg)
 655 {
 656         struct bge_jslot *entry = (struct bge_jslot *)arg;
 657         struct bge_softc *sc = entry->bge_sc;
 658
 659         if (sc == NULL)
 660                 panic("bge_jref: can't find softc pointer!");
 661
 662         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 663                 panic("bge_jref: asked to reference buffer "
 664                     "that we don't manage!");
 665         else if (entry->bge_inuse == 0)
 666                 panic("bge_jref: buffer already free!");
 667         else
 668                 entry->bge_inuse++;
 669 }
 670
 671 /*
 672  * Release a jumbo buffer.
 673  */
 674 static void
 675 bge_jfree(void *arg)
 676 {
 677         struct bge_jslot *entry = (struct bge_jslot *)arg;
 678         struct bge_softc *sc = entry->bge_sc;
 679
 680         if (sc == NULL)
 681                 panic("bge_jfree: can't find softc pointer!");
 682
 683         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 684                 panic("bge_jfree: asked to free buffer that we don't manage!");
 685         else if (entry->bge_inuse == 0)
 686                 panic("bge_jfree: buffer already free!");
 687         else if (--entry->bge_inuse == 0)
 688                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 689 }
 690
 691
 692 /*
 693  * Intialize a standard receive ring descriptor.
 694  */
 695 static int
 696 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 697 {
 698         struct mbuf *m_new = NULL;
 699         struct bge_rx_bd *r;
 700
 701         if (m == NULL) {
 702                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 703                 if (m_new == NULL)
 704                         return(ENOBUFS);
 705
 706                 MCLGET(m_new, MB_DONTWAIT);
 707                 if (!(m_new->m_flags & M_EXT)) {
 708                         m_freem(m_new);
 709                         return(ENOBUFS);
 710                 }
 711                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 712         } else {
 713                 m_new = m;
 714                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 715                 m_new->m_data = m_new->m_ext.ext_buf;
 716         }
 717
 718         if (!sc->bge_rx_alignment_bug)
 719                 m_adj(m_new, ETHER_ALIGN);
 720         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 721         r = &sc->bge_rdata->bge_rx_std_ring[i];
 722         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 723         r->bge_flags = BGE_RXBDFLAG_END;
 724         r->bge_len = m_new->m_len;
 725         r->bge_idx = i;
 726
 727         return(0);
 728 }
 729
 730 /*
 731  * Initialize a jumbo receive ring descriptor. This allocates
 732  * a jumbo buffer from the pool managed internally by the driver.
 733  */
 734 static int
 735 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 736 {
 737         struct mbuf *m_new = NULL;
 738         struct bge_rx_bd *r;
 739
 740         if (m == NULL) {
 741                 struct bge_jslot *buf;
 742
 743                 /* Allocate the mbuf. */
 744                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 745                 if (m_new == NULL)
 746                         return(ENOBUFS);
 747
 748                 /* Allocate the jumbo buffer */
 749                 buf = bge_jalloc(sc);
 750                 if (buf == NULL) {
 751                         m_freem(m_new);
 752                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 753                             "-- packet dropped!\n");
 754                         return(ENOBUFS);
 755                 }
 756
 757                 /* Attach the buffer to the mbuf. */
 758                 m_new->m_ext.ext_arg = buf;
 759                 m_new->m_ext.ext_buf = buf->bge_buf;
 760                 m_new->m_ext.ext_nfree.new = bge_jfree;
 761                 m_new->m_ext.ext_nref.new = bge_jref;
 762                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 763
 764                 m_new->m_data = m_new->m_ext.ext_buf;
 765                 m_new->m_flags |= M_EXT;
 766                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 767         } else {
 768                 m_new = m;
 769                 m_new->m_data = m_new->m_ext.ext_buf;
 770                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 771         }
 772
 773         if (!sc->bge_rx_alignment_bug)
 774                 m_adj(m_new, ETHER_ALIGN);
 775         /* Set up the descriptor. */
 776         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 777         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 778         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 779         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 780         r->bge_len = m_new->m_len;
 781         r->bge_idx = i;
 782
 783         return(0);
 784 }
 785
 786 /*
 787  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 788  * that's 1MB or memory, which is a lot. For now, we fill only the first
 789  * 256 ring entries and hope that our CPU is fast enough to keep up with
 790  * the NIC.
 791  */
 792 static int
 793 bge_init_rx_ring_std(struct bge_softc *sc)
 794 {
 795         int i;
 796
 797         for (i = 0; i < BGE_SSLOTS; i++) {
 798                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 799                         return(ENOBUFS);
 800         };
 801
 802         sc->bge_std = i - 1;
 803         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 804
 805         return(0);
 806 }
 807
 808 static void
 809 bge_free_rx_ring_std(struct bge_softc *sc)
 810 {
 811         int i;
 812
 813         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 814                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 815                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 816                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 817                 }
 818                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 819                     sizeof(struct bge_rx_bd));
 820         }
 821 }
 822
 823 static int
 824 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 825 {
 826         int i;
 827         struct bge_rcb *rcb;
 828
 829         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 830                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 831                         return(ENOBUFS);
 832         };
 833
 834         sc->bge_jumbo = i - 1;
 835
 836         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 837         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 838         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 839
 840         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 841
 842         return(0);
 843 }
 844
 845 static void
 846 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 847 {
 848         int i;
 849
 850         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 851                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 852                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 853                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 854                 }
 855                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 856                     sizeof(struct bge_rx_bd));
 857         }
 858 }
 859
 860 static void
 861 bge_free_tx_ring(struct bge_softc *sc)
 862 {
 863         int i;
 864
 865         if (sc->bge_rdata->bge_tx_ring == NULL)
 866                 return;
 867
 868         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 869                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 870                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 871                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 872                 }
 873                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 874                     sizeof(struct bge_tx_bd));
 875         }
 876 }
 877
 878 static int
 879 bge_init_tx_ring(struct bge_softc *sc)
 880 {
 881         sc->bge_txcnt = 0;
 882         sc->bge_tx_saved_considx = 0;
 883
 884         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 885         /* 5700 b2 errata */
 886         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 887                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 888
 889         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 890         /* 5700 b2 errata */
 891         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 892                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 893
 894         return(0);
 895 }
 896
 897 static void
 898 bge_setmulti(struct bge_softc *sc)
 899 {
 900         struct ifnet *ifp;
 901         struct ifmultiaddr *ifma;
 902         uint32_t hashes[4] = { 0, 0, 0, 0 };
 903         int h, i;
 904
 905         ifp = &sc->arpcom.ac_if;
 906
 907         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 908                 for (i = 0; i < 4; i++)
 909                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 910                 return;
 911         }
 912
 913         /* First, zot all the existing filters. */
 914         for (i = 0; i < 4; i++)
 915                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 916
 917         /* Now program new ones. */
 918         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 919                 if (ifma->ifma_addr->sa_family != AF_LINK)
 920                         continue;
 921                 h = ether_crc32_le(
 922                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 923                     ETHER_ADDR_LEN) & 0x7f;
 924                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 925         }
 926
 927         for (i = 0; i < 4; i++)
 928                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 929 }
 930
 931 /*
 932  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 933  * self-test results.
 934  */
 935 static int
 936 bge_chipinit(struct bge_softc *sc)
 937 {
 938         int i;
 939         uint32_t dma_rw_ctl;
 940
 941         /* Set endianness before we access any non-PCI registers. */
 942 #if BYTE_ORDER == BIG_ENDIAN
 943         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 944             BGE_BIGENDIAN_INIT, 4);
 945 #else
 946         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 947             BGE_LITTLEENDIAN_INIT, 4);
 948 #endif
 949
 950         /*
 951          * Check the 'ROM failed' bit on the RX CPU to see if
 952          * self-tests passed.
 953          */
 954         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 955                 if_printf(&sc->arpcom.ac_if,
 956                           "RX CPU self-diagnostics failed!\n");
 957                 return(ENODEV);
 958         }
 959
 960         /* Clear the MAC control register */
 961         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 962
 963         /*
 964          * Clear the MAC statistics block in the NIC's
 965          * internal memory.
 966          */
 967         for (i = BGE_STATS_BLOCK;
 968             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 969                 BGE_MEMWIN_WRITE(sc, i, 0);
 970
 971         for (i = BGE_STATUS_BLOCK;
 972             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 973                 BGE_MEMWIN_WRITE(sc, i, 0);
 974
 975         /* Set up the PCI DMA control register. */
 976         if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
 977             BGE_PCISTATE_PCI_BUSMODE) {
 978                 /* Conventional PCI bus */
 979                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 980                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 981                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 982                     (0x0F);
 983         } else {
 984                 /* PCI-X bus */
 985                 /*
 986                  * The 5704 uses a different encoding of read/write
 987                  * watermarks.
 988                  */
 989                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 990                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 991                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 992                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 993                 else
 994                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 995                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 996                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 997                             (0x0F);
 998
 999                 /*
1000                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1001                  * for hardware bugs.
1002                  */
1003                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1004                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1005                         uint32_t tmp;
1006
1007                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1008                         if (tmp == 0x6 || tmp == 0x7)
1009                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1010                 }
1011         }
1012
1013         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1014             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1015             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1016                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1017         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1018
1019         /*
1020          * Set up general mode register.
1021          */
1022         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1023             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1024             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1025             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1026
1027         /*
1028          * Disable memory write invalidate.  Apparently it is not supported
1029          * properly by these devices.
1030          */
1031         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1032
1033         /* Set the timer prescaler (always 66Mhz) */
1034         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1035
1036         return(0);
1037 }
1038
1039 static int
1040 bge_blockinit(struct bge_softc *sc)
1041 {
1042         struct bge_rcb *rcb;
1043         volatile struct bge_rcb *vrcb;
1044         int i;
1045
1046         /*
1047          * Initialize the memory window pointer register so that
1048          * we can access the first 32K of internal NIC RAM. This will
1049          * allow us to set up the TX send ring RCBs and the RX return
1050          * ring RCBs, plus other things which live in NIC memory.
1051          */
1052         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1053
1054         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1055
1056         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1057                 /* Configure mbuf memory pool */
1058                 if (sc->bge_extram) {
1059                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1060                             BGE_EXT_SSRAM);
1061                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1062                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1063                         else
1064                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1065                 } else {
1066                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1067                             BGE_BUFFPOOL_1);
1068                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1069                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1070                         else
1071                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1072                 }
1073
1074                 /* Configure DMA resource pool */
1075                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1076                     BGE_DMA_DESCRIPTORS);
1077                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1078         }
1079
1080         /* Configure mbuf pool watermarks */
1081         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1082                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1083                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1084         } else {
1085                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1086                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1087         }
1088         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1089
1090         /* Configure DMA resource watermarks */
1091         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1092         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1093
1094         /* Enable buffer manager */
1095         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1096                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1097                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1098
1099                 /* Poll for buffer manager start indication */
1100                 for (i = 0; i < BGE_TIMEOUT; i++) {
1101                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1102                                 break;
1103                         DELAY(10);
1104                 }
1105
1106                 if (i == BGE_TIMEOUT) {
1107                         if_printf(&sc->arpcom.ac_if,
1108                                   "buffer manager failed to start\n");
1109                         return(ENXIO);
1110                 }
1111         }
1112
1113         /* Enable flow-through queues */
1114         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1115         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1116
1117         /* Wait until queue initialization is complete */
1118         for (i = 0; i < BGE_TIMEOUT; i++) {
1119                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1120                         break;
1121                 DELAY(10);
1122         }
1123
1124         if (i == BGE_TIMEOUT) {
1125                 if_printf(&sc->arpcom.ac_if,
1126                           "flow-through queue init failed\n");
1127                 return(ENXIO);
1128         }
1129
1130         /* Initialize the standard RX ring control block */
1131         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1132         BGE_HOSTADDR(rcb->bge_hostaddr,
1133             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1134         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1135                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1136         else
1137                 rcb->bge_maxlen_flags =
1138                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1139         if (sc->bge_extram)
1140                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1141         else
1142                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1143         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1144         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1145         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1146         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1147
1148         /*
1149          * Initialize the jumbo RX ring control block
1150          * We set the 'ring disabled' bit in the flags
1151          * field until we're actually ready to start
1152          * using this ring (i.e. once we set the MTU
1153          * high enough to require it).
1154          */
1155         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1156                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1157                 BGE_HOSTADDR(rcb->bge_hostaddr,
1158                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1159                 rcb->bge_maxlen_flags =
1160                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1161                     BGE_RCB_FLAG_RING_DISABLED);
1162                 if (sc->bge_extram)
1163                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1164                 else
1165                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1166                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1167                     rcb->bge_hostaddr.bge_addr_hi);
1168                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1169                     rcb->bge_hostaddr.bge_addr_lo);
1170                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1171                     rcb->bge_maxlen_flags);
1172                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1173
1174                 /* Set up dummy disabled mini ring RCB */
1175                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1176                 rcb->bge_maxlen_flags =
1177                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1178                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1179                     rcb->bge_maxlen_flags);
1180         }
1181
1182         /*
1183          * Set the BD ring replentish thresholds. The recommended
1184          * values are 1/8th the number of descriptors allocated to
1185          * each ring.
1186          */
1187         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1188         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1189
1190         /*
1191          * Disable all unused send rings by setting the 'ring disabled'
1192          * bit in the flags field of all the TX send ring control blocks.
1193          * These are located in NIC memory.
1194          */
1195         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1196             BGE_SEND_RING_RCB);
1197         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1198                 vrcb->bge_maxlen_flags =
1199                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1200                 vrcb->bge_nicaddr = 0;
1201                 vrcb++;
1202         }
1203
1204         /* Configure TX RCB 0 (we use only the first ring) */
1205         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1206             BGE_SEND_RING_RCB);
1207         vrcb->bge_hostaddr.bge_addr_hi = 0;
1208         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1209         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1210         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1211                 vrcb->bge_maxlen_flags =
1212                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1213
1214         /* Disable all unused RX return rings */
1215         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1216             BGE_RX_RETURN_RING_RCB);
1217         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1218                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1219                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1220                 vrcb->bge_maxlen_flags =
1221                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1222                     BGE_RCB_FLAG_RING_DISABLED);
1223                 vrcb->bge_nicaddr = 0;
1224                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1225                     (i * (sizeof(uint64_t))), 0);
1226                 vrcb++;
1227         }
1228
1229         /* Initialize RX ring indexes */
1230         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1231         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1232         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1233
1234         /*
1235          * Set up RX return ring 0
1236          * Note that the NIC address for RX return rings is 0x00000000.
1237          * The return rings live entirely within the host, so the
1238          * nicaddr field in the RCB isn't used.
1239          */
1240         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1241             BGE_RX_RETURN_RING_RCB);
1242         vrcb->bge_hostaddr.bge_addr_hi = 0;
1243         BGE_HOSTADDR(vrcb->bge_hostaddr,
1244             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1245         vrcb->bge_nicaddr = 0x00000000;
1246         vrcb->bge_maxlen_flags =
1247             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1248
1249         /* Set random backoff seed for TX */
1250         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1251             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1252             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1253             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1254             BGE_TX_BACKOFF_SEED_MASK);
1255
1256         /* Set inter-packet gap */
1257         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1258
1259         /*
1260          * Specify which ring to use for packets that don't match
1261          * any RX rules.
1262          */
1263         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1264
1265         /*
1266          * Configure number of RX lists. One interrupt distribution
1267          * list, sixteen active lists, one bad frames class.
1268          */
1269         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1270
1271         /* Inialize RX list placement stats mask. */
1272         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1273         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1274
1275         /* Disable host coalescing until we get it set up */
1276         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1277
1278         /* Poll to make sure it's shut down. */
1279         for (i = 0; i < BGE_TIMEOUT; i++) {
1280                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1281                         break;
1282                 DELAY(10);
1283         }
1284
1285         if (i == BGE_TIMEOUT) {
1286                 if_printf(&sc->arpcom.ac_if,
1287                           "host coalescing engine failed to idle\n");
1288                 return(ENXIO);
1289         }
1290
1291         /* Set up host coalescing defaults */
1292         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1293         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1294         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1295         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1296         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1297                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1298                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1299         }
1300         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1301         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1302
1303         /* Set up address of statistics block */
1304         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1305                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1306                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1307                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1308
1309                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1310                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1311                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1312         }
1313
1314         /* Set up address of status block */
1315         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1316         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1317             vtophys(&sc->bge_rdata->bge_status_block));
1318
1319         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1320         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1321
1322         /* Turn on host coalescing state machine */
1323         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1324
1325         /* Turn on RX BD completion state machine and enable attentions */
1326         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1327             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1328
1329         /* Turn on RX list placement state machine */
1330         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1331
1332         /* Turn on RX list selector state machine. */
1333         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1334                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1335
1336         /* Turn on DMA, clear stats */
1337         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1338             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1339             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1340             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1341             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1342
1343         /* Set misc. local control, enable interrupts on attentions */
1344         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1345
1346 #ifdef notdef
1347         /* Assert GPIO pins for PHY reset */
1348         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1349             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1350         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1351             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1352 #endif
1353
1354         /* Turn on DMA completion state machine */
1355         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1356                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1357
1358         /* Turn on write DMA state machine */
1359         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1360             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1361
1362         /* Turn on read DMA state machine */
1363         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1364             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1365
1366         /* Turn on RX data completion state machine */
1367         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1368
1369         /* Turn on RX BD initiator state machine */
1370         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1371
1372         /* Turn on RX data and RX BD initiator state machine */
1373         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1374
1375         /* Turn on Mbuf cluster free state machine */
1376         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1377                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1378
1379         /* Turn on send BD completion state machine */
1380         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1381
1382         /* Turn on send data completion state machine */
1383         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1384
1385         /* Turn on send data initiator state machine */
1386         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1387
1388         /* Turn on send BD initiator state machine */
1389         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1390
1391         /* Turn on send BD selector state machine */
1392         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1393
1394         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1395         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1396             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1397
1398         /* ack/clear link change events */
1399         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1400             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1401             BGE_MACSTAT_LINK_CHANGED);
1402
1403         /* Enable PHY auto polling (for MII/GMII only) */
1404         if (sc->bge_tbi) {
1405                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1406         } else {
1407                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1408                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1409                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1410                             BGE_EVTENB_MI_INTERRUPT);
1411         }
1412
1413         /* Enable link state change attentions. */
1414         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1415
1416         return(0);
1417 }
1418
1419 /*
1420  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1421  * against our list and return its name if we find a match. Note
1422  * that since the Broadcom controller contains VPD support, we
1423  * can get the device name string from the controller itself instead
1424  * of the compiled-in string. This is a little slow, but it guarantees
1425  * we'll always announce the right product name.
1426  */
1427 static int
1428 bge_probe(device_t dev)
1429 {
1430         struct bge_softc *sc;
1431         struct bge_type *t;
1432         char *descbuf;
1433         uint16_t product, vendor;
1434
1435         product = pci_get_device(dev);
1436         vendor = pci_get_vendor(dev);
1437
1438         for (t = bge_devs; t->bge_name != NULL; t++) {
1439                 if (vendor == t->bge_vid && product == t->bge_did)
1440                         break;
1441         }
1442
1443         if (t->bge_name == NULL)
1444                 return(ENXIO);
1445
1446         sc = device_get_softc(dev);
1447 #ifdef notdef
1448         sc->bge_dev = dev;
1449
1450         bge_vpd_read(sc);
1451         device_set_desc(dev, sc->bge_vpd_prodname);
1452 #endif
1453         descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1454         snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1455             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1456         device_set_desc_copy(dev, descbuf);
1457         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1458                 sc->bge_no_3_led = 1;
1459         free(descbuf, M_TEMP);
1460         return(0);
1461 }
1462
1463 static int
1464 bge_attach(device_t dev)
1465 {
1466         int s;
1467         uint32_t command;
1468         struct ifnet *ifp;
1469         struct bge_softc *sc;
1470         uint32_t hwcfg = 0;
1471         uint32_t mac_addr = 0;
1472         int error = 0, rid;
1473         uint8_t ether_addr[ETHER_ADDR_LEN];
1474
1475         s = splimp();
1476
1477         sc = device_get_softc(dev);
1478         sc->bge_dev = dev;
1479         callout_init(&sc->bge_stat_timer);
1480
1481         /*
1482          * Map control/status registers.
1483          */
1484         pci_enable_busmaster(dev);
1485         pci_enable_io(dev, SYS_RES_MEMORY);
1486         command = pci_read_config(dev, PCIR_COMMAND, 4);
1487
1488         if (!(command & PCIM_CMD_MEMEN)) {
1489                 device_printf(dev, "failed to enable memory mapping!\n");
1490                 error = ENXIO;
1491                 goto fail;
1492         }
1493
1494         rid = BGE_PCI_BAR0;
1495         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1496             RF_ACTIVE);
1497
1498         if (sc->bge_res == NULL) {
1499                 device_printf(dev, "couldn't map memory\n");
1500                 error = ENXIO;
1501                 goto fail;
1502         }
1503
1504         sc->bge_btag = rman_get_bustag(sc->bge_res);
1505         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1506         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1507
1508         /* Allocate interrupt */
1509         rid = 0;
1510
1511         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1512             RF_SHAREABLE | RF_ACTIVE);
1513
1514         if (sc->bge_irq == NULL) {
1515                 device_printf(dev, "couldn't map interrupt\n");
1516                 error = ENXIO;
1517                 goto fail;
1518         }
1519
1520         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1521            bge_intr, sc, &sc->bge_intrhand);
1522
1523         if (error) {
1524                 bge_release_resources(sc);
1525                 device_printf(dev, "couldn't set up irq\n");
1526                 goto fail;
1527         }
1528
1529         ifp = &sc->arpcom.ac_if;
1530         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1531
1532         /* Try to reset the chip. */
1533         bge_reset(sc);
1534
1535         if (bge_chipinit(sc)) {
1536                 device_printf(dev, "chip initialization failed\n");
1537                 bge_release_resources(sc);
1538                 error = ENXIO;
1539                 goto fail;
1540         }
1541
1542         /*
1543          * Get station address from the EEPROM.
1544          */
1545         mac_addr = bge_readmem_ind(sc, 0x0c14);
1546         if ((mac_addr >> 16) == 0x484b) {
1547                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1548                 ether_addr[1] = (uint8_t)mac_addr;
1549                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1550                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1551                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1552                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1553                 ether_addr[5] = (uint8_t)mac_addr;
1554         } else if (bge_read_eeprom(sc, ether_addr,
1555             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1556                 device_printf(dev, "failed to read station address\n");
1557                 bge_release_resources(sc);
1558                 error = ENXIO;
1559                 goto fail;
1560         }
1561
1562         /* Allocate the general information block and ring buffers. */
1563         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1564             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1565
1566         if (sc->bge_rdata == NULL) {
1567                 bge_release_resources(sc);
1568                 error = ENXIO;
1569                 device_printf(dev, "no memory for list buffers!\n");
1570                 goto fail;
1571         }
1572
1573         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1574
1575         /* Save ASIC rev. */
1576
1577         sc->bge_chipid =
1578             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1579             BGE_PCIMISCCTL_ASICREV;
1580         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1581         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1582
1583         /*
1584          * Try to allocate memory for jumbo buffers.
1585          * The 5705 does not appear to support jumbo frames.
1586          */
1587         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1588                 if (bge_alloc_jumbo_mem(sc)) {
1589                         device_printf(dev, "jumbo buffer allocation failed\n");
1590                         bge_release_resources(sc);
1591                         error = ENXIO;
1592                         goto fail;
1593                 }
1594         }
1595
1596         /* Set default tuneable values. */
1597         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1598         sc->bge_rx_coal_ticks = 150;
1599         sc->bge_tx_coal_ticks = 150;
1600         sc->bge_rx_max_coal_bds = 64;
1601         sc->bge_tx_max_coal_bds = 128;
1602
1603         /* 5705 limits RX return ring to 512 entries. */
1604         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1605                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1606         else
1607                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1608
1609         /* Set up ifnet structure */
1610         ifp->if_softc = sc;
1611         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1612         ifp->if_ioctl = bge_ioctl;
1613         ifp->if_start = bge_start;
1614         ifp->if_watchdog = bge_watchdog;
1615         ifp->if_init = bge_init;
1616         ifp->if_mtu = ETHERMTU;
1617         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1618         ifq_set_ready(&ifp->if_snd);
1619         ifp->if_hwassist = BGE_CSUM_FEATURES;
1620         ifp->if_capabilities = IFCAP_HWCSUM;
1621         ifp->if_capenable = ifp->if_capabilities;
1622
1623         /*
1624          * Figure out what sort of media we have by checking the
1625          * hardware config word in the first 32k of NIC internal memory,
1626          * or fall back to examining the EEPROM if necessary.
1627          * Note: on some BCM5700 cards, this value appears to be unset.
1628          * If that's the case, we have to rely on identifying the NIC
1629          * by its PCI subsystem ID, as we do below for the SysKonnect
1630          * SK-9D41.
1631          */
1632         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1633                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1634         else {
1635                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1636                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1637                 hwcfg = ntohl(hwcfg);
1638         }
1639
1640         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1641                 sc->bge_tbi = 1;
1642
1643         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1644         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1645                 sc->bge_tbi = 1;
1646
1647         if (sc->bge_tbi) {
1648                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1649                     bge_ifmedia_upd, bge_ifmedia_sts);
1650                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1651                 ifmedia_add(&sc->bge_ifmedia,
1652                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1653                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1654                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1655         } else {
1656                 /*
1657                  * Do transceiver setup.
1658                  */
1659                 if (mii_phy_probe(dev, &sc->bge_miibus,
1660                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1661                         device_printf(dev, "MII without any PHY!\n");
1662                         bge_release_resources(sc);
1663                         bge_free_jumbo_mem(sc);
1664                         error = ENXIO;
1665                         goto fail;
1666                 }
1667         }
1668
1669         /*
1670          * When using the BCM5701 in PCI-X mode, data corruption has
1671          * been observed in the first few bytes of some received packets.
1672          * Aligning the packet buffer in memory eliminates the corruption.
1673          * Unfortunately, this misaligns the packet payloads.  On platforms
1674          * which do not support unaligned accesses, we will realign the
1675          * payloads by copying the received packets.
1676          */
1677         switch (sc->bge_chipid) {
1678         case BGE_CHIPID_BCM5701_A0:
1679         case BGE_CHIPID_BCM5701_B0:
1680         case BGE_CHIPID_BCM5701_B2:
1681         case BGE_CHIPID_BCM5701_B5:
1682                 /* If in PCI-X mode, work around the alignment bug. */
1683                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1684                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1685                     BGE_PCISTATE_PCI_BUSSPEED)
1686                         sc->bge_rx_alignment_bug = 1;
1687                 break;
1688         }
1689
1690         /*
1691          * Call MI attach routine.
1692          */
1693         ether_ifattach(ifp, ether_addr);
1694
1695 fail:
1696         splx(s);
1697
1698         return(error);
1699 }
1700
1701 static int
1702 bge_detach(device_t dev)
1703 {
1704         struct bge_softc *sc;
1705         struct ifnet *ifp;
1706         int s;
1707
1708         s = splimp();
1709
1710         sc = device_get_softc(dev);
1711         ifp = &sc->arpcom.ac_if;
1712
1713         ether_ifdetach(ifp);
1714         bge_stop(sc);
1715         bge_reset(sc);
1716
1717         if (sc->bge_tbi) {
1718                 ifmedia_removeall(&sc->bge_ifmedia);
1719         } else {
1720                 bus_generic_detach(dev);
1721                 device_delete_child(dev, sc->bge_miibus);
1722         }
1723
1724         bge_release_resources(sc);
1725         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1726                 bge_free_jumbo_mem(sc);
1727
1728         splx(s);
1729
1730         return(0);
1731 }
1732
1733 static void
1734 bge_release_resources(struct bge_softc *sc)
1735 {
1736         device_t dev;
1737
1738         dev = sc->bge_dev;
1739
1740         if (sc->bge_vpd_prodname != NULL)
1741                 free(sc->bge_vpd_prodname, M_DEVBUF);
1742
1743         if (sc->bge_vpd_readonly != NULL)
1744                 free(sc->bge_vpd_readonly, M_DEVBUF);
1745
1746         if (sc->bge_intrhand != NULL)
1747                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1748
1749         if (sc->bge_irq != NULL)
1750                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1751
1752         if (sc->bge_res != NULL)
1753                 bus_release_resource(dev, SYS_RES_MEMORY,
1754                     BGE_PCI_BAR0, sc->bge_res);
1755
1756         if (sc->bge_rdata != NULL)
1757                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1758                            M_DEVBUF);
1759
1760         return;
1761 }
1762
1763 static void
1764 bge_reset(struct bge_softc *sc)
1765 {
1766         device_t dev;
1767         uint32_t cachesize, command, pcistate;
1768         int i, val = 0;
1769
1770         dev = sc->bge_dev;
1771
1772         /* Save some important PCI state. */
1773         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1774         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1775         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1776
1777         pci_write_config(dev, BGE_PCI_MISC_CTL,
1778             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1779             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1780
1781         /* Issue global reset */
1782         bge_writereg_ind(sc, BGE_MISC_CFG,
1783                          BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1));
1784
1785         DELAY(1000);
1786
1787         /* Reset some of the PCI state that got zapped by reset */
1788         pci_write_config(dev, BGE_PCI_MISC_CTL,
1789             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1790             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1791         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1792         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1793         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1794
1795         /*
1796          * Prevent PXE restart: write a magic number to the
1797          * general communications memory at 0xB50.
1798          */
1799         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1800         /*
1801          * Poll the value location we just wrote until
1802          * we see the 1's complement of the magic number.
1803          * This indicates that the firmware initialization
1804          * is complete.
1805          */
1806         for (i = 0; i < BGE_TIMEOUT; i++) {
1807                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1808                 if (val == ~BGE_MAGIC_NUMBER)
1809                         break;
1810                 DELAY(10);
1811         }
1812
1813         if (i == BGE_TIMEOUT) {
1814                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1815                 return;
1816         }
1817
1818         /*
1819          * XXX Wait for the value of the PCISTATE register to
1820          * return to its original pre-reset state. This is a
1821          * fairly good indicator of reset completion. If we don't
1822          * wait for the reset to fully complete, trying to read
1823          * from the device's non-PCI registers may yield garbage
1824          * results.
1825          */
1826         for (i = 0; i < BGE_TIMEOUT; i++) {
1827                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1828                         break;
1829                 DELAY(10);
1830         }
1831
1832         /* Enable memory arbiter. */
1833         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1834                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1835
1836         /* Fix up byte swapping */
1837         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1838             BGE_MODECTL_BYTESWAP_DATA);
1839
1840         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1841
1842         DELAY(10000);
1843
1844         return;
1845 }
1846
1847 /*
1848  * Frame reception handling. This is called if there's a frame
1849  * on the receive return list.
1850  *
1851  * Note: we have to be able to handle two possibilities here:
1852  * 1) the frame is from the jumbo recieve ring
1853  * 2) the frame is from the standard receive ring
1854  */
1855
1856 static void
1857 bge_rxeof(struct bge_softc *sc)
1858 {
1859         struct ifnet *ifp;
1860         int stdcnt = 0, jumbocnt = 0;
1861
1862         ifp = &sc->arpcom.ac_if;
1863
1864         while(sc->bge_rx_saved_considx !=
1865             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1866                 struct bge_rx_bd        *cur_rx;
1867                 uint32_t                rxidx;
1868                 struct mbuf             *m = NULL;
1869                 uint16_t                vlan_tag = 0;
1870                 int                     have_tag = 0;
1871
1872                 cur_rx =
1873             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1874
1875                 rxidx = cur_rx->bge_idx;
1876                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1877
1878                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1879                         have_tag = 1;
1880                         vlan_tag = cur_rx->bge_vlan_tag;
1881                 }
1882
1883                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1884                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1885                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1886                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1887                         jumbocnt++;
1888                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1889                                 ifp->if_ierrors++;
1890                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1891                                 continue;
1892                         }
1893                         if (bge_newbuf_jumbo(sc,
1894                             sc->bge_jumbo, NULL) == ENOBUFS) {
1895                                 ifp->if_ierrors++;
1896                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1897                                 continue;
1898                         }
1899                 } else {
1900                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1901                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1902                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1903                         stdcnt++;
1904                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1905                                 ifp->if_ierrors++;
1906                                 bge_newbuf_std(sc, sc->bge_std, m);
1907                                 continue;
1908                         }
1909                         if (bge_newbuf_std(sc, sc->bge_std,
1910                             NULL) == ENOBUFS) {
1911                                 ifp->if_ierrors++;
1912                                 bge_newbuf_std(sc, sc->bge_std, m);
1913                                 continue;
1914                         }
1915                 }
1916
1917                 ifp->if_ipackets++;
1918 #ifndef __i386__
1919                 /*
1920                  * The i386 allows unaligned accesses, but for other
1921                  * platforms we must make sure the payload is aligned.
1922                  */
1923                 if (sc->bge_rx_alignment_bug) {
1924                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1925                             cur_rx->bge_len);
1926                         m->m_data += ETHER_ALIGN;
1927                 }
1928 #endif
1929                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
1930                 m->m_pkthdr.rcvif = ifp;
1931
1932 #if 0 /* currently broken for some packets, possibly related to TCP options */
1933                 if (ifp->if_hwassist) {
1934                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1935                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1936                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1937                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1938                                 m->m_pkthdr.csum_data =
1939                                     cur_rx->bge_tcp_udp_csum;
1940                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1941                         }
1942                 }
1943 #endif
1944
1945                 /*
1946                  * If we received a packet with a vlan tag, pass it
1947                  * to vlan_input() instead of ether_input().
1948                  */
1949                 if (have_tag) {
1950                         VLAN_INPUT_TAG(m, vlan_tag);
1951                         have_tag = vlan_tag = 0;
1952                         continue;
1953                 }
1954
1955                 (*ifp->if_input)(ifp, m);
1956         }
1957
1958         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1959         if (stdcnt)
1960                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1961         if (jumbocnt)
1962                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1963 }
1964
1965 static void
1966 bge_txeof(struct bge_softc *sc)
1967 {
1968         struct bge_tx_bd *cur_tx = NULL;
1969         struct ifnet *ifp;
1970
1971         ifp = &sc->arpcom.ac_if;
1972
1973         /*
1974          * Go through our tx ring and free mbufs for those
1975          * frames that have been sent.
1976          */
1977         while (sc->bge_tx_saved_considx !=
1978             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
1979                 uint32_t                idx = 0;
1980
1981                 idx = sc->bge_tx_saved_considx;
1982                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
1983                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
1984                         ifp->if_opackets++;
1985                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
1986                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
1987                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
1988                 }
1989                 sc->bge_txcnt--;
1990                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
1991                 ifp->if_timer = 0;
1992         }
1993
1994         if (cur_tx != NULL)
1995                 ifp->if_flags &= ~IFF_OACTIVE;
1996 }
1997
1998 static void
1999 bge_intr(void *xsc)
2000 {
2001         struct bge_softc *sc = xsc;
2002         struct ifnet *ifp = &sc->arpcom.ac_if;
2003         uint32_t status;
2004
2005 #ifdef notdef
2006         /* Avoid this for now -- checking this register is expensive. */
2007         /* Make sure this is really our interrupt. */
2008         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2009                 return;
2010 #endif
2011         /* Ack interrupt and stop others from occuring. */
2012         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2013
2014         /*
2015          * Process link state changes.
2016          * Grrr. The link status word in the status block does
2017          * not work correctly on the BCM5700 rev AX and BX chips,
2018          * according to all available information. Hence, we have
2019          * to enable MII interrupts in order to properly obtain
2020          * async link changes. Unfortunately, this also means that
2021          * we have to read the MAC status register to detect link
2022          * changes, thereby adding an additional register access to
2023          * the interrupt handler.
2024          */
2025
2026         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2027                 status = CSR_READ_4(sc, BGE_MAC_STS);
2028                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2029                         sc->bge_link = 0;
2030                         callout_stop(&sc->bge_stat_timer);
2031                         bge_tick(sc);
2032                         /* Clear the interrupt */
2033                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2034                             BGE_EVTENB_MI_INTERRUPT);
2035                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2036                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2037                             BRGPHY_INTRS);
2038                 }
2039         } else {
2040                 if ((sc->bge_rdata->bge_status_block.bge_status &
2041                     BGE_STATFLAG_UPDATED) &&
2042                     (sc->bge_rdata->bge_status_block.bge_status &
2043                     BGE_STATFLAG_LINKSTATE_CHANGED)) {
2044                         sc->bge_rdata->bge_status_block.bge_status &=
2045                                 ~(BGE_STATFLAG_UPDATED|
2046                                 BGE_STATFLAG_LINKSTATE_CHANGED);
2047                         /*
2048                          * Sometimes PCS encoding errors are detected in
2049                          * TBI mode (on fiber NICs), and for some reason
2050                          * the chip will signal them as link changes.
2051                          * If we get a link change event, but the 'PCS
2052                          * encoding error' bit in the MAC status register
2053                          * is set, don't bother doing a link check.
2054                          * This avoids spurious "gigabit link up" messages
2055                          * that sometimes appear on fiber NICs during
2056                          * periods of heavy traffic. (There should be no
2057                          * effect on copper NICs.)
2058                          */
2059                         status = CSR_READ_4(sc, BGE_MAC_STS);
2060                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2061                             BGE_MACSTAT_MI_COMPLETE))) {
2062                                 sc->bge_link = 0;
2063                                 callout_stop(&sc->bge_stat_timer);
2064                                 bge_tick(sc);
2065                         }
2066                         sc->bge_link = 0;
2067                         callout_stop(&sc->bge_stat_timer);
2068                         bge_tick(sc);
2069                         /* Clear the interrupt */
2070                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2071                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2072                             BGE_MACSTAT_LINK_CHANGED);
2073
2074                         /* Force flush the status block cached by PCI bridge */
2075                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2076                 }
2077         }
2078
2079         if (ifp->if_flags & IFF_RUNNING) {
2080                 /* Check RX return ring producer/consumer */
2081                 bge_rxeof(sc);
2082
2083                 /* Check TX ring producer/consumer */
2084                 bge_txeof(sc);
2085         }
2086
2087         bge_handle_events(sc);
2088
2089         /* Re-enable interrupts. */
2090         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2091
2092         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2093                 (*ifp->if_start)(ifp);
2094 }
2095
2096 static void
2097 bge_tick(void *xsc)
2098 {
2099         struct bge_softc *sc = xsc;
2100         struct ifnet *ifp = &sc->arpcom.ac_if;
2101         struct mii_data *mii = NULL;
2102         struct ifmedia *ifm = NULL;
2103         int s;
2104
2105         s = splimp();
2106
2107         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2108                 bge_stats_update_regs(sc);
2109         else
2110                 bge_stats_update(sc);
2111         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2112         if (sc->bge_link) {
2113                 splx(s);
2114                 return;
2115         }
2116
2117         if (sc->bge_tbi) {
2118                 ifm = &sc->bge_ifmedia;
2119                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2120                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2121                         sc->bge_link++;
2122                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2123                         if_printf(ifp, "gigabit link up\n");
2124                         if (!ifq_is_empty(&ifp->if_snd))
2125                                 (*ifp->if_start)(ifp);
2126                 }
2127                 splx(s);
2128                 return;
2129         }
2130
2131         mii = device_get_softc(sc->bge_miibus);
2132         mii_tick(mii);
2133
2134         if (!sc->bge_link) {
2135                 mii_pollstat(mii);
2136                 if (mii->mii_media_status & IFM_ACTIVE &&
2137                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2138                         sc->bge_link++;
2139                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2140                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2141                                 if_printf(ifp, "gigabit link up\n");
2142                         if (!ifq_is_empty(&ifp->if_snd))
2143                                 (*ifp->if_start)(ifp);
2144                 }
2145         }
2146
2147         splx(s);
2148 }
2149
2150 static void
2151 bge_stats_update_regs(struct bge_softc *sc)
2152 {
2153         struct ifnet *ifp = &sc->arpcom.ac_if;
2154         struct bge_mac_stats_regs stats;
2155         uint32_t *s;
2156         int i;
2157
2158         s = (uint32_t *)&stats;
2159         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2160                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2161                 s++;
2162         }
2163
2164         ifp->if_collisions +=
2165            (stats.dot3StatsSingleCollisionFrames +
2166            stats.dot3StatsMultipleCollisionFrames +
2167            stats.dot3StatsExcessiveCollisions +
2168            stats.dot3StatsLateCollisions) -
2169            ifp->if_collisions;
2170 }
2171
2172 static void
2173 bge_stats_update(struct bge_softc *sc)
2174 {
2175         struct ifnet *ifp = &sc->arpcom.ac_if;
2176         struct bge_stats *stats;
2177
2178         stats = (struct bge_stats *)(sc->bge_vhandle +
2179             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2180
2181         ifp->if_collisions +=
2182            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2183            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2184            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2185            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2186            ifp->if_collisions;
2187
2188 #ifdef notdef
2189         ifp->if_collisions +=
2190            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2191            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2192            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2193            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2194            ifp->if_collisions;
2195 #endif
2196 }
2197
2198 /*
2199  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2200  * pointers to descriptors.
2201  */
2202 static int
2203 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2204 {
2205         struct bge_tx_bd *f = NULL;
2206         struct mbuf *m;
2207         uint32_t frag, cur, cnt = 0;
2208         uint16_t csum_flags = 0;
2209         struct ifvlan *ifv = NULL;
2210
2211         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2212             m_head->m_pkthdr.rcvif != NULL &&
2213             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2214                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2215
2216         m = m_head;
2217         cur = frag = *txidx;
2218
2219         if (m_head->m_pkthdr.csum_flags) {
2220                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2221                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2222                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2223                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2224                 if (m_head->m_flags & M_LASTFRAG)
2225                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2226                 else if (m_head->m_flags & M_FRAG)
2227                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2228         }
2229         /*
2230          * Start packing the mbufs in this chain into
2231          * the fragment pointers. Stop when we run out
2232          * of fragments or hit the end of the mbuf chain.
2233          */
2234         for (m = m_head; m != NULL; m = m->m_next) {
2235                 if (m->m_len != 0) {
2236                         f = &sc->bge_rdata->bge_tx_ring[frag];
2237                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2238                                 break;
2239                         BGE_HOSTADDR(f->bge_addr,
2240                             vtophys(mtod(m, vm_offset_t)));
2241                         f->bge_len = m->m_len;
2242                         f->bge_flags = csum_flags;
2243                         if (ifv != NULL) {
2244                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2245                                 f->bge_vlan_tag = ifv->ifv_tag;
2246                         } else {
2247                                 f->bge_vlan_tag = 0;
2248                         }
2249                         /*
2250                          * Sanity check: avoid coming within 16 descriptors
2251                          * of the end of the ring.
2252                          */
2253                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2254                                 return(ENOBUFS);
2255                         cur = frag;
2256                         BGE_INC(frag, BGE_TX_RING_CNT);
2257                         cnt++;
2258                 }
2259         }
2260
2261         if (m != NULL)
2262                 return(ENOBUFS);
2263
2264         if (frag == sc->bge_tx_saved_considx)
2265                 return(ENOBUFS);
2266
2267         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2268         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2269         sc->bge_txcnt += cnt;
2270
2271         *txidx = frag;
2272
2273         return(0);
2274 }
2275
2276 /*
2277  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2278  * to the mbuf data regions directly in the transmit descriptors.
2279  */
2280 static void
2281 bge_start(struct ifnet *ifp)
2282 {
2283         struct bge_softc *sc;
2284         struct mbuf *m_head = NULL;
2285         uint32_t prodidx = 0;
2286
2287         sc = ifp->if_softc;
2288
2289         if (!sc->bge_link)
2290                 return;
2291
2292         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2293
2294         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2295                 m_head = ifq_poll(&ifp->if_snd);
2296                 if (m_head == NULL)
2297                         break;
2298
2299                 /*
2300                  * XXX
2301                  * safety overkill.  If this is a fragmented packet chain
2302                  * with delayed TCP/UDP checksums, then only encapsulate
2303                  * it if we have enough descriptors to handle the entire
2304                  * chain at once.
2305                  * (paranoia -- may not actually be needed)
2306                  */
2307                 if (m_head->m_flags & M_FIRSTFRAG &&
2308                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2309                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2310                             m_head->m_pkthdr.csum_data + 16) {
2311                                 ifp->if_flags |= IFF_OACTIVE;
2312                                 break;
2313                         }
2314                 }
2315
2316                 /*
2317                  * Pack the data into the transmit ring. If we
2318                  * don't have room, set the OACTIVE flag and wait
2319                  * for the NIC to drain the ring.
2320                  */
2321                 if (bge_encap(sc, m_head, &prodidx)) {
2322                         ifp->if_flags |= IFF_OACTIVE;
2323                         break;
2324                 }
2325                 m_head = ifq_dequeue(&ifp->if_snd);
2326
2327                 BPF_MTAP(ifp, m_head);
2328         }
2329
2330         /* Transmit */
2331         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2332         /* 5700 b2 errata */
2333         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2334                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2335
2336         /*
2337          * Set a timeout in case the chip goes out to lunch.
2338          */
2339         ifp->if_timer = 5;
2340 }
2341
2342 static void
2343 bge_init(void *xsc)
2344 {
2345         struct bge_softc *sc = xsc;
2346         struct ifnet *ifp = &sc->arpcom.ac_if;
2347         uint16_t *m;
2348         int s;
2349
2350         s = splimp();
2351
2352         if (ifp->if_flags & IFF_RUNNING) {
2353                 splx(s);
2354                 return;
2355         }
2356
2357         /* Cancel pending I/O and flush buffers. */
2358         bge_stop(sc);
2359         bge_reset(sc);
2360         bge_chipinit(sc);
2361
2362         /*
2363          * Init the various state machines, ring
2364          * control blocks and firmware.
2365          */
2366         if (bge_blockinit(sc)) {
2367                 if_printf(ifp, "initialization failure\n");
2368                 splx(s);
2369                 return;
2370         }
2371
2372         /* Specify MTU. */
2373         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2374             ETHER_HDR_LEN + ETHER_CRC_LEN);
2375
2376         /* Load our MAC address. */
2377         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2378         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2379         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2380
2381         /* Enable or disable promiscuous mode as needed. */
2382         if (ifp->if_flags & IFF_PROMISC) {
2383                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2384         } else {
2385                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2386         }
2387
2388         /* Program multicast filter. */
2389         bge_setmulti(sc);
2390
2391         /* Init RX ring. */
2392         bge_init_rx_ring_std(sc);
2393
2394         /*
2395          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2396          * memory to insure that the chip has in fact read the first
2397          * entry of the ring.
2398          */
2399         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2400                 uint32_t                v, i;
2401                 for (i = 0; i < 10; i++) {
2402                         DELAY(20);
2403                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2404                         if (v == (MCLBYTES - ETHER_ALIGN))
2405                                 break;
2406                 }
2407                 if (i == 10)
2408                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2409         }
2410
2411         /* Init jumbo RX ring. */
2412         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2413                 bge_init_rx_ring_jumbo(sc);
2414
2415         /* Init our RX return ring index */
2416         sc->bge_rx_saved_considx = 0;
2417
2418         /* Init TX ring. */
2419         bge_init_tx_ring(sc);
2420
2421         /* Turn on transmitter */
2422         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2423
2424         /* Turn on receiver */
2425         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2426
2427         /* Tell firmware we're alive. */
2428         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2429
2430         /* Enable host interrupts. */
2431         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2432         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2433         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2434
2435         bge_ifmedia_upd(ifp);
2436
2437         ifp->if_flags |= IFF_RUNNING;
2438         ifp->if_flags &= ~IFF_OACTIVE;
2439
2440         splx(s);
2441
2442         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2443 }
2444
2445 /*
2446  * Set media options.
2447  */
2448 static int
2449 bge_ifmedia_upd(struct ifnet *ifp)
2450 {
2451         struct bge_softc *sc = ifp->if_softc;
2452         struct ifmedia *ifm = &sc->bge_ifmedia;
2453         struct mii_data *mii;
2454
2455         /* If this is a 1000baseX NIC, enable the TBI port. */
2456         if (sc->bge_tbi) {
2457                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2458                         return(EINVAL);
2459                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2460                 case IFM_AUTO:
2461                         break;
2462                 case IFM_1000_SX:
2463                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2464                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2465                                     BGE_MACMODE_HALF_DUPLEX);
2466                         } else {
2467                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2468                                     BGE_MACMODE_HALF_DUPLEX);
2469                         }
2470                         break;
2471                 default:
2472                         return(EINVAL);
2473                 }
2474                 return(0);
2475         }
2476
2477         mii = device_get_softc(sc->bge_miibus);
2478         sc->bge_link = 0;
2479         if (mii->mii_instance) {
2480                 struct mii_softc *miisc;
2481                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2482                     miisc = LIST_NEXT(miisc, mii_list))
2483                         mii_phy_reset(miisc);
2484         }
2485         mii_mediachg(mii);
2486
2487         return(0);
2488 }
2489
2490 /*
2491  * Report current media status.
2492  */
2493 static void
2494 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2495 {
2496         struct bge_softc *sc = ifp->if_softc;
2497         struct mii_data *mii;
2498
2499         if (sc->bge_tbi) {
2500                 ifmr->ifm_status = IFM_AVALID;
2501                 ifmr->ifm_active = IFM_ETHER;
2502                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2503                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2504                         ifmr->ifm_status |= IFM_ACTIVE;
2505                 ifmr->ifm_active |= IFM_1000_SX;
2506                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2507                         ifmr->ifm_active |= IFM_HDX;
2508                 else
2509                         ifmr->ifm_active |= IFM_FDX;
2510                 return;
2511         }
2512
2513         mii = device_get_softc(sc->bge_miibus);
2514         mii_pollstat(mii);
2515         ifmr->ifm_active = mii->mii_media_active;
2516         ifmr->ifm_status = mii->mii_media_status;
2517 }
2518
2519 static int
2520 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2521 {
2522         struct bge_softc *sc = ifp->if_softc;
2523         struct ifreq *ifr = (struct ifreq *) data;
2524         int s, mask, error = 0;
2525         struct mii_data *mii;
2526
2527         s = splimp();
2528
2529         switch(command) {
2530         case SIOCSIFADDR:
2531         case SIOCGIFADDR:
2532                 error = ether_ioctl(ifp, command, data);
2533                 break;
2534         case SIOCSIFMTU:
2535                 /* Disallow jumbo frames on 5705. */
2536                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2537                     ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2538                         error = EINVAL;
2539                 else {
2540                         ifp->if_mtu = ifr->ifr_mtu;
2541                         ifp->if_flags &= ~IFF_RUNNING;
2542                         bge_init(sc);
2543                 }
2544                 break;
2545         case SIOCSIFFLAGS:
2546                 if (ifp->if_flags & IFF_UP) {
2547                         /*
2548                          * If only the state of the PROMISC flag changed,
2549                          * then just use the 'set promisc mode' command
2550                          * instead of reinitializing the entire NIC. Doing
2551                          * a full re-init means reloading the firmware and
2552                          * waiting for it to start up, which may take a
2553                          * second or two.
2554                          */
2555                         if (ifp->if_flags & IFF_RUNNING &&
2556                             ifp->if_flags & IFF_PROMISC &&
2557                             !(sc->bge_if_flags & IFF_PROMISC)) {
2558                                 BGE_SETBIT(sc, BGE_RX_MODE,
2559                                     BGE_RXMODE_RX_PROMISC);
2560                         } else if (ifp->if_flags & IFF_RUNNING &&
2561                             !(ifp->if_flags & IFF_PROMISC) &&
2562                             sc->bge_if_flags & IFF_PROMISC) {
2563                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2564                                     BGE_RXMODE_RX_PROMISC);
2565                         } else
2566                                 bge_init(sc);
2567                 } else {
2568                         if (ifp->if_flags & IFF_RUNNING) {
2569                                 bge_stop(sc);
2570                         }
2571                 }
2572                 sc->bge_if_flags = ifp->if_flags;
2573                 error = 0;
2574                 break;
2575         case SIOCADDMULTI:
2576         case SIOCDELMULTI:
2577                 if (ifp->if_flags & IFF_RUNNING) {
2578                         bge_setmulti(sc);
2579                         error = 0;
2580                 }
2581                 break;
2582         case SIOCSIFMEDIA:
2583         case SIOCGIFMEDIA:
2584                 if (sc->bge_tbi) {
2585                         error = ifmedia_ioctl(ifp, ifr,
2586                             &sc->bge_ifmedia, command);
2587                 } else {
2588                         mii = device_get_softc(sc->bge_miibus);
2589                         error = ifmedia_ioctl(ifp, ifr,
2590                             &mii->mii_media, command);
2591                 }
2592                 break;
2593         case SIOCSIFCAP:
2594                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2595                 if (mask & IFCAP_HWCSUM) {
2596                         if (IFCAP_HWCSUM & ifp->if_capenable)
2597                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2598                         else
2599                                 ifp->if_capenable |= IFCAP_HWCSUM;
2600                 }
2601                 error = 0;
2602                 break;
2603         default:
2604                 error = EINVAL;
2605                 break;
2606         }
2607
2608         splx(s);
2609
2610         return(error);
2611 }
2612
2613 static void
2614 bge_watchdog(struct ifnet *ifp)
2615 {
2616         struct bge_softc *sc = ifp->if_softc;
2617
2618         if_printf(ifp, "watchdog timeout -- resetting\n");
2619
2620         ifp->if_flags &= ~IFF_RUNNING;
2621         bge_init(sc);
2622
2623         ifp->if_oerrors++;
2624 }
2625
2626 /*
2627  * Stop the adapter and free any mbufs allocated to the
2628  * RX and TX lists.
2629  */
2630 static void
2631 bge_stop(struct bge_softc *sc)
2632 {
2633         struct ifnet *ifp = &sc->arpcom.ac_if;
2634         struct ifmedia_entry *ifm;
2635         struct mii_data *mii = NULL;
2636         int mtmp, itmp;
2637
2638         if (!sc->bge_tbi)
2639                 mii = device_get_softc(sc->bge_miibus);
2640
2641         callout_stop(&sc->bge_stat_timer);
2642
2643         /*
2644          * Disable all of the receiver blocks
2645          */
2646         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2647         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2648         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2649         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2650                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2651         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2652         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2653         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2654
2655         /*
2656          * Disable all of the transmit blocks
2657          */
2658         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2659         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2660         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2661         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2662         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2663         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2664                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2665         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2666
2667         /*
2668          * Shut down all of the memory managers and related
2669          * state machines.
2670          */
2671         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2672         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2673         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2674                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2675         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2676         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2677         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2678                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2679                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2680         }
2681
2682         /* Disable host interrupts. */
2683         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2684         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2685
2686         /*
2687          * Tell firmware we're shutting down.
2688          */
2689         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2690
2691         /* Free the RX lists. */
2692         bge_free_rx_ring_std(sc);
2693
2694         /* Free jumbo RX list. */
2695         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2696                 bge_free_rx_ring_jumbo(sc);
2697
2698         /* Free TX buffers. */
2699         bge_free_tx_ring(sc);
2700
2701         /*
2702          * Isolate/power down the PHY, but leave the media selection
2703          * unchanged so that things will be put back to normal when
2704          * we bring the interface back up.
2705          */
2706         if (!sc->bge_tbi) {
2707                 itmp = ifp->if_flags;
2708                 ifp->if_flags |= IFF_UP;
2709                 ifm = mii->mii_media.ifm_cur;
2710                 mtmp = ifm->ifm_media;
2711                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2712                 mii_mediachg(mii);
2713                 ifm->ifm_media = mtmp;
2714                 ifp->if_flags = itmp;
2715         }
2716
2717         sc->bge_link = 0;
2718
2719         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2720
2721         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2722 }
2723
2724 /*
2725  * Stop all chip I/O so that the kernel's probe routines don't
2726  * get confused by errant DMAs when rebooting.
2727  */
2728 static void
2729 bge_shutdown(device_t dev)
2730 {
2731         struct bge_softc *sc = device_get_softc(dev);
2732
2733         bge_stop(sc);
2734         bge_reset(sc);
2735 }