2 BFD maintains relocations in much the same way it maintains
3 symbols: they are left alone until required, then read in
4 en-masse and translated into an internal form. A common
5 routine @code{bfd_perform_relocation} acts upon the
6 canonical form to do the fixup.
8 Relocations are maintained on a per section basis,
9 while symbols are maintained on a per BFD basis.
11 All that a back end has to do to fit the BFD interface is to create
12 a @code{struct reloc_cache_entry} for each relocation
13 in a particular section, and fill in the right bits of the structures.
21 @node typedef arelent, howto manager, Relocations, Relocations
22 @subsection typedef arelent
23 This is the structure of a relocation entry:
28 typedef enum bfd_reloc_status
30 /* No errors detected. */
33 /* The relocation was performed, but there was an overflow. */
36 /* The address to relocate was not within the section supplied. */
39 /* Used by special functions. */
42 /* Unsupported relocation size requested. */
43 bfd_reloc_notsupported,
48 /* The symbol to relocate against was undefined. */
51 /* The relocation was performed, but may not be ok - presently
52 generated only when linking i960 coff files with i960 b.out
53 symbols. If this type is returned, the error_message argument
54 to bfd_perform_relocation will be set. */
57 bfd_reloc_status_type;
60 typedef struct reloc_cache_entry
62 /* A pointer into the canonical table of pointers. */
63 struct symbol_cache_entry **sym_ptr_ptr;
65 /* offset in section. */
66 bfd_size_type address;
68 /* addend for relocation value. */
71 /* Pointer to how to perform the required relocation. */
72 reloc_howto_type *howto;
78 @strong{Description}@*
79 Here is a description of each of the fields within an @code{arelent}:
86 The symbol table pointer points to a pointer to the symbol
87 associated with the relocation request. It is
88 the pointer into the table returned by the back end's
89 @code{get_symtab} action. @xref{Symbols}. The symbol is referenced
90 through a pointer to a pointer so that tools like the linker
91 can fix up all the symbols of the same name by modifying only
92 one pointer. The relocation routine looks in the symbol and
93 uses the base of the section the symbol is attached to and the
94 value of the symbol as the initial relocation offset. If the
95 symbol pointer is zero, then the section provided is looked up.
102 The @code{address} field gives the offset in bytes from the base of
103 the section data which owns the relocation record to the first
104 byte of relocatable information. The actual data relocated
105 will be relative to this point; for example, a relocation
106 type which modifies the bottom two bytes of a four byte word
107 would not touch the first byte pointed to in a big endian
115 The @code{addend} is a value provided by the back end to be added (!)
116 to the relocation offset. Its interpretation is dependent upon
117 the howto. For example, on the 68k the code:
123 return foo[0x12345678];
127 Could be compiled into:
137 This could create a reloc pointing to @code{foo}, but leave the
138 offset in the data, something like:
141 RELOCATION RECORDS FOR [.text]:
145 00000000 4e56 fffc ; linkw fp,#-4
146 00000004 1039 1234 5678 ; moveb @@#12345678,d0
147 0000000a 49c0 ; extbl d0
148 0000000c 4e5e ; unlk fp
152 Using coff and an 88k, some instructions don't have enough
153 space in them to represent the full address range, and
154 pointers have to be loaded in two parts. So you'd get something like:
157 or.u r13,r0,hi16(_foo+0x12345678)
158 ld.b r2,r13,lo16(_foo+0x12345678)
162 This should create two relocs, both pointing to @code{_foo}, and with
163 0x12340000 in their addend field. The data would consist of:
166 RELOCATION RECORDS FOR [.text]:
168 00000002 HVRT16 _foo+0x12340000
169 00000006 LVRT16 _foo+0x12340000
171 00000000 5da05678 ; or.u r13,r0,0x5678
172 00000004 1c4d5678 ; ld.b r2,r13,0x5678
173 00000008 f400c001 ; jmp r1
176 The relocation routine digs out the value from the data, adds
177 it to the addend to get the original offset, and then adds the
178 value of @code{_foo}. Note that all 32 bits have to be kept around
179 somewhere, to cope with carry from bit 15 to bit 16.
181 One further example is the sparc and the a.out format. The
182 sparc has a similar problem to the 88k, in that some
183 instructions don't have room for an entire offset, but on the
184 sparc the parts are created in odd sized lumps. The designers of
185 the a.out format chose to not use the data within the section
186 for storing part of the offset; all the offset is kept within
187 the reloc. Anything in the data should be ignored.
191 sethi %hi(_foo+0x12345678),%g2
192 ldsb [%g2+%lo(_foo+0x12345678)],%i0
197 Both relocs contain a pointer to @code{foo}, and the offsets
201 RELOCATION RECORDS FOR [.text]:
203 00000004 HI22 _foo+0x12345678
204 00000008 LO10 _foo+0x12345678
206 00000000 9de3bf90 ; save %sp,-112,%sp
207 00000004 05000000 ; sethi %hi(_foo+0),%g2
208 00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
209 0000000c 81c7e008 ; ret
210 00000010 81e80000 ; restore
218 The @code{howto} field can be imagined as a
219 relocation instruction. It is a pointer to a structure which
220 contains information on what to do with all of the other
221 information in the reloc record and data section. A back end
222 would normally have a relocation instruction set and turn
223 relocations into pointers to the correct structure on input -
224 but it would be possible to create each howto field on demand.
226 @subsubsection @code{enum complain_overflow}
227 Indicates what sort of overflow checking should be done when
228 performing a relocation.
233 enum complain_overflow
235 /* Do not complain on overflow. */
236 complain_overflow_dont,
238 /* Complain if the bitfield overflows, whether it is considered
239 as signed or unsigned. */
240 complain_overflow_bitfield,
242 /* Complain if the value overflows when considered as signed
244 complain_overflow_signed,
246 /* Complain if the value overflows when considered as an
248 complain_overflow_unsigned
251 @subsubsection @code{reloc_howto_type}
252 The @code{reloc_howto_type} is a structure which contains all the
253 information that libbfd needs to know to tie up a back end's data.
257 struct symbol_cache_entry; /* Forward declaration. */
259 struct reloc_howto_struct
261 /* The type field has mainly a documentary use - the back end can
262 do what it wants with it, though normally the back end's
263 external idea of what a reloc number is stored
264 in this field. For example, a PC relative word relocation
265 in a coff environment has the type 023 - because that's
266 what the outside world calls a R_PCRWORD reloc. */
269 /* The value the final relocation is shifted right by. This drops
270 unwanted data from the relocation. */
271 unsigned int rightshift;
273 /* The size of the item to be relocated. This is *not* a
274 power-of-two measure. To get the number of bytes operated
275 on by a type of relocation, use bfd_get_reloc_size. */
278 /* The number of bits in the item to be relocated. This is used
279 when doing overflow checking. */
280 unsigned int bitsize;
282 /* Notes that the relocation is relative to the location in the
283 data section of the addend. The relocation function will
284 subtract from the relocation value the address of the location
288 /* The bit position of the reloc value in the destination.
289 The relocated value is left shifted by this amount. */
292 /* What type of overflow error should be checked for when
294 enum complain_overflow complain_on_overflow;
296 /* If this field is non null, then the supplied function is
297 called rather than the normal function. This allows really
298 strange relocation methods to be accomodated (e.g., i960 callj
300 bfd_reloc_status_type (*special_function)
301 PARAMS ((bfd *, arelent *, struct symbol_cache_entry *, PTR, asection *,
304 /* The textual name of the relocation type. */
307 /* Some formats record a relocation addend in the section contents
308 rather than with the relocation. For ELF formats this is the
309 distinction between USE_REL and USE_RELA (though the code checks
310 for USE_REL == 1/0). The value of this field is TRUE if the
311 addend is recorded with the section contents; when performing a
312 partial link (ld -r) the section contents (the data) will be
313 modified. The value of this field is FALSE if addends are
314 recorded with the relocation (in arelent.addend); when performing
315 a partial link the relocation will be modified.
316 All relocations for all ELF USE_RELA targets should set this field
317 to FALSE (values of TRUE should be looked on with suspicion).
318 However, the converse is not true: not all relocations of all ELF
319 USE_REL targets set this field to TRUE. Why this is so is peculiar
320 to each particular target. For relocs that aren't used in partial
321 links (e.g. GOT stuff) it doesn't matter what this is set to. */
322 boolean partial_inplace;
324 /* The src_mask selects which parts of the read in data
325 are to be used in the relocation sum. E.g., if this was an 8 bit
326 byte of data which we read and relocated, this would be
327 0x000000ff. When we have relocs which have an addend, such as
328 sun4 extended relocs, the value in the offset part of a
329 relocating field is garbage so we never use it. In this case
330 the mask would be 0x00000000. */
333 /* The dst_mask selects which parts of the instruction are replaced
334 into the instruction. In most cases src_mask == dst_mask,
335 except in the above special case, where dst_mask would be
336 0x000000ff, and src_mask would be 0x00000000. */
339 /* When some formats create PC relative instructions, they leave
340 the value of the pc of the place being relocated in the offset
341 slot of the instruction, so that a PC relative relocation can
342 be made just by adding in an ordinary offset (e.g., sun3 a.out).
343 Some formats leave the displacement part of an instruction
344 empty (e.g., m88k bcs); this flag signals the fact. */
345 boolean pcrel_offset;
349 @findex The HOWTO Macro
350 @subsubsection @code{The HOWTO Macro}
351 @strong{Description}@*
352 The HOWTO define is horrible and will go away.
354 #define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
355 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
358 @strong{Description}@*
359 And will be replaced with the totally magic way. But for the
360 moment, we are compatible, so do it this way.
362 #define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
363 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
364 NAME, false, 0, 0, IN)
368 @strong{Description}@*
369 This is used to fill in an empty howto entry in an array.
371 #define EMPTY_HOWTO(C) \
372 HOWTO ((C), 0, 0, 0, false, 0, complain_overflow_dont, NULL, \
373 NULL, false, 0, 0, false)
377 @strong{Description}@*
378 Helper routine to turn a symbol into a relocation value.
380 #define HOWTO_PREPARE(relocation, symbol) \
382 if (symbol != (asymbol *) NULL) \
384 if (bfd_is_com_section (symbol->section)) \
390 relocation = symbol->value; \
397 @findex bfd_get_reloc_size
398 @subsubsection @code{bfd_get_reloc_size}
401 unsigned int bfd_get_reloc_size (reloc_howto_type *);
403 @strong{Description}@*
404 For a reloc_howto_type that operates on a fixed number of bytes,
405 this returns the number of bytes operated on.
407 @findex arelent_chain
408 @subsubsection @code{arelent_chain}
409 @strong{Description}@*
410 How relocs are tied together in an @code{asection}:
412 typedef struct relent_chain
415 struct relent_chain *next;
421 @findex bfd_check_overflow
422 @subsubsection @code{bfd_check_overflow}
425 bfd_reloc_status_type
427 (enum complain_overflow how,
428 unsigned int bitsize,
429 unsigned int rightshift,
430 unsigned int addrsize,
433 @strong{Description}@*
434 Perform overflow checking on @var{relocation} which has
435 @var{bitsize} significant bits and will be shifted right by
436 @var{rightshift} bits, on a machine with addresses containing
437 @var{addrsize} significant bits. The result is either of
438 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
440 @findex bfd_perform_relocation
441 @subsubsection @code{bfd_perform_relocation}
444 bfd_reloc_status_type
445 bfd_perform_relocation
447 arelent *reloc_entry,
449 asection *input_section,
451 char **error_message);
453 @strong{Description}@*
454 If @var{output_bfd} is supplied to this function, the
455 generated image will be relocatable; the relocations are
456 copied to the output file after they have been changed to
457 reflect the new state of the world. There are two ways of
458 reflecting the results of partial linkage in an output file:
459 by modifying the output data in place, and by modifying the
460 relocation record. Some native formats (e.g., basic a.out and
461 basic coff) have no way of specifying an addend in the
462 relocation type, so the addend has to go in the output data.
463 This is no big deal since in these formats the output data
464 slot will always be big enough for the addend. Complex reloc
465 types with addends were invented to solve just this problem.
466 The @var{error_message} argument is set to an error message if
467 this return @code{bfd_reloc_dangerous}.
469 @findex bfd_install_relocation
470 @subsubsection @code{bfd_install_relocation}
473 bfd_reloc_status_type
474 bfd_install_relocation
476 arelent *reloc_entry,
477 PTR data, bfd_vma data_start,
478 asection *input_section,
479 char **error_message);
481 @strong{Description}@*
482 This looks remarkably like @code{bfd_perform_relocation}, except it
483 does not expect that the section contents have been filled in.
484 I.e., it's suitable for use when creating, rather than applying
487 For now, this function should be considered reserved for the
491 @node howto manager, , typedef arelent, Relocations
492 @section The howto manager
493 When an application wants to create a relocation, but doesn't
494 know what the target machine might call it, it can find out by
495 using this bit of code.
497 @findex bfd_reloc_code_type
498 @subsubsection @code{bfd_reloc_code_type}
499 @strong{Description}@*
500 The insides of a reloc code. The idea is that, eventually, there
501 will be one enumerator for every type of relocation we ever do.
502 Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
503 return a howto pointer.
505 This does mean that the application must determine the correct
506 enumerator value; you can't get a howto pointer from a random set
509 Here are the possible values for @code{enum bfd_reloc_code_real}:
511 @deffn {} BFD_RELOC_64
512 @deffnx {} BFD_RELOC_32
513 @deffnx {} BFD_RELOC_26
514 @deffnx {} BFD_RELOC_24
515 @deffnx {} BFD_RELOC_16
516 @deffnx {} BFD_RELOC_14
517 @deffnx {} BFD_RELOC_8
518 Basic absolute relocations of N bits.
520 @deffn {} BFD_RELOC_64_PCREL
521 @deffnx {} BFD_RELOC_32_PCREL
522 @deffnx {} BFD_RELOC_24_PCREL
523 @deffnx {} BFD_RELOC_16_PCREL
524 @deffnx {} BFD_RELOC_12_PCREL
525 @deffnx {} BFD_RELOC_8_PCREL
526 PC-relative relocations. Sometimes these are relative to the address
527 of the relocation itself; sometimes they are relative to the start of
528 the section containing the relocation. It depends on the specific target.
530 The 24-bit relocation is used in some Intel 960 configurations.
532 @deffn {} BFD_RELOC_32_GOT_PCREL
533 @deffnx {} BFD_RELOC_16_GOT_PCREL
534 @deffnx {} BFD_RELOC_8_GOT_PCREL
535 @deffnx {} BFD_RELOC_32_GOTOFF
536 @deffnx {} BFD_RELOC_16_GOTOFF
537 @deffnx {} BFD_RELOC_LO16_GOTOFF
538 @deffnx {} BFD_RELOC_HI16_GOTOFF
539 @deffnx {} BFD_RELOC_HI16_S_GOTOFF
540 @deffnx {} BFD_RELOC_8_GOTOFF
541 @deffnx {} BFD_RELOC_64_PLT_PCREL
542 @deffnx {} BFD_RELOC_32_PLT_PCREL
543 @deffnx {} BFD_RELOC_24_PLT_PCREL
544 @deffnx {} BFD_RELOC_16_PLT_PCREL
545 @deffnx {} BFD_RELOC_8_PLT_PCREL
546 @deffnx {} BFD_RELOC_64_PLTOFF
547 @deffnx {} BFD_RELOC_32_PLTOFF
548 @deffnx {} BFD_RELOC_16_PLTOFF
549 @deffnx {} BFD_RELOC_LO16_PLTOFF
550 @deffnx {} BFD_RELOC_HI16_PLTOFF
551 @deffnx {} BFD_RELOC_HI16_S_PLTOFF
552 @deffnx {} BFD_RELOC_8_PLTOFF
555 @deffn {} BFD_RELOC_68K_GLOB_DAT
556 @deffnx {} BFD_RELOC_68K_JMP_SLOT
557 @deffnx {} BFD_RELOC_68K_RELATIVE
558 Relocations used by 68K ELF.
560 @deffn {} BFD_RELOC_32_BASEREL
561 @deffnx {} BFD_RELOC_16_BASEREL
562 @deffnx {} BFD_RELOC_LO16_BASEREL
563 @deffnx {} BFD_RELOC_HI16_BASEREL
564 @deffnx {} BFD_RELOC_HI16_S_BASEREL
565 @deffnx {} BFD_RELOC_8_BASEREL
566 @deffnx {} BFD_RELOC_RVA
567 Linkage-table relative.
569 @deffn {} BFD_RELOC_8_FFnn
570 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
572 @deffn {} BFD_RELOC_32_PCREL_S2
573 @deffnx {} BFD_RELOC_16_PCREL_S2
574 @deffnx {} BFD_RELOC_23_PCREL_S2
575 These PC-relative relocations are stored as word displacements --
576 i.e., byte displacements shifted right two bits. The 30-bit word
577 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
578 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
579 signed 16-bit displacement is used on the MIPS, and the 23-bit
580 displacement is used on the Alpha.
582 @deffn {} BFD_RELOC_HI22
583 @deffnx {} BFD_RELOC_LO10
584 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
585 the target word. These are used on the SPARC.
587 @deffn {} BFD_RELOC_GPREL16
588 @deffnx {} BFD_RELOC_GPREL32
589 For systems that allocate a Global Pointer register, these are
590 displacements off that register. These relocation types are
591 handled specially, because the value the register will have is
592 decided relatively late.
594 @deffn {} BFD_RELOC_I960_CALLJ
595 Reloc types used for i960/b.out.
597 @deffn {} BFD_RELOC_NONE
598 @deffnx {} BFD_RELOC_SPARC_WDISP22
599 @deffnx {} BFD_RELOC_SPARC22
600 @deffnx {} BFD_RELOC_SPARC13
601 @deffnx {} BFD_RELOC_SPARC_GOT10
602 @deffnx {} BFD_RELOC_SPARC_GOT13
603 @deffnx {} BFD_RELOC_SPARC_GOT22
604 @deffnx {} BFD_RELOC_SPARC_PC10
605 @deffnx {} BFD_RELOC_SPARC_PC22
606 @deffnx {} BFD_RELOC_SPARC_WPLT30
607 @deffnx {} BFD_RELOC_SPARC_COPY
608 @deffnx {} BFD_RELOC_SPARC_GLOB_DAT
609 @deffnx {} BFD_RELOC_SPARC_JMP_SLOT
610 @deffnx {} BFD_RELOC_SPARC_RELATIVE
611 @deffnx {} BFD_RELOC_SPARC_UA16
612 @deffnx {} BFD_RELOC_SPARC_UA32
613 @deffnx {} BFD_RELOC_SPARC_UA64
614 SPARC ELF relocations. There is probably some overlap with other
615 relocation types already defined.
617 @deffn {} BFD_RELOC_SPARC_BASE13
618 @deffnx {} BFD_RELOC_SPARC_BASE22
619 I think these are specific to SPARC a.out (e.g., Sun 4).
621 @deffn {} BFD_RELOC_SPARC_64
622 @deffnx {} BFD_RELOC_SPARC_10
623 @deffnx {} BFD_RELOC_SPARC_11
624 @deffnx {} BFD_RELOC_SPARC_OLO10
625 @deffnx {} BFD_RELOC_SPARC_HH22
626 @deffnx {} BFD_RELOC_SPARC_HM10
627 @deffnx {} BFD_RELOC_SPARC_LM22
628 @deffnx {} BFD_RELOC_SPARC_PC_HH22
629 @deffnx {} BFD_RELOC_SPARC_PC_HM10
630 @deffnx {} BFD_RELOC_SPARC_PC_LM22
631 @deffnx {} BFD_RELOC_SPARC_WDISP16
632 @deffnx {} BFD_RELOC_SPARC_WDISP19
633 @deffnx {} BFD_RELOC_SPARC_7
634 @deffnx {} BFD_RELOC_SPARC_6
635 @deffnx {} BFD_RELOC_SPARC_5
636 @deffnx {} BFD_RELOC_SPARC_DISP64
637 @deffnx {} BFD_RELOC_SPARC_PLT32
638 @deffnx {} BFD_RELOC_SPARC_PLT64
639 @deffnx {} BFD_RELOC_SPARC_HIX22
640 @deffnx {} BFD_RELOC_SPARC_LOX10
641 @deffnx {} BFD_RELOC_SPARC_H44
642 @deffnx {} BFD_RELOC_SPARC_M44
643 @deffnx {} BFD_RELOC_SPARC_L44
644 @deffnx {} BFD_RELOC_SPARC_REGISTER
647 @deffn {} BFD_RELOC_SPARC_REV32
648 SPARC little endian relocation
650 @deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
651 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
652 "addend" in some special way.
653 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
654 writing; when reading, it will be the absolute section symbol. The
655 addend is the displacement in bytes of the "lda" instruction from
656 the "ldah" instruction (which is at the address of this reloc).
658 @deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
659 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
660 with GPDISP_HI16 relocs. The addend is ignored when writing the
661 relocations out, and is filled in with the file's GP value on
662 reading, for convenience.
664 @deffn {} BFD_RELOC_ALPHA_GPDISP
665 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
666 relocation except that there is no accompanying GPDISP_LO16
669 @deffn {} BFD_RELOC_ALPHA_LITERAL
670 @deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
671 @deffnx {} BFD_RELOC_ALPHA_LITUSE
672 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
673 the assembler turns it into a LDQ instruction to load the address of
674 the symbol, and then fills in a register in the real instruction.
676 The LITERAL reloc, at the LDQ instruction, refers to the .lita
677 section symbol. The addend is ignored when writing, but is filled
678 in with the file's GP value on reading, for convenience, as with the
681 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
682 It should refer to the symbol to be referenced, as with 16_GOTOFF,
683 but it generates output not based on the position within the .got
684 section, but relative to the GP value chosen for the file during the
687 The LITUSE reloc, on the instruction using the loaded address, gives
688 information to the linker that it might be able to use to optimize
689 away some literal section references. The symbol is ignored (read
690 as the absolute section symbol), and the "addend" indicates the type
691 of instruction using the register:
692 1 - "memory" fmt insn
693 2 - byte-manipulation (byte offset reg)
694 3 - jsr (target of branch)
696 @deffn {} BFD_RELOC_ALPHA_HINT
697 The HINT relocation indicates a value that should be filled into the
698 "hint" field of a jmp/jsr/ret instruction, for possible branch-
699 prediction logic which may be provided on some processors.
701 @deffn {} BFD_RELOC_ALPHA_LINKAGE
702 The LINKAGE relocation outputs a linkage pair in the object file,
703 which is filled by the linker.
705 @deffn {} BFD_RELOC_ALPHA_CODEADDR
706 The CODEADDR relocation outputs a STO_CA in the object file,
707 which is filled by the linker.
709 @deffn {} BFD_RELOC_ALPHA_GPREL_HI16
710 @deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
711 The GPREL_HI/LO relocations together form a 32-bit offset from the
714 @deffn {} BFD_RELOC_ALPHA_BRSGP
715 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
716 share a common GP, and the target address is adjusted for
717 STO_ALPHA_STD_GPLOAD.
719 @deffn {} BFD_RELOC_MIPS_JMP
720 Bits 27..2 of the relocation address shifted right 2 bits;
721 simple reloc otherwise.
723 @deffn {} BFD_RELOC_MIPS16_JMP
724 The MIPS16 jump instruction.
726 @deffn {} BFD_RELOC_MIPS16_GPREL
727 MIPS16 GP relative reloc.
729 @deffn {} BFD_RELOC_HI16
730 High 16 bits of 32-bit value; simple reloc.
732 @deffn {} BFD_RELOC_HI16_S
733 High 16 bits of 32-bit value but the low 16 bits will be sign
734 extended and added to form the final result. If the low 16
735 bits form a negative number, we need to add one to the high value
736 to compensate for the borrow when the low bits are added.
738 @deffn {} BFD_RELOC_LO16
741 @deffn {} BFD_RELOC_PCREL_HI16_S
742 Like BFD_RELOC_HI16_S, but PC relative.
744 @deffn {} BFD_RELOC_PCREL_LO16
745 Like BFD_RELOC_LO16, but PC relative.
747 @deffn {} BFD_RELOC_MIPS_LITERAL
748 Relocation against a MIPS literal section.
750 @deffn {} BFD_RELOC_MIPS_GOT16
751 @deffnx {} BFD_RELOC_MIPS_CALL16
752 @deffnx {} BFD_RELOC_MIPS_GOT_HI16
753 @deffnx {} BFD_RELOC_MIPS_GOT_LO16
754 @deffnx {} BFD_RELOC_MIPS_CALL_HI16
755 @deffnx {} BFD_RELOC_MIPS_CALL_LO16
756 @deffnx {} BFD_RELOC_MIPS_SUB
757 @deffnx {} BFD_RELOC_MIPS_GOT_PAGE
758 @deffnx {} BFD_RELOC_MIPS_GOT_OFST
759 @deffnx {} BFD_RELOC_MIPS_GOT_DISP
760 @deffnx {} BFD_RELOC_MIPS_SHIFT5
761 @deffnx {} BFD_RELOC_MIPS_SHIFT6
762 @deffnx {} BFD_RELOC_MIPS_INSERT_A
763 @deffnx {} BFD_RELOC_MIPS_INSERT_B
764 @deffnx {} BFD_RELOC_MIPS_DELETE
765 @deffnx {} BFD_RELOC_MIPS_HIGHEST
766 @deffnx {} BFD_RELOC_MIPS_HIGHER
767 @deffnx {} BFD_RELOC_MIPS_SCN_DISP
768 @deffnx {} BFD_RELOC_MIPS_REL16
769 @deffnx {} BFD_RELOC_MIPS_RELGOT
770 @deffnx {} BFD_RELOC_MIPS_JALR
771 MIPS ELF relocations.
773 @deffn {} BFD_RELOC_386_GOT32
774 @deffnx {} BFD_RELOC_386_PLT32
775 @deffnx {} BFD_RELOC_386_COPY
776 @deffnx {} BFD_RELOC_386_GLOB_DAT
777 @deffnx {} BFD_RELOC_386_JUMP_SLOT
778 @deffnx {} BFD_RELOC_386_RELATIVE
779 @deffnx {} BFD_RELOC_386_GOTOFF
780 @deffnx {} BFD_RELOC_386_GOTPC
783 @deffn {} BFD_RELOC_X86_64_GOT32
784 @deffnx {} BFD_RELOC_X86_64_PLT32
785 @deffnx {} BFD_RELOC_X86_64_COPY
786 @deffnx {} BFD_RELOC_X86_64_GLOB_DAT
787 @deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
788 @deffnx {} BFD_RELOC_X86_64_RELATIVE
789 @deffnx {} BFD_RELOC_X86_64_GOTPCREL
790 @deffnx {} BFD_RELOC_X86_64_32S
791 x86-64/elf relocations
793 @deffn {} BFD_RELOC_NS32K_IMM_8
794 @deffnx {} BFD_RELOC_NS32K_IMM_16
795 @deffnx {} BFD_RELOC_NS32K_IMM_32
796 @deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
797 @deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
798 @deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
799 @deffnx {} BFD_RELOC_NS32K_DISP_8
800 @deffnx {} BFD_RELOC_NS32K_DISP_16
801 @deffnx {} BFD_RELOC_NS32K_DISP_32
802 @deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
803 @deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
804 @deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
807 @deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
808 @deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
811 @deffn {} BFD_RELOC_PJ_CODE_HI16
812 @deffnx {} BFD_RELOC_PJ_CODE_LO16
813 @deffnx {} BFD_RELOC_PJ_CODE_DIR16
814 @deffnx {} BFD_RELOC_PJ_CODE_DIR32
815 @deffnx {} BFD_RELOC_PJ_CODE_REL16
816 @deffnx {} BFD_RELOC_PJ_CODE_REL32
817 Picojava relocs. Not all of these appear in object files.
819 @deffn {} BFD_RELOC_PPC_B26
820 @deffnx {} BFD_RELOC_PPC_BA26
821 @deffnx {} BFD_RELOC_PPC_TOC16
822 @deffnx {} BFD_RELOC_PPC_B16
823 @deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
824 @deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
825 @deffnx {} BFD_RELOC_PPC_BA16
826 @deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
827 @deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
828 @deffnx {} BFD_RELOC_PPC_COPY
829 @deffnx {} BFD_RELOC_PPC_GLOB_DAT
830 @deffnx {} BFD_RELOC_PPC_JMP_SLOT
831 @deffnx {} BFD_RELOC_PPC_RELATIVE
832 @deffnx {} BFD_RELOC_PPC_LOCAL24PC
833 @deffnx {} BFD_RELOC_PPC_EMB_NADDR32
834 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16
835 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
836 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
837 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
838 @deffnx {} BFD_RELOC_PPC_EMB_SDAI16
839 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
840 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
841 @deffnx {} BFD_RELOC_PPC_EMB_SDA21
842 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF
843 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
844 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
845 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
846 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
847 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
848 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA
849 @deffnx {} BFD_RELOC_PPC64_HIGHER
850 @deffnx {} BFD_RELOC_PPC64_HIGHER_S
851 @deffnx {} BFD_RELOC_PPC64_HIGHEST
852 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S
853 @deffnx {} BFD_RELOC_PPC64_TOC16_LO
854 @deffnx {} BFD_RELOC_PPC64_TOC16_HI
855 @deffnx {} BFD_RELOC_PPC64_TOC16_HA
856 @deffnx {} BFD_RELOC_PPC64_TOC
857 @deffnx {} BFD_RELOC_PPC64_PLTGOT16
858 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
859 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
860 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
861 @deffnx {} BFD_RELOC_PPC64_ADDR16_DS
862 @deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
863 @deffnx {} BFD_RELOC_PPC64_GOT16_DS
864 @deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
865 @deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
866 @deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
867 @deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
868 @deffnx {} BFD_RELOC_PPC64_TOC16_DS
869 @deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
870 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
871 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
872 Power(rs6000) and PowerPC relocations.
874 @deffn {} BFD_RELOC_I370_D12
875 IBM 370/390 relocations
877 @deffn {} BFD_RELOC_CTOR
878 The type of reloc used to build a contructor table - at the moment
879 probably a 32 bit wide absolute relocation, but the target can choose.
880 It generally does map to one of the other relocation types.
882 @deffn {} BFD_RELOC_ARM_PCREL_BRANCH
883 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
884 not stored in the instruction.
886 @deffn {} BFD_RELOC_ARM_PCREL_BLX
887 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
888 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
889 field in the instruction.
891 @deffn {} BFD_RELOC_THUMB_PCREL_BLX
892 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
893 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
894 field in the instruction.
896 @deffn {} BFD_RELOC_ARM_IMMEDIATE
897 @deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
898 @deffnx {} BFD_RELOC_ARM_OFFSET_IMM
899 @deffnx {} BFD_RELOC_ARM_SHIFT_IMM
900 @deffnx {} BFD_RELOC_ARM_SWI
901 @deffnx {} BFD_RELOC_ARM_MULTI
902 @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
903 @deffnx {} BFD_RELOC_ARM_ADR_IMM
904 @deffnx {} BFD_RELOC_ARM_LDR_IMM
905 @deffnx {} BFD_RELOC_ARM_LITERAL
906 @deffnx {} BFD_RELOC_ARM_IN_POOL
907 @deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
908 @deffnx {} BFD_RELOC_ARM_HWLITERAL
909 @deffnx {} BFD_RELOC_ARM_THUMB_ADD
910 @deffnx {} BFD_RELOC_ARM_THUMB_IMM
911 @deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
912 @deffnx {} BFD_RELOC_ARM_THUMB_OFFSET
913 @deffnx {} BFD_RELOC_ARM_GOT12
914 @deffnx {} BFD_RELOC_ARM_GOT32
915 @deffnx {} BFD_RELOC_ARM_JUMP_SLOT
916 @deffnx {} BFD_RELOC_ARM_COPY
917 @deffnx {} BFD_RELOC_ARM_GLOB_DAT
918 @deffnx {} BFD_RELOC_ARM_PLT32
919 @deffnx {} BFD_RELOC_ARM_RELATIVE
920 @deffnx {} BFD_RELOC_ARM_GOTOFF
921 @deffnx {} BFD_RELOC_ARM_GOTPC
922 These relocs are only used within the ARM assembler. They are not
923 (at present) written to any object files.
925 @deffn {} BFD_RELOC_SH_PCDISP8BY2
926 @deffnx {} BFD_RELOC_SH_PCDISP12BY2
927 @deffnx {} BFD_RELOC_SH_IMM4
928 @deffnx {} BFD_RELOC_SH_IMM4BY2
929 @deffnx {} BFD_RELOC_SH_IMM4BY4
930 @deffnx {} BFD_RELOC_SH_IMM8
931 @deffnx {} BFD_RELOC_SH_IMM8BY2
932 @deffnx {} BFD_RELOC_SH_IMM8BY4
933 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
934 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
935 @deffnx {} BFD_RELOC_SH_SWITCH16
936 @deffnx {} BFD_RELOC_SH_SWITCH32
937 @deffnx {} BFD_RELOC_SH_USES
938 @deffnx {} BFD_RELOC_SH_COUNT
939 @deffnx {} BFD_RELOC_SH_ALIGN
940 @deffnx {} BFD_RELOC_SH_CODE
941 @deffnx {} BFD_RELOC_SH_DATA
942 @deffnx {} BFD_RELOC_SH_LABEL
943 @deffnx {} BFD_RELOC_SH_LOOP_START
944 @deffnx {} BFD_RELOC_SH_LOOP_END
945 @deffnx {} BFD_RELOC_SH_COPY
946 @deffnx {} BFD_RELOC_SH_GLOB_DAT
947 @deffnx {} BFD_RELOC_SH_JMP_SLOT
948 @deffnx {} BFD_RELOC_SH_RELATIVE
949 @deffnx {} BFD_RELOC_SH_GOTPC
950 @deffnx {} BFD_RELOC_SH_GOT_LOW16
951 @deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
952 @deffnx {} BFD_RELOC_SH_GOT_MEDHI16
953 @deffnx {} BFD_RELOC_SH_GOT_HI16
954 @deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
955 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
956 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
957 @deffnx {} BFD_RELOC_SH_GOTPLT_HI16
958 @deffnx {} BFD_RELOC_SH_PLT_LOW16
959 @deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
960 @deffnx {} BFD_RELOC_SH_PLT_MEDHI16
961 @deffnx {} BFD_RELOC_SH_PLT_HI16
962 @deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
963 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
964 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
965 @deffnx {} BFD_RELOC_SH_GOTOFF_HI16
966 @deffnx {} BFD_RELOC_SH_GOTPC_LOW16
967 @deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
968 @deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
969 @deffnx {} BFD_RELOC_SH_GOTPC_HI16
970 @deffnx {} BFD_RELOC_SH_COPY64
971 @deffnx {} BFD_RELOC_SH_GLOB_DAT64
972 @deffnx {} BFD_RELOC_SH_JMP_SLOT64
973 @deffnx {} BFD_RELOC_SH_RELATIVE64
974 @deffnx {} BFD_RELOC_SH_GOT10BY4
975 @deffnx {} BFD_RELOC_SH_GOT10BY8
976 @deffnx {} BFD_RELOC_SH_GOTPLT10BY4
977 @deffnx {} BFD_RELOC_SH_GOTPLT10BY8
978 @deffnx {} BFD_RELOC_SH_GOTPLT32
979 @deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
980 @deffnx {} BFD_RELOC_SH_IMMU5
981 @deffnx {} BFD_RELOC_SH_IMMS6
982 @deffnx {} BFD_RELOC_SH_IMMS6BY32
983 @deffnx {} BFD_RELOC_SH_IMMU6
984 @deffnx {} BFD_RELOC_SH_IMMS10
985 @deffnx {} BFD_RELOC_SH_IMMS10BY2
986 @deffnx {} BFD_RELOC_SH_IMMS10BY4
987 @deffnx {} BFD_RELOC_SH_IMMS10BY8
988 @deffnx {} BFD_RELOC_SH_IMMS16
989 @deffnx {} BFD_RELOC_SH_IMMU16
990 @deffnx {} BFD_RELOC_SH_IMM_LOW16
991 @deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
992 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
993 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
994 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16
995 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
996 @deffnx {} BFD_RELOC_SH_IMM_HI16
997 @deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
998 @deffnx {} BFD_RELOC_SH_PT_16
999 Hitachi SH relocs. Not all of these appear in object files.
1001 @deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9
1002 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1003 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1004 Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
1005 be zero and is not stored in the instruction.
1007 @deffn {} BFD_RELOC_ARC_B22_PCREL
1009 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
1010 not stored in the instruction. The high 20 bits are installed in bits 26
1011 through 7 of the instruction.
1013 @deffn {} BFD_RELOC_ARC_B26
1014 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
1015 stored in the instruction. The high 24 bits are installed in bits 23
1018 @deffn {} BFD_RELOC_D10V_10_PCREL_R
1019 Mitsubishi D10V relocs.
1020 This is a 10-bit reloc with the right 2 bits
1023 @deffn {} BFD_RELOC_D10V_10_PCREL_L
1024 Mitsubishi D10V relocs.
1025 This is a 10-bit reloc with the right 2 bits
1026 assumed to be 0. This is the same as the previous reloc
1027 except it is in the left container, i.e.,
1028 shifted left 15 bits.
1030 @deffn {} BFD_RELOC_D10V_18
1031 This is an 18-bit reloc with the right 2 bits
1034 @deffn {} BFD_RELOC_D10V_18_PCREL
1035 This is an 18-bit reloc with the right 2 bits
1038 @deffn {} BFD_RELOC_D30V_6
1039 Mitsubishi D30V relocs.
1040 This is a 6-bit absolute reloc.
1042 @deffn {} BFD_RELOC_D30V_9_PCREL
1043 This is a 6-bit pc-relative reloc with
1044 the right 3 bits assumed to be 0.
1046 @deffn {} BFD_RELOC_D30V_9_PCREL_R
1047 This is a 6-bit pc-relative reloc with
1048 the right 3 bits assumed to be 0. Same
1049 as the previous reloc but on the right side
1052 @deffn {} BFD_RELOC_D30V_15
1053 This is a 12-bit absolute reloc with the
1054 right 3 bitsassumed to be 0.
1056 @deffn {} BFD_RELOC_D30V_15_PCREL
1057 This is a 12-bit pc-relative reloc with
1058 the right 3 bits assumed to be 0.
1060 @deffn {} BFD_RELOC_D30V_15_PCREL_R
1061 This is a 12-bit pc-relative reloc with
1062 the right 3 bits assumed to be 0. Same
1063 as the previous reloc but on the right side
1066 @deffn {} BFD_RELOC_D30V_21
1067 This is an 18-bit absolute reloc with
1068 the right 3 bits assumed to be 0.
1070 @deffn {} BFD_RELOC_D30V_21_PCREL
1071 This is an 18-bit pc-relative reloc with
1072 the right 3 bits assumed to be 0.
1074 @deffn {} BFD_RELOC_D30V_21_PCREL_R
1075 This is an 18-bit pc-relative reloc with
1076 the right 3 bits assumed to be 0. Same
1077 as the previous reloc but on the right side
1080 @deffn {} BFD_RELOC_D30V_32
1081 This is a 32-bit absolute reloc.
1083 @deffn {} BFD_RELOC_D30V_32_PCREL
1084 This is a 32-bit pc-relative reloc.
1086 @deffn {} BFD_RELOC_M32R_24
1087 Mitsubishi M32R relocs.
1088 This is a 24 bit absolute address.
1090 @deffn {} BFD_RELOC_M32R_10_PCREL
1091 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1093 @deffn {} BFD_RELOC_M32R_18_PCREL
1094 This is an 18-bit reloc with the right 2 bits assumed to be 0.
1096 @deffn {} BFD_RELOC_M32R_26_PCREL
1097 This is a 26-bit reloc with the right 2 bits assumed to be 0.
1099 @deffn {} BFD_RELOC_M32R_HI16_ULO
1100 This is a 16-bit reloc containing the high 16 bits of an address
1101 used when the lower 16 bits are treated as unsigned.
1103 @deffn {} BFD_RELOC_M32R_HI16_SLO
1104 This is a 16-bit reloc containing the high 16 bits of an address
1105 used when the lower 16 bits are treated as signed.
1107 @deffn {} BFD_RELOC_M32R_LO16
1108 This is a 16-bit reloc containing the lower 16 bits of an address.
1110 @deffn {} BFD_RELOC_M32R_SDA16
1111 This is a 16-bit reloc containing the small data area offset for use in
1112 add3, load, and store instructions.
1114 @deffn {} BFD_RELOC_V850_9_PCREL
1115 This is a 9-bit reloc
1117 @deffn {} BFD_RELOC_V850_22_PCREL
1118 This is a 22-bit reloc
1120 @deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1121 This is a 16 bit offset from the short data area pointer.
1123 @deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1124 This is a 16 bit offset (of which only 15 bits are used) from the
1125 short data area pointer.
1127 @deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1128 This is a 16 bit offset from the zero data area pointer.
1130 @deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1131 This is a 16 bit offset (of which only 15 bits are used) from the
1132 zero data area pointer.
1134 @deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1135 This is an 8 bit offset (of which only 6 bits are used) from the
1136 tiny data area pointer.
1138 @deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1139 This is an 8bit offset (of which only 7 bits are used) from the tiny
1142 @deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1143 This is a 7 bit offset from the tiny data area pointer.
1145 @deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1146 This is a 16 bit offset from the tiny data area pointer.
1148 @deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1149 This is a 5 bit offset (of which only 4 bits are used) from the tiny
1152 @deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1153 This is a 4 bit offset from the tiny data area pointer.
1155 @deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1156 This is a 16 bit offset from the short data area pointer, with the
1157 bits placed non-contigously in the instruction.
1159 @deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1160 This is a 16 bit offset from the zero data area pointer, with the
1161 bits placed non-contigously in the instruction.
1163 @deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1164 This is a 6 bit offset from the call table base pointer.
1166 @deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1167 This is a 16 bit offset from the call table base pointer.
1169 @deffn {} BFD_RELOC_MN10300_32_PCREL
1170 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1173 @deffn {} BFD_RELOC_MN10300_16_PCREL
1174 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1177 @deffn {} BFD_RELOC_TIC30_LDP
1178 This is a 8bit DP reloc for the tms320c30, where the most
1179 significant 8 bits of a 24 bit word are placed into the least
1180 significant 8 bits of the opcode.
1182 @deffn {} BFD_RELOC_TIC54X_PARTLS7
1183 This is a 7bit reloc for the tms320c54x, where the least
1184 significant 7 bits of a 16 bit word are placed into the least
1185 significant 7 bits of the opcode.
1187 @deffn {} BFD_RELOC_TIC54X_PARTMS9
1188 This is a 9bit DP reloc for the tms320c54x, where the most
1189 significant 9 bits of a 16 bit word are placed into the least
1190 significant 9 bits of the opcode.
1192 @deffn {} BFD_RELOC_TIC54X_23
1193 This is an extended address 23-bit reloc for the tms320c54x.
1195 @deffn {} BFD_RELOC_TIC54X_16_OF_23
1196 This is a 16-bit reloc for the tms320c54x, where the least
1197 significant 16 bits of a 23-bit extended address are placed into
1200 @deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1201 This is a reloc for the tms320c54x, where the most
1202 significant 7 bits of a 23-bit extended address are placed into
1205 @deffn {} BFD_RELOC_FR30_48
1206 This is a 48 bit reloc for the FR30 that stores 32 bits.
1208 @deffn {} BFD_RELOC_FR30_20
1209 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1212 @deffn {} BFD_RELOC_FR30_6_IN_4
1213 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1216 @deffn {} BFD_RELOC_FR30_8_IN_8
1217 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1220 @deffn {} BFD_RELOC_FR30_9_IN_8
1221 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1224 @deffn {} BFD_RELOC_FR30_10_IN_8
1225 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1228 @deffn {} BFD_RELOC_FR30_9_PCREL
1229 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1230 short offset into 8 bits.
1232 @deffn {} BFD_RELOC_FR30_12_PCREL
1233 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1234 short offset into 11 bits.
1236 @deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1237 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1238 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1239 @deffnx {} BFD_RELOC_MCORE_PCREL_32
1240 @deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1241 @deffnx {} BFD_RELOC_MCORE_RVA
1242 Motorola Mcore relocations.
1244 @deffn {} BFD_RELOC_MMIX_GETA
1245 @deffnx {} BFD_RELOC_MMIX_GETA_1
1246 @deffnx {} BFD_RELOC_MMIX_GETA_2
1247 @deffnx {} BFD_RELOC_MMIX_GETA_3
1248 These are relocations for the GETA instruction.
1250 @deffn {} BFD_RELOC_MMIX_CBRANCH
1251 @deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1252 @deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1253 @deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1254 @deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1255 These are relocations for a conditional branch instruction.
1257 @deffn {} BFD_RELOC_MMIX_PUSHJ
1258 @deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1259 @deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1260 @deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1261 These are relocations for the PUSHJ instruction.
1263 @deffn {} BFD_RELOC_MMIX_JMP
1264 @deffnx {} BFD_RELOC_MMIX_JMP_1
1265 @deffnx {} BFD_RELOC_MMIX_JMP_2
1266 @deffnx {} BFD_RELOC_MMIX_JMP_3
1267 These are relocations for the JMP instruction.
1269 @deffn {} BFD_RELOC_MMIX_ADDR19
1270 This is a relocation for a relative address as in a GETA instruction or
1273 @deffn {} BFD_RELOC_MMIX_ADDR27
1274 This is a relocation for a relative address as in a JMP instruction.
1276 @deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1277 This is a relocation for an instruction field that may be a general
1278 register or a value 0..255.
1280 @deffn {} BFD_RELOC_MMIX_REG
1281 This is a relocation for an instruction field that may be a general
1284 @deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1285 This is a relocation for two instruction fields holding a register and
1286 an offset, the equivalent of the relocation.
1288 @deffn {} BFD_RELOC_MMIX_LOCAL
1289 This relocation is an assertion that the expression is not allocated as
1290 a global register. It does not modify contents.
1292 @deffn {} BFD_RELOC_AVR_7_PCREL
1293 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1294 short offset into 7 bits.
1296 @deffn {} BFD_RELOC_AVR_13_PCREL
1297 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1298 short offset into 12 bits.
1300 @deffn {} BFD_RELOC_AVR_16_PM
1301 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1302 program memory address) into 16 bits.
1304 @deffn {} BFD_RELOC_AVR_LO8_LDI
1305 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1306 data memory address) into 8 bit immediate value of LDI insn.
1308 @deffn {} BFD_RELOC_AVR_HI8_LDI
1309 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1310 of data memory address) into 8 bit immediate value of LDI insn.
1312 @deffn {} BFD_RELOC_AVR_HH8_LDI
1313 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1314 of program memory address) into 8 bit immediate value of LDI insn.
1316 @deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1317 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1318 (usually data memory address) into 8 bit immediate value of SUBI insn.
1320 @deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1321 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1322 (high 8 bit of data memory address) into 8 bit immediate value of
1325 @deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1326 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1327 (most high 8 bit of program memory address) into 8 bit immediate value
1328 of LDI or SUBI insn.
1330 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1331 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1332 command address) into 8 bit immediate value of LDI insn.
1334 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1335 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1336 of command address) into 8 bit immediate value of LDI insn.
1338 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1339 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1340 of command address) into 8 bit immediate value of LDI insn.
1342 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1343 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1344 (usually command address) into 8 bit immediate value of SUBI insn.
1346 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1347 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1348 (high 8 bit of 16 bit command address) into 8 bit immediate value
1351 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1352 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1353 (high 6 bit of 22 bit command address) into 8 bit immediate
1356 @deffn {} BFD_RELOC_AVR_CALL
1357 This is a 32 bit reloc for the AVR that stores 23 bit value
1360 @deffn {} BFD_RELOC_390_12
1363 @deffn {} BFD_RELOC_390_GOT12
1366 @deffn {} BFD_RELOC_390_PLT32
1367 32 bit PC relative PLT address.
1369 @deffn {} BFD_RELOC_390_COPY
1370 Copy symbol at runtime.
1372 @deffn {} BFD_RELOC_390_GLOB_DAT
1375 @deffn {} BFD_RELOC_390_JMP_SLOT
1378 @deffn {} BFD_RELOC_390_RELATIVE
1379 Adjust by program base.
1381 @deffn {} BFD_RELOC_390_GOTPC
1382 32 bit PC relative offset to GOT.
1384 @deffn {} BFD_RELOC_390_GOT16
1387 @deffn {} BFD_RELOC_390_PC16DBL
1388 PC relative 16 bit shifted by 1.
1390 @deffn {} BFD_RELOC_390_PLT16DBL
1391 16 bit PC rel. PLT shifted by 1.
1393 @deffn {} BFD_RELOC_390_PC32DBL
1394 PC relative 32 bit shifted by 1.
1396 @deffn {} BFD_RELOC_390_PLT32DBL
1397 32 bit PC rel. PLT shifted by 1.
1399 @deffn {} BFD_RELOC_390_GOTPCDBL
1400 32 bit PC rel. GOT shifted by 1.
1402 @deffn {} BFD_RELOC_390_GOT64
1405 @deffn {} BFD_RELOC_390_PLT64
1406 64 bit PC relative PLT address.
1408 @deffn {} BFD_RELOC_390_GOTENT
1409 32 bit rel. offset to GOT entry.
1411 @deffn {} BFD_RELOC_VTABLE_INHERIT
1412 @deffnx {} BFD_RELOC_VTABLE_ENTRY
1413 These two relocations are used by the linker to determine which of
1414 the entries in a C++ virtual function table are actually used. When
1415 the --gc-sections option is given, the linker will zero out the entries
1416 that are not used, so that the code for those functions need not be
1417 included in the output.
1419 VTABLE_INHERIT is a zero-space relocation used to describe to the
1420 linker the inheritence tree of a C++ virtual function table. The
1421 relocation's symbol should be the parent class' vtable, and the
1422 relocation should be located at the child vtable.
1424 VTABLE_ENTRY is a zero-space relocation that describes the use of a
1425 virtual function table entry. The reloc's symbol should refer to the
1426 table of the class mentioned in the code. Off of that base, an offset
1427 describes the entry that is being used. For Rela hosts, this offset
1428 is stored in the reloc's addend. For Rel hosts, we are forced to put
1429 this offset in the reloc's section offset.
1431 @deffn {} BFD_RELOC_IA64_IMM14
1432 @deffnx {} BFD_RELOC_IA64_IMM22
1433 @deffnx {} BFD_RELOC_IA64_IMM64
1434 @deffnx {} BFD_RELOC_IA64_DIR32MSB
1435 @deffnx {} BFD_RELOC_IA64_DIR32LSB
1436 @deffnx {} BFD_RELOC_IA64_DIR64MSB
1437 @deffnx {} BFD_RELOC_IA64_DIR64LSB
1438 @deffnx {} BFD_RELOC_IA64_GPREL22
1439 @deffnx {} BFD_RELOC_IA64_GPREL64I
1440 @deffnx {} BFD_RELOC_IA64_GPREL32MSB
1441 @deffnx {} BFD_RELOC_IA64_GPREL32LSB
1442 @deffnx {} BFD_RELOC_IA64_GPREL64MSB
1443 @deffnx {} BFD_RELOC_IA64_GPREL64LSB
1444 @deffnx {} BFD_RELOC_IA64_LTOFF22
1445 @deffnx {} BFD_RELOC_IA64_LTOFF64I
1446 @deffnx {} BFD_RELOC_IA64_PLTOFF22
1447 @deffnx {} BFD_RELOC_IA64_PLTOFF64I
1448 @deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
1449 @deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
1450 @deffnx {} BFD_RELOC_IA64_FPTR64I
1451 @deffnx {} BFD_RELOC_IA64_FPTR32MSB
1452 @deffnx {} BFD_RELOC_IA64_FPTR32LSB
1453 @deffnx {} BFD_RELOC_IA64_FPTR64MSB
1454 @deffnx {} BFD_RELOC_IA64_FPTR64LSB
1455 @deffnx {} BFD_RELOC_IA64_PCREL21B
1456 @deffnx {} BFD_RELOC_IA64_PCREL21BI
1457 @deffnx {} BFD_RELOC_IA64_PCREL21M
1458 @deffnx {} BFD_RELOC_IA64_PCREL21F
1459 @deffnx {} BFD_RELOC_IA64_PCREL22
1460 @deffnx {} BFD_RELOC_IA64_PCREL60B
1461 @deffnx {} BFD_RELOC_IA64_PCREL64I
1462 @deffnx {} BFD_RELOC_IA64_PCREL32MSB
1463 @deffnx {} BFD_RELOC_IA64_PCREL32LSB
1464 @deffnx {} BFD_RELOC_IA64_PCREL64MSB
1465 @deffnx {} BFD_RELOC_IA64_PCREL64LSB
1466 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
1467 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
1468 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
1469 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
1470 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
1471 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
1472 @deffnx {} BFD_RELOC_IA64_SEGREL32MSB
1473 @deffnx {} BFD_RELOC_IA64_SEGREL32LSB
1474 @deffnx {} BFD_RELOC_IA64_SEGREL64MSB
1475 @deffnx {} BFD_RELOC_IA64_SEGREL64LSB
1476 @deffnx {} BFD_RELOC_IA64_SECREL32MSB
1477 @deffnx {} BFD_RELOC_IA64_SECREL32LSB
1478 @deffnx {} BFD_RELOC_IA64_SECREL64MSB
1479 @deffnx {} BFD_RELOC_IA64_SECREL64LSB
1480 @deffnx {} BFD_RELOC_IA64_REL32MSB
1481 @deffnx {} BFD_RELOC_IA64_REL32LSB
1482 @deffnx {} BFD_RELOC_IA64_REL64MSB
1483 @deffnx {} BFD_RELOC_IA64_REL64LSB
1484 @deffnx {} BFD_RELOC_IA64_LTV32MSB
1485 @deffnx {} BFD_RELOC_IA64_LTV32LSB
1486 @deffnx {} BFD_RELOC_IA64_LTV64MSB
1487 @deffnx {} BFD_RELOC_IA64_LTV64LSB
1488 @deffnx {} BFD_RELOC_IA64_IPLTMSB
1489 @deffnx {} BFD_RELOC_IA64_IPLTLSB
1490 @deffnx {} BFD_RELOC_IA64_COPY
1491 @deffnx {} BFD_RELOC_IA64_TPREL22
1492 @deffnx {} BFD_RELOC_IA64_TPREL64MSB
1493 @deffnx {} BFD_RELOC_IA64_TPREL64LSB
1494 @deffnx {} BFD_RELOC_IA64_LTOFF_TP22
1495 @deffnx {} BFD_RELOC_IA64_LTOFF22X
1496 @deffnx {} BFD_RELOC_IA64_LDXMOV
1497 Intel IA64 Relocations.
1499 @deffn {} BFD_RELOC_M68HC11_HI8
1500 Motorola 68HC11 reloc.
1501 This is the 8 bits high part of an absolute address.
1503 @deffn {} BFD_RELOC_M68HC11_LO8
1504 Motorola 68HC11 reloc.
1505 This is the 8 bits low part of an absolute address.
1507 @deffn {} BFD_RELOC_M68HC11_3B
1508 Motorola 68HC11 reloc.
1509 This is the 3 bits of a value.
1511 @deffn {} BFD_RELOC_CRIS_BDISP8
1512 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
1513 @deffnx {} BFD_RELOC_CRIS_SIGNED_6
1514 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
1515 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
1516 These relocs are only used within the CRIS assembler. They are not
1517 (at present) written to any object files.
1519 @deffn {} BFD_RELOC_CRIS_COPY
1520 @deffnx {} BFD_RELOC_CRIS_GLOB_DAT
1521 @deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
1522 @deffnx {} BFD_RELOC_CRIS_RELATIVE
1523 Relocs used in ELF shared libraries for CRIS.
1525 @deffn {} BFD_RELOC_CRIS_32_GOT
1526 32-bit offset to symbol-entry within GOT.
1528 @deffn {} BFD_RELOC_CRIS_16_GOT
1529 16-bit offset to symbol-entry within GOT.
1531 @deffn {} BFD_RELOC_CRIS_32_GOTPLT
1532 32-bit offset to symbol-entry within GOT, with PLT handling.
1534 @deffn {} BFD_RELOC_CRIS_16_GOTPLT
1535 16-bit offset to symbol-entry within GOT, with PLT handling.
1537 @deffn {} BFD_RELOC_CRIS_32_GOTREL
1538 32-bit offset to symbol, relative to GOT.
1540 @deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
1541 32-bit offset to symbol with PLT entry, relative to GOT.
1543 @deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
1544 32-bit offset to symbol with PLT entry, relative to this relocation.
1546 @deffn {} BFD_RELOC_860_COPY
1547 @deffnx {} BFD_RELOC_860_GLOB_DAT
1548 @deffnx {} BFD_RELOC_860_JUMP_SLOT
1549 @deffnx {} BFD_RELOC_860_RELATIVE
1550 @deffnx {} BFD_RELOC_860_PC26
1551 @deffnx {} BFD_RELOC_860_PLT26
1552 @deffnx {} BFD_RELOC_860_PC16
1553 @deffnx {} BFD_RELOC_860_LOW0
1554 @deffnx {} BFD_RELOC_860_SPLIT0
1555 @deffnx {} BFD_RELOC_860_LOW1
1556 @deffnx {} BFD_RELOC_860_SPLIT1
1557 @deffnx {} BFD_RELOC_860_LOW2
1558 @deffnx {} BFD_RELOC_860_SPLIT2
1559 @deffnx {} BFD_RELOC_860_LOW3
1560 @deffnx {} BFD_RELOC_860_LOGOT0
1561 @deffnx {} BFD_RELOC_860_SPGOT0
1562 @deffnx {} BFD_RELOC_860_LOGOT1
1563 @deffnx {} BFD_RELOC_860_SPGOT1
1564 @deffnx {} BFD_RELOC_860_LOGOTOFF0
1565 @deffnx {} BFD_RELOC_860_SPGOTOFF0
1566 @deffnx {} BFD_RELOC_860_LOGOTOFF1
1567 @deffnx {} BFD_RELOC_860_SPGOTOFF1
1568 @deffnx {} BFD_RELOC_860_LOGOTOFF2
1569 @deffnx {} BFD_RELOC_860_LOGOTOFF3
1570 @deffnx {} BFD_RELOC_860_LOPC
1571 @deffnx {} BFD_RELOC_860_HIGHADJ
1572 @deffnx {} BFD_RELOC_860_HAGOT
1573 @deffnx {} BFD_RELOC_860_HAGOTOFF
1574 @deffnx {} BFD_RELOC_860_HAPC
1575 @deffnx {} BFD_RELOC_860_HIGH
1576 @deffnx {} BFD_RELOC_860_HIGOT
1577 @deffnx {} BFD_RELOC_860_HIGOTOFF
1578 Intel i860 Relocations.
1580 @deffn {} BFD_RELOC_OPENRISC_ABS_26
1581 @deffnx {} BFD_RELOC_OPENRISC_REL_26
1582 OpenRISC Relocations.
1584 @deffn {} BFD_RELOC_H8_DIR16A8
1585 @deffnx {} BFD_RELOC_H8_DIR16R8
1586 @deffnx {} BFD_RELOC_H8_DIR24A8
1587 @deffnx {} BFD_RELOC_H8_DIR24R8
1588 @deffnx {} BFD_RELOC_H8_DIR32A16
1591 @deffn {} BFD_RELOC_XSTORMY16_REL_12
1592 @deffnx {} BFD_RELOC_XSTORMY16_24
1593 @deffnx {} BFD_RELOC_XSTORMY16_FPTR16
1594 Sony Xstormy16 Relocations.
1599 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
1601 @findex bfd_reloc_type_lookup
1602 @subsubsection @code{bfd_reloc_type_lookup}
1606 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code);
1608 @strong{Description}@*
1609 Return a pointer to a howto structure which, when
1610 invoked, will perform the relocation @var{code} on data from the
1613 @findex bfd_default_reloc_type_lookup
1614 @subsubsection @code{bfd_default_reloc_type_lookup}
1617 reloc_howto_type *bfd_default_reloc_type_lookup
1618 (bfd *abfd, bfd_reloc_code_real_type code);
1620 @strong{Description}@*
1621 Provides a default relocation lookup routine for any architecture.
1623 @findex bfd_get_reloc_code_name
1624 @subsubsection @code{bfd_get_reloc_code_name}
1627 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
1629 @strong{Description}@*
1630 Provides a printable name for the supplied relocation code.
1631 Useful mainly for printing error messages.
1633 @findex bfd_generic_relax_section
1634 @subsubsection @code{bfd_generic_relax_section}
1637 boolean bfd_generic_relax_section
1640 struct bfd_link_info *,
1643 @strong{Description}@*
1644 Provides default handling for relaxing for back ends which
1645 don't do relaxing -- i.e., does nothing.
1647 @findex bfd_generic_gc_sections
1648 @subsubsection @code{bfd_generic_gc_sections}
1651 boolean bfd_generic_gc_sections
1652 (bfd *, struct bfd_link_info *);
1654 @strong{Description}@*
1655 Provides default handling for relaxing for back ends which
1656 don't do section gc -- i.e., does nothing.
1658 @findex bfd_generic_merge_sections
1659 @subsubsection @code{bfd_generic_merge_sections}
1662 boolean bfd_generic_merge_sections
1663 (bfd *, struct bfd_link_info *);
1665 @strong{Description}@*
1666 Provides default handling for SEC_MERGE section merging for back ends
1667 which don't have SEC_MERGE support -- i.e., does nothing.
1669 @findex bfd_generic_get_relocated_section_contents
1670 @subsubsection @code{bfd_generic_get_relocated_section_contents}
1674 bfd_generic_get_relocated_section_contents (bfd *abfd,
1675 struct bfd_link_info *link_info,
1676 struct bfd_link_order *link_order,
1678 boolean relocateable,
1681 @strong{Description}@*
1682 Provides default handling of relocation effort for back ends
1683 which can't be bothered to do it efficiently.