2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/firewire/fwohcireg.h,v 1.15 2004/01/06 14:24:01 simokawa Exp $
35 * $DragonFly: src/sys/bus/firewire/fwohcireg.h,v 1.7 2004/07/16 09:10:50 asmodai Exp $
38 #define PCI_CBMEM 0x10
40 #define FW_VENDORID_NEC 0x1033
41 #define FW_VENDORID_TI 0x104c
42 #define FW_VENDORID_SONY 0x104d
43 #define FW_VENDORID_VIA 0x1106
44 #define FW_VENDORID_RICOH 0x1180
45 #define FW_VENDORID_APPLE 0x106b
46 #define FW_VENDORID_LUCENT 0x11c1
48 #define FW_DEVICE_UPD861 (0x0063 << 16)
49 #define FW_DEVICE_UPD871 (0x00ce << 16)
50 #define FW_DEVICE_UPD72870 (0x00cd << 16)
51 #define FW_DEVICE_UPD72873 (0x00e7 << 16)
52 #define FW_DEVICE_UPD72874 (0x00f2 << 16)
53 #define FW_DEVICE_TITSB22 (0x8009 << 16)
54 #define FW_DEVICE_TITSB23 (0x8019 << 16)
55 #define FW_DEVICE_TITSB26 (0x8020 << 16)
56 #define FW_DEVICE_TITSB43 (0x8021 << 16)
57 #define FW_DEVICE_TITSB43A (0x8023 << 16)
58 #define FW_DEVICE_TITSB43AB23 (0x8024 << 16)
59 #define FW_DEVICE_TITSB82AA2 (0x8025 << 16)
60 #define FW_DEVICE_TITSB43AB21 (0x8026 << 16)
61 #define FW_DEVICE_TIPCI4410A (0x8017 << 16)
62 #define FW_DEVICE_TIPCI4450 (0x8011 << 16)
63 #define FW_DEVICE_TIPCI4451 (0x8027 << 16)
64 #define FW_DEVICE_CX3022 (0x8039 << 16)
65 #define FW_DEVICE_VT6306 (0x3044 << 16)
66 #define FW_DEVICE_R5C551 (0x0551 << 16)
67 #define FW_DEVICE_R5C552 (0x0552 << 16)
68 #define FW_DEVICE_PANGEA (0x0030 << 16)
69 #define FW_DEVICE_UNINORTH (0x0031 << 16)
70 #define FW_DEVICE_FW322 (0x5811 << 16)
72 #define PCI_INTERFACE_OHCI 0x10
74 #define FW_OHCI_BASE_REG 0x10
76 #define OHCI_DMA_ITCH 0x20
77 #define OHCI_DMA_IRCH 0x20
79 #define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
82 typedef u_int32_t fwohcireg_t;
85 #if BYTE_ORDER == BIG_ENDIAN
86 #define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y))
87 #define FWOHCI_DMA_READ(x) le32toh(x)
88 #define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y))
89 #define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y)))
91 #define FWOHCI_DMA_WRITE(x, y) ((x) = (y))
92 #define FWOHCI_DMA_READ(x) (x)
93 #define FWOHCI_DMA_SET(x, y) ((x) |= (y))
94 #define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y))
107 #define OHCI_STATUS_SHIFT 16
108 #define OHCI_COUNT_MASK 0xffff
109 #define OHCI_OUTPUT_MORE (0 << 28)
110 #define OHCI_OUTPUT_LAST (1 << 28)
111 #define OHCI_INPUT_MORE (2 << 28)
112 #define OHCI_INPUT_LAST (3 << 28)
113 #define OHCI_STORE_QUAD (4 << 28)
114 #define OHCI_LOAD_QUAD (5 << 28)
115 #define OHCI_NOP (6 << 28)
116 #define OHCI_STOP (7 << 28)
117 #define OHCI_STORE (8 << 28)
118 #define OHCI_CMD_MASK (0xf << 28)
120 #define OHCI_UPDATE (1 << 27)
122 #define OHCI_KEY_ST0 (0 << 24)
123 #define OHCI_KEY_ST1 (1 << 24)
124 #define OHCI_KEY_ST2 (2 << 24)
125 #define OHCI_KEY_ST3 (3 << 24)
126 #define OHCI_KEY_REGS (5 << 24)
127 #define OHCI_KEY_SYS (6 << 24)
128 #define OHCI_KEY_DEVICE (7 << 24)
129 #define OHCI_KEY_MASK (7 << 24)
131 #define OHCI_INTERRUPT_NEVER (0 << 20)
132 #define OHCI_INTERRUPT_TRUE (1 << 20)
133 #define OHCI_INTERRUPT_FALSE (2 << 20)
134 #define OHCI_INTERRUPT_ALWAYS (3 << 20)
136 #define OHCI_BRANCH_NEVER (0 << 18)
137 #define OHCI_BRANCH_TRUE (1 << 18)
138 #define OHCI_BRANCH_FALSE (2 << 18)
139 #define OHCI_BRANCH_ALWAYS (3 << 18)
140 #define OHCI_BRANCH_MASK (3 << 18)
142 #define OHCI_WAIT_NEVER (0 << 16)
143 #define OHCI_WAIT_TRUE (1 << 16)
144 #define OHCI_WAIT_FALSE (2 << 16)
145 #define OHCI_WAIT_ALWAYS (3 << 16)
148 #define OHCI_SPD_S100 0x4
149 #define OHCI_SPD_S200 0x1
150 #define OHCI_SPD_S400 0x2
153 #define FWOHCIEV_NOSTAT 0
154 #define FWOHCIEV_LONGP 2
155 #define FWOHCIEV_MISSACK 3
156 #define FWOHCIEV_UNDRRUN 4
157 #define FWOHCIEV_OVRRUN 5
158 #define FWOHCIEV_DESCERR 6
159 #define FWOHCIEV_DTRDERR 7
160 #define FWOHCIEV_DTWRERR 8
161 #define FWOHCIEV_BUSRST 9
162 #define FWOHCIEV_TIMEOUT 0xa
163 #define FWOHCIEV_TCODERR 0xb
164 #define FWOHCIEV_UNKNOWN 0xe
165 #define FWOHCIEV_FLUSHED 0xf
166 #define FWOHCIEV_ACKCOMPL 0x11
167 #define FWOHCIEV_ACKPEND 0x12
168 #define FWOHCIEV_ACKBSX 0x14
169 #define FWOHCIEV_ACKBSA 0x15
170 #define FWOHCIEV_ACKBSB 0x16
171 #define FWOHCIEV_ACKTARD 0x1b
172 #define FWOHCIEV_ACKDERR 0x1d
173 #define FWOHCIEV_ACKTERR 0x1e
175 #define FWOHCIEV_MASK 0x1f
180 #define OHCI_CNTL_CYCMATCH_S (0x1 << 31)
182 #define OHCI_CNTL_BUFFIL (0x1 << 31)
183 #define OHCI_CNTL_ISOHDR (0x1 << 30)
184 #define OHCI_CNTL_CYCMATCH_R (0x1 << 29)
185 #define OHCI_CNTL_MULTICH (0x1 << 28)
187 #define OHCI_CNTL_DMA_RUN (0x1 << 15)
188 #define OHCI_CNTL_DMA_WAKE (0x1 << 12)
189 #define OHCI_CNTL_DMA_DEAD (0x1 << 11)
190 #define OHCI_CNTL_DMA_ACTIVE (0x1 << 10)
191 #define OHCI_CNTL_DMA_BT (0x1 << 8)
192 #define OHCI_CNTL_DMA_BAD (0x1 << 7)
193 #define OHCI_CNTL_DMA_STAT (0xff)
195 fwohcireg_t cntl_clr;
206 fwohcireg_t cntl_clr;
211 struct ohci_registers {
212 fwohcireg_t ver; /* Version No. 0x0 */
213 fwohcireg_t guid; /* GUID_ROM No. 0x4 */
214 fwohcireg_t retry; /* AT retries 0x8 */
215 #define FWOHCI_RETRY 0x8
216 fwohcireg_t csr_data; /* CSR data 0xc */
217 fwohcireg_t csr_cmp; /* CSR compare 0x10 */
218 fwohcireg_t csr_cntl; /* CSR compare 0x14 */
219 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
220 fwohcireg_t bus_id; /* BUS_ID 0x1c */
221 fwohcireg_t bus_opt; /* BUS option 0x20 */
222 #define FWOHCIGUID_H 0x24
223 #define FWOHCIGUID_L 0x28
224 fwohcireg_t guid_hi; /* GUID hi 0x24 */
225 fwohcireg_t guid_lo; /* GUID lo 0x28 */
226 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
227 fwohcireg_t config_rom; /* config ROM map 0x34 */
228 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
229 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
230 fwohcireg_t vender; /* vender ID 0x40 */
231 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
232 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
233 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
234 #define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */
235 #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */
236 #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */
237 #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */
238 #define OHCI_HCC_LPS (1 << 19) /* LPS */
239 #define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */
240 #define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */
241 #define OHCI_HCC_RESET (1 << 16) /* softReset */
242 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
243 fwohcireg_t dummy3[1]; /* dummy 0x60 */
244 fwohcireg_t sid_buf; /* self id buffer 0x64 */
245 fwohcireg_t sid_cnt; /* self id count 0x68 */
246 fwohcireg_t dummy4[1]; /* dummy 0x6c */
247 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
248 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
249 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
250 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
251 #define FWOHCI_INTSTAT 0x80
252 #define FWOHCI_INTSTATCLR 0x84
253 #define FWOHCI_INTMASK 0x88
254 #define FWOHCI_INTMASKCLR 0x8c
255 fwohcireg_t int_stat; /* 0x80 */
256 fwohcireg_t int_clear; /* 0x84 */
257 fwohcireg_t int_mask; /* 0x88 */
258 fwohcireg_t int_mask_clear; /* 0x8c */
259 fwohcireg_t it_int_stat; /* 0x90 */
260 fwohcireg_t it_int_clear; /* 0x94 */
261 fwohcireg_t it_int_mask; /* 0x98 */
262 fwohcireg_t it_mask_clear; /* 0x9c */
263 fwohcireg_t ir_int_stat; /* 0xa0 */
264 fwohcireg_t ir_int_clear; /* 0xa4 */
265 fwohcireg_t ir_int_mask; /* 0xa8 */
266 fwohcireg_t ir_mask_clear; /* 0xac */
267 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
268 fwohcireg_t fairness; /* fairness control 0xdc */
269 fwohcireg_t link_cntl; /* Chip control 0xe0*/
270 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
271 #define FWOHCI_NODEID 0xe8
272 fwohcireg_t node; /* Node ID 0xe8 */
273 #define OHCI_NODE_VALID (1 << 31)
274 #define OHCI_NODE_ROOT (1 << 30)
276 #define OHCI_ASYSRCBUS 1
278 fwohcireg_t phy_access; /* PHY cntl 0xec */
279 #define PHYDEV_RDDONE (1<<31)
280 #define PHYDEV_RDCMD (1<<15)
281 #define PHYDEV_WRCMD (1<<14)
282 #define PHYDEV_REGADDR 8
283 #define PHYDEV_WRDATA 0
284 #define PHYDEV_RDADDR 24
285 #define PHYDEV_RDDATA 16
287 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
288 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
289 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
290 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
291 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
292 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
293 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
294 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
295 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
296 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
298 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
300 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
302 /* 0x180, 0x184, 0x188, 0x18c */
303 /* 0x190, 0x194, 0x198, 0x19c */
304 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */
305 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */
306 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */
307 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */
308 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */
309 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */
310 struct ohci_dma dma_ch[0x4];
312 /* 0x200, 0x204, 0x208, 0x20c */
313 /* 0x210, 0x204, 0x208, 0x20c */
314 struct ohci_itdma dma_itch[0x20];
316 /* 0x400, 0x404, 0x408, 0x40c */
317 /* 0x410, 0x404, 0x408, 0x40c */
318 struct ohci_dma dma_irch[0x20];
322 STAILQ_ENTRY(fwohcidb_tr) link;
323 struct fw_xfer *xfer;
325 bus_dmamap_t dma_map;
332 * OHCI info structure.
334 struct fwohci_txpkthdr{
338 #if BYTE_ORDER == BIG_ENDIAN
339 u_int32_t spd:16, /* XXX include reserved field */
347 spd:16; /* XXX include reserved fields */
351 #if BYTE_ORDER == BIG_ENDIAN
371 #if BYTE_ORDER == BIG_ENDIAN
388 struct fwohci_trailer{
393 #define OHCI_CNTL_CYCSRC (0x1 << 22)
394 #define OHCI_CNTL_CYCMTR (0x1 << 21)
395 #define OHCI_CNTL_CYCTIMER (0x1 << 20)
396 #define OHCI_CNTL_PHYPKT (0x1 << 10)
397 #define OHCI_CNTL_SID (0x1 << 9)
399 #define OHCI_INT_DMA_ATRQ (0x1 << 0)
400 #define OHCI_INT_DMA_ATRS (0x1 << 1)
401 #define OHCI_INT_DMA_ARRQ (0x1 << 2)
402 #define OHCI_INT_DMA_ARRS (0x1 << 3)
403 #define OHCI_INT_DMA_PRRQ (0x1 << 4)
404 #define OHCI_INT_DMA_PRRS (0x1 << 5)
405 #define OHCI_INT_DMA_IT (0x1 << 6)
406 #define OHCI_INT_DMA_IR (0x1 << 7)
407 #define OHCI_INT_PW_ERR (0x1 << 8)
408 #define OHCI_INT_LR_ERR (0x1 << 9)
410 #define OHCI_INT_PHY_SID (0x1 << 16)
411 #define OHCI_INT_PHY_BUS_R (0x1 << 17)
413 #define OHCI_INT_REG_FAIL (0x1 << 18)
415 #define OHCI_INT_PHY_INT (0x1 << 19)
416 #define OHCI_INT_CYC_START (0x1 << 20)
417 #define OHCI_INT_CYC_64SECOND (0x1 << 21)
418 #define OHCI_INT_CYC_LOST (0x1 << 22)
419 #define OHCI_INT_CYC_ERR (0x1 << 23)
421 #define OHCI_INT_ERR (0x1 << 24)
422 #define OHCI_INT_CYC_LONG (0x1 << 25)
423 #define OHCI_INT_PHY_REG (0x1 << 26)
425 #define OHCI_INT_EN (0x1 << 31)
427 #define IP_CHANNELS 0x0234
428 #define FWOHCI_MAXREC 2048
430 #define OHCI_ISORA 0x02
431 #define OHCI_ISORB 0x04
433 #define FWOHCITCODE_PHY 0xe