sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <netinet/ip.h>
  72 #include <netinet/tcp.h>
  73
  74 #include <net/bpf.h>
  75 #include <net/ethernet.h>
  76 #include <net/if.h>
  77 #include <net/if_arp.h>
  78 #include <net/if_dl.h>
  79 #include <net/if_media.h>
  80 #include <net/if_types.h>
  81 #include <net/ifq_var.h>
  82 #include <net/vlan/if_vlan_var.h>
  83 #include <net/vlan/if_vlan_ether.h>
  84
  85 #include <dev/netif/mii_layer/mii.h>
  86 #include <dev/netif/mii_layer/miivar.h>
  87 #include <dev/netif/mii_layer/brgphyreg.h>
  88
  89 #include <bus/pci/pcireg.h>
  90 #include <bus/pci/pcivar.h>
  91
  92 #include "miibus_if.h"
  93
  94 #include <dev/netif/bce/if_bcereg.h>
  95 #include <dev/netif/bce/if_bcefw.h>
  96
  97 /****************************************************************************/
  98 /* BCE Debug Options                                                        */
  99 /****************************************************************************/
 100 #ifdef BCE_DEBUG
 101
 102 static uint32_t bce_debug = BCE_WARN;
 103
 104 /*
 105  *          0 = Never
 106  *          1 = 1 in 2,147,483,648
 107  *        256 = 1 in     8,388,608
 108  *       2048 = 1 in     1,048,576
 109  *      65536 = 1 in        32,768
 110  *    1048576 = 1 in         2,048
 111  *  268435456 = 1 in             8
 112  *  536870912 = 1 in             4
 113  * 1073741824 = 1 in             2
 114  *
 115  * bce_debug_mbuf_allocation_failure:
 116  *     How often to simulate an mbuf allocation failure.
 117  *
 118  * bce_debug_dma_map_addr_failure:
 119  *     How often to simulate a DMA mapping failure.
 120  *
 121  * bce_debug_bootcode_running_failure:
 122  *     How often to simulate a bootcode failure.
 123  */
 124 static int      bce_debug_mbuf_allocation_failure = 0;
 125 static int      bce_debug_dma_map_addr_failure = 0;
 126 static int      bce_debug_bootcode_running_failure = 0;
 127
 128 #endif  /* BCE_DEBUG */
 129
 130
 131 /****************************************************************************/
 132 /* PCI Device ID Table                                                      */
 133 /*                                                                          */
 134 /* Used by bce_probe() to identify the devices supported by this driver.    */
 135 /****************************************************************************/
 136 #define BCE_DEVDESC_MAX         64
 137
 138 static struct bce_type bce_devs[] = {
 139         /* BCM5706C Controllers and OEM boards. */
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 141                 "HP NC370T Multifunction Gigabit Server Adapter" },
 142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 143                 "HP NC370i Multifunction Gigabit Server Adapter" },
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 145                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 147                 "HP NC371i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 149                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 150
 151         /* BCM5706S controllers and OEM boards. */
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 153                 "HP NC370F Multifunction Gigabit Server Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 155                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 156
 157         /* BCM5708C controllers and OEM boards. */
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 159                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 161                 "HP NC373i Multifunction Gigabit Server Adapter" },
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 163                 "HP NC374m PCIe Multifunction Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 165                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 166
 167         /* BCM5708S controllers and OEM boards. */
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 169                 "HP NC373m Multifunction Gigabit Server Adapter" },
 170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 171                 "HP NC373i Multifunction Gigabit Server Adapter" },
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 173                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 175                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 176
 177         /* BCM5709C controllers and OEM boards. */
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 179                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 181                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 183                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 184
 185         /* BCM5709S controllers and OEM boards. */
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 187                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 189                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 191                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 192
 193         /* BCM5716 controllers and OEM boards. */
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 196
 197         { 0, 0, 0, 0, NULL }
 198 };
 199
 200
 201 /****************************************************************************/
 202 /* Supported Flash NVRAM device data.                                       */
 203 /****************************************************************************/
 204 static const struct flash_spec flash_table[] =
 205 {
 206 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 207 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 208
 209         /* Slow EEPROM */
 210         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 211          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 212          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 213          "EEPROM - slow"},
 214         /* Expansion entry 0001 */
 215         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 216          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 217          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 218          "Entry 0001"},
 219         /* Saifun SA25F010 (non-buffered flash) */
 220         /* strap, cfg1, & write1 need updates */
 221         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 222          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 223          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 224          "Non-buffered flash (128kB)"},
 225         /* Saifun SA25F020 (non-buffered flash) */
 226         /* strap, cfg1, & write1 need updates */
 227         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 228          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 229          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 230          "Non-buffered flash (256kB)"},
 231         /* Expansion entry 0100 */
 232         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 233          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 234          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 235          "Entry 0100"},
 236         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 237         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 238          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 239          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 240          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 241         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 242         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 243          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 244          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 245          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 246         /* Saifun SA25F005 (non-buffered flash) */
 247         /* strap, cfg1, & write1 need updates */
 248         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 249          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 250          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 251          "Non-buffered flash (64kB)"},
 252         /* Fast EEPROM */
 253         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 254          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 255          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 256          "EEPROM - fast"},
 257         /* Expansion entry 1001 */
 258         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 259          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 260          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 261          "Entry 1001"},
 262         /* Expansion entry 1010 */
 263         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 264          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 265          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 266          "Entry 1010"},
 267         /* ATMEL AT45DB011B (buffered flash) */
 268         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 269          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 270          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 271          "Buffered flash (128kB)"},
 272         /* Expansion entry 1100 */
 273         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 274          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 275          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 276          "Entry 1100"},
 277         /* Expansion entry 1101 */
 278         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 279          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 280          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 281          "Entry 1101"},
 282         /* Ateml Expansion entry 1110 */
 283         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 284          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 285          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 286          "Entry 1110 (Atmel)"},
 287         /* ATMEL AT45DB021B (buffered flash) */
 288         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 289          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 290          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 291          "Buffered flash (256kB)"},
 292 };
 293
 294 /*
 295  * The BCM5709 controllers transparently handle the
 296  * differences between Atmel 264 byte pages and all
 297  * flash devices which use 256 byte pages, so no
 298  * logical-to-physical mapping is required in the
 299  * driver.
 300  */
 301 static struct flash_spec flash_5709 = {
 302         .flags          = BCE_NV_BUFFERED,
 303         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 304         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 305         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 306         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 307         .name           = "5709/5716 buffered flash (256kB)",
 308 };
 309
 310
 311 /****************************************************************************/
 312 /* DragonFly device entry points.                                           */
 313 /****************************************************************************/
 314 static int      bce_probe(device_t);
 315 static int      bce_attach(device_t);
 316 static int      bce_detach(device_t);
 317 static void     bce_shutdown(device_t);
 318
 319 /****************************************************************************/
 320 /* BCE Debug Data Structure Dump Routines                                   */
 321 /****************************************************************************/
 322 #ifdef BCE_DEBUG
 323 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 324 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 325 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 326 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 327 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 328                                 struct l2_fhdr *) __unused;
 329 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 331 static void     bce_dump_status_block(struct bce_softc *);
 332 static void     bce_dump_driver_state(struct bce_softc *);
 333 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 334 static void     bce_dump_hw_state(struct bce_softc *);
 335 static void     bce_dump_txp_state(struct bce_softc *);
 336 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 337 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 338 static void     bce_freeze_controller(struct bce_softc *) __unused;
 339 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 340 static void     bce_breakpoint(struct bce_softc *);
 341 #endif  /* BCE_DEBUG */
 342
 343
 344 /****************************************************************************/
 345 /* BCE Register/Memory Access Routines                                      */
 346 /****************************************************************************/
 347 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 348 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 349 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 350 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 351 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 352 static int      bce_miibus_read_reg(device_t, int, int);
 353 static int      bce_miibus_write_reg(device_t, int, int, int);
 354 static void     bce_miibus_statchg(device_t);
 355
 356
 357 /****************************************************************************/
 358 /* BCE NVRAM Access Routines                                                */
 359 /****************************************************************************/
 360 static int      bce_acquire_nvram_lock(struct bce_softc *);
 361 static int      bce_release_nvram_lock(struct bce_softc *);
 362 static void     bce_enable_nvram_access(struct bce_softc *);
 363 static void     bce_disable_nvram_access(struct bce_softc *);
 364 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 365                                      uint32_t);
 366 static int      bce_init_nvram(struct bce_softc *);
 367 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 368 static int      bce_nvram_test(struct bce_softc *);
 369
 370 /****************************************************************************/
 371 /* BCE DMA Allocate/Free Routines                                           */
 372 /****************************************************************************/
 373 static int      bce_dma_alloc(struct bce_softc *);
 374 static void     bce_dma_free(struct bce_softc *);
 375 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 376
 377 /****************************************************************************/
 378 /* BCE Firmware Synchronization and Load                                    */
 379 /****************************************************************************/
 380 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 381 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 382                                  uint32_t, uint32_t);
 383 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 384                                 struct fw_info *);
 385 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 386 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 387 static void     bce_start_rxp_cpu(struct bce_softc *);
 388 static void     bce_init_rxp_cpu(struct bce_softc *);
 389 static void     bce_init_txp_cpu(struct bce_softc *);
 390 static void     bce_init_tpat_cpu(struct bce_softc *);
 391 static void     bce_init_cp_cpu(struct bce_softc *);
 392 static void     bce_init_com_cpu(struct bce_softc *);
 393 static void     bce_init_cpus(struct bce_softc *);
 394
 395 static void     bce_stop(struct bce_softc *);
 396 static int      bce_reset(struct bce_softc *, uint32_t);
 397 static int      bce_chipinit(struct bce_softc *);
 398 static int      bce_blockinit(struct bce_softc *);
 399 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 400                                uint32_t *, int);
 401 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 402 static void     bce_probe_pci_caps(struct bce_softc *);
 403 static void     bce_print_adapter_info(struct bce_softc *);
 404 static void     bce_get_media(struct bce_softc *);
 405
 406 static void     bce_init_tx_context(struct bce_softc *);
 407 static int      bce_init_tx_chain(struct bce_softc *);
 408 static void     bce_init_rx_context(struct bce_softc *);
 409 static int      bce_init_rx_chain(struct bce_softc *);
 410 static void     bce_free_rx_chain(struct bce_softc *);
 411 static void     bce_free_tx_chain(struct bce_softc *);
 412
 413 static int      bce_encap(struct bce_softc *, struct mbuf **);
 414 static int      bce_tso_setup(struct bce_softc *, struct mbuf **,
 415                     uint16_t *, uint16_t *);
 416 static void     bce_start(struct ifnet *);
 417 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 418 static void     bce_watchdog(struct ifnet *);
 419 static int      bce_ifmedia_upd(struct ifnet *);
 420 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 421 static void     bce_init(void *);
 422 static void     bce_mgmt_init(struct bce_softc *);
 423
 424 static int      bce_init_ctx(struct bce_softc *);
 425 static void     bce_get_mac_addr(struct bce_softc *);
 426 static void     bce_set_mac_addr(struct bce_softc *);
 427 static void     bce_phy_intr(struct bce_softc *);
 428 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
 429 static void     bce_tx_intr(struct bce_softc *, uint16_t);
 430 static void     bce_disable_intr(struct bce_softc *);
 431 static void     bce_enable_intr(struct bce_softc *);
 432 static void     bce_reenable_intr(struct bce_softc *);
 433
 434 #ifdef DEVICE_POLLING
 435 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 436 #endif
 437 static void     bce_intr(struct bce_softc *);
 438 static void     bce_intr_legacy(void *);
 439 static void     bce_intr_msi(void *);
 440 static void     bce_intr_msi_oneshot(void *);
 441 static void     bce_set_rx_mode(struct bce_softc *);
 442 static void     bce_stats_update(struct bce_softc *);
 443 static void     bce_tick(void *);
 444 static void     bce_tick_serialized(struct bce_softc *);
 445 static void     bce_pulse(void *);
 446 static void     bce_pulse_check_msi(struct bce_softc *);
 447 static void     bce_add_sysctls(struct bce_softc *);
 448
 449 static void     bce_coal_change(struct bce_softc *);
 450 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 451 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 452 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 453 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 454 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 457 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 458 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 459                                        uint32_t *, uint32_t);
 460
 461 /*
 462  * NOTE:
 463  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 464  * takes 1023 as the TX ticks limit.  However, using 1023 will
 465  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 466  * there is _no_ network activity on the NIC.
 467  */
 468 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 469 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 470 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 471 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 472 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 473 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 474 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
 475 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
 476
 477 static int      bce_msi_enable = 1;
 478
 479 static int      bce_rx_pages = RX_PAGES_DEFAULT;
 480 static int      bce_tx_pages = TX_PAGES_DEFAULT;
 481
 482 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 483 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 484 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 485 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 486 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 487 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 488 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 489 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 490 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 491 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 492 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 493
 494 /****************************************************************************/
 495 /* DragonFly device dispatch table.                                         */
 496 /****************************************************************************/
 497 static device_method_t bce_methods[] = {
 498         /* Device interface */
 499         DEVMETHOD(device_probe,         bce_probe),
 500         DEVMETHOD(device_attach,        bce_attach),
 501         DEVMETHOD(device_detach,        bce_detach),
 502         DEVMETHOD(device_shutdown,      bce_shutdown),
 503
 504         /* bus interface */
 505         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 506         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 507
 508         /* MII interface */
 509         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 510         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 511         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 512
 513         { 0, 0 }
 514 };
 515
 516 static driver_t bce_driver = {
 517         "bce",
 518         bce_methods,
 519         sizeof(struct bce_softc)
 520 };
 521
 522 static devclass_t bce_devclass;
 523
 524
 525 DECLARE_DUMMY_MODULE(if_bce);
 526 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 527 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 528 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 529
 530
 531 /****************************************************************************/
 532 /* Device probe function.                                                   */
 533 /*                                                                          */
 534 /* Compares the device to the driver's list of supported devices and        */
 535 /* reports back to the OS whether this is the right driver for the device.  */
 536 /*                                                                          */
 537 /* Returns:                                                                 */
 538 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 539 /****************************************************************************/
 540 static int
 541 bce_probe(device_t dev)
 542 {
 543         struct bce_type *t;
 544         uint16_t vid, did, svid, sdid;
 545
 546         /* Get the data for the device to be probed. */
 547         vid  = pci_get_vendor(dev);
 548         did  = pci_get_device(dev);
 549         svid = pci_get_subvendor(dev);
 550         sdid = pci_get_subdevice(dev);
 551
 552         /* Look through the list of known devices for a match. */
 553         for (t = bce_devs; t->bce_name != NULL; ++t) {
 554                 if (vid == t->bce_vid && did == t->bce_did &&
 555                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 556                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 557                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 558                         char *descbuf;
 559
 560                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 561
 562                         /* Print out the device identity. */
 563                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 564                                   t->bce_name,
 565                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 566
 567                         device_set_desc_copy(dev, descbuf);
 568                         kfree(descbuf, M_TEMP);
 569                         return 0;
 570                 }
 571         }
 572         return ENXIO;
 573 }
 574
 575
 576 /****************************************************************************/
 577 /* PCI Capabilities Probe Function.                                         */
 578 /*                                                                          */
 579 /* Walks the PCI capabiites list for the device to find what features are   */
 580 /* supported.                                                               */
 581 /*                                                                          */
 582 /* Returns:                                                                 */
 583 /*   None.                                                                  */
 584 /****************************************************************************/
 585 static void
 586 bce_print_adapter_info(struct bce_softc *sc)
 587 {
 588         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 589
 590         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 591                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 592
 593         /* Bus info. */
 594         if (sc->bce_flags & BCE_PCIE_FLAG) {
 595                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 596                 switch (sc->link_speed) {
 597                 case 1:
 598                         kprintf("2.5Gbps); ");
 599                         break;
 600                 case 2:
 601                         kprintf("5Gbps); ");
 602                         break;
 603                 default:
 604                         kprintf("Unknown link speed); ");
 605                         break;
 606                 }
 607         } else {
 608                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 609                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 610                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 611                     sc->bus_speed_mhz);
 612         }
 613
 614         /* Firmware version and device features. */
 615         kprintf("B/C (%s)", sc->bce_bc_ver);
 616
 617         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 618             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 619                 kprintf("; Flags(");
 620                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 621                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 622                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 623                         kprintf(" 2.5G");
 624                 kprintf(")");
 625         }
 626         kprintf("\n");
 627 }
 628
 629
 630 /****************************************************************************/
 631 /* PCI Capabilities Probe Function.                                         */
 632 /*                                                                          */
 633 /* Walks the PCI capabiites list for the device to find what features are   */
 634 /* supported.                                                               */
 635 /*                                                                          */
 636 /* Returns:                                                                 */
 637 /*   None.                                                                  */
 638 /****************************************************************************/
 639 static void
 640 bce_probe_pci_caps(struct bce_softc *sc)
 641 {
 642         device_t dev = sc->bce_dev;
 643         uint8_t ptr;
 644
 645         if (pci_is_pcix(dev))
 646                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 647
 648         ptr = pci_get_pciecap_ptr(dev);
 649         if (ptr) {
 650                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 651
 652                 sc->link_speed = link_status & 0xf;
 653                 sc->link_width = (link_status >> 4) & 0x3f;
 654                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 655                 sc->bce_flags |= BCE_PCIE_FLAG;
 656         }
 657 }
 658
 659
 660 /****************************************************************************/
 661 /* Device attach function.                                                  */
 662 /*                                                                          */
 663 /* Allocates device resources, performs secondary chip identification,      */
 664 /* resets and initializes the hardware, and initializes driver instance     */
 665 /* variables.                                                               */
 666 /*                                                                          */
 667 /* Returns:                                                                 */
 668 /*   0 on success, positive value on failure.                               */
 669 /****************************************************************************/
 670 static int
 671 bce_attach(device_t dev)
 672 {
 673         struct bce_softc *sc = device_get_softc(dev);
 674         struct ifnet *ifp = &sc->arpcom.ac_if;
 675         uint32_t val;
 676         u_int irq_flags;
 677         void (*irq_handle)(void *);
 678         int rid, rc = 0;
 679         int i, j;
 680         struct mii_probe_args mii_args;
 681         uintptr_t mii_priv = 0;
 682
 683         sc->bce_dev = dev;
 684         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 685
 686         pci_enable_busmaster(dev);
 687
 688         bce_probe_pci_caps(sc);
 689
 690         /* Allocate PCI memory resources. */
 691         rid = PCIR_BAR(0);
 692         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 693                                                  RF_ACTIVE | PCI_RF_DENSE);
 694         if (sc->bce_res_mem == NULL) {
 695                 device_printf(dev, "PCI memory allocation failed\n");
 696                 return ENXIO;
 697         }
 698         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 699         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 700
 701         /* Allocate PCI IRQ resources. */
 702         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 703             &sc->bce_irq_rid, &irq_flags);
 704
 705         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 706             &sc->bce_irq_rid, irq_flags);
 707         if (sc->bce_res_irq == NULL) {
 708                 device_printf(dev, "PCI map interrupt failed\n");
 709                 rc = ENXIO;
 710                 goto fail;
 711         }
 712
 713         /*
 714          * Configure byte swap and enable indirect register access.
 715          * Rely on CPU to do target byte swapping on big endian systems.
 716          * Access to registers outside of PCI configurtion space are not
 717          * valid until this is done.
 718          */
 719         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 720                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 721                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 722
 723         /* Save ASIC revsion info. */
 724         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 725
 726         /* Weed out any non-production controller revisions. */
 727         switch (BCE_CHIP_ID(sc)) {
 728         case BCE_CHIP_ID_5706_A0:
 729         case BCE_CHIP_ID_5706_A1:
 730         case BCE_CHIP_ID_5708_A0:
 731         case BCE_CHIP_ID_5708_B0:
 732         case BCE_CHIP_ID_5709_A0:
 733         case BCE_CHIP_ID_5709_B0:
 734         case BCE_CHIP_ID_5709_B1:
 735 #ifdef foo
 736         /* 5709C B2 seems to work fine */
 737         case BCE_CHIP_ID_5709_B2:
 738 #endif
 739                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 740                               BCE_CHIP_ID(sc));
 741                 rc = ENODEV;
 742                 goto fail;
 743         }
 744
 745         mii_priv |= BRGPHY_FLAG_WIRESPEED;
 746         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 747                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
 748                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
 749                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
 750         } else {
 751                 mii_priv |= BRGPHY_FLAG_BER_BUG;
 752         }
 753
 754         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
 755                 irq_handle = bce_intr_legacy;
 756         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
 757                 irq_handle = bce_intr_msi;
 758                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 759                         irq_handle = bce_intr_msi_oneshot;
 760                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
 761                 }
 762         } else {
 763                 panic("%s: unsupported intr type %d",
 764                     device_get_nameunit(dev), sc->bce_irq_type);
 765         }
 766
 767         /*
 768          * Find the base address for shared memory access.
 769          * Newer versions of bootcode use a signature and offset
 770          * while older versions use a fixed address.
 771          */
 772         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 773         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 774             BCE_SHM_HDR_SIGNATURE_SIG) {
 775                 /* Multi-port devices use different offsets in shared memory. */
 776                 sc->bce_shmem_base = REG_RD_IND(sc,
 777                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 778         } else {
 779                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 780         }
 781         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 782
 783         /* Fetch the bootcode revision. */
 784         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 785         for (i = 0, j = 0; i < 3; i++) {
 786                 uint8_t num;
 787                 int k, skip0;
 788
 789                 num = (uint8_t)(val >> (24 - (i * 8)));
 790                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 791                         if (num >= k || !skip0 || k == 1) {
 792                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 793                                 skip0 = 0;
 794                         }
 795                 }
 796                 if (i != 2)
 797                         sc->bce_bc_ver[j++] = '.';
 798         }
 799
 800         /* Check if any management firwmare is running. */
 801         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 802         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 803                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 804
 805                 /* Allow time for firmware to enter the running state. */
 806                 for (i = 0; i < 30; i++) {
 807                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 808                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 809                                 break;
 810                         DELAY(10000);
 811                 }
 812         }
 813
 814         /* Check the current bootcode state. */
 815         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 816             BCE_CONDITION_MFW_RUN_MASK;
 817         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 818             val != BCE_CONDITION_MFW_RUN_NONE) {
 819                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 820
 821                 for (i = 0, j = 0; j < 3; j++) {
 822                         val = bce_reg_rd_ind(sc, addr + j * 4);
 823                         val = bswap32(val);
 824                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 825                         i += 4;
 826                 }
 827         }
 828
 829         /* Get PCI bus information (speed and type). */
 830         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 831         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 832                 uint32_t clkreg;
 833
 834                 sc->bce_flags |= BCE_PCIX_FLAG;
 835
 836                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 837                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 838                 switch (clkreg) {
 839                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 840                         sc->bus_speed_mhz = 133;
 841                         break;
 842
 843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 844                         sc->bus_speed_mhz = 100;
 845                         break;
 846
 847                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 848                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 849                         sc->bus_speed_mhz = 66;
 850                         break;
 851
 852                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 853                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 854                         sc->bus_speed_mhz = 50;
 855                         break;
 856
 857                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 858                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 859                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 860                         sc->bus_speed_mhz = 33;
 861                         break;
 862                 }
 863         } else {
 864                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 865                         sc->bus_speed_mhz = 66;
 866                 else
 867                         sc->bus_speed_mhz = 33;
 868         }
 869
 870         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 871                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 872
 873         /* Reset the controller. */
 874         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 875         if (rc != 0)
 876                 goto fail;
 877
 878         /* Initialize the controller. */
 879         rc = bce_chipinit(sc);
 880         if (rc != 0) {
 881                 device_printf(dev, "Controller initialization failed!\n");
 882                 goto fail;
 883         }
 884
 885         /* Perform NVRAM test. */
 886         rc = bce_nvram_test(sc);
 887         if (rc != 0) {
 888                 device_printf(dev, "NVRAM test failed!\n");
 889                 goto fail;
 890         }
 891
 892         /* Fetch the permanent Ethernet MAC address. */
 893         bce_get_mac_addr(sc);
 894
 895         /*
 896          * Trip points control how many BDs
 897          * should be ready before generating an
 898          * interrupt while ticks control how long
 899          * a BD can sit in the chain before
 900          * generating an interrupt.  Set the default
 901          * values for the RX and TX rings.
 902          */
 903
 904 #ifdef BCE_DRBUG
 905         /* Force more frequent interrupts. */
 906         sc->bce_tx_quick_cons_trip_int = 1;
 907         sc->bce_tx_quick_cons_trip     = 1;
 908         sc->bce_tx_ticks_int           = 0;
 909         sc->bce_tx_ticks               = 0;
 910
 911         sc->bce_rx_quick_cons_trip_int = 1;
 912         sc->bce_rx_quick_cons_trip     = 1;
 913         sc->bce_rx_ticks_int           = 0;
 914         sc->bce_rx_ticks               = 0;
 915 #else
 916         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 917         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 918         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 919         sc->bce_tx_ticks               = bce_tx_ticks;
 920
 921         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 922         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 923         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 924         sc->bce_rx_ticks               = bce_rx_ticks;
 925 #endif
 926
 927         /* Update statistics once every second. */
 928         sc->bce_stats_ticks = 1000000 & 0xffff00;
 929
 930         /* Find the media type for the adapter. */
 931         bce_get_media(sc);
 932
 933         /* Allocate DMA memory resources. */
 934         rc = bce_dma_alloc(sc);
 935         if (rc != 0) {
 936                 device_printf(dev, "DMA resource allocation failed!\n");
 937                 goto fail;
 938         }
 939
 940         /* Initialize the ifnet interface. */
 941         ifp->if_softc = sc;
 942         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 943         ifp->if_ioctl = bce_ioctl;
 944         ifp->if_start = bce_start;
 945         ifp->if_init = bce_init;
 946         ifp->if_watchdog = bce_watchdog;
 947 #ifdef DEVICE_POLLING
 948         ifp->if_poll = bce_poll;
 949 #endif
 950         ifp->if_mtu = ETHERMTU;
 951         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
 952         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 953         ifp->if_capenable = ifp->if_capabilities;
 954         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
 955         ifq_set_ready(&ifp->if_snd);
 956
 957         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 958                 ifp->if_baudrate = IF_Gbps(2.5);
 959         else
 960                 ifp->if_baudrate = IF_Gbps(1);
 961
 962         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 963         sc->mbuf_alloc_size  = MCLBYTES;
 964
 965         /*
 966          * Look for our PHY.
 967          */
 968         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
 969         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
 970         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
 971         mii_args.mii_priv = mii_priv;
 972
 973         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
 974         if (rc != 0) {
 975                 device_printf(dev, "PHY probe failed!\n");
 976                 goto fail;
 977         }
 978
 979         /* Attach to the Ethernet interface list. */
 980         ether_ifattach(ifp, sc->eaddr, NULL);
 981
 982         callout_init_mp(&sc->bce_tick_callout);
 983         callout_init_mp(&sc->bce_pulse_callout);
 984
 985         /* Hookup IRQ last. */
 986         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
 987                             &sc->bce_intrhand, ifp->if_serializer);
 988         if (rc != 0) {
 989                 device_printf(dev, "Failed to setup IRQ!\n");
 990                 ether_ifdetach(ifp);
 991                 goto fail;
 992         }
 993
 994         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
 995         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 996
 997         /* Print some important debugging info. */
 998         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 999
1000         /* Add the supported sysctls to the kernel. */
1001         bce_add_sysctls(sc);
1002
1003         /*
1004          * The chip reset earlier notified the bootcode that
1005          * a driver is present.  We now need to start our pulse
1006          * routine so that the bootcode is reminded that we're
1007          * still running.
1008          */
1009         bce_pulse(sc);
1010
1011         /* Get the firmware running so IPMI still works */
1012         bce_mgmt_init(sc);
1013
1014         if (bootverbose)
1015                 bce_print_adapter_info(sc);
1016
1017         return 0;
1018 fail:
1019         bce_detach(dev);
1020         return(rc);
1021 }
1022
1023
1024 /****************************************************************************/
1025 /* Device detach function.                                                  */
1026 /*                                                                          */
1027 /* Stops the controller, resets the controller, and releases resources.     */
1028 /*                                                                          */
1029 /* Returns:                                                                 */
1030 /*   0 on success, positive value on failure.                               */
1031 /****************************************************************************/
1032 static int
1033 bce_detach(device_t dev)
1034 {
1035         struct bce_softc *sc = device_get_softc(dev);
1036
1037         if (device_is_attached(dev)) {
1038                 struct ifnet *ifp = &sc->arpcom.ac_if;
1039                 uint32_t msg;
1040
1041                 /* Stop and reset the controller. */
1042                 lwkt_serialize_enter(ifp->if_serializer);
1043                 callout_stop(&sc->bce_pulse_callout);
1044                 bce_stop(sc);
1045                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1046                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1047                 else
1048                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1049                 bce_reset(sc, msg);
1050                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1051                 lwkt_serialize_exit(ifp->if_serializer);
1052
1053                 ether_ifdetach(ifp);
1054         }
1055
1056         /* If we have a child device on the MII bus remove it too. */
1057         if (sc->bce_miibus)
1058                 device_delete_child(dev, sc->bce_miibus);
1059         bus_generic_detach(dev);
1060
1061         if (sc->bce_res_irq != NULL) {
1062                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1063                     sc->bce_res_irq);
1064         }
1065
1066         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1067                 pci_release_msi(dev);
1068
1069         if (sc->bce_res_mem != NULL) {
1070                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1071                                      sc->bce_res_mem);
1072         }
1073
1074         bce_dma_free(sc);
1075
1076         if (sc->bce_sysctl_tree != NULL)
1077                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1078
1079         return 0;
1080 }
1081
1082
1083 /****************************************************************************/
1084 /* Device shutdown function.                                                */
1085 /*                                                                          */
1086 /* Stops and resets the controller.                                         */
1087 /*                                                                          */
1088 /* Returns:                                                                 */
1089 /*   Nothing                                                                */
1090 /****************************************************************************/
1091 static void
1092 bce_shutdown(device_t dev)
1093 {
1094         struct bce_softc *sc = device_get_softc(dev);
1095         struct ifnet *ifp = &sc->arpcom.ac_if;
1096         uint32_t msg;
1097
1098         lwkt_serialize_enter(ifp->if_serializer);
1099         bce_stop(sc);
1100         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1101                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1102         else
1103                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1104         bce_reset(sc, msg);
1105         lwkt_serialize_exit(ifp->if_serializer);
1106 }
1107
1108
1109 /****************************************************************************/
1110 /* Indirect register read.                                                  */
1111 /*                                                                          */
1112 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1113 /* configuration space.  Using this mechanism avoids issues with posted     */
1114 /* reads but is much slower than memory-mapped I/O.                         */
1115 /*                                                                          */
1116 /* Returns:                                                                 */
1117 /*   The value of the register.                                             */
1118 /****************************************************************************/
1119 static uint32_t
1120 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1121 {
1122         device_t dev = sc->bce_dev;
1123
1124         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1125 #ifdef BCE_DEBUG
1126         {
1127                 uint32_t val;
1128                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1129                 DBPRINT(sc, BCE_EXCESSIVE,
1130                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1131                         __func__, offset, val);
1132                 return val;
1133         }
1134 #else
1135         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1136 #endif
1137 }
1138
1139
1140 /****************************************************************************/
1141 /* Indirect register write.                                                 */
1142 /*                                                                          */
1143 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1144 /* configuration space.  Using this mechanism avoids issues with posted     */
1145 /* writes but is muchh slower than memory-mapped I/O.                       */
1146 /*                                                                          */
1147 /* Returns:                                                                 */
1148 /*   Nothing.                                                               */
1149 /****************************************************************************/
1150 static void
1151 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1152 {
1153         device_t dev = sc->bce_dev;
1154
1155         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1156                 __func__, offset, val);
1157
1158         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1159         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1160 }
1161
1162
1163 /****************************************************************************/
1164 /* Shared memory write.                                                     */
1165 /*                                                                          */
1166 /* Writes NetXtreme II shared memory region.                                */
1167 /*                                                                          */
1168 /* Returns:                                                                 */
1169 /*   Nothing.                                                               */
1170 /****************************************************************************/
1171 static void
1172 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1173 {
1174         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1175 }
1176
1177
1178 /****************************************************************************/
1179 /* Shared memory read.                                                      */
1180 /*                                                                          */
1181 /* Reads NetXtreme II shared memory region.                                 */
1182 /*                                                                          */
1183 /* Returns:                                                                 */
1184 /*   The 32 bit value read.                                                 */
1185 /****************************************************************************/
1186 static u32
1187 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1188 {
1189         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1190 }
1191
1192
1193 /****************************************************************************/
1194 /* Context memory write.                                                    */
1195 /*                                                                          */
1196 /* The NetXtreme II controller uses context memory to track connection      */
1197 /* information for L2 and higher network protocols.                         */
1198 /*                                                                          */
1199 /* Returns:                                                                 */
1200 /*   Nothing.                                                               */
1201 /****************************************************************************/
1202 static void
1203 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1204     uint32_t ctx_val)
1205 {
1206         uint32_t idx, offset = ctx_offset + cid_addr;
1207         uint32_t val, retry_cnt = 5;
1208
1209         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1210             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1211                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1212                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1213
1214                 for (idx = 0; idx < retry_cnt; idx++) {
1215                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1216                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1217                                 break;
1218                         DELAY(5);
1219                 }
1220
1221                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1222                         device_printf(sc->bce_dev,
1223                             "Unable to write CTX memory: "
1224                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1225                             cid_addr, ctx_offset);
1226                 }
1227         } else {
1228                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1229                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1230         }
1231 }
1232
1233
1234 /****************************************************************************/
1235 /* PHY register read.                                                       */
1236 /*                                                                          */
1237 /* Implements register reads on the MII bus.                                */
1238 /*                                                                          */
1239 /* Returns:                                                                 */
1240 /*   The value of the register.                                             */
1241 /****************************************************************************/
1242 static int
1243 bce_miibus_read_reg(device_t dev, int phy, int reg)
1244 {
1245         struct bce_softc *sc = device_get_softc(dev);
1246         uint32_t val;
1247         int i;
1248
1249         /* Make sure we are accessing the correct PHY address. */
1250         KASSERT(phy == sc->bce_phy_addr,
1251             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1252
1253         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1254                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1255                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1256
1257                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1258                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1259
1260                 DELAY(40);
1261         }
1262
1263         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1264               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1265               BCE_EMAC_MDIO_COMM_START_BUSY;
1266         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1267
1268         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1269                 DELAY(10);
1270
1271                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1272                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1273                         DELAY(5);
1274
1275                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1276                         val &= BCE_EMAC_MDIO_COMM_DATA;
1277                         break;
1278                 }
1279         }
1280
1281         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1282                 if_printf(&sc->arpcom.ac_if,
1283                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1284                           phy, reg);
1285                 val = 0x0;
1286         } else {
1287                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1288         }
1289
1290         DBPRINT(sc, BCE_EXCESSIVE,
1291                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1292                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1293
1294         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1295                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1296                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1297
1298                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1299                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1300
1301                 DELAY(40);
1302         }
1303         return (val & 0xffff);
1304 }
1305
1306
1307 /****************************************************************************/
1308 /* PHY register write.                                                      */
1309 /*                                                                          */
1310 /* Implements register writes on the MII bus.                               */
1311 /*                                                                          */
1312 /* Returns:                                                                 */
1313 /*   The value of the register.                                             */
1314 /****************************************************************************/
1315 static int
1316 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1317 {
1318         struct bce_softc *sc = device_get_softc(dev);
1319         uint32_t val1;
1320         int i;
1321
1322         /* Make sure we are accessing the correct PHY address. */
1323         KASSERT(phy == sc->bce_phy_addr,
1324             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1325
1326         DBPRINT(sc, BCE_EXCESSIVE,
1327                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1328                 __func__, phy, (uint16_t)(reg & 0xffff),
1329                 (uint16_t)(val & 0xffff));
1330
1331         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1332                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1333                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1334
1335                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1336                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1337
1338                 DELAY(40);
1339         }
1340
1341         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1342                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1343                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1344         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1345
1346         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1347                 DELAY(10);
1348
1349                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1350                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1351                         DELAY(5);
1352                         break;
1353                 }
1354         }
1355
1356         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1357                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1358
1359         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1360                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1361                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1362
1363                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1364                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1365
1366                 DELAY(40);
1367         }
1368         return 0;
1369 }
1370
1371
1372 /****************************************************************************/
1373 /* MII bus status change.                                                   */
1374 /*                                                                          */
1375 /* Called by the MII bus driver when the PHY establishes link to set the    */
1376 /* MAC interface registers.                                                 */
1377 /*                                                                          */
1378 /* Returns:                                                                 */
1379 /*   Nothing.                                                               */
1380 /****************************************************************************/
1381 static void
1382 bce_miibus_statchg(device_t dev)
1383 {
1384         struct bce_softc *sc = device_get_softc(dev);
1385         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1386
1387         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1388                 mii->mii_media_active);
1389
1390 #ifdef BCE_DEBUG
1391         /* Decode the interface media flags. */
1392         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1393         switch(IFM_TYPE(mii->mii_media_active)) {
1394         case IFM_ETHER:
1395                 kprintf("Ethernet )");
1396                 break;
1397         default:
1398                 kprintf("Unknown )");
1399                 break;
1400         }
1401
1402         kprintf(" Media Options: ( ");
1403         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1404         case IFM_AUTO:
1405                 kprintf("Autoselect )");
1406                 break;
1407         case IFM_MANUAL:
1408                 kprintf("Manual )");
1409                 break;
1410         case IFM_NONE:
1411                 kprintf("None )");
1412                 break;
1413         case IFM_10_T:
1414                 kprintf("10Base-T )");
1415                 break;
1416         case IFM_100_TX:
1417                 kprintf("100Base-TX )");
1418                 break;
1419         case IFM_1000_SX:
1420                 kprintf("1000Base-SX )");
1421                 break;
1422         case IFM_1000_T:
1423                 kprintf("1000Base-T )");
1424                 break;
1425         default:
1426                 kprintf("Other )");
1427                 break;
1428         }
1429
1430         kprintf(" Global Options: (");
1431         if (mii->mii_media_active & IFM_FDX)
1432                 kprintf(" FullDuplex");
1433         if (mii->mii_media_active & IFM_HDX)
1434                 kprintf(" HalfDuplex");
1435         if (mii->mii_media_active & IFM_LOOP)
1436                 kprintf(" Loopback");
1437         if (mii->mii_media_active & IFM_FLAG0)
1438                 kprintf(" Flag0");
1439         if (mii->mii_media_active & IFM_FLAG1)
1440                 kprintf(" Flag1");
1441         if (mii->mii_media_active & IFM_FLAG2)
1442                 kprintf(" Flag2");
1443         kprintf(" )\n");
1444 #endif
1445
1446         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1447
1448         /*
1449          * Set MII or GMII interface based on the speed negotiated
1450          * by the PHY.
1451          */
1452         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1453             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1454                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1455                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1456         } else {
1457                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1458                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1459         }
1460
1461         /*
1462          * Set half or full duplex based on the duplicity negotiated
1463          * by the PHY.
1464          */
1465         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1466                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1467                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1468         } else {
1469                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1470                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1471         }
1472 }
1473
1474
1475 /****************************************************************************/
1476 /* Acquire NVRAM lock.                                                      */
1477 /*                                                                          */
1478 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1479 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1480 /* for use by the driver.                                                   */
1481 /*                                                                          */
1482 /* Returns:                                                                 */
1483 /*   0 on success, positive value on failure.                               */
1484 /****************************************************************************/
1485 static int
1486 bce_acquire_nvram_lock(struct bce_softc *sc)
1487 {
1488         uint32_t val;
1489         int j;
1490
1491         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1492
1493         /* Request access to the flash interface. */
1494         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1495         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1496                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1497                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1498                         break;
1499
1500                 DELAY(5);
1501         }
1502
1503         if (j >= NVRAM_TIMEOUT_COUNT) {
1504                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1505                 return EBUSY;
1506         }
1507         return 0;
1508 }
1509
1510
1511 /****************************************************************************/
1512 /* Release NVRAM lock.                                                      */
1513 /*                                                                          */
1514 /* When the caller is finished accessing NVRAM the lock must be released.   */
1515 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1516 /* for use by the driver.                                                   */
1517 /*                                                                          */
1518 /* Returns:                                                                 */
1519 /*   0 on success, positive value on failure.                               */
1520 /****************************************************************************/
1521 static int
1522 bce_release_nvram_lock(struct bce_softc *sc)
1523 {
1524         int j;
1525         uint32_t val;
1526
1527         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1528
1529         /*
1530          * Relinquish nvram interface.
1531          */
1532         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1533
1534         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1535                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1536                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1537                         break;
1538
1539                 DELAY(5);
1540         }
1541
1542         if (j >= NVRAM_TIMEOUT_COUNT) {
1543                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1544                 return EBUSY;
1545         }
1546         return 0;
1547 }
1548
1549
1550 /****************************************************************************/
1551 /* Enable NVRAM access.                                                     */
1552 /*                                                                          */
1553 /* Before accessing NVRAM for read or write operations the caller must      */
1554 /* enabled NVRAM access.                                                    */
1555 /*                                                                          */
1556 /* Returns:                                                                 */
1557 /*   Nothing.                                                               */
1558 /****************************************************************************/
1559 static void
1560 bce_enable_nvram_access(struct bce_softc *sc)
1561 {
1562         uint32_t val;
1563
1564         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1565
1566         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1567         /* Enable both bits, even on read. */
1568         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1569                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1570 }
1571
1572
1573 /****************************************************************************/
1574 /* Disable NVRAM access.                                                    */
1575 /*                                                                          */
1576 /* When the caller is finished accessing NVRAM access must be disabled.     */
1577 /*                                                                          */
1578 /* Returns:                                                                 */
1579 /*   Nothing.                                                               */
1580 /****************************************************************************/
1581 static void
1582 bce_disable_nvram_access(struct bce_softc *sc)
1583 {
1584         uint32_t val;
1585
1586         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1587
1588         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1589
1590         /* Disable both bits, even after read. */
1591         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1592                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1593 }
1594
1595
1596 /****************************************************************************/
1597 /* Read a dword (32 bits) from NVRAM.                                       */
1598 /*                                                                          */
1599 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1600 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1601 /*                                                                          */
1602 /* Returns:                                                                 */
1603 /*   0 on success and the 32 bit value read, positive value on failure.     */
1604 /****************************************************************************/
1605 static int
1606 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1607                      uint32_t cmd_flags)
1608 {
1609         uint32_t cmd;
1610         int i, rc = 0;
1611
1612         /* Build the command word. */
1613         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1614
1615         /* Calculate the offset for buffered flash. */
1616         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1617                 offset = ((offset / sc->bce_flash_info->page_size) <<
1618                           sc->bce_flash_info->page_bits) +
1619                          (offset % sc->bce_flash_info->page_size);
1620         }
1621
1622         /*
1623          * Clear the DONE bit separately, set the address to read,
1624          * and issue the read.
1625          */
1626         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1627         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1628         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1629
1630         /* Wait for completion. */
1631         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1632                 uint32_t val;
1633
1634                 DELAY(5);
1635
1636                 val = REG_RD(sc, BCE_NVM_COMMAND);
1637                 if (val & BCE_NVM_COMMAND_DONE) {
1638                         val = REG_RD(sc, BCE_NVM_READ);
1639
1640                         val = be32toh(val);
1641                         memcpy(ret_val, &val, 4);
1642                         break;
1643                 }
1644         }
1645
1646         /* Check for errors. */
1647         if (i >= NVRAM_TIMEOUT_COUNT) {
1648                 if_printf(&sc->arpcom.ac_if,
1649                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1650                           offset);
1651                 rc = EBUSY;
1652         }
1653         return rc;
1654 }
1655
1656
1657 /****************************************************************************/
1658 /* Initialize NVRAM access.                                                 */
1659 /*                                                                          */
1660 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1661 /* access that device.                                                      */
1662 /*                                                                          */
1663 /* Returns:                                                                 */
1664 /*   0 on success, positive value on failure.                               */
1665 /****************************************************************************/
1666 static int
1667 bce_init_nvram(struct bce_softc *sc)
1668 {
1669         uint32_t val;
1670         int j, entry_count, rc = 0;
1671         const struct flash_spec *flash;
1672
1673         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1674
1675         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1676             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1677                 sc->bce_flash_info = &flash_5709;
1678                 goto bce_init_nvram_get_flash_size;
1679         }
1680
1681         /* Determine the selected interface. */
1682         val = REG_RD(sc, BCE_NVM_CFG1);
1683
1684         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1685
1686         /*
1687          * Flash reconfiguration is required to support additional
1688          * NVRAM devices not directly supported in hardware.
1689          * Check if the flash interface was reconfigured
1690          * by the bootcode.
1691          */
1692
1693         if (val & 0x40000000) {
1694                 /* Flash interface reconfigured by bootcode. */
1695
1696                 DBPRINT(sc, BCE_INFO_LOAD,
1697                         "%s(): Flash WAS reconfigured.\n", __func__);
1698
1699                 for (j = 0, flash = flash_table; j < entry_count;
1700                      j++, flash++) {
1701                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1702                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1703                                 sc->bce_flash_info = flash;
1704                                 break;
1705                         }
1706                 }
1707         } else {
1708                 /* Flash interface not yet reconfigured. */
1709                 uint32_t mask;
1710
1711                 DBPRINT(sc, BCE_INFO_LOAD,
1712                         "%s(): Flash was NOT reconfigured.\n", __func__);
1713
1714                 if (val & (1 << 23))
1715                         mask = FLASH_BACKUP_STRAP_MASK;
1716                 else
1717                         mask = FLASH_STRAP_MASK;
1718
1719                 /* Look for the matching NVRAM device configuration data. */
1720                 for (j = 0, flash = flash_table; j < entry_count;
1721                      j++, flash++) {
1722                         /* Check if the device matches any of the known devices. */
1723                         if ((val & mask) == (flash->strapping & mask)) {
1724                                 /* Found a device match. */
1725                                 sc->bce_flash_info = flash;
1726
1727                                 /* Request access to the flash interface. */
1728                                 rc = bce_acquire_nvram_lock(sc);
1729                                 if (rc != 0)
1730                                         return rc;
1731
1732                                 /* Reconfigure the flash interface. */
1733                                 bce_enable_nvram_access(sc);
1734                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1735                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1736                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1737                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1738                                 bce_disable_nvram_access(sc);
1739                                 bce_release_nvram_lock(sc);
1740                                 break;
1741                         }
1742                 }
1743         }
1744
1745         /* Check if a matching device was found. */
1746         if (j == entry_count) {
1747                 sc->bce_flash_info = NULL;
1748                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1749                 return ENODEV;
1750         }
1751
1752 bce_init_nvram_get_flash_size:
1753         /* Write the flash config data to the shared memory interface. */
1754         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1755             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1756         if (val)
1757                 sc->bce_flash_size = val;
1758         else
1759                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1760
1761         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1762                 __func__, sc->bce_flash_info->total_size);
1763
1764         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1765
1766         return rc;
1767 }
1768
1769
1770 /****************************************************************************/
1771 /* Read an arbitrary range of data from NVRAM.                              */
1772 /*                                                                          */
1773 /* Prepares the NVRAM interface for access and reads the requested data     */
1774 /* into the supplied buffer.                                                */
1775 /*                                                                          */
1776 /* Returns:                                                                 */
1777 /*   0 on success and the data read, positive value on failure.             */
1778 /****************************************************************************/
1779 static int
1780 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1781                int buf_size)
1782 {
1783         uint32_t cmd_flags, offset32, len32, extra;
1784         int rc = 0;
1785
1786         if (buf_size == 0)
1787                 return 0;
1788
1789         /* Request access to the flash interface. */
1790         rc = bce_acquire_nvram_lock(sc);
1791         if (rc != 0)
1792                 return rc;
1793
1794         /* Enable access to flash interface */
1795         bce_enable_nvram_access(sc);
1796
1797         len32 = buf_size;
1798         offset32 = offset;
1799         extra = 0;
1800
1801         cmd_flags = 0;
1802
1803         /* XXX should we release nvram lock if read_dword() fails? */
1804         if (offset32 & 3) {
1805                 uint8_t buf[4];
1806                 uint32_t pre_len;
1807
1808                 offset32 &= ~3;
1809                 pre_len = 4 - (offset & 3);
1810
1811                 if (pre_len >= len32) {
1812                         pre_len = len32;
1813                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1814                 } else {
1815                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1816                 }
1817
1818                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1819                 if (rc)
1820                         return rc;
1821
1822                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1823
1824                 offset32 += 4;
1825                 ret_buf += pre_len;
1826                 len32 -= pre_len;
1827         }
1828
1829         if (len32 & 3) {
1830                 extra = 4 - (len32 & 3);
1831                 len32 = (len32 + 4) & ~3;
1832         }
1833
1834         if (len32 == 4) {
1835                 uint8_t buf[4];
1836
1837                 if (cmd_flags)
1838                         cmd_flags = BCE_NVM_COMMAND_LAST;
1839                 else
1840                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1841                                     BCE_NVM_COMMAND_LAST;
1842
1843                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1844
1845                 memcpy(ret_buf, buf, 4 - extra);
1846         } else if (len32 > 0) {
1847                 uint8_t buf[4];
1848
1849                 /* Read the first word. */
1850                 if (cmd_flags)
1851                         cmd_flags = 0;
1852                 else
1853                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1854
1855                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1856
1857                 /* Advance to the next dword. */
1858                 offset32 += 4;
1859                 ret_buf += 4;
1860                 len32 -= 4;
1861
1862                 while (len32 > 4 && rc == 0) {
1863                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1864
1865                         /* Advance to the next dword. */
1866                         offset32 += 4;
1867                         ret_buf += 4;
1868                         len32 -= 4;
1869                 }
1870
1871                 if (rc)
1872                         goto bce_nvram_read_locked_exit;
1873
1874                 cmd_flags = BCE_NVM_COMMAND_LAST;
1875                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1876
1877                 memcpy(ret_buf, buf, 4 - extra);
1878         }
1879
1880 bce_nvram_read_locked_exit:
1881         /* Disable access to flash interface and release the lock. */
1882         bce_disable_nvram_access(sc);
1883         bce_release_nvram_lock(sc);
1884
1885         return rc;
1886 }
1887
1888
1889 /****************************************************************************/
1890 /* Verifies that NVRAM is accessible and contains valid data.               */
1891 /*                                                                          */
1892 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1893 /* correct.                                                                 */
1894 /*                                                                          */
1895 /* Returns:                                                                 */
1896 /*   0 on success, positive value on failure.                               */
1897 /****************************************************************************/
1898 static int
1899 bce_nvram_test(struct bce_softc *sc)
1900 {
1901         uint32_t buf[BCE_NVRAM_SIZE / 4];
1902         uint32_t magic, csum;
1903         uint8_t *data = (uint8_t *)buf;
1904         int rc = 0;
1905
1906         /*
1907          * Check that the device NVRAM is valid by reading
1908          * the magic value at offset 0.
1909          */
1910         rc = bce_nvram_read(sc, 0, data, 4);
1911         if (rc != 0)
1912                 return rc;
1913
1914         magic = be32toh(buf[0]);
1915         if (magic != BCE_NVRAM_MAGIC) {
1916                 if_printf(&sc->arpcom.ac_if,
1917                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1918                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1919                 return ENODEV;
1920         }
1921
1922         /*
1923          * Verify that the device NVRAM includes valid
1924          * configuration data.
1925          */
1926         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1927         if (rc != 0)
1928                 return rc;
1929
1930         csum = ether_crc32_le(data, 0x100);
1931         if (csum != BCE_CRC32_RESIDUAL) {
1932                 if_printf(&sc->arpcom.ac_if,
1933                           "Invalid Manufacturing Information NVRAM CRC! "
1934                           "Expected: 0x%08X, Found: 0x%08X\n",
1935                           BCE_CRC32_RESIDUAL, csum);
1936                 return ENODEV;
1937         }
1938
1939         csum = ether_crc32_le(data + 0x100, 0x100);
1940         if (csum != BCE_CRC32_RESIDUAL) {
1941                 if_printf(&sc->arpcom.ac_if,
1942                           "Invalid Feature Configuration Information "
1943                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1944                           BCE_CRC32_RESIDUAL, csum);
1945                 rc = ENODEV;
1946         }
1947         return rc;
1948 }
1949
1950
1951 /****************************************************************************/
1952 /* Identifies the current media type of the controller and sets the PHY     */
1953 /* address.                                                                 */
1954 /*                                                                          */
1955 /* Returns:                                                                 */
1956 /*   Nothing.                                                               */
1957 /****************************************************************************/
1958 static void
1959 bce_get_media(struct bce_softc *sc)
1960 {
1961         uint32_t val;
1962
1963         sc->bce_phy_addr = 1;
1964
1965         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1966             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1967                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1968                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1969                 uint32_t strap;
1970
1971                 /*
1972                  * The BCM5709S is software configurable
1973                  * for Copper or SerDes operation.
1974                  */
1975                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1976                         return;
1977                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1978                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1979                         return;
1980                 }
1981
1982                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1983                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1984                 } else {
1985                         strap =
1986                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1987                 }
1988
1989                 if (pci_get_function(sc->bce_dev) == 0) {
1990                         switch (strap) {
1991                         case 0x4:
1992                         case 0x5:
1993                         case 0x6:
1994                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1995                                 break;
1996                         }
1997                 } else {
1998                         switch (strap) {
1999                         case 0x1:
2000                         case 0x2:
2001                         case 0x4:
2002                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2003                                 break;
2004                         }
2005                 }
2006         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2007                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2008         }
2009
2010         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2011                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2012                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2013                         sc->bce_phy_addr = 2;
2014                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2015                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2016                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2017                 }
2018         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2019             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2020                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2021         }
2022 }
2023
2024
2025 /****************************************************************************/
2026 /* Free any DMA memory owned by the driver.                                 */
2027 /*                                                                          */
2028 /* Scans through each data structre that requires DMA memory and frees      */
2029 /* the memory if allocated.                                                 */
2030 /*                                                                          */
2031 /* Returns:                                                                 */
2032 /*   Nothing.                                                               */
2033 /****************************************************************************/
2034 static void
2035 bce_dma_free(struct bce_softc *sc)
2036 {
2037         int i;
2038
2039         /* Destroy the status block. */
2040         if (sc->status_tag != NULL) {
2041                 if (sc->status_block != NULL) {
2042                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2043                         bus_dmamem_free(sc->status_tag, sc->status_block,
2044                                         sc->status_map);
2045                 }
2046                 bus_dma_tag_destroy(sc->status_tag);
2047         }
2048
2049         /* Destroy the statistics block. */
2050         if (sc->stats_tag != NULL) {
2051                 if (sc->stats_block != NULL) {
2052                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2053                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2054                                         sc->stats_map);
2055                 }
2056                 bus_dma_tag_destroy(sc->stats_tag);
2057         }
2058
2059         /* Destroy the CTX DMA stuffs. */
2060         if (sc->ctx_tag != NULL) {
2061                 for (i = 0; i < sc->ctx_pages; i++) {
2062                         if (sc->ctx_block[i] != NULL) {
2063                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2064                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2065                                                 sc->ctx_map[i]);
2066                         }
2067                 }
2068                 bus_dma_tag_destroy(sc->ctx_tag);
2069         }
2070
2071         /* Destroy the TX buffer descriptor DMA stuffs. */
2072         if (sc->tx_bd_chain_tag != NULL) {
2073                 for (i = 0; i < sc->tx_pages; i++) {
2074                         if (sc->tx_bd_chain[i] != NULL) {
2075                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2076                                                   sc->tx_bd_chain_map[i]);
2077                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2078                                                 sc->tx_bd_chain[i],
2079                                                 sc->tx_bd_chain_map[i]);
2080                         }
2081                 }
2082                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2083         }
2084
2085         /* Destroy the RX buffer descriptor DMA stuffs. */
2086         if (sc->rx_bd_chain_tag != NULL) {
2087                 for (i = 0; i < sc->rx_pages; i++) {
2088                         if (sc->rx_bd_chain[i] != NULL) {
2089                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2090                                                   sc->rx_bd_chain_map[i]);
2091                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2092                                                 sc->rx_bd_chain[i],
2093                                                 sc->rx_bd_chain_map[i]);
2094                         }
2095                 }
2096                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2097         }
2098
2099         /* Destroy the TX mbuf DMA stuffs. */
2100         if (sc->tx_mbuf_tag != NULL) {
2101                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2102                         /* Must have been unloaded in bce_stop() */
2103                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2104                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2105                                            sc->tx_mbuf_map[i]);
2106                 }
2107                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2108         }
2109
2110         /* Destroy the RX mbuf DMA stuffs. */
2111         if (sc->rx_mbuf_tag != NULL) {
2112                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2113                         /* Must have been unloaded in bce_stop() */
2114                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2115                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2116                                            sc->rx_mbuf_map[i]);
2117                 }
2118                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2119                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2120         }
2121
2122         /* Destroy the parent tag */
2123         if (sc->parent_tag != NULL)
2124                 bus_dma_tag_destroy(sc->parent_tag);
2125
2126         if (sc->tx_bd_chain_map != NULL)
2127                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2128         if (sc->tx_bd_chain != NULL)
2129                 kfree(sc->tx_bd_chain, M_DEVBUF);
2130         if (sc->tx_bd_chain_paddr != NULL)
2131                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2132
2133         if (sc->rx_bd_chain_map != NULL)
2134                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2135         if (sc->rx_bd_chain != NULL)
2136                 kfree(sc->rx_bd_chain, M_DEVBUF);
2137         if (sc->rx_bd_chain_paddr != NULL)
2138                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2139
2140         if (sc->tx_mbuf_map != NULL)
2141                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2142         if (sc->tx_mbuf_ptr != NULL)
2143                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2144
2145         if (sc->rx_mbuf_map != NULL)
2146                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2147         if (sc->rx_mbuf_ptr != NULL)
2148                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2149         if (sc->rx_mbuf_paddr != NULL)
2150                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2151 }
2152
2153
2154 /****************************************************************************/
2155 /* Get DMA memory from the OS.                                              */
2156 /*                                                                          */
2157 /* Validates that the OS has provided DMA buffers in response to a          */
2158 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2159 /* When the callback is used the OS will return 0 for the mapping function  */
2160 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2161 /* failures back to the caller.                                             */
2162 /*                                                                          */
2163 /* Returns:                                                                 */
2164 /*   Nothing.                                                               */
2165 /****************************************************************************/
2166 static void
2167 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2168 {
2169         bus_addr_t *busaddr = arg;
2170
2171         /*
2172          * Simulate a mapping failure.
2173          * XXX not correct.
2174          */
2175         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2176                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2177                         __FILE__, __LINE__);
2178                 error = ENOMEM);
2179
2180         /* Check for an error and signal the caller that an error occurred. */
2181         if (error)
2182                 return;
2183
2184         KASSERT(nseg == 1, ("only one segment is allowed"));
2185         *busaddr = segs->ds_addr;
2186 }
2187
2188
2189 /****************************************************************************/
2190 /* Allocate any DMA memory needed by the driver.                            */
2191 /*                                                                          */
2192 /* Allocates DMA memory needed for the various global structures needed by  */
2193 /* hardware.                                                                */
2194 /*                                                                          */
2195 /* Memory alignment requirements:                                           */
2196 /* -----------------+----------+----------+----------+----------+           */
2197 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2198 /* -----------------+----------+----------+----------+----------+           */
2199 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2200 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2201 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2202 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2203 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2204 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2205 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2206 /* -----------------+----------+----------+----------+----------+           */
2207 /*                                                                          */
2208 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2209 /*                                                                          */
2210 /* Returns:                                                                 */
2211 /*   0 for success, positive value for failure.                             */
2212 /****************************************************************************/
2213 static int
2214 bce_dma_alloc(struct bce_softc *sc)
2215 {
2216         struct ifnet *ifp = &sc->arpcom.ac_if;
2217         int i, j, rc = 0, pages;
2218         bus_addr_t busaddr, max_busaddr;
2219         bus_size_t status_align, stats_align;
2220
2221         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2222         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2223                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2224                 pages = RX_PAGES_DEFAULT;
2225         }
2226         sc->rx_pages = pages;
2227
2228         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2229         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2230                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2231                 pages = TX_PAGES_DEFAULT;
2232         }
2233         sc->tx_pages = pages;
2234
2235         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2236             M_DEVBUF, M_WAITOK | M_ZERO);
2237         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2238             M_DEVBUF, M_WAITOK | M_ZERO);
2239         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2240             M_DEVBUF, M_WAITOK | M_ZERO);
2241
2242         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2243             M_DEVBUF, M_WAITOK | M_ZERO);
2244         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2245             M_DEVBUF, M_WAITOK | M_ZERO);
2246         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2247             M_DEVBUF, M_WAITOK | M_ZERO);
2248
2249         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2250             M_DEVBUF, M_WAITOK | M_ZERO);
2251         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2252             M_DEVBUF, M_WAITOK | M_ZERO);
2253
2254         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2255             M_DEVBUF, M_WAITOK | M_ZERO);
2256         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2257             M_DEVBUF, M_WAITOK | M_ZERO);
2258         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260
2261         /*
2262          * The embedded PCIe to PCI-X bridge (EPB)
2263          * in the 5708 cannot address memory above
2264          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2265          */
2266         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2267                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2268         else
2269                 max_busaddr = BUS_SPACE_MAXADDR;
2270
2271         /*
2272          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2273          */
2274         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2275             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2276                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2277                 if (sc->ctx_pages == 0)
2278                         sc->ctx_pages = 1;
2279                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2280                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2281                             sc->ctx_pages);
2282                         return ENOMEM;
2283                 }
2284                 status_align = 16;
2285                 stats_align = 16;
2286         } else {
2287                 status_align = 8;
2288                 stats_align = 8;
2289         }
2290
2291         /*
2292          * Allocate the parent bus DMA tag appropriate for PCI.
2293          */
2294         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2295                                 max_busaddr, BUS_SPACE_MAXADDR,
2296                                 NULL, NULL,
2297                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2298                                 BUS_SPACE_MAXSIZE_32BIT,
2299                                 0, &sc->parent_tag);
2300         if (rc != 0) {
2301                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2302                 return rc;
2303         }
2304
2305         /*
2306          * Allocate status block.
2307          */
2308         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2309                                 status_align, BCE_STATUS_BLK_SZ,
2310                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2311                                 &sc->status_tag, &sc->status_map,
2312                                 &sc->status_block_paddr);
2313         if (sc->status_block == NULL) {
2314                 if_printf(ifp, "Could not allocate status block!\n");
2315                 return ENOMEM;
2316         }
2317
2318         /*
2319          * Allocate statistics block.
2320          */
2321         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2322                                 stats_align, BCE_STATS_BLK_SZ,
2323                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2324                                 &sc->stats_tag, &sc->stats_map,
2325                                 &sc->stats_block_paddr);
2326         if (sc->stats_block == NULL) {
2327                 if_printf(ifp, "Could not allocate statistics block!\n");
2328                 return ENOMEM;
2329         }
2330
2331         /*
2332          * Allocate context block, if needed
2333          */
2334         if (sc->ctx_pages != 0) {
2335                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2336                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2337                                         NULL, NULL,
2338                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2339                                         0, &sc->ctx_tag);
2340                 if (rc != 0) {
2341                         if_printf(ifp, "Could not allocate "
2342                                   "context block DMA tag!\n");
2343                         return rc;
2344                 }
2345
2346                 for (i = 0; i < sc->ctx_pages; i++) {
2347                         rc = bus_dmamem_alloc(sc->ctx_tag,
2348                                               (void **)&sc->ctx_block[i],
2349                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2350                                               BUS_DMA_COHERENT,
2351                                               &sc->ctx_map[i]);
2352                         if (rc != 0) {
2353                                 if_printf(ifp, "Could not allocate %dth context "
2354                                           "DMA memory!\n", i);
2355                                 return rc;
2356                         }
2357
2358                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2359                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2360                                              bce_dma_map_addr, &busaddr,
2361                                              BUS_DMA_WAITOK);
2362                         if (rc != 0) {
2363                                 if (rc == EINPROGRESS) {
2364                                         panic("%s coherent memory loading "
2365                                               "is still in progress!", ifp->if_xname);
2366                                 }
2367                                 if_printf(ifp, "Could not map %dth context "
2368                                           "DMA memory!\n", i);
2369                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2370                                                 sc->ctx_map[i]);
2371                                 sc->ctx_block[i] = NULL;
2372                                 return rc;
2373                         }
2374                         sc->ctx_paddr[i] = busaddr;
2375                 }
2376         }
2377
2378         /*
2379          * Create a DMA tag for the TX buffer descriptor chain,
2380          * allocate and clear the  memory, and fetch the
2381          * physical address of the block.
2382          */
2383         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2384                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2385                                 NULL, NULL,
2386                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2387                                 0, &sc->tx_bd_chain_tag);
2388         if (rc != 0) {
2389                 if_printf(ifp, "Could not allocate "
2390                           "TX descriptor chain DMA tag!\n");
2391                 return rc;
2392         }
2393
2394         for (i = 0; i < sc->tx_pages; i++) {
2395                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2396                                       (void **)&sc->tx_bd_chain[i],
2397                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2398                                       BUS_DMA_COHERENT,
2399                                       &sc->tx_bd_chain_map[i]);
2400                 if (rc != 0) {
2401                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2402                                   "chain DMA memory!\n", i);
2403                         return rc;
2404                 }
2405
2406                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2407                                      sc->tx_bd_chain_map[i],
2408                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2409                                      bce_dma_map_addr, &busaddr,
2410                                      BUS_DMA_WAITOK);
2411                 if (rc != 0) {
2412                         if (rc == EINPROGRESS) {
2413                                 panic("%s coherent memory loading "
2414                                       "is still in progress!", ifp->if_xname);
2415                         }
2416                         if_printf(ifp, "Could not map %dth TX descriptor "
2417                                   "chain DMA memory!\n", i);
2418                         bus_dmamem_free(sc->tx_bd_chain_tag,
2419                                         sc->tx_bd_chain[i],
2420                                         sc->tx_bd_chain_map[i]);
2421                         sc->tx_bd_chain[i] = NULL;
2422                         return rc;
2423                 }
2424
2425                 sc->tx_bd_chain_paddr[i] = busaddr;
2426                 /* DRC - Fix for 64 bit systems. */
2427                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2428                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2429         }
2430
2431         /* Create a DMA tag for TX mbufs. */
2432         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2433                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2434                                 NULL, NULL,
2435                                 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2436                                 BCE_MAX_SEGMENTS, PAGE_SIZE,
2437                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2438                                 BUS_DMA_ONEBPAGE,
2439                                 &sc->tx_mbuf_tag);
2440         if (rc != 0) {
2441                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2442                 return rc;
2443         }
2444
2445         /* Create DMA maps for the TX mbufs clusters. */
2446         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2447                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2448                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2449                                        &sc->tx_mbuf_map[i]);
2450                 if (rc != 0) {
2451                         for (j = 0; j < i; ++j) {
2452                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2453                                                    sc->tx_mbuf_map[i]);
2454                         }
2455                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2456                         sc->tx_mbuf_tag = NULL;
2457
2458                         if_printf(ifp, "Unable to create "
2459                                   "%dth TX mbuf DMA map!\n", i);
2460                         return rc;
2461                 }
2462         }
2463
2464         /*
2465          * Create a DMA tag for the RX buffer descriptor chain,
2466          * allocate and clear the  memory, and fetch the physical
2467          * address of the blocks.
2468          */
2469         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2470                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2471                                 NULL, NULL,
2472                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2473                                 0, &sc->rx_bd_chain_tag);
2474         if (rc != 0) {
2475                 if_printf(ifp, "Could not allocate "
2476                           "RX descriptor chain DMA tag!\n");
2477                 return rc;
2478         }
2479
2480         for (i = 0; i < sc->rx_pages; i++) {
2481                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2482                                       (void **)&sc->rx_bd_chain[i],
2483                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2484                                       BUS_DMA_COHERENT,
2485                                       &sc->rx_bd_chain_map[i]);
2486                 if (rc != 0) {
2487                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2488                                   "chain DMA memory!\n", i);
2489                         return rc;
2490                 }
2491
2492                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2493                                      sc->rx_bd_chain_map[i],
2494                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2495                                      bce_dma_map_addr, &busaddr,
2496                                      BUS_DMA_WAITOK);
2497                 if (rc != 0) {
2498                         if (rc == EINPROGRESS) {
2499                                 panic("%s coherent memory loading "
2500                                       "is still in progress!", ifp->if_xname);
2501                         }
2502                         if_printf(ifp, "Could not map %dth RX descriptor "
2503                                   "chain DMA memory!\n", i);
2504                         bus_dmamem_free(sc->rx_bd_chain_tag,
2505                                         sc->rx_bd_chain[i],
2506                                         sc->rx_bd_chain_map[i]);
2507                         sc->rx_bd_chain[i] = NULL;
2508                         return rc;
2509                 }
2510
2511                 sc->rx_bd_chain_paddr[i] = busaddr;
2512                 /* DRC - Fix for 64 bit systems. */
2513                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2514                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2515         }
2516
2517         /* Create a DMA tag for RX mbufs. */
2518         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2519                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2520                                 NULL, NULL,
2521                                 MCLBYTES, 1, MCLBYTES,
2522                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2523                                 BUS_DMA_WAITOK,
2524                                 &sc->rx_mbuf_tag);
2525         if (rc != 0) {
2526                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2527                 return rc;
2528         }
2529
2530         /* Create tmp DMA map for RX mbuf clusters. */
2531         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2532                                &sc->rx_mbuf_tmpmap);
2533         if (rc != 0) {
2534                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2535                 sc->rx_mbuf_tag = NULL;
2536
2537                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2538                 return rc;
2539         }
2540
2541         /* Create DMA maps for the RX mbuf clusters. */
2542         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2543                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2544                                        &sc->rx_mbuf_map[i]);
2545                 if (rc != 0) {
2546                         for (j = 0; j < i; ++j) {
2547                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2548                                                    sc->rx_mbuf_map[j]);
2549                         }
2550                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2551                         sc->rx_mbuf_tag = NULL;
2552
2553                         if_printf(ifp, "Unable to create "
2554                                   "%dth RX mbuf DMA map!\n", i);
2555                         return rc;
2556                 }
2557         }
2558         return 0;
2559 }
2560
2561
2562 /****************************************************************************/
2563 /* Firmware synchronization.                                                */
2564 /*                                                                          */
2565 /* Before performing certain events such as a chip reset, synchronize with  */
2566 /* the firmware first.                                                      */
2567 /*                                                                          */
2568 /* Returns:                                                                 */
2569 /*   0 for success, positive value for failure.                             */
2570 /****************************************************************************/
2571 static int
2572 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2573 {
2574         int i, rc = 0;
2575         uint32_t val;
2576
2577         /* Don't waste any time if we've timed out before. */
2578         if (sc->bce_fw_timed_out)
2579                 return EBUSY;
2580
2581         /* Increment the message sequence number. */
2582         sc->bce_fw_wr_seq++;
2583         msg_data |= sc->bce_fw_wr_seq;
2584
2585         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2586
2587         /* Send the message to the bootcode driver mailbox. */
2588         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2589
2590         /* Wait for the bootcode to acknowledge the message. */
2591         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2592                 /* Check for a response in the bootcode firmware mailbox. */
2593                 val = bce_shmem_rd(sc, BCE_FW_MB);
2594                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2595                         break;
2596                 DELAY(1000);
2597         }
2598
2599         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2600         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2601             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2602                 if_printf(&sc->arpcom.ac_if,
2603                           "Firmware synchronization timeout! "
2604                           "msg_data = 0x%08X\n", msg_data);
2605
2606                 msg_data &= ~BCE_DRV_MSG_CODE;
2607                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2608
2609                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2610
2611                 sc->bce_fw_timed_out = 1;
2612                 rc = EBUSY;
2613         }
2614         return rc;
2615 }
2616
2617
2618 /****************************************************************************/
2619 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2620 /*                                                                          */
2621 /* Returns:                                                                 */
2622 /*   Nothing.                                                               */
2623 /****************************************************************************/
2624 static void
2625 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2626                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2627 {
2628         int i;
2629         uint32_t val;
2630
2631         for (i = 0; i < rv2p_code_len; i += 8) {
2632                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2633                 rv2p_code++;
2634                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2635                 rv2p_code++;
2636
2637                 if (rv2p_proc == RV2P_PROC1) {
2638                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2639                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2640                 } else {
2641                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2642                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2643                 }
2644         }
2645
2646         /* Reset the processor, un-stall is done later. */
2647         if (rv2p_proc == RV2P_PROC1)
2648                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2649         else
2650                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2651 }
2652
2653
2654 /****************************************************************************/
2655 /* Load RISC processor firmware.                                            */
2656 /*                                                                          */
2657 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2658 /* associated with a particular processor.                                  */
2659 /*                                                                          */
2660 /* Returns:                                                                 */
2661 /*   Nothing.                                                               */
2662 /****************************************************************************/
2663 static void
2664 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2665                 struct fw_info *fw)
2666 {
2667         uint32_t offset;
2668         int j;
2669
2670         bce_halt_cpu(sc, cpu_reg);
2671
2672         /* Load the Text area. */
2673         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2674         if (fw->text) {
2675                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2676                         REG_WR_IND(sc, offset, fw->text[j]);
2677         }
2678
2679         /* Load the Data area. */
2680         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2681         if (fw->data) {
2682                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2683                         REG_WR_IND(sc, offset, fw->data[j]);
2684         }
2685
2686         /* Load the SBSS area. */
2687         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2688         if (fw->sbss) {
2689                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2690                         REG_WR_IND(sc, offset, fw->sbss[j]);
2691         }
2692
2693         /* Load the BSS area. */
2694         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2695         if (fw->bss) {
2696                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2697                         REG_WR_IND(sc, offset, fw->bss[j]);
2698         }
2699
2700         /* Load the Read-Only area. */
2701         offset = cpu_reg->spad_base +
2702                 (fw->rodata_addr - cpu_reg->mips_view_base);
2703         if (fw->rodata) {
2704                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2705                         REG_WR_IND(sc, offset, fw->rodata[j]);
2706         }
2707
2708         /* Clear the pre-fetch instruction and set the FW start address. */
2709         REG_WR_IND(sc, cpu_reg->inst, 0);
2710         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2711 }
2712
2713
2714 /****************************************************************************/
2715 /* Starts the RISC processor.                                               */
2716 /*                                                                          */
2717 /* Assumes the CPU starting address has already been set.                   */
2718 /*                                                                          */
2719 /* Returns:                                                                 */
2720 /*   Nothing.                                                               */
2721 /****************************************************************************/
2722 static void
2723 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2724 {
2725         uint32_t val;
2726
2727         /* Start the CPU. */
2728         val = REG_RD_IND(sc, cpu_reg->mode);
2729         val &= ~cpu_reg->mode_value_halt;
2730         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2731         REG_WR_IND(sc, cpu_reg->mode, val);
2732 }
2733
2734
2735 /****************************************************************************/
2736 /* Halts the RISC processor.                                                */
2737 /*                                                                          */
2738 /* Returns:                                                                 */
2739 /*   Nothing.                                                               */
2740 /****************************************************************************/
2741 static void
2742 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2743 {
2744         uint32_t val;
2745
2746         /* Halt the CPU. */
2747         val = REG_RD_IND(sc, cpu_reg->mode);
2748         val |= cpu_reg->mode_value_halt;
2749         REG_WR_IND(sc, cpu_reg->mode, val);
2750         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2751 }
2752
2753
2754 /****************************************************************************/
2755 /* Start the RX CPU.                                                        */
2756 /*                                                                          */
2757 /* Returns:                                                                 */
2758 /*   Nothing.                                                               */
2759 /****************************************************************************/
2760 static void
2761 bce_start_rxp_cpu(struct bce_softc *sc)
2762 {
2763         struct cpu_reg cpu_reg;
2764
2765         cpu_reg.mode = BCE_RXP_CPU_MODE;
2766         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2767         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2768         cpu_reg.state = BCE_RXP_CPU_STATE;
2769         cpu_reg.state_value_clear = 0xffffff;
2770         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2771         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2772         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2773         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2774         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2775         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2776         cpu_reg.mips_view_base = 0x8000000;
2777
2778         bce_start_cpu(sc, &cpu_reg);
2779 }
2780
2781
2782 /****************************************************************************/
2783 /* Initialize the RX CPU.                                                   */
2784 /*                                                                          */
2785 /* Returns:                                                                 */
2786 /*   Nothing.                                                               */
2787 /****************************************************************************/
2788 static void
2789 bce_init_rxp_cpu(struct bce_softc *sc)
2790 {
2791         struct cpu_reg cpu_reg;
2792         struct fw_info fw;
2793
2794         cpu_reg.mode = BCE_RXP_CPU_MODE;
2795         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2796         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2797         cpu_reg.state = BCE_RXP_CPU_STATE;
2798         cpu_reg.state_value_clear = 0xffffff;
2799         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2800         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2801         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2802         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2803         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2804         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2805         cpu_reg.mips_view_base = 0x8000000;
2806
2807         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2808             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2809                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2810                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2811                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2812                 fw.start_addr = bce_RXP_b09FwStartAddr;
2813
2814                 fw.text_addr = bce_RXP_b09FwTextAddr;
2815                 fw.text_len = bce_RXP_b09FwTextLen;
2816                 fw.text_index = 0;
2817                 fw.text = bce_RXP_b09FwText;
2818
2819                 fw.data_addr = bce_RXP_b09FwDataAddr;
2820                 fw.data_len = bce_RXP_b09FwDataLen;
2821                 fw.data_index = 0;
2822                 fw.data = bce_RXP_b09FwData;
2823
2824                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2825                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2826                 fw.sbss_index = 0;
2827                 fw.sbss = bce_RXP_b09FwSbss;
2828
2829                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2830                 fw.bss_len = bce_RXP_b09FwBssLen;
2831                 fw.bss_index = 0;
2832                 fw.bss = bce_RXP_b09FwBss;
2833
2834                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2835                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2836                 fw.rodata_index = 0;
2837                 fw.rodata = bce_RXP_b09FwRodata;
2838         } else {
2839                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2840                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2841                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2842                 fw.start_addr = bce_RXP_b06FwStartAddr;
2843
2844                 fw.text_addr = bce_RXP_b06FwTextAddr;
2845                 fw.text_len = bce_RXP_b06FwTextLen;
2846                 fw.text_index = 0;
2847                 fw.text = bce_RXP_b06FwText;
2848
2849                 fw.data_addr = bce_RXP_b06FwDataAddr;
2850                 fw.data_len = bce_RXP_b06FwDataLen;
2851                 fw.data_index = 0;
2852                 fw.data = bce_RXP_b06FwData;
2853
2854                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2855                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2856                 fw.sbss_index = 0;
2857                 fw.sbss = bce_RXP_b06FwSbss;
2858
2859                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2860                 fw.bss_len = bce_RXP_b06FwBssLen;
2861                 fw.bss_index = 0;
2862                 fw.bss = bce_RXP_b06FwBss;
2863
2864                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2865                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2866                 fw.rodata_index = 0;
2867                 fw.rodata = bce_RXP_b06FwRodata;
2868         }
2869
2870         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2871         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2872         /* Delay RXP start until initialization is complete. */
2873 }
2874
2875
2876 /****************************************************************************/
2877 /* Initialize the TX CPU.                                                   */
2878 /*                                                                          */
2879 /* Returns:                                                                 */
2880 /*   Nothing.                                                               */
2881 /****************************************************************************/
2882 static void
2883 bce_init_txp_cpu(struct bce_softc *sc)
2884 {
2885         struct cpu_reg cpu_reg;
2886         struct fw_info fw;
2887
2888         cpu_reg.mode = BCE_TXP_CPU_MODE;
2889         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2890         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2891         cpu_reg.state = BCE_TXP_CPU_STATE;
2892         cpu_reg.state_value_clear = 0xffffff;
2893         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2894         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2895         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2896         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2897         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2898         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2899         cpu_reg.mips_view_base = 0x8000000;
2900
2901         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2902             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2903                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2904                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2905                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2906                 fw.start_addr = bce_TXP_b09FwStartAddr;
2907
2908                 fw.text_addr = bce_TXP_b09FwTextAddr;
2909                 fw.text_len = bce_TXP_b09FwTextLen;
2910                 fw.text_index = 0;
2911                 fw.text = bce_TXP_b09FwText;
2912
2913                 fw.data_addr = bce_TXP_b09FwDataAddr;
2914                 fw.data_len = bce_TXP_b09FwDataLen;
2915                 fw.data_index = 0;
2916                 fw.data = bce_TXP_b09FwData;
2917
2918                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2919                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2920                 fw.sbss_index = 0;
2921                 fw.sbss = bce_TXP_b09FwSbss;
2922
2923                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2924                 fw.bss_len = bce_TXP_b09FwBssLen;
2925                 fw.bss_index = 0;
2926                 fw.bss = bce_TXP_b09FwBss;
2927
2928                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2929                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2930                 fw.rodata_index = 0;
2931                 fw.rodata = bce_TXP_b09FwRodata;
2932         } else {
2933                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2934                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2935                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2936                 fw.start_addr = bce_TXP_b06FwStartAddr;
2937
2938                 fw.text_addr = bce_TXP_b06FwTextAddr;
2939                 fw.text_len = bce_TXP_b06FwTextLen;
2940                 fw.text_index = 0;
2941                 fw.text = bce_TXP_b06FwText;
2942
2943                 fw.data_addr = bce_TXP_b06FwDataAddr;
2944                 fw.data_len = bce_TXP_b06FwDataLen;
2945                 fw.data_index = 0;
2946                 fw.data = bce_TXP_b06FwData;
2947
2948                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2949                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2950                 fw.sbss_index = 0;
2951                 fw.sbss = bce_TXP_b06FwSbss;
2952
2953                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2954                 fw.bss_len = bce_TXP_b06FwBssLen;
2955                 fw.bss_index = 0;
2956                 fw.bss = bce_TXP_b06FwBss;
2957
2958                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2959                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2960                 fw.rodata_index = 0;
2961                 fw.rodata = bce_TXP_b06FwRodata;
2962         }
2963
2964         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2965         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2966         bce_start_cpu(sc, &cpu_reg);
2967 }
2968
2969
2970 /****************************************************************************/
2971 /* Initialize the TPAT CPU.                                                 */
2972 /*                                                                          */
2973 /* Returns:                                                                 */
2974 /*   Nothing.                                                               */
2975 /****************************************************************************/
2976 static void
2977 bce_init_tpat_cpu(struct bce_softc *sc)
2978 {
2979         struct cpu_reg cpu_reg;
2980         struct fw_info fw;
2981
2982         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2983         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2984         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2985         cpu_reg.state = BCE_TPAT_CPU_STATE;
2986         cpu_reg.state_value_clear = 0xffffff;
2987         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2988         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2989         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2990         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2991         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2992         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2993         cpu_reg.mips_view_base = 0x8000000;
2994
2995         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2996             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2997                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2998                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2999                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3000                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3001
3002                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3003                 fw.text_len = bce_TPAT_b09FwTextLen;
3004                 fw.text_index = 0;
3005                 fw.text = bce_TPAT_b09FwText;
3006
3007                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3008                 fw.data_len = bce_TPAT_b09FwDataLen;
3009                 fw.data_index = 0;
3010                 fw.data = bce_TPAT_b09FwData;
3011
3012                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3013                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3014                 fw.sbss_index = 0;
3015                 fw.sbss = bce_TPAT_b09FwSbss;
3016
3017                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3018                 fw.bss_len = bce_TPAT_b09FwBssLen;
3019                 fw.bss_index = 0;
3020                 fw.bss = bce_TPAT_b09FwBss;
3021
3022                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3023                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3024                 fw.rodata_index = 0;
3025                 fw.rodata = bce_TPAT_b09FwRodata;
3026         } else {
3027                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3028                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3029                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3030                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3031
3032                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3033                 fw.text_len = bce_TPAT_b06FwTextLen;
3034                 fw.text_index = 0;
3035                 fw.text = bce_TPAT_b06FwText;
3036
3037                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3038                 fw.data_len = bce_TPAT_b06FwDataLen;
3039                 fw.data_index = 0;
3040                 fw.data = bce_TPAT_b06FwData;
3041
3042                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3043                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3044                 fw.sbss_index = 0;
3045                 fw.sbss = bce_TPAT_b06FwSbss;
3046
3047                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3048                 fw.bss_len = bce_TPAT_b06FwBssLen;
3049                 fw.bss_index = 0;
3050                 fw.bss = bce_TPAT_b06FwBss;
3051
3052                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3053                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3054                 fw.rodata_index = 0;
3055                 fw.rodata = bce_TPAT_b06FwRodata;
3056         }
3057
3058         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3059         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3060         bce_start_cpu(sc, &cpu_reg);
3061 }
3062
3063
3064 /****************************************************************************/
3065 /* Initialize the CP CPU.                                                   */
3066 /*                                                                          */
3067 /* Returns:                                                                 */
3068 /*   Nothing.                                                               */
3069 /****************************************************************************/
3070 static void
3071 bce_init_cp_cpu(struct bce_softc *sc)
3072 {
3073         struct cpu_reg cpu_reg;
3074         struct fw_info fw;
3075
3076         cpu_reg.mode = BCE_CP_CPU_MODE;
3077         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3078         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3079         cpu_reg.state = BCE_CP_CPU_STATE;
3080         cpu_reg.state_value_clear = 0xffffff;
3081         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3082         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3083         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3084         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3085         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3086         cpu_reg.spad_base = BCE_CP_SCRATCH;
3087         cpu_reg.mips_view_base = 0x8000000;
3088
3089         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3090             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3091                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3092                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3093                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3094                 fw.start_addr = bce_CP_b09FwStartAddr;
3095
3096                 fw.text_addr = bce_CP_b09FwTextAddr;
3097                 fw.text_len = bce_CP_b09FwTextLen;
3098                 fw.text_index = 0;
3099                 fw.text = bce_CP_b09FwText;
3100
3101                 fw.data_addr = bce_CP_b09FwDataAddr;
3102                 fw.data_len = bce_CP_b09FwDataLen;
3103                 fw.data_index = 0;
3104                 fw.data = bce_CP_b09FwData;
3105
3106                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3107                 fw.sbss_len = bce_CP_b09FwSbssLen;
3108                 fw.sbss_index = 0;
3109                 fw.sbss = bce_CP_b09FwSbss;
3110
3111                 fw.bss_addr = bce_CP_b09FwBssAddr;
3112                 fw.bss_len = bce_CP_b09FwBssLen;
3113                 fw.bss_index = 0;
3114                 fw.bss = bce_CP_b09FwBss;
3115
3116                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3117                 fw.rodata_len = bce_CP_b09FwRodataLen;
3118                 fw.rodata_index = 0;
3119                 fw.rodata = bce_CP_b09FwRodata;
3120         } else {
3121                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3122                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3123                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3124                 fw.start_addr = bce_CP_b06FwStartAddr;
3125
3126                 fw.text_addr = bce_CP_b06FwTextAddr;
3127                 fw.text_len = bce_CP_b06FwTextLen;
3128                 fw.text_index = 0;
3129                 fw.text = bce_CP_b06FwText;
3130
3131                 fw.data_addr = bce_CP_b06FwDataAddr;
3132                 fw.data_len = bce_CP_b06FwDataLen;
3133                 fw.data_index = 0;
3134                 fw.data = bce_CP_b06FwData;
3135
3136                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3137                 fw.sbss_len = bce_CP_b06FwSbssLen;
3138                 fw.sbss_index = 0;
3139                 fw.sbss = bce_CP_b06FwSbss;
3140
3141                 fw.bss_addr = bce_CP_b06FwBssAddr;
3142                 fw.bss_len = bce_CP_b06FwBssLen;
3143                 fw.bss_index = 0;
3144                 fw.bss = bce_CP_b06FwBss;
3145
3146                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3147                 fw.rodata_len = bce_CP_b06FwRodataLen;
3148                 fw.rodata_index = 0;
3149                 fw.rodata = bce_CP_b06FwRodata;
3150         }
3151
3152         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3153         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3154         bce_start_cpu(sc, &cpu_reg);
3155 }
3156
3157
3158 /****************************************************************************/
3159 /* Initialize the COM CPU.                                                 */
3160 /*                                                                          */
3161 /* Returns:                                                                 */
3162 /*   Nothing.                                                               */
3163 /****************************************************************************/
3164 static void
3165 bce_init_com_cpu(struct bce_softc *sc)
3166 {
3167         struct cpu_reg cpu_reg;
3168         struct fw_info fw;
3169
3170         cpu_reg.mode = BCE_COM_CPU_MODE;
3171         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3172         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3173         cpu_reg.state = BCE_COM_CPU_STATE;
3174         cpu_reg.state_value_clear = 0xffffff;
3175         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3176         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3177         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3178         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3179         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3180         cpu_reg.spad_base = BCE_COM_SCRATCH;
3181         cpu_reg.mips_view_base = 0x8000000;
3182
3183         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3184             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3185                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3186                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3187                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3188                 fw.start_addr = bce_COM_b09FwStartAddr;
3189
3190                 fw.text_addr = bce_COM_b09FwTextAddr;
3191                 fw.text_len = bce_COM_b09FwTextLen;
3192                 fw.text_index = 0;
3193                 fw.text = bce_COM_b09FwText;
3194
3195                 fw.data_addr = bce_COM_b09FwDataAddr;
3196                 fw.data_len = bce_COM_b09FwDataLen;
3197                 fw.data_index = 0;
3198                 fw.data = bce_COM_b09FwData;
3199
3200                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3201                 fw.sbss_len = bce_COM_b09FwSbssLen;
3202                 fw.sbss_index = 0;
3203                 fw.sbss = bce_COM_b09FwSbss;
3204
3205                 fw.bss_addr = bce_COM_b09FwBssAddr;
3206                 fw.bss_len = bce_COM_b09FwBssLen;
3207                 fw.bss_index = 0;
3208                 fw.bss = bce_COM_b09FwBss;
3209
3210                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3211                 fw.rodata_len = bce_COM_b09FwRodataLen;
3212                 fw.rodata_index = 0;
3213                 fw.rodata = bce_COM_b09FwRodata;
3214         } else {
3215                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3216                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3217                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3218                 fw.start_addr = bce_COM_b06FwStartAddr;
3219
3220                 fw.text_addr = bce_COM_b06FwTextAddr;
3221                 fw.text_len = bce_COM_b06FwTextLen;
3222                 fw.text_index = 0;
3223                 fw.text = bce_COM_b06FwText;
3224
3225                 fw.data_addr = bce_COM_b06FwDataAddr;
3226                 fw.data_len = bce_COM_b06FwDataLen;
3227                 fw.data_index = 0;
3228                 fw.data = bce_COM_b06FwData;
3229
3230                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3231                 fw.sbss_len = bce_COM_b06FwSbssLen;
3232                 fw.sbss_index = 0;
3233                 fw.sbss = bce_COM_b06FwSbss;
3234
3235                 fw.bss_addr = bce_COM_b06FwBssAddr;
3236                 fw.bss_len = bce_COM_b06FwBssLen;
3237                 fw.bss_index = 0;
3238                 fw.bss = bce_COM_b06FwBss;
3239
3240                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3241                 fw.rodata_len = bce_COM_b06FwRodataLen;
3242                 fw.rodata_index = 0;
3243                 fw.rodata = bce_COM_b06FwRodata;
3244         }
3245
3246         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3247         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3248         bce_start_cpu(sc, &cpu_reg);
3249 }
3250
3251
3252 /****************************************************************************/
3253 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3254 /*                                                                          */
3255 /* Loads the firmware for each CPU and starts the CPU.                      */
3256 /*                                                                          */
3257 /* Returns:                                                                 */
3258 /*   Nothing.                                                               */
3259 /****************************************************************************/
3260 static void
3261 bce_init_cpus(struct bce_softc *sc)
3262 {
3263         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3264             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3265                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3266                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3267                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3268                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3269                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3270                 } else {
3271                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3272                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3273                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3274                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3275                 }
3276         } else {
3277                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3278                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3279                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3280                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3281         }
3282
3283         bce_init_rxp_cpu(sc);
3284         bce_init_txp_cpu(sc);
3285         bce_init_tpat_cpu(sc);
3286         bce_init_com_cpu(sc);
3287         bce_init_cp_cpu(sc);
3288 }
3289
3290
3291 /****************************************************************************/
3292 /* Initialize context memory.                                               */
3293 /*                                                                          */
3294 /* Clears the memory associated with each Context ID (CID).                 */
3295 /*                                                                          */
3296 /* Returns:                                                                 */
3297 /*   Nothing.                                                               */
3298 /****************************************************************************/
3299 static int
3300 bce_init_ctx(struct bce_softc *sc)
3301 {
3302         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3303             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3304                 /* DRC: Replace this constant value with a #define. */
3305                 int i, retry_cnt = 10;
3306                 uint32_t val;
3307
3308                 /*
3309                  * BCM5709 context memory may be cached
3310                  * in host memory so prepare the host memory
3311                  * for access.
3312                  */
3313                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3314                     (1 << 12);
3315                 val |= (BCM_PAGE_BITS - 8) << 16;
3316                 REG_WR(sc, BCE_CTX_COMMAND, val);
3317
3318                 /* Wait for mem init command to complete. */
3319                 for (i = 0; i < retry_cnt; i++) {
3320                         val = REG_RD(sc, BCE_CTX_COMMAND);
3321                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3322                                 break;
3323                         DELAY(2);
3324                 }
3325                 if (i == retry_cnt) {
3326                         device_printf(sc->bce_dev,
3327                             "Context memory initialization failed!\n");
3328                         return ETIMEDOUT;
3329                 }
3330
3331                 for (i = 0; i < sc->ctx_pages; i++) {
3332                         int j;
3333
3334                         /*
3335                          * Set the physical address of the context
3336                          * memory cache.
3337                          */
3338                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3339                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3340                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3341                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3342                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3343                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3344                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3345
3346                         /*
3347                          * Verify that the context memory write was successful.
3348                          */
3349                         for (j = 0; j < retry_cnt; j++) {
3350                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3351                                 if ((val &
3352                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3353                                         break;
3354                                 DELAY(5);
3355                         }
3356                         if (j == retry_cnt) {
3357                                 device_printf(sc->bce_dev,
3358                                     "Failed to initialize context page!\n");
3359                                 return ETIMEDOUT;
3360                         }
3361                 }
3362         } else {
3363                 uint32_t vcid_addr, offset;
3364
3365                 /*
3366                  * For the 5706/5708, context memory is local to
3367                  * the controller, so initialize the controller
3368                  * context memory.
3369                  */
3370
3371                 vcid_addr = GET_CID_ADDR(96);
3372                 while (vcid_addr) {
3373                         vcid_addr -= PHY_CTX_SIZE;
3374
3375                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3376                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3377
3378                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3379                                 CTX_WR(sc, 0x00, offset, 0);
3380
3381                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3382                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3383                 }
3384         }
3385         return 0;
3386 }
3387
3388
3389 /****************************************************************************/
3390 /* Fetch the permanent MAC address of the controller.                       */
3391 /*                                                                          */
3392 /* Returns:                                                                 */
3393 /*   Nothing.                                                               */
3394 /****************************************************************************/
3395 static void
3396 bce_get_mac_addr(struct bce_softc *sc)
3397 {
3398         uint32_t mac_lo = 0, mac_hi = 0;
3399
3400         /*
3401          * The NetXtreme II bootcode populates various NIC
3402          * power-on and runtime configuration items in a
3403          * shared memory area.  The factory configured MAC
3404          * address is available from both NVRAM and the
3405          * shared memory area so we'll read the value from
3406          * shared memory for speed.
3407          */
3408
3409         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3410         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3411
3412         if (mac_lo == 0 && mac_hi == 0) {
3413                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3414         } else {
3415                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3416                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3417                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3418                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3419                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3420                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3421         }
3422
3423         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3424 }
3425
3426
3427 /****************************************************************************/
3428 /* Program the MAC address.                                                 */
3429 /*                                                                          */
3430 /* Returns:                                                                 */
3431 /*   Nothing.                                                               */
3432 /****************************************************************************/
3433 static void
3434 bce_set_mac_addr(struct bce_softc *sc)
3435 {
3436         const uint8_t *mac_addr = sc->eaddr;
3437         uint32_t val;
3438
3439         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3440                 sc->eaddr, ":");
3441
3442         val = (mac_addr[0] << 8) | mac_addr[1];
3443         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3444
3445         val = (mac_addr[2] << 24) |
3446               (mac_addr[3] << 16) |
3447               (mac_addr[4] << 8) |
3448               mac_addr[5];
3449         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3450 }
3451
3452
3453 /****************************************************************************/
3454 /* Stop the controller.                                                     */
3455 /*                                                                          */
3456 /* Returns:                                                                 */
3457 /*   Nothing.                                                               */
3458 /****************************************************************************/
3459 static void
3460 bce_stop(struct bce_softc *sc)
3461 {
3462         struct ifnet *ifp = &sc->arpcom.ac_if;
3463
3464         ASSERT_SERIALIZED(ifp->if_serializer);
3465
3466         callout_stop(&sc->bce_tick_callout);
3467
3468         /* Disable the transmit/receive blocks. */
3469         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3470         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3471         DELAY(20);
3472
3473         bce_disable_intr(sc);
3474
3475         /* Free the RX lists. */
3476         bce_free_rx_chain(sc);
3477
3478         /* Free TX buffers. */
3479         bce_free_tx_chain(sc);
3480
3481         sc->bce_link = 0;
3482         sc->bce_coalchg_mask = 0;
3483
3484         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3485         ifp->if_timer = 0;
3486 }
3487
3488
3489 static int
3490 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3491 {
3492         uint32_t val;
3493         int i, rc = 0;
3494
3495         /* Wait for pending PCI transactions to complete. */
3496         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3497                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3498                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3499                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3500                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3501         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3502         DELAY(5);
3503
3504         /* Disable DMA */
3505         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3506             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3507                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3508                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3509                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3510         }
3511
3512         /* Assume bootcode is running. */
3513         sc->bce_fw_timed_out = 0;
3514         sc->bce_drv_cardiac_arrest = 0;
3515
3516         /* Give the firmware a chance to prepare for the reset. */
3517         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3518         if (rc) {
3519                 if_printf(&sc->arpcom.ac_if,
3520                           "Firmware is not ready for reset\n");
3521                 return rc;
3522         }
3523
3524         /* Set a firmware reminder that this is a soft reset. */
3525         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3526             BCE_DRV_RESET_SIGNATURE_MAGIC);
3527
3528         /* Dummy read to force the chip to complete all current transactions. */
3529         val = REG_RD(sc, BCE_MISC_ID);
3530
3531         /* Chip reset. */
3532         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3533             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3534                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3535                 REG_RD(sc, BCE_MISC_COMMAND);
3536                 DELAY(5);
3537
3538                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3539                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3540
3541                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3542         } else {
3543                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3544                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3545                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3546                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3547
3548                 /* Allow up to 30us for reset to complete. */
3549                 for (i = 0; i < 10; i++) {
3550                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3551                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3552                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3553                                 break;
3554                         DELAY(10);
3555                 }
3556
3557                 /* Check that reset completed successfully. */
3558                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3559                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3560                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3561                         return EBUSY;
3562                 }
3563         }
3564
3565         /* Make sure byte swapping is properly configured. */
3566         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3567         if (val != 0x01020304) {
3568                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3569                 return ENODEV;
3570         }
3571
3572         /* Just completed a reset, assume that firmware is running again. */
3573         sc->bce_fw_timed_out = 0;
3574         sc->bce_drv_cardiac_arrest = 0;
3575
3576         /* Wait for the firmware to finish its initialization. */
3577         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3578         if (rc) {
3579                 if_printf(&sc->arpcom.ac_if,
3580                           "Firmware did not complete initialization!\n");
3581         }
3582         return rc;
3583 }
3584
3585
3586 static int
3587 bce_chipinit(struct bce_softc *sc)
3588 {
3589         uint32_t val;
3590         int rc = 0;
3591
3592         /* Make sure the interrupt is not active. */
3593         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3594         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3595
3596         /*
3597          * Initialize DMA byte/word swapping, configure the number of DMA
3598          * channels and PCI clock compensation delay.
3599          */
3600         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3601               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3602 #if BYTE_ORDER == BIG_ENDIAN
3603               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3604 #endif
3605               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3606               DMA_READ_CHANS << 12 |
3607               DMA_WRITE_CHANS << 16;
3608
3609         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3610
3611         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3612                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3613
3614         /*
3615          * This setting resolves a problem observed on certain Intel PCI
3616          * chipsets that cannot handle multiple outstanding DMA operations.
3617          * See errata E9_5706A1_65.
3618          */
3619         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3620             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3621             !(sc->bce_flags & BCE_PCIX_FLAG))
3622                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3623
3624         REG_WR(sc, BCE_DMA_CONFIG, val);
3625
3626         /* Enable the RX_V2P and Context state machines before access. */
3627         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3628                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3629                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3630                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3631
3632         /* Initialize context mapping and zero out the quick contexts. */
3633         rc = bce_init_ctx(sc);
3634         if (rc != 0)
3635                 return rc;
3636
3637         /* Initialize the on-boards CPUs */
3638         bce_init_cpus(sc);
3639
3640         /* Enable management frames (NC-SI) to flow to the MCP. */
3641         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3642                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3643                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3644                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3645         }
3646
3647         /* Prepare NVRAM for access. */
3648         rc = bce_init_nvram(sc);
3649         if (rc != 0)
3650                 return rc;
3651
3652         /* Set the kernel bypass block size */
3653         val = REG_RD(sc, BCE_MQ_CONFIG);
3654         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3655         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3656
3657         /* Enable bins used on the 5709/5716. */
3658         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3659             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3660                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3661                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3662                         val |= BCE_MQ_CONFIG_HALT_DIS;
3663         }
3664
3665         REG_WR(sc, BCE_MQ_CONFIG, val);
3666
3667         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3668         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3669         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3670
3671         /* Set the page size and clear the RV2P processor stall bits. */
3672         val = (BCM_PAGE_BITS - 8) << 24;
3673         REG_WR(sc, BCE_RV2P_CONFIG, val);
3674
3675         /* Configure page size. */
3676         val = REG_RD(sc, BCE_TBDR_CONFIG);
3677         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3678         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3679         REG_WR(sc, BCE_TBDR_CONFIG, val);
3680
3681         /* Set the perfect match control register to default. */
3682         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3683
3684         return 0;
3685 }
3686
3687
3688 /****************************************************************************/
3689 /* Initialize the controller in preparation to send/receive traffic.        */
3690 /*                                                                          */
3691 /* Returns:                                                                 */
3692 /*   0 for success, positive value for failure.                             */
3693 /****************************************************************************/
3694 static int
3695 bce_blockinit(struct bce_softc *sc)
3696 {
3697         uint32_t reg, val;
3698         int rc = 0;
3699
3700         /* Load the hardware default MAC address. */
3701         bce_set_mac_addr(sc);
3702
3703         /* Set the Ethernet backoff seed value */
3704         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3705               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3706         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3707
3708         sc->last_status_idx = 0;
3709         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3710
3711         sc->pulse_check_status_idx = 0xffff;
3712
3713         /* Set up link change interrupt generation. */
3714         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3715
3716         /* Program the physical address of the status block. */
3717         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3718         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3719
3720         /* Program the physical address of the statistics block. */
3721         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3722                BCE_ADDR_LO(sc->stats_block_paddr));
3723         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3724                BCE_ADDR_HI(sc->stats_block_paddr));
3725
3726         /* Program various host coalescing parameters. */
3727         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3728                (sc->bce_tx_quick_cons_trip_int << 16) |
3729                sc->bce_tx_quick_cons_trip);
3730         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3731                (sc->bce_rx_quick_cons_trip_int << 16) |
3732                sc->bce_rx_quick_cons_trip);
3733         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3734                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3735         REG_WR(sc, BCE_HC_TX_TICKS,
3736                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3737         REG_WR(sc, BCE_HC_RX_TICKS,
3738                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3739         REG_WR(sc, BCE_HC_COM_TICKS,
3740                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3741         REG_WR(sc, BCE_HC_CMD_TICKS,
3742                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3743         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3744         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3745
3746         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3747         if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3748                 if (bootverbose)
3749                         if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3750                 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3751         }
3752         REG_WR(sc, BCE_HC_CONFIG, val);
3753
3754         /* Clear the internal statistics counters. */
3755         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3756
3757         /* Verify that bootcode is running. */
3758         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3759
3760         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3761                 if_printf(&sc->arpcom.ac_if,
3762                           "%s(%d): Simulating bootcode failure.\n",
3763                           __FILE__, __LINE__);
3764                 reg = 0);
3765
3766         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3767             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3768                 if_printf(&sc->arpcom.ac_if,
3769                           "Bootcode not running! Found: 0x%08X, "
3770                           "Expected: 08%08X\n",
3771                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3772                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3773                 return ENODEV;
3774         }
3775
3776         /* Enable DMA */
3777         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3778             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3779                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3780                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3781                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3782         }
3783
3784         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3785         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3786
3787         /* Enable link state change interrupt generation. */
3788         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3789
3790         /* Enable the RXP. */
3791         bce_start_rxp_cpu(sc);
3792
3793         /* Disable management frames (NC-SI) from flowing to the MCP. */
3794         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3795                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3796                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3797                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3798         }
3799
3800         /* Enable all remaining blocks in the MAC. */
3801         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3802             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3803                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3804                     BCE_MISC_ENABLE_DEFAULT_XI);
3805         } else {
3806                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3807         }
3808         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3809         DELAY(20);
3810
3811         /* Save the current host coalescing block settings. */
3812         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3813
3814         return 0;
3815 }
3816
3817
3818 /****************************************************************************/
3819 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3820 /*                                                                          */
3821 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3822 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3823 /* necessary.                                                               */
3824 /*                                                                          */
3825 /* Returns:                                                                 */
3826 /*   0 for success, positive value for failure.                             */
3827 /****************************************************************************/
3828 static int
3829 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3830                uint32_t *prod_bseq, int init)
3831 {
3832         bus_dmamap_t map;
3833         bus_dma_segment_t seg;
3834         struct mbuf *m_new;
3835         int error, nseg;
3836 #ifdef BCE_DEBUG
3837         uint16_t debug_chain_prod = *chain_prod;
3838 #endif
3839
3840         /* Make sure the inputs are valid. */
3841         DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3842                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3843                           "RX producer out of range: 0x%04X > 0x%04X\n",
3844                           __FILE__, __LINE__,
3845                           *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3846
3847         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3848                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3849
3850         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3851                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3852                           "Simulating mbuf allocation failure.\n",
3853                           __FILE__, __LINE__);
3854                 sc->mbuf_alloc_failed++;
3855                 return ENOBUFS);
3856
3857         /* This is a new mbuf allocation. */
3858         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3859         if (m_new == NULL)
3860                 return ENOBUFS;
3861         DBRUNIF(1, sc->rx_mbuf_alloc++);
3862
3863         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3864
3865         /* Map the mbuf cluster into device memory. */
3866         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3867                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3868                         BUS_DMA_NOWAIT);
3869         if (error) {
3870                 m_freem(m_new);
3871                 if (init) {
3872                         if_printf(&sc->arpcom.ac_if,
3873                                   "Error mapping mbuf into RX chain!\n");
3874                 }
3875                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3876                 return error;
3877         }
3878
3879         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3880                 bus_dmamap_unload(sc->rx_mbuf_tag,
3881                                   sc->rx_mbuf_map[*chain_prod]);
3882         }
3883
3884         map = sc->rx_mbuf_map[*chain_prod];
3885         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3886         sc->rx_mbuf_tmpmap = map;
3887
3888         /* Watch for overflow. */
3889         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3890                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3891                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3892                           __FILE__, __LINE__, sc->free_rx_bd,
3893                           (uint16_t)USABLE_RX_BD(sc)));
3894
3895         /* Update some debug statistic counters */
3896         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3897                 sc->rx_low_watermark = sc->free_rx_bd);
3898         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3899
3900         /* Save the mbuf and update our counter. */
3901         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3902         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3903         sc->free_rx_bd--;
3904
3905         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3906
3907         DBRUN(BCE_VERBOSE_RECV,
3908               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3909
3910         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3911                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3912
3913         return 0;
3914 }
3915
3916
3917 static void
3918 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3919 {
3920         struct rx_bd *rxbd;
3921         bus_addr_t paddr;
3922         int len;
3923
3924         paddr = sc->rx_mbuf_paddr[chain_prod];
3925         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3926
3927         /* Setup the rx_bd for the first segment. */
3928         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3929
3930         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3931         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3932         rxbd->rx_bd_len = htole32(len);
3933         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3934         *prod_bseq += len;
3935
3936         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3937 }
3938
3939
3940 /****************************************************************************/
3941 /* Initialize the TX context memory.                                        */
3942 /*                                                                          */
3943 /* Returns:                                                                 */
3944 /*   Nothing                                                                */
3945 /****************************************************************************/
3946 static void
3947 bce_init_tx_context(struct bce_softc *sc)
3948 {
3949         uint32_t val;
3950
3951         /* Initialize the context ID for an L2 TX chain. */
3952         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3953             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3954                 /* Set the CID type to support an L2 connection. */
3955                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3956                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3957                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3958                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3959
3960                 /* Point the hardware to the first page in the chain. */
3961                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3962                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3963                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3964                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3965                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3966                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3967         } else {
3968                 /* Set the CID type to support an L2 connection. */
3969                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3970                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3971                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3972                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3973
3974                 /* Point the hardware to the first page in the chain. */
3975                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3976                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3977                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3978                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3979                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3980                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3981         }
3982 }
3983
3984
3985 /****************************************************************************/
3986 /* Allocate memory and initialize the TX data structures.                   */
3987 /*                                                                          */
3988 /* Returns:                                                                 */
3989 /*   0 for success, positive value for failure.                             */
3990 /****************************************************************************/
3991 static int
3992 bce_init_tx_chain(struct bce_softc *sc)
3993 {
3994         struct tx_bd *txbd;
3995         int i, rc = 0;
3996
3997         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3998
3999         /* Set the initial TX producer/consumer indices. */
4000         sc->tx_prod = 0;
4001         sc->tx_cons = 0;
4002         sc->tx_prod_bseq   = 0;
4003         sc->used_tx_bd = 0;
4004         sc->max_tx_bd = USABLE_TX_BD(sc);
4005         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4006         DBRUNIF(1, sc->tx_full_count = 0);
4007
4008         /*
4009          * The NetXtreme II supports a linked-list structre called
4010          * a Buffer Descriptor Chain (or BD chain).  A BD chain
4011          * consists of a series of 1 or more chain pages, each of which
4012          * consists of a fixed number of BD entries.
4013          * The last BD entry on each page is a pointer to the next page
4014          * in the chain, and the last pointer in the BD chain
4015          * points back to the beginning of the chain.
4016          */
4017
4018         /* Set the TX next pointer chain entries. */
4019         for (i = 0; i < sc->tx_pages; i++) {
4020                 int j;
4021
4022                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4023
4024                 /* Check if we've reached the last page. */
4025                 if (i == (sc->tx_pages - 1))
4026                         j = 0;
4027                 else
4028                         j = i + 1;
4029
4030                 txbd->tx_bd_haddr_hi =
4031                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4032                 txbd->tx_bd_haddr_lo =
4033                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4034         }
4035         bce_init_tx_context(sc);
4036
4037         return(rc);
4038 }
4039
4040
4041 /****************************************************************************/
4042 /* Free memory and clear the TX data structures.                            */
4043 /*                                                                          */
4044 /* Returns:                                                                 */
4045 /*   Nothing.                                                               */
4046 /****************************************************************************/
4047 static void
4048 bce_free_tx_chain(struct bce_softc *sc)
4049 {
4050         int i;
4051
4052         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4053
4054         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4055         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4056                 if (sc->tx_mbuf_ptr[i] != NULL) {
4057                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4058                         m_freem(sc->tx_mbuf_ptr[i]);
4059                         sc->tx_mbuf_ptr[i] = NULL;
4060                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4061                 }
4062         }
4063
4064         /* Clear each TX chain page. */
4065         for (i = 0; i < sc->tx_pages; i++)
4066                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4067         sc->used_tx_bd = 0;
4068
4069         /* Check if we lost any mbufs in the process. */
4070         DBRUNIF((sc->tx_mbuf_alloc),
4071                 if_printf(&sc->arpcom.ac_if,
4072                           "%s(%d): Memory leak! "
4073                           "Lost %d mbufs from tx chain!\n",
4074                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
4075
4076         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4077 }
4078
4079
4080 /****************************************************************************/
4081 /* Initialize the RX context memory.                                        */
4082 /*                                                                          */
4083 /* Returns:                                                                 */
4084 /*   Nothing                                                                */
4085 /****************************************************************************/
4086 static void
4087 bce_init_rx_context(struct bce_softc *sc)
4088 {
4089         uint32_t val;
4090
4091         /* Initialize the context ID for an L2 RX chain. */
4092         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4093             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4094
4095         /*
4096          * Set the level for generating pause frames
4097          * when the number of available rx_bd's gets
4098          * too low (the low watermark) and the level
4099          * when pause frames can be stopped (the high
4100          * watermark).
4101          */
4102         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4103             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4104                 uint32_t lo_water, hi_water;
4105
4106                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4107                 hi_water = USABLE_RX_BD(sc) / 4;
4108
4109                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4110                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4111
4112                 if (hi_water > 0xf)
4113                         hi_water = 0xf;
4114                 else if (hi_water == 0)
4115                         lo_water = 0;
4116                 val |= lo_water |
4117                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4118         }
4119
4120         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4121
4122         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4123         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4124             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4125                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4126                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4127         }
4128
4129         /* Point the hardware to the first page in the chain. */
4130         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4131         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4132         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4133         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4134 }
4135
4136
4137 /****************************************************************************/
4138 /* Allocate memory and initialize the RX data structures.                   */
4139 /*                                                                          */
4140 /* Returns:                                                                 */
4141 /*   0 for success, positive value for failure.                             */
4142 /****************************************************************************/
4143 static int
4144 bce_init_rx_chain(struct bce_softc *sc)
4145 {
4146         struct rx_bd *rxbd;
4147         int i, rc = 0;
4148         uint16_t prod, chain_prod;
4149         uint32_t prod_bseq;
4150
4151         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4152
4153         /* Initialize the RX producer and consumer indices. */
4154         sc->rx_prod = 0;
4155         sc->rx_cons = 0;
4156         sc->rx_prod_bseq = 0;
4157         sc->free_rx_bd = USABLE_RX_BD(sc);
4158         sc->max_rx_bd = USABLE_RX_BD(sc);
4159         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4160         DBRUNIF(1, sc->rx_empty_count = 0);
4161
4162         /* Initialize the RX next pointer chain entries. */
4163         for (i = 0; i < sc->rx_pages; i++) {
4164                 int j;
4165
4166                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4167
4168                 /* Check if we've reached the last page. */
4169                 if (i == (sc->rx_pages - 1))
4170                         j = 0;
4171                 else
4172                         j = i + 1;
4173
4174                 /* Setup the chain page pointers. */
4175                 rxbd->rx_bd_haddr_hi =
4176                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4177                 rxbd->rx_bd_haddr_lo =
4178                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4179         }
4180
4181         /* Allocate mbuf clusters for the rx_bd chain. */
4182         prod = prod_bseq = 0;
4183         while (prod < TOTAL_RX_BD(sc)) {
4184                 chain_prod = RX_CHAIN_IDX(sc, prod);
4185                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4186                         if_printf(&sc->arpcom.ac_if,
4187                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4188                                   chain_prod);
4189                         rc = ENOBUFS;
4190                         break;
4191                 }
4192                 prod = NEXT_RX_BD(prod);
4193         }
4194
4195         /* Save the RX chain producer index. */
4196         sc->rx_prod = prod;
4197         sc->rx_prod_bseq = prod_bseq;
4198
4199         /* Tell the chip about the waiting rx_bd's. */
4200         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4201             sc->rx_prod);
4202         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4203             sc->rx_prod_bseq);
4204
4205         bce_init_rx_context(sc);
4206
4207         return(rc);
4208 }
4209
4210
4211 /****************************************************************************/
4212 /* Free memory and clear the RX data structures.                            */
4213 /*                                                                          */
4214 /* Returns:                                                                 */
4215 /*   Nothing.                                                               */
4216 /****************************************************************************/
4217 static void
4218 bce_free_rx_chain(struct bce_softc *sc)
4219 {
4220         int i;
4221
4222         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4223
4224         /* Free any mbufs still in the RX mbuf chain. */
4225         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4226                 if (sc->rx_mbuf_ptr[i] != NULL) {
4227                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4228                         m_freem(sc->rx_mbuf_ptr[i]);
4229                         sc->rx_mbuf_ptr[i] = NULL;
4230                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4231                 }
4232         }
4233
4234         /* Clear each RX chain page. */
4235         for (i = 0; i < sc->rx_pages; i++)
4236                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4237
4238         /* Check if we lost any mbufs in the process. */
4239         DBRUNIF((sc->rx_mbuf_alloc),
4240                 if_printf(&sc->arpcom.ac_if,
4241                           "%s(%d): Memory leak! "
4242                           "Lost %d mbufs from rx chain!\n",
4243                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4244
4245         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4246 }
4247
4248
4249 /****************************************************************************/
4250 /* Set media options.                                                       */
4251 /*                                                                          */
4252 /* Returns:                                                                 */
4253 /*   0 for success, positive value for failure.                             */
4254 /****************************************************************************/
4255 static int
4256 bce_ifmedia_upd(struct ifnet *ifp)
4257 {
4258         struct bce_softc *sc = ifp->if_softc;
4259         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4260         int error = 0;
4261
4262         /*
4263          * 'mii' will be NULL, when this function is called on following
4264          * code path: bce_attach() -> bce_mgmt_init()
4265          */
4266         if (mii != NULL) {
4267                 /* Make sure the MII bus has been enumerated. */
4268                 sc->bce_link = 0;
4269                 if (mii->mii_instance) {
4270                         struct mii_softc *miisc;
4271
4272                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4273                                 mii_phy_reset(miisc);
4274                 }
4275                 error = mii_mediachg(mii);
4276         }
4277         return error;
4278 }
4279
4280
4281 /****************************************************************************/
4282 /* Reports current media status.                                            */
4283 /*                                                                          */
4284 /* Returns:                                                                 */
4285 /*   Nothing.                                                               */
4286 /****************************************************************************/
4287 static void
4288 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4289 {
4290         struct bce_softc *sc = ifp->if_softc;
4291         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4292
4293         mii_pollstat(mii);
4294         ifmr->ifm_active = mii->mii_media_active;
4295         ifmr->ifm_status = mii->mii_media_status;
4296 }
4297
4298
4299 /****************************************************************************/
4300 /* Handles PHY generated interrupt events.                                  */
4301 /*                                                                          */
4302 /* Returns:                                                                 */
4303 /*   Nothing.                                                               */
4304 /****************************************************************************/
4305 static void
4306 bce_phy_intr(struct bce_softc *sc)
4307 {
4308         uint32_t new_link_state, old_link_state;
4309         struct ifnet *ifp = &sc->arpcom.ac_if;
4310
4311         ASSERT_SERIALIZED(ifp->if_serializer);
4312
4313         new_link_state = sc->status_block->status_attn_bits &
4314                          STATUS_ATTN_BITS_LINK_STATE;
4315         old_link_state = sc->status_block->status_attn_bits_ack &
4316                          STATUS_ATTN_BITS_LINK_STATE;
4317
4318         /* Handle any changes if the link state has changed. */
4319         if (new_link_state != old_link_state) { /* XXX redundant? */
4320                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4321
4322                 /* Update the status_attn_bits_ack field in the status block. */
4323                 if (new_link_state) {
4324                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4325                                STATUS_ATTN_BITS_LINK_STATE);
4326                         if (bootverbose)
4327                                 if_printf(ifp, "Link is now UP.\n");
4328                 } else {
4329                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4330                                STATUS_ATTN_BITS_LINK_STATE);
4331                         if (bootverbose)
4332                                 if_printf(ifp, "Link is now DOWN.\n");
4333                 }
4334
4335                 /*
4336                  * Assume link is down and allow tick routine to
4337                  * update the state based on the actual media state.
4338                  */
4339                 sc->bce_link = 0;
4340                 callout_stop(&sc->bce_tick_callout);
4341                 bce_tick_serialized(sc);
4342         }
4343
4344         /* Acknowledge the link change interrupt. */
4345         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4346 }
4347
4348
4349 /****************************************************************************/
4350 /* Reads the receive consumer value from the status block (skipping over    */
4351 /* chain page pointer if necessary).                                        */
4352 /*                                                                          */
4353 /* Returns:                                                                 */
4354 /*   hw_cons                                                                */
4355 /****************************************************************************/
4356 static __inline uint16_t
4357 bce_get_hw_rx_cons(struct bce_softc *sc)
4358 {
4359         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4360
4361         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4362                 hw_cons++;
4363         return hw_cons;
4364 }
4365
4366
4367 /****************************************************************************/
4368 /* Handles received frame interrupt events.                                 */
4369 /*                                                                          */
4370 /* Returns:                                                                 */
4371 /*   Nothing.                                                               */
4372 /****************************************************************************/
4373 static void
4374 bce_rx_intr(struct bce_softc *sc, int count, uint16_t hw_cons)
4375 {
4376         struct ifnet *ifp = &sc->arpcom.ac_if;
4377         uint16_t sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4378         uint32_t sw_prod_bseq;
4379
4380         ASSERT_SERIALIZED(ifp->if_serializer);
4381
4382         /* Get working copies of the driver's view of the RX indices. */
4383         sw_cons = sc->rx_cons;
4384         sw_prod = sc->rx_prod;
4385         sw_prod_bseq = sc->rx_prod_bseq;
4386
4387         /* Scan through the receive chain as long as there is work to do. */
4388         while (sw_cons != hw_cons) {
4389                 struct mbuf *m = NULL;
4390                 struct l2_fhdr *l2fhdr = NULL;
4391                 struct rx_bd *rxbd;
4392                 unsigned int len;
4393                 uint32_t status = 0;
4394
4395 #ifdef DEVICE_POLLING
4396                 if (count >= 0 && count-- == 0)
4397                         break;
4398 #endif
4399
4400                 /*
4401                  * Convert the producer/consumer indices
4402                  * to an actual rx_bd index.
4403                  */
4404                 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4405                 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4406
4407                 /* Get the used rx_bd. */
4408                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4409                                        [RX_IDX(sw_chain_cons)];
4410                 sc->free_rx_bd++;
4411
4412                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4413                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4414                         if (sw_chain_cons != sw_chain_prod) {
4415                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4416                                           "drop!\n", sw_chain_cons,
4417                                           sw_chain_prod);
4418                                 ifp->if_ierrors++;
4419
4420                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4421                                                      &sw_prod_bseq);
4422                                 m = NULL;
4423                                 goto bce_rx_int_next_rx;
4424                         }
4425
4426                         /* Unmap the mbuf from DMA space. */
4427                         bus_dmamap_sync(sc->rx_mbuf_tag,
4428                                         sc->rx_mbuf_map[sw_chain_cons],
4429                                         BUS_DMASYNC_POSTREAD);
4430
4431                         /* Save the mbuf from the driver's chain. */
4432                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4433
4434                         /*
4435                          * Frames received on the NetXteme II are prepended
4436                          * with an l2_fhdr structure which provides status
4437                          * information about the received frame (including
4438                          * VLAN tags and checksum info).  The frames are also
4439                          * automatically adjusted to align the IP header
4440                          * (i.e. two null bytes are inserted before the
4441                          * Ethernet header).  As a result the data DMA'd by
4442                          * the controller into the mbuf is as follows:
4443                          *
4444                          * +---------+-----+---------------------+-----+
4445                          * | l2_fhdr | pad | packet data         | FCS |
4446                          * +---------+-----+---------------------+-----+
4447                          *
4448                          * The l2_fhdr needs to be checked and skipped and the
4449                          * FCS needs to be stripped before sending the packet
4450                          * up the stack.
4451                          */
4452                         l2fhdr = mtod(m, struct l2_fhdr *);
4453
4454                         len = l2fhdr->l2_fhdr_pkt_len;
4455                         status = l2fhdr->l2_fhdr_status;
4456
4457                         len -= ETHER_CRC_LEN;
4458
4459                         /* Check the received frame for errors. */
4460                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4461                                       L2_FHDR_ERRORS_PHY_DECODE |
4462                                       L2_FHDR_ERRORS_ALIGNMENT |
4463                                       L2_FHDR_ERRORS_TOO_SHORT |
4464                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4465                                 ifp->if_ierrors++;
4466
4467                                 /* Reuse the mbuf for a new frame. */
4468                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4469                                                      &sw_prod_bseq);
4470                                 m = NULL;
4471                                 goto bce_rx_int_next_rx;
4472                         }
4473
4474                         /*
4475                          * Get a new mbuf for the rx_bd.   If no new
4476                          * mbufs are available then reuse the current mbuf,
4477                          * log an ierror on the interface, and generate
4478                          * an error in the system log.
4479                          */
4480                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4481                                            &sw_prod_bseq, 0)) {
4482                                 ifp->if_ierrors++;
4483
4484                                 /* Try and reuse the exisitng mbuf. */
4485                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4486                                                      &sw_prod_bseq);
4487                                 m = NULL;
4488                                 goto bce_rx_int_next_rx;
4489                         }
4490
4491                         /*
4492                          * Skip over the l2_fhdr when passing
4493                          * the data up the stack.
4494                          */
4495                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4496
4497                         m->m_pkthdr.len = m->m_len = len;
4498                         m->m_pkthdr.rcvif = ifp;
4499
4500                         /* Validate the checksum if offload enabled. */
4501                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4502                                 /* Check for an IP datagram. */
4503                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4504                                         m->m_pkthdr.csum_flags |=
4505                                                 CSUM_IP_CHECKED;
4506
4507                                         /* Check if the IP checksum is valid. */
4508                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4509                                              0xffff) == 0) {
4510                                                 m->m_pkthdr.csum_flags |=
4511                                                         CSUM_IP_VALID;
4512                                         }
4513                                 }
4514
4515                                 /* Check for a valid TCP/UDP frame. */
4516                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4517                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4518
4519                                         /* Check for a good TCP/UDP checksum. */
4520                                         if ((status &
4521                                              (L2_FHDR_ERRORS_TCP_XSUM |
4522                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4523                                                 m->m_pkthdr.csum_data =
4524                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4525                                                 m->m_pkthdr.csum_flags |=
4526                                                         CSUM_DATA_VALID |
4527                                                         CSUM_PSEUDO_HDR;
4528                                         }
4529                                 }
4530                         }
4531
4532                         ifp->if_ipackets++;
4533 bce_rx_int_next_rx:
4534                         sw_prod = NEXT_RX_BD(sw_prod);
4535                 }
4536
4537                 sw_cons = NEXT_RX_BD(sw_cons);
4538
4539                 /* If we have a packet, pass it up the stack */
4540                 if (m) {
4541                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4542                                 m->m_flags |= M_VLANTAG;
4543                                 m->m_pkthdr.ether_vlantag =
4544                                         l2fhdr->l2_fhdr_vlan_tag;
4545                         }
4546                         ifp->if_input(ifp, m);
4547                 }
4548         }
4549
4550         sc->rx_cons = sw_cons;
4551         sc->rx_prod = sw_prod;
4552         sc->rx_prod_bseq = sw_prod_bseq;
4553
4554         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4555             sc->rx_prod);
4556         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4557             sc->rx_prod_bseq);
4558 }
4559
4560
4561 /****************************************************************************/
4562 /* Reads the transmit consumer value from the status block (skipping over   */
4563 /* chain page pointer if necessary).                                        */
4564 /*                                                                          */
4565 /* Returns:                                                                 */
4566 /*   hw_cons                                                                */
4567 /****************************************************************************/
4568 static __inline uint16_t
4569 bce_get_hw_tx_cons(struct bce_softc *sc)
4570 {
4571         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4572
4573         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4574                 hw_cons++;
4575         return hw_cons;
4576 }
4577
4578
4579 /****************************************************************************/
4580 /* Handles transmit completion interrupt events.                            */
4581 /*                                                                          */
4582 /* Returns:                                                                 */
4583 /*   Nothing.                                                               */
4584 /****************************************************************************/
4585 static void
4586 bce_tx_intr(struct bce_softc *sc, uint16_t hw_tx_cons)
4587 {
4588         struct ifnet *ifp = &sc->arpcom.ac_if;
4589         uint16_t sw_tx_cons, sw_tx_chain_cons;
4590
4591         ASSERT_SERIALIZED(ifp->if_serializer);
4592
4593         /* Get the hardware's view of the TX consumer index. */
4594         sw_tx_cons = sc->tx_cons;
4595
4596         /* Cycle through any completed TX chain page entries. */
4597         while (sw_tx_cons != hw_tx_cons) {
4598                 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4599
4600                 /*
4601                  * Free the associated mbuf. Remember
4602                  * that only the last tx_bd of a packet
4603                  * has an mbuf pointer and DMA map.
4604                  */
4605                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4606                         /* Unmap the mbuf. */
4607                         bus_dmamap_unload(sc->tx_mbuf_tag,
4608                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4609
4610                         /* Free the mbuf. */
4611                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4612                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4613
4614                         ifp->if_opackets++;
4615                 }
4616
4617                 sc->used_tx_bd--;
4618                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4619         }
4620
4621         if (sc->used_tx_bd == 0) {
4622                 /* Clear the TX timeout timer. */
4623                 ifp->if_timer = 0;
4624         }
4625
4626         /* Clear the tx hardware queue full flag. */
4627         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE)
4628                 ifp->if_flags &= ~IFF_OACTIVE;
4629         sc->tx_cons = sw_tx_cons;
4630 }
4631
4632
4633 /****************************************************************************/
4634 /* Disables interrupt generation.                                           */
4635 /*                                                                          */
4636 /* Returns:                                                                 */
4637 /*   Nothing.                                                               */
4638 /****************************************************************************/
4639 static void
4640 bce_disable_intr(struct bce_softc *sc)
4641 {
4642         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4643         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4644         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4645 }
4646
4647
4648 /****************************************************************************/
4649 /* Enables interrupt generation.                                            */
4650 /*                                                                          */
4651 /* Returns:                                                                 */
4652 /*   Nothing.                                                               */
4653 /****************************************************************************/
4654 static void
4655 bce_enable_intr(struct bce_softc *sc)
4656 {
4657         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4658
4659         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4660                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4661                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4662         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4663                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4664
4665         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4666 }
4667
4668
4669 /****************************************************************************/
4670 /* Reenables interrupt generation during interrupt handling.                */
4671 /*                                                                          */
4672 /* Returns:                                                                 */
4673 /*   Nothing.                                                               */
4674 /****************************************************************************/
4675 static void
4676 bce_reenable_intr(struct bce_softc *sc)
4677 {
4678         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
4679                 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4680                        BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4681                        BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4682         }
4683         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4684                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4685 }
4686
4687 /****************************************************************************/
4688 /* Handles controller initialization.                                       */
4689 /*                                                                          */
4690 /* Returns:                                                                 */
4691 /*   Nothing.                                                               */
4692 /****************************************************************************/
4693 static void
4694 bce_init(void *xsc)
4695 {
4696         struct bce_softc *sc = xsc;
4697         struct ifnet *ifp = &sc->arpcom.ac_if;
4698         uint32_t ether_mtu;
4699         int error;
4700
4701         ASSERT_SERIALIZED(ifp->if_serializer);
4702
4703         /* Check if the driver is still running and bail out if it is. */
4704         if (ifp->if_flags & IFF_RUNNING)
4705                 return;
4706
4707         bce_stop(sc);
4708
4709         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4710         if (error) {
4711                 if_printf(ifp, "Controller reset failed!\n");
4712                 goto back;
4713         }
4714
4715         error = bce_chipinit(sc);
4716         if (error) {
4717                 if_printf(ifp, "Controller initialization failed!\n");
4718                 goto back;
4719         }
4720
4721         error = bce_blockinit(sc);
4722         if (error) {
4723                 if_printf(ifp, "Block initialization failed!\n");
4724                 goto back;
4725         }
4726
4727         /* Load our MAC address. */
4728         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4729         bce_set_mac_addr(sc);
4730
4731         /* Calculate and program the Ethernet MTU size. */
4732         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4733
4734         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4735
4736         /*
4737          * Program the mtu, enabling jumbo frame
4738          * support if necessary.  Also set the mbuf
4739          * allocation count for RX frames.
4740          */
4741         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4742 #ifdef notyet
4743                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4744                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4745                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4746                 sc->mbuf_alloc_size = MJUM9BYTES;
4747 #else
4748                 panic("jumbo buffer is not supported yet");
4749 #endif
4750         } else {
4751                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4752                 sc->mbuf_alloc_size = MCLBYTES;
4753         }
4754
4755         /* Calculate the RX Ethernet frame size for rx_bd's. */
4756         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4757
4758         DBPRINT(sc, BCE_INFO,
4759                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4760                 "max_frame_size = %d\n",
4761                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4762                 sc->max_frame_size);
4763
4764         /* Program appropriate promiscuous/multicast filtering. */
4765         bce_set_rx_mode(sc);
4766
4767         /* Init RX buffer descriptor chain. */
4768         bce_init_rx_chain(sc);  /* XXX return value */
4769
4770         /* Init TX buffer descriptor chain. */
4771         bce_init_tx_chain(sc);  /* XXX return value */
4772
4773 #ifdef DEVICE_POLLING
4774         /* Disable interrupts if we are polling. */
4775         if (ifp->if_flags & IFF_POLLING) {
4776                 bce_disable_intr(sc);
4777
4778                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4779                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4780                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4781                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4782         } else
4783 #endif
4784         /* Enable host interrupts. */
4785         bce_enable_intr(sc);
4786
4787         bce_ifmedia_upd(ifp);
4788
4789         ifp->if_flags |= IFF_RUNNING;
4790         ifp->if_flags &= ~IFF_OACTIVE;
4791
4792         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4793 back:
4794         if (error)
4795                 bce_stop(sc);
4796 }
4797
4798
4799 /****************************************************************************/
4800 /* Initialize the controller just enough so that any management firmware    */
4801 /* running on the device will continue to operate corectly.                 */
4802 /*                                                                          */
4803 /* Returns:                                                                 */
4804 /*   Nothing.                                                               */
4805 /****************************************************************************/
4806 static void
4807 bce_mgmt_init(struct bce_softc *sc)
4808 {
4809         struct ifnet *ifp = &sc->arpcom.ac_if;
4810
4811         /* Bail out if management firmware is not running. */
4812         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4813                 return;
4814
4815         /* Enable all critical blocks in the MAC. */
4816         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4817             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4818                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4819                     BCE_MISC_ENABLE_DEFAULT_XI);
4820         } else {
4821                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4822         }
4823         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4824         DELAY(20);
4825
4826         bce_ifmedia_upd(ifp);
4827 }
4828
4829
4830 /****************************************************************************/
4831 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4832 /* memory visible to the controller.                                        */
4833 /*                                                                          */
4834 /* Returns:                                                                 */
4835 /*   0 for success, positive value for failure.                             */
4836 /****************************************************************************/
4837 static int
4838 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4839 {
4840         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4841         bus_dmamap_t map, tmp_map;
4842         struct mbuf *m0 = *m_head;
4843         struct tx_bd *txbd = NULL;
4844         uint16_t vlan_tag = 0, flags = 0, mss = 0;
4845         uint16_t chain_prod, chain_prod_start, prod;
4846         uint32_t prod_bseq;
4847         int i, error, maxsegs, nsegs;
4848
4849         /* Transfer any checksum offload flags to the bd. */
4850         if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
4851                 error = bce_tso_setup(sc, m_head, &flags, &mss);
4852                 if (error)
4853                         return ENOBUFS;
4854                 m0 = *m_head;
4855         } else if (m0->m_pkthdr.csum_flags & BCE_CSUM_FEATURES) {
4856                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4857                         flags |= TX_BD_FLAGS_IP_CKSUM;
4858                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4859                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4860         }
4861
4862         /* Transfer any VLAN tags to the bd. */
4863         if (m0->m_flags & M_VLANTAG) {
4864                 flags |= TX_BD_FLAGS_VLAN_TAG;
4865                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4866         }
4867
4868         prod = sc->tx_prod;
4869         chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
4870
4871         /* Map the mbuf into DMAable memory. */
4872         map = sc->tx_mbuf_map[chain_prod_start];
4873
4874         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4875         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4876                 ("not enough segments %d", maxsegs));
4877         if (maxsegs > BCE_MAX_SEGMENTS)
4878                 maxsegs = BCE_MAX_SEGMENTS;
4879
4880         /* Map the mbuf into our DMA address space. */
4881         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4882                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4883         if (error)
4884                 goto back;
4885         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4886
4887         /* Reset m0 */
4888         m0 = *m_head;
4889
4890         /* prod points to an empty tx_bd at this point. */
4891         prod_bseq  = sc->tx_prod_bseq;
4892
4893         /*
4894          * Cycle through each mbuf segment that makes up
4895          * the outgoing frame, gathering the mapping info
4896          * for that segment and creating a tx_bd to for
4897          * the mbuf.
4898          */
4899         for (i = 0; i < nsegs; i++) {
4900                 chain_prod = TX_CHAIN_IDX(sc, prod);
4901                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4902
4903                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4904                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4905                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
4906                     htole16(segs[i].ds_len);
4907                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4908                 txbd->tx_bd_flags = htole16(flags);
4909
4910                 prod_bseq += segs[i].ds_len;
4911                 if (i == 0)
4912                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4913                 prod = NEXT_TX_BD(prod);
4914         }
4915
4916         /* Set the END flag on the last TX buffer descriptor. */
4917         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4918
4919         /*
4920          * Ensure that the mbuf pointer for this transmission
4921          * is placed at the array index of the last
4922          * descriptor in this chain.  This is done
4923          * because a single map is used for all
4924          * segments of the mbuf and we don't want to
4925          * unload the map before all of the segments
4926          * have been freed.
4927          */
4928         sc->tx_mbuf_ptr[chain_prod] = m0;
4929
4930         tmp_map = sc->tx_mbuf_map[chain_prod];
4931         sc->tx_mbuf_map[chain_prod] = map;
4932         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4933
4934         sc->used_tx_bd += nsegs;
4935
4936         /* prod points to the next free tx_bd at this point. */
4937         sc->tx_prod = prod;
4938         sc->tx_prod_bseq = prod_bseq;
4939 back:
4940         if (error) {
4941                 m_freem(*m_head);
4942                 *m_head = NULL;
4943         }
4944         return error;
4945 }
4946
4947
4948 /****************************************************************************/
4949 /* Main transmit routine when called from another routine with a lock.      */
4950 /*                                                                          */
4951 /* Returns:                                                                 */
4952 /*   Nothing.                                                               */
4953 /****************************************************************************/
4954 static void
4955 bce_start(struct ifnet *ifp)
4956 {
4957         struct bce_softc *sc = ifp->if_softc;
4958         int count = 0;
4959
4960         ASSERT_SERIALIZED(ifp->if_serializer);
4961
4962         /* If there's no link or the transmit queue is empty then just exit. */
4963         if (!sc->bce_link) {
4964                 ifq_purge(&ifp->if_snd);
4965                 return;
4966         }
4967
4968         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4969                 return;
4970
4971         for (;;) {
4972                 struct mbuf *m_head;
4973
4974                 /*
4975                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4976                  * unlikely to fail.
4977                  */
4978                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4979                         ifp->if_flags |= IFF_OACTIVE;
4980                         break;
4981                 }
4982
4983                 /* Check for any frames to send. */
4984                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4985                 if (m_head == NULL)
4986                         break;
4987
4988                 /*
4989                  * Pack the data into the transmit ring. If we
4990                  * don't have room, place the mbuf back at the
4991                  * head of the queue and set the OACTIVE flag
4992                  * to wait for the NIC to drain the chain.
4993                  */
4994                 if (bce_encap(sc, &m_head)) {
4995                         ifp->if_oerrors++;
4996                         if (sc->used_tx_bd == 0) {
4997                                 continue;
4998                         } else {
4999                                 ifp->if_flags |= IFF_OACTIVE;
5000                                 break;
5001                         }
5002                 }
5003
5004                 count++;
5005
5006                 /* Send a copy of the frame to any BPF listeners. */
5007                 ETHER_BPF_MTAP(ifp, m_head);
5008         }
5009
5010         if (count == 0) {
5011                 /* no packets were dequeued */
5012                 return;
5013         }
5014
5015         REG_WR(sc, BCE_MQ_COMMAND,
5016             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5017
5018         /* Start the transmit. */
5019         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX,
5020             sc->tx_prod);
5021         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ,
5022             sc->tx_prod_bseq);
5023
5024         /* Set the tx timeout. */
5025         ifp->if_timer = BCE_TX_TIMEOUT;
5026 }
5027
5028
5029 /****************************************************************************/
5030 /* Handles any IOCTL calls from the operating system.                       */
5031 /*                                                                          */
5032 /* Returns:                                                                 */
5033 /*   0 for success, positive value for failure.                             */
5034 /****************************************************************************/
5035 static int
5036 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5037 {
5038         struct bce_softc *sc = ifp->if_softc;
5039         struct ifreq *ifr = (struct ifreq *)data;
5040         struct mii_data *mii;
5041         int mask, error = 0;
5042
5043         ASSERT_SERIALIZED(ifp->if_serializer);
5044
5045         switch(command) {
5046         case SIOCSIFMTU:
5047                 /* Check that the MTU setting is supported. */
5048                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5049 #ifdef notyet
5050                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5051 #else
5052                     ifr->ifr_mtu > ETHERMTU
5053 #endif
5054                    ) {
5055                         error = EINVAL;
5056                         break;
5057                 }
5058
5059                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5060
5061                 ifp->if_mtu = ifr->ifr_mtu;
5062                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5063                 bce_init(sc);
5064                 break;
5065
5066         case SIOCSIFFLAGS:
5067                 if (ifp->if_flags & IFF_UP) {
5068                         if (ifp->if_flags & IFF_RUNNING) {
5069                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5070
5071                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5072                                         bce_set_rx_mode(sc);
5073                         } else {
5074                                 bce_init(sc);
5075                         }
5076                 } else if (ifp->if_flags & IFF_RUNNING) {
5077                         bce_stop(sc);
5078
5079                         /* If MFW is running, restart the controller a bit. */
5080                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5081                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5082                                 bce_chipinit(sc);
5083                                 bce_mgmt_init(sc);
5084                         }
5085                 }
5086                 sc->bce_if_flags = ifp->if_flags;
5087                 break;
5088
5089         case SIOCADDMULTI:
5090         case SIOCDELMULTI:
5091                 if (ifp->if_flags & IFF_RUNNING)
5092                         bce_set_rx_mode(sc);
5093                 break;
5094
5095         case SIOCSIFMEDIA:
5096         case SIOCGIFMEDIA:
5097                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5098                         sc->bce_phy_flags);
5099                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5100
5101                 mii = device_get_softc(sc->bce_miibus);
5102                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5103                 break;
5104
5105         case SIOCSIFCAP:
5106                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5107                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5108                         (uint32_t) mask);
5109
5110                 if (mask & IFCAP_HWCSUM) {
5111                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5112                         if (ifp->if_capenable & IFCAP_TXCSUM)
5113                                 ifp->if_hwassist |= BCE_CSUM_FEATURES;
5114                         else
5115                                 ifp->if_hwassist &= ~BCE_CSUM_FEATURES;
5116                 }
5117                 if (mask & IFCAP_TSO) {
5118                         ifp->if_capenable ^= IFCAP_TSO;
5119                         if (ifp->if_capenable & IFCAP_TSO)
5120                                 ifp->if_hwassist |= CSUM_TSO;
5121                         else
5122                                 ifp->if_hwassist &= ~CSUM_TSO;
5123                 }
5124                 break;
5125
5126         default:
5127                 error = ether_ioctl(ifp, command, data);
5128                 break;
5129         }
5130         return error;
5131 }
5132
5133
5134 /****************************************************************************/
5135 /* Transmit timeout handler.                                                */
5136 /*                                                                          */
5137 /* Returns:                                                                 */
5138 /*   Nothing.                                                               */
5139 /****************************************************************************/
5140 static void
5141 bce_watchdog(struct ifnet *ifp)
5142 {
5143         struct bce_softc *sc = ifp->if_softc;
5144
5145         ASSERT_SERIALIZED(ifp->if_serializer);
5146
5147         DBRUN(BCE_VERBOSE_SEND,
5148               bce_dump_driver_state(sc);
5149               bce_dump_status_block(sc));
5150
5151         /*
5152          * If we are in this routine because of pause frames, then
5153          * don't reset the hardware.
5154          */
5155         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5156                 return;
5157
5158         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5159
5160         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5161
5162         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5163         bce_init(sc);
5164
5165         ifp->if_oerrors++;
5166
5167         if (!ifq_is_empty(&ifp->if_snd))
5168                 if_devstart(ifp);
5169 }
5170
5171
5172 #ifdef DEVICE_POLLING
5173
5174 static void
5175 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5176 {
5177         struct bce_softc *sc = ifp->if_softc;
5178         struct status_block *sblk = sc->status_block;
5179         uint16_t hw_tx_cons, hw_rx_cons;
5180
5181         ASSERT_SERIALIZED(ifp->if_serializer);
5182
5183         switch (cmd) {
5184         case POLL_REGISTER:
5185                 bce_disable_intr(sc);
5186
5187                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5188                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5189                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5190                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5191                 return;
5192         case POLL_DEREGISTER:
5193                 bce_enable_intr(sc);
5194
5195                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5196                        (sc->bce_tx_quick_cons_trip_int << 16) |
5197                        sc->bce_tx_quick_cons_trip);
5198                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5199                        (sc->bce_rx_quick_cons_trip_int << 16) |
5200                        sc->bce_rx_quick_cons_trip);
5201                 return;
5202         default:
5203                 break;
5204         }
5205
5206         /*
5207          * Save the status block index value for use when enabling
5208          * the interrupt.
5209          */
5210         sc->last_status_idx = sblk->status_idx;
5211
5212         /* Make sure status index is extracted before rx/tx cons */
5213         cpu_lfence();
5214
5215         if (cmd == POLL_AND_CHECK_STATUS) {
5216                 uint32_t status_attn_bits;
5217
5218                 status_attn_bits = sblk->status_attn_bits;
5219
5220                 /* Was it a link change interrupt? */
5221                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5222                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5223                         bce_phy_intr(sc);
5224
5225                 /* Clear any transient status updates during link state change. */
5226                 REG_WR(sc, BCE_HC_COMMAND,
5227                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5228                 REG_RD(sc, BCE_HC_COMMAND);
5229
5230                 /*
5231                  * If any other attention is asserted then
5232                  * the chip is toast.
5233                  */
5234                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5235                      (sblk->status_attn_bits_ack &
5236                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5237                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5238                                   sblk->status_attn_bits);
5239                         bce_init(sc);
5240                         return;
5241                 }
5242         }
5243
5244         hw_rx_cons = bce_get_hw_rx_cons(sc);
5245         hw_tx_cons = bce_get_hw_tx_cons(sc);
5246
5247         /* Check for any completed RX frames. */
5248         if (hw_rx_cons != sc->rx_cons)
5249                 bce_rx_intr(sc, count, hw_rx_cons);
5250
5251         /* Check for any completed TX frames. */
5252         if (hw_tx_cons != sc->tx_cons)
5253                 bce_tx_intr(sc, hw_tx_cons);
5254
5255         /* Check for new frames to transmit. */
5256         if (!ifq_is_empty(&ifp->if_snd))
5257                 if_devstart(ifp);
5258 }
5259
5260 #endif  /* DEVICE_POLLING */
5261
5262
5263 /*
5264  * Interrupt handler.
5265  */
5266 /****************************************************************************/
5267 /* Main interrupt entry point.  Verifies that the controller generated the  */
5268 /* interrupt and then calls a separate routine for handle the various       */
5269 /* interrupt causes (PHY, TX, RX).                                          */
5270 /*                                                                          */
5271 /* Returns:                                                                 */
5272 /*   0 for success, positive value for failure.                             */
5273 /****************************************************************************/
5274 static void
5275 bce_intr(struct bce_softc *sc)
5276 {
5277         struct ifnet *ifp = &sc->arpcom.ac_if;
5278         struct status_block *sblk;
5279         uint16_t hw_rx_cons, hw_tx_cons;
5280         uint32_t status_attn_bits;
5281
5282         ASSERT_SERIALIZED(ifp->if_serializer);
5283
5284         sblk = sc->status_block;
5285
5286         /*
5287          * Save the status block index value for use during
5288          * the next interrupt.
5289          */
5290         sc->last_status_idx = sblk->status_idx;
5291
5292         /* Make sure status index is extracted before rx/tx cons */
5293         cpu_lfence();
5294
5295         /* Check if the hardware has finished any work. */
5296         hw_rx_cons = bce_get_hw_rx_cons(sc);
5297         hw_tx_cons = bce_get_hw_tx_cons(sc);
5298
5299         status_attn_bits = sblk->status_attn_bits;
5300
5301         /* Was it a link change interrupt? */
5302         if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5303             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5304                 bce_phy_intr(sc);
5305
5306                 /*
5307                  * Clear any transient status updates during link state
5308                  * change.
5309                  */
5310                 REG_WR(sc, BCE_HC_COMMAND,
5311                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5312                 REG_RD(sc, BCE_HC_COMMAND);
5313         }
5314
5315         /*
5316          * If any other attention is asserted then
5317          * the chip is toast.
5318          */
5319         if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5320             (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5321                 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5322                           sblk->status_attn_bits);
5323                 bce_init(sc);
5324                 return;
5325         }
5326
5327         /* Check for any completed RX frames. */
5328         if (hw_rx_cons != sc->rx_cons)
5329                 bce_rx_intr(sc, -1, hw_rx_cons);
5330
5331         /* Check for any completed TX frames. */
5332         if (hw_tx_cons != sc->tx_cons)
5333                 bce_tx_intr(sc, hw_tx_cons);
5334
5335         /* Re-enable interrupts. */
5336         bce_reenable_intr(sc);
5337
5338         if (sc->bce_coalchg_mask)
5339                 bce_coal_change(sc);
5340
5341         /* Handle any frames that arrived while handling the interrupt. */
5342         if (!ifq_is_empty(&ifp->if_snd))
5343                 if_devstart(ifp);
5344 }
5345
5346 static void
5347 bce_intr_legacy(void *xsc)
5348 {
5349         struct bce_softc *sc = xsc;
5350         struct status_block *sblk;
5351
5352         sblk = sc->status_block;
5353
5354         /*
5355          * If the hardware status block index matches the last value
5356          * read by the driver and we haven't asserted our interrupt
5357          * then there's nothing to do.
5358          */
5359         if (sblk->status_idx == sc->last_status_idx &&
5360             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5361              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5362                 return;
5363
5364         /* Ack the interrupt and stop others from occuring. */
5365         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5366                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5367                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5368
5369         /*
5370          * Read back to deassert IRQ immediately to avoid too
5371          * many spurious interrupts.
5372          */
5373         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5374
5375         bce_intr(sc);
5376 }
5377
5378 static void
5379 bce_intr_msi(void *xsc)
5380 {
5381         struct bce_softc *sc = xsc;
5382
5383         /* Ack the interrupt and stop others from occuring. */
5384         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5385                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5386                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5387
5388         bce_intr(sc);
5389 }
5390
5391 static void
5392 bce_intr_msi_oneshot(void *xsc)
5393 {
5394         bce_intr(xsc);
5395 }
5396
5397
5398 /****************************************************************************/
5399 /* Programs the various packet receive modes (broadcast and multicast).     */
5400 /*                                                                          */
5401 /* Returns:                                                                 */
5402 /*   Nothing.                                                               */
5403 /****************************************************************************/
5404 static void
5405 bce_set_rx_mode(struct bce_softc *sc)
5406 {
5407         struct ifnet *ifp = &sc->arpcom.ac_if;
5408         struct ifmultiaddr *ifma;
5409         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5410         uint32_t rx_mode, sort_mode;
5411         int h, i;
5412
5413         ASSERT_SERIALIZED(ifp->if_serializer);
5414
5415         /* Initialize receive mode default settings. */
5416         rx_mode = sc->rx_mode &
5417                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5418                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5419         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5420
5421         /*
5422          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5423          * be enbled.
5424          */
5425         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5426             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5427                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5428
5429         /*
5430          * Check for promiscuous, all multicast, or selected
5431          * multicast address filtering.
5432          */
5433         if (ifp->if_flags & IFF_PROMISC) {
5434                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5435
5436                 /* Enable promiscuous mode. */
5437                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5438                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5439         } else if (ifp->if_flags & IFF_ALLMULTI) {
5440                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5441
5442                 /* Enable all multicast addresses. */
5443                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5444                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5445                                0xffffffff);
5446                 }
5447                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5448         } else {
5449                 /* Accept one or more multicast(s). */
5450                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5451
5452                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5453                         if (ifma->ifma_addr->sa_family != AF_LINK)
5454                                 continue;
5455                         h = ether_crc32_le(
5456                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5457                             ETHER_ADDR_LEN) & 0xFF;
5458                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5459                 }
5460
5461                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5462                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5463                                hashes[i]);
5464                 }
5465                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5466         }
5467
5468         /* Only make changes if the recive mode has actually changed. */
5469         if (rx_mode != sc->rx_mode) {
5470                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5471                         rx_mode);
5472
5473                 sc->rx_mode = rx_mode;
5474                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5475         }
5476
5477         /* Disable and clear the exisitng sort before enabling a new sort. */
5478         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5479         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5480         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5481 }
5482
5483
5484 /****************************************************************************/
5485 /* Called periodically to updates statistics from the controllers           */
5486 /* statistics block.                                                        */
5487 /*                                                                          */
5488 /* Returns:                                                                 */
5489 /*   Nothing.                                                               */
5490 /****************************************************************************/
5491 static void
5492 bce_stats_update(struct bce_softc *sc)
5493 {
5494         struct ifnet *ifp = &sc->arpcom.ac_if;
5495         struct statistics_block *stats = sc->stats_block;
5496
5497         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5498
5499         ASSERT_SERIALIZED(ifp->if_serializer);
5500
5501         /*
5502          * Certain controllers don't report carrier sense errors correctly.
5503          * See errata E11_5708CA0_1165.
5504          */
5505         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5506             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5507                 ifp->if_oerrors +=
5508                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5509         }
5510
5511         /*
5512          * Update the sysctl statistics from the hardware statistics.
5513          */
5514         sc->stat_IfHCInOctets =
5515                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5516                  (uint64_t)stats->stat_IfHCInOctets_lo;
5517
5518         sc->stat_IfHCInBadOctets =
5519                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5520                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5521
5522         sc->stat_IfHCOutOctets =
5523                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5524                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5525
5526         sc->stat_IfHCOutBadOctets =
5527                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5528                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5529
5530         sc->stat_IfHCInUcastPkts =
5531                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5532                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5533
5534         sc->stat_IfHCInMulticastPkts =
5535                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5536                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5537
5538         sc->stat_IfHCInBroadcastPkts =
5539                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5540                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5541
5542         sc->stat_IfHCOutUcastPkts =
5543                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5544                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5545
5546         sc->stat_IfHCOutMulticastPkts =
5547                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5548                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5549
5550         sc->stat_IfHCOutBroadcastPkts =
5551                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5552                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5553
5554         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5555                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5556
5557         sc->stat_Dot3StatsCarrierSenseErrors =
5558                 stats->stat_Dot3StatsCarrierSenseErrors;
5559
5560         sc->stat_Dot3StatsFCSErrors =
5561                 stats->stat_Dot3StatsFCSErrors;
5562
5563         sc->stat_Dot3StatsAlignmentErrors =
5564                 stats->stat_Dot3StatsAlignmentErrors;
5565
5566         sc->stat_Dot3StatsSingleCollisionFrames =
5567                 stats->stat_Dot3StatsSingleCollisionFrames;
5568
5569         sc->stat_Dot3StatsMultipleCollisionFrames =
5570                 stats->stat_Dot3StatsMultipleCollisionFrames;
5571
5572         sc->stat_Dot3StatsDeferredTransmissions =
5573                 stats->stat_Dot3StatsDeferredTransmissions;
5574
5575         sc->stat_Dot3StatsExcessiveCollisions =
5576                 stats->stat_Dot3StatsExcessiveCollisions;
5577
5578         sc->stat_Dot3StatsLateCollisions =
5579                 stats->stat_Dot3StatsLateCollisions;
5580
5581         sc->stat_EtherStatsCollisions =
5582                 stats->stat_EtherStatsCollisions;
5583
5584         sc->stat_EtherStatsFragments =
5585                 stats->stat_EtherStatsFragments;
5586
5587         sc->stat_EtherStatsJabbers =
5588                 stats->stat_EtherStatsJabbers;
5589
5590         sc->stat_EtherStatsUndersizePkts =
5591                 stats->stat_EtherStatsUndersizePkts;
5592
5593         sc->stat_EtherStatsOverrsizePkts =
5594                 stats->stat_EtherStatsOverrsizePkts;
5595
5596         sc->stat_EtherStatsPktsRx64Octets =
5597                 stats->stat_EtherStatsPktsRx64Octets;
5598
5599         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5600                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5601
5602         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5603                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5604
5605         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5606                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5607
5608         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5609                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5610
5611         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5612                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5613
5614         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5615                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5616
5617         sc->stat_EtherStatsPktsTx64Octets =
5618                 stats->stat_EtherStatsPktsTx64Octets;
5619
5620         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5621                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5622
5623         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5624                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5625
5626         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5627                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5628
5629         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5630                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5631
5632         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5633                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5634
5635         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5636                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5637
5638         sc->stat_XonPauseFramesReceived =
5639                 stats->stat_XonPauseFramesReceived;
5640
5641         sc->stat_XoffPauseFramesReceived =
5642                 stats->stat_XoffPauseFramesReceived;
5643
5644         sc->stat_OutXonSent =
5645                 stats->stat_OutXonSent;
5646
5647         sc->stat_OutXoffSent =
5648                 stats->stat_OutXoffSent;
5649
5650         sc->stat_FlowControlDone =
5651                 stats->stat_FlowControlDone;
5652
5653         sc->stat_MacControlFramesReceived =
5654                 stats->stat_MacControlFramesReceived;
5655
5656         sc->stat_XoffStateEntered =
5657                 stats->stat_XoffStateEntered;
5658
5659         sc->stat_IfInFramesL2FilterDiscards =
5660                 stats->stat_IfInFramesL2FilterDiscards;
5661
5662         sc->stat_IfInRuleCheckerDiscards =
5663                 stats->stat_IfInRuleCheckerDiscards;
5664
5665         sc->stat_IfInFTQDiscards =
5666                 stats->stat_IfInFTQDiscards;
5667
5668         sc->stat_IfInMBUFDiscards =
5669                 stats->stat_IfInMBUFDiscards;
5670
5671         sc->stat_IfInRuleCheckerP4Hit =
5672                 stats->stat_IfInRuleCheckerP4Hit;
5673
5674         sc->stat_CatchupInRuleCheckerDiscards =
5675                 stats->stat_CatchupInRuleCheckerDiscards;
5676
5677         sc->stat_CatchupInFTQDiscards =
5678                 stats->stat_CatchupInFTQDiscards;
5679
5680         sc->stat_CatchupInMBUFDiscards =
5681                 stats->stat_CatchupInMBUFDiscards;
5682
5683         sc->stat_CatchupInRuleCheckerP4Hit =
5684                 stats->stat_CatchupInRuleCheckerP4Hit;
5685
5686         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5687
5688         /*
5689          * Update the interface statistics from the
5690          * hardware statistics.
5691          */
5692         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5693
5694         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5695             (u_long)sc->stat_EtherStatsOverrsizePkts +
5696             (u_long)sc->stat_IfInMBUFDiscards +
5697             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5698             (u_long)sc->stat_Dot3StatsFCSErrors +
5699             (u_long)sc->stat_IfInRuleCheckerDiscards +
5700             (u_long)sc->stat_IfInFTQDiscards +
5701             (u_long)sc->com_no_buffers;
5702
5703         ifp->if_oerrors =
5704             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5705             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5706             (u_long)sc->stat_Dot3StatsLateCollisions;
5707
5708         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5709 }
5710
5711
5712 /****************************************************************************/
5713 /* Periodic function to notify the bootcode that the driver is still        */
5714 /* present.                                                                 */
5715 /*                                                                          */
5716 /* Returns:                                                                 */
5717 /*   Nothing.                                                               */
5718 /****************************************************************************/
5719 static void
5720 bce_pulse(void *xsc)
5721 {
5722         struct bce_softc *sc = xsc;
5723         struct ifnet *ifp = &sc->arpcom.ac_if;
5724         uint32_t msg;
5725
5726         lwkt_serialize_enter(ifp->if_serializer);
5727
5728         if (ifp->if_flags & IFF_RUNNING) {
5729                 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5730                     (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5731                         bce_pulse_check_msi(sc);
5732         }
5733
5734         /* Tell the firmware that the driver is still running. */
5735         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5736         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5737
5738         /* Update the bootcode condition. */
5739         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5740
5741         /* Report whether the bootcode still knows the driver is running. */
5742         if (!sc->bce_drv_cardiac_arrest) {
5743                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5744                         sc->bce_drv_cardiac_arrest = 1;
5745                         if_printf(ifp, "Bootcode lost the driver pulse! "
5746                             "(bc_state = 0x%08X)\n", sc->bc_state);
5747                 }
5748         } else {
5749                 /*
5750                  * Not supported by all bootcode versions.
5751                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5752                  * will require the driver to reset the
5753                  * controller to clear this condition.
5754                  */
5755                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5756                         sc->bce_drv_cardiac_arrest = 0;
5757                         if_printf(ifp, "Bootcode found the driver pulse! "
5758                             "(bc_state = 0x%08X)\n", sc->bc_state);
5759                 }
5760         }
5761
5762         /* Schedule the next pulse. */
5763         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5764
5765         lwkt_serialize_exit(ifp->if_serializer);
5766 }
5767
5768 static void
5769 bce_pulse_check_msi(struct bce_softc *sc)
5770 {
5771         int check = 0;
5772
5773         if (bce_get_hw_rx_cons(sc) != sc->rx_cons) {
5774                 check = 1;
5775         } else if (bce_get_hw_tx_cons(sc) != sc->tx_cons) {
5776                 check = 1;
5777         } else {
5778                 struct status_block *sblk = sc->status_block;
5779
5780                 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5781                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5782                         check = 1;
5783         }
5784
5785         if (check) {
5786                 uint32_t msi_ctrl;
5787
5788                 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5789                 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
5790                         return;
5791
5792                 if (sc->pulse_check_status_idx == sc->last_status_idx) {
5793                         if_printf(&sc->arpcom.ac_if, "missing MSI\n");
5794
5795                         REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5796                             msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5797                         REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5798
5799                         bce_intr_msi(sc);
5800                 }
5801         }
5802         sc->pulse_check_status_idx = sc->last_status_idx;
5803 }
5804
5805 /****************************************************************************/
5806 /* Periodic function to perform maintenance tasks.                          */
5807 /*                                                                          */
5808 /* Returns:                                                                 */
5809 /*   Nothing.                                                               */
5810 /****************************************************************************/
5811 static void
5812 bce_tick_serialized(struct bce_softc *sc)
5813 {
5814         struct ifnet *ifp = &sc->arpcom.ac_if;
5815         struct mii_data *mii;
5816
5817         ASSERT_SERIALIZED(ifp->if_serializer);
5818
5819         /* Update the statistics from the hardware statistics block. */
5820         bce_stats_update(sc);
5821
5822         /* Schedule the next tick. */
5823         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5824
5825         /* If link is up already up then we're done. */
5826         if (sc->bce_link)
5827                 return;
5828
5829         mii = device_get_softc(sc->bce_miibus);
5830         mii_tick(mii);
5831
5832         /* Check if the link has come up. */
5833         if ((mii->mii_media_status & IFM_ACTIVE) &&
5834             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5835                 sc->bce_link++;
5836                 /* Now that link is up, handle any outstanding TX traffic. */
5837                 if (!ifq_is_empty(&ifp->if_snd))
5838                         if_devstart(ifp);
5839         }
5840 }
5841
5842
5843 static void
5844 bce_tick(void *xsc)
5845 {
5846         struct bce_softc *sc = xsc;
5847         struct ifnet *ifp = &sc->arpcom.ac_if;
5848
5849         lwkt_serialize_enter(ifp->if_serializer);
5850         bce_tick_serialized(sc);
5851         lwkt_serialize_exit(ifp->if_serializer);
5852 }
5853
5854
5855 #ifdef BCE_DEBUG
5856 /****************************************************************************/
5857 /* Allows the driver state to be dumped through the sysctl interface.       */
5858 /*                                                                          */
5859 /* Returns:                                                                 */
5860 /*   0 for success, positive value for failure.                             */
5861 /****************************************************************************/
5862 static int
5863 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5864 {
5865         int error;
5866         int result;
5867         struct bce_softc *sc;
5868
5869         result = -1;
5870         error = sysctl_handle_int(oidp, &result, 0, req);
5871
5872         if (error || !req->newptr)
5873                 return (error);
5874
5875         if (result == 1) {
5876                 sc = (struct bce_softc *)arg1;
5877                 bce_dump_driver_state(sc);
5878         }
5879
5880         return error;
5881 }
5882
5883
5884 /****************************************************************************/
5885 /* Allows the hardware state to be dumped through the sysctl interface.     */
5886 /*                                                                          */
5887 /* Returns:                                                                 */
5888 /*   0 for success, positive value for failure.                             */
5889 /****************************************************************************/
5890 static int
5891 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5892 {
5893         int error;
5894         int result;
5895         struct bce_softc *sc;
5896
5897         result = -1;
5898         error = sysctl_handle_int(oidp, &result, 0, req);
5899
5900         if (error || !req->newptr)
5901                 return (error);
5902
5903         if (result == 1) {
5904                 sc = (struct bce_softc *)arg1;
5905                 bce_dump_hw_state(sc);
5906         }
5907
5908         return error;
5909 }
5910
5911
5912 /****************************************************************************/
5913 /* Provides a sysctl interface to allows dumping the RX chain.              */
5914 /*                                                                          */
5915 /* Returns:                                                                 */
5916 /*   0 for success, positive value for failure.                             */
5917 /****************************************************************************/
5918 static int
5919 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5920 {
5921         int error;
5922         int result;
5923         struct bce_softc *sc;
5924
5925         result = -1;
5926         error = sysctl_handle_int(oidp, &result, 0, req);
5927
5928         if (error || !req->newptr)
5929                 return (error);
5930
5931         if (result == 1) {
5932                 sc = (struct bce_softc *)arg1;
5933                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
5934         }
5935
5936         return error;
5937 }
5938
5939
5940 /****************************************************************************/
5941 /* Provides a sysctl interface to allows dumping the TX chain.              */
5942 /*                                                                          */
5943 /* Returns:                                                                 */
5944 /*   0 for success, positive value for failure.                             */
5945 /****************************************************************************/
5946 static int
5947 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5948 {
5949         int error;
5950         int result;
5951         struct bce_softc *sc;
5952
5953         result = -1;
5954         error = sysctl_handle_int(oidp, &result, 0, req);
5955
5956         if (error || !req->newptr)
5957                 return (error);
5958
5959         if (result == 1) {
5960                 sc = (struct bce_softc *)arg1;
5961                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
5962         }
5963
5964         return error;
5965 }
5966
5967
5968 /****************************************************************************/
5969 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5970 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5971 /*                                                                          */
5972 /* Returns:                                                                 */
5973 /*   0 for success, positive value for failure.                             */
5974 /****************************************************************************/
5975 static int
5976 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5977 {
5978         struct bce_softc *sc;
5979         int error;
5980         uint32_t val, result;
5981
5982         result = -1;
5983         error = sysctl_handle_int(oidp, &result, 0, req);
5984         if (error || (req->newptr == NULL))
5985                 return (error);
5986
5987         /* Make sure the register is accessible. */
5988         if (result < 0x8000) {
5989                 sc = (struct bce_softc *)arg1;
5990                 val = REG_RD(sc, result);
5991                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5992                           result, val);
5993         } else if (result < 0x0280000) {
5994                 sc = (struct bce_softc *)arg1;
5995                 val = REG_RD_IND(sc, result);
5996                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5997                           result, val);
5998         }
5999         return (error);
6000 }
6001
6002
6003 /****************************************************************************/
6004 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
6005 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
6006 /*                                                                          */
6007 /* Returns:                                                                 */
6008 /*   0 for success, positive value for failure.                             */
6009 /****************************************************************************/
6010 static int
6011 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6012 {
6013         struct bce_softc *sc;
6014         device_t dev;
6015         int error, result;
6016         uint16_t val;
6017
6018         result = -1;
6019         error = sysctl_handle_int(oidp, &result, 0, req);
6020         if (error || (req->newptr == NULL))
6021                 return (error);
6022
6023         /* Make sure the register is accessible. */
6024         if (result < 0x20) {
6025                 sc = (struct bce_softc *)arg1;
6026                 dev = sc->bce_dev;
6027                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6028                 if_printf(&sc->arpcom.ac_if,
6029                           "phy 0x%02X = 0x%04X\n", result, val);
6030         }
6031         return (error);
6032 }
6033
6034
6035 /****************************************************************************/
6036 /* Provides a sysctl interface to forcing the driver to dump state and      */
6037 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
6038 /*                                                                          */
6039 /* Returns:                                                                 */
6040 /*   0 for success, positive value for failure.                             */
6041 /****************************************************************************/
6042 static int
6043 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6044 {
6045         int error;
6046         int result;
6047         struct bce_softc *sc;
6048
6049         result = -1;
6050         error = sysctl_handle_int(oidp, &result, 0, req);
6051
6052         if (error || !req->newptr)
6053                 return (error);
6054
6055         if (result == 1) {
6056                 sc = (struct bce_softc *)arg1;
6057                 bce_breakpoint(sc);
6058         }
6059
6060         return error;
6061 }
6062 #endif
6063
6064
6065 /****************************************************************************/
6066 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6067 /*                                                                          */
6068 /* Returns:                                                                 */
6069 /*   0 for success, positive value for failure.                             */
6070 /****************************************************************************/
6071 static void
6072 bce_add_sysctls(struct bce_softc *sc)
6073 {
6074         struct sysctl_ctx_list *ctx;
6075         struct sysctl_oid_list *children;
6076
6077         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6078         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6079                                               SYSCTL_STATIC_CHILDREN(_hw),
6080                                               OID_AUTO,
6081                                               device_get_nameunit(sc->bce_dev),
6082                                               CTLFLAG_RD, 0, "");
6083         if (sc->bce_sysctl_tree == NULL) {
6084                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6085                 return;
6086         }
6087
6088         ctx = &sc->bce_sysctl_ctx;
6089         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6090
6091         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6092                         CTLTYPE_INT | CTLFLAG_RW,
6093                         sc, 0, bce_sysctl_tx_bds_int, "I",
6094                         "Send max coalesced BD count during interrupt");
6095         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6096                         CTLTYPE_INT | CTLFLAG_RW,
6097                         sc, 0, bce_sysctl_tx_bds, "I",
6098                         "Send max coalesced BD count");
6099         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6100                         CTLTYPE_INT | CTLFLAG_RW,
6101                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6102                         "Send coalescing ticks during interrupt");
6103         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6104                         CTLTYPE_INT | CTLFLAG_RW,
6105                         sc, 0, bce_sysctl_tx_ticks, "I",
6106                         "Send coalescing ticks");
6107
6108         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6109                         CTLTYPE_INT | CTLFLAG_RW,
6110                         sc, 0, bce_sysctl_rx_bds_int, "I",
6111                         "Receive max coalesced BD count during interrupt");
6112         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6113                         CTLTYPE_INT | CTLFLAG_RW,
6114                         sc, 0, bce_sysctl_rx_bds, "I",
6115                         "Receive max coalesced BD count");
6116         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6117                         CTLTYPE_INT | CTLFLAG_RW,
6118                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6119                         "Receive coalescing ticks during interrupt");
6120         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6121                         CTLTYPE_INT | CTLFLAG_RW,
6122                         sc, 0, bce_sysctl_rx_ticks, "I",
6123                         "Receive coalescing ticks");
6124
6125         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6126                 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6127         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6128                 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6129
6130 #ifdef BCE_DEBUG
6131         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6132                 "rx_low_watermark",
6133                 CTLFLAG_RD, &sc->rx_low_watermark,
6134                 0, "Lowest level of free rx_bd's");
6135
6136         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6137                 "rx_empty_count",
6138                 CTLFLAG_RD, &sc->rx_empty_count,
6139                 0, "Number of times the RX chain was empty");
6140
6141         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6142                 "tx_hi_watermark",
6143                 CTLFLAG_RD, &sc->tx_hi_watermark,
6144                 0, "Highest level of used tx_bd's");
6145
6146         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6147                 "tx_full_count",
6148                 CTLFLAG_RD, &sc->tx_full_count,
6149                 0, "Number of times the TX chain was full");
6150
6151         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6152                 "l2fhdr_status_errors",
6153                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6154                 0, "l2_fhdr status errors");
6155
6156         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6157                 "unexpected_attentions",
6158                 CTLFLAG_RD, &sc->unexpected_attentions,
6159                 0, "unexpected attentions");
6160
6161         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6162                 "lost_status_block_updates",
6163                 CTLFLAG_RD, &sc->lost_status_block_updates,
6164                 0, "lost status block updates");
6165
6166         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6167                 "mbuf_alloc_failed",
6168                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6169                 0, "mbuf cluster allocation failures");
6170 #endif
6171
6172         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6173                 "stat_IfHCInOctets",
6174                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6175                 "Bytes received");
6176
6177         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6178                 "stat_IfHCInBadOctets",
6179                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6180                 "Bad bytes received");
6181
6182         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6183                 "stat_IfHCOutOctets",
6184                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6185                 "Bytes sent");
6186
6187         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6188                 "stat_IfHCOutBadOctets",
6189                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6190                 "Bad bytes sent");
6191
6192         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6193                 "stat_IfHCInUcastPkts",
6194                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6195                 "Unicast packets received");
6196
6197         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6198                 "stat_IfHCInMulticastPkts",
6199                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6200                 "Multicast packets received");
6201
6202         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6203                 "stat_IfHCInBroadcastPkts",
6204                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6205                 "Broadcast packets received");
6206
6207         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6208                 "stat_IfHCOutUcastPkts",
6209                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6210                 "Unicast packets sent");
6211
6212         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6213                 "stat_IfHCOutMulticastPkts",
6214                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6215                 "Multicast packets sent");
6216
6217         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6218                 "stat_IfHCOutBroadcastPkts",
6219                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6220                 "Broadcast packets sent");
6221
6222         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6223                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6224                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6225                 0, "Internal MAC transmit errors");
6226
6227         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6228                 "stat_Dot3StatsCarrierSenseErrors",
6229                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6230                 0, "Carrier sense errors");
6231
6232         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6233                 "stat_Dot3StatsFCSErrors",
6234                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6235                 0, "Frame check sequence errors");
6236
6237         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6238                 "stat_Dot3StatsAlignmentErrors",
6239                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6240                 0, "Alignment errors");
6241
6242         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6243                 "stat_Dot3StatsSingleCollisionFrames",
6244                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6245                 0, "Single Collision Frames");
6246
6247         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6248                 "stat_Dot3StatsMultipleCollisionFrames",
6249                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6250                 0, "Multiple Collision Frames");
6251
6252         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6253                 "stat_Dot3StatsDeferredTransmissions",
6254                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6255                 0, "Deferred Transmissions");
6256
6257         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6258                 "stat_Dot3StatsExcessiveCollisions",
6259                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6260                 0, "Excessive Collisions");
6261
6262         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6263                 "stat_Dot3StatsLateCollisions",
6264                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6265                 0, "Late Collisions");
6266
6267         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6268                 "stat_EtherStatsCollisions",
6269                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6270                 0, "Collisions");
6271
6272         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6273                 "stat_EtherStatsFragments",
6274                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6275                 0, "Fragments");
6276
6277         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6278                 "stat_EtherStatsJabbers",
6279                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6280                 0, "Jabbers");
6281
6282         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6283                 "stat_EtherStatsUndersizePkts",
6284                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6285                 0, "Undersize packets");
6286
6287         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6288                 "stat_EtherStatsOverrsizePkts",
6289                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6290                 0, "stat_EtherStatsOverrsizePkts");
6291
6292         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6293                 "stat_EtherStatsPktsRx64Octets",
6294                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6295                 0, "Bytes received in 64 byte packets");
6296
6297         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6298                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6299                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6300                 0, "Bytes received in 65 to 127 byte packets");
6301
6302         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6303                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6304                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6305                 0, "Bytes received in 128 to 255 byte packets");
6306
6307         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6308                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6309                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6310                 0, "Bytes received in 256 to 511 byte packets");
6311
6312         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6313                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6314                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6315                 0, "Bytes received in 512 to 1023 byte packets");
6316
6317         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6318                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6319                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6320                 0, "Bytes received in 1024 t0 1522 byte packets");
6321
6322         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6323                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6324                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6325                 0, "Bytes received in 1523 to 9022 byte packets");
6326
6327         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6328                 "stat_EtherStatsPktsTx64Octets",
6329                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6330                 0, "Bytes sent in 64 byte packets");
6331
6332         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6333                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6334                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6335                 0, "Bytes sent in 65 to 127 byte packets");
6336
6337         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6338                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6339                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6340                 0, "Bytes sent in 128 to 255 byte packets");
6341
6342         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6343                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6344                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6345                 0, "Bytes sent in 256 to 511 byte packets");
6346
6347         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6348                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6349                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6350                 0, "Bytes sent in 512 to 1023 byte packets");
6351
6352         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6353                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6354                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6355                 0, "Bytes sent in 1024 to 1522 byte packets");
6356
6357         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6358                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6359                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6360                 0, "Bytes sent in 1523 to 9022 byte packets");
6361
6362         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6363                 "stat_XonPauseFramesReceived",
6364                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6365                 0, "XON pause frames receved");
6366
6367         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6368                 "stat_XoffPauseFramesReceived",
6369                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6370                 0, "XOFF pause frames received");
6371
6372         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6373                 "stat_OutXonSent",
6374                 CTLFLAG_RD, &sc->stat_OutXonSent,
6375                 0, "XON pause frames sent");
6376
6377         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6378                 "stat_OutXoffSent",
6379                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6380                 0, "XOFF pause frames sent");
6381
6382         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6383                 "stat_FlowControlDone",
6384                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6385                 0, "Flow control done");
6386
6387         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6388                 "stat_MacControlFramesReceived",
6389                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6390                 0, "MAC control frames received");
6391
6392         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6393                 "stat_XoffStateEntered",
6394                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6395                 0, "XOFF state entered");
6396
6397         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6398                 "stat_IfInFramesL2FilterDiscards",
6399                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6400                 0, "Received L2 packets discarded");
6401
6402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6403                 "stat_IfInRuleCheckerDiscards",
6404                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6405                 0, "Received packets discarded by rule");
6406
6407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6408                 "stat_IfInFTQDiscards",
6409                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6410                 0, "Received packet FTQ discards");
6411
6412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6413                 "stat_IfInMBUFDiscards",
6414                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6415                 0, "Received packets discarded due to lack of controller buffer memory");
6416
6417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6418                 "stat_IfInRuleCheckerP4Hit",
6419                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6420                 0, "Received packets rule checker hits");
6421
6422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6423                 "stat_CatchupInRuleCheckerDiscards",
6424                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6425                 0, "Received packets discarded in Catchup path");
6426
6427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6428                 "stat_CatchupInFTQDiscards",
6429                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6430                 0, "Received packets discarded in FTQ in Catchup path");
6431
6432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6433                 "stat_CatchupInMBUFDiscards",
6434                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6435                 0, "Received packets discarded in controller buffer memory in Catchup path");
6436
6437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6438                 "stat_CatchupInRuleCheckerP4Hit",
6439                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6440                 0, "Received packets rule checker hits in Catchup path");
6441
6442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6443                 "com_no_buffers",
6444                 CTLFLAG_RD, &sc->com_no_buffers,
6445                 0, "Valid packets received but no RX buffers available");
6446
6447 #ifdef BCE_DEBUG
6448         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6449                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6450                 (void *)sc, 0,
6451                 bce_sysctl_driver_state, "I", "Drive state information");
6452
6453         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6454                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6455                 (void *)sc, 0,
6456                 bce_sysctl_hw_state, "I", "Hardware state information");
6457
6458         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6459                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6460                 (void *)sc, 0,
6461                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6462
6463         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6464                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6465                 (void *)sc, 0,
6466                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6467
6468         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6469                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6470                 (void *)sc, 0,
6471                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6472
6473         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6474                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6475                 (void *)sc, 0,
6476                 bce_sysctl_reg_read, "I", "Register read");
6477
6478         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6479                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6480                 (void *)sc, 0,
6481                 bce_sysctl_phy_read, "I", "PHY register read");
6482
6483 #endif
6484
6485 }
6486
6487
6488 /****************************************************************************/
6489 /* BCE Debug Routines                                                       */
6490 /****************************************************************************/
6491 #ifdef BCE_DEBUG
6492
6493 /****************************************************************************/
6494 /* Freezes the controller to allow for a cohesive state dump.               */
6495 /*                                                                          */
6496 /* Returns:                                                                 */
6497 /*   Nothing.                                                               */
6498 /****************************************************************************/
6499 static void
6500 bce_freeze_controller(struct bce_softc *sc)
6501 {
6502         uint32_t val;
6503
6504         val = REG_RD(sc, BCE_MISC_COMMAND);
6505         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6506         REG_WR(sc, BCE_MISC_COMMAND, val);
6507 }
6508
6509
6510 /****************************************************************************/
6511 /* Unfreezes the controller after a freeze operation.  This may not always  */
6512 /* work and the controller will require a reset!                            */
6513 /*                                                                          */
6514 /* Returns:                                                                 */
6515 /*   Nothing.                                                               */
6516 /****************************************************************************/
6517 static void
6518 bce_unfreeze_controller(struct bce_softc *sc)
6519 {
6520         uint32_t val;
6521
6522         val = REG_RD(sc, BCE_MISC_COMMAND);
6523         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6524         REG_WR(sc, BCE_MISC_COMMAND, val);
6525 }
6526
6527
6528 /****************************************************************************/
6529 /* Prints out information about an mbuf.                                    */
6530 /*                                                                          */
6531 /* Returns:                                                                 */
6532 /*   Nothing.                                                               */
6533 /****************************************************************************/
6534 static void
6535 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6536 {
6537         struct ifnet *ifp = &sc->arpcom.ac_if;
6538         uint32_t val_hi, val_lo;
6539         struct mbuf *mp = m;
6540
6541         if (m == NULL) {
6542                 /* Index out of range. */
6543                 if_printf(ifp, "mbuf: null pointer\n");
6544                 return;
6545         }
6546
6547         while (mp) {
6548                 val_hi = BCE_ADDR_HI(mp);
6549                 val_lo = BCE_ADDR_LO(mp);
6550                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6551                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6552
6553                 if (mp->m_flags & M_EXT)
6554                         kprintf("M_EXT ");
6555                 if (mp->m_flags & M_PKTHDR)
6556                         kprintf("M_PKTHDR ");
6557                 if (mp->m_flags & M_EOR)
6558                         kprintf("M_EOR ");
6559 #ifdef M_RDONLY
6560                 if (mp->m_flags & M_RDONLY)
6561                         kprintf("M_RDONLY ");
6562 #endif
6563
6564                 val_hi = BCE_ADDR_HI(mp->m_data);
6565                 val_lo = BCE_ADDR_LO(mp->m_data);
6566                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6567
6568                 if (mp->m_flags & M_PKTHDR) {
6569                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6570                         if (mp->m_flags & M_BCAST)
6571                                 kprintf("M_BCAST ");
6572                         if (mp->m_flags & M_MCAST)
6573                                 kprintf("M_MCAST ");
6574                         if (mp->m_flags & M_FRAG)
6575                                 kprintf("M_FRAG ");
6576                         if (mp->m_flags & M_FIRSTFRAG)
6577                                 kprintf("M_FIRSTFRAG ");
6578                         if (mp->m_flags & M_LASTFRAG)
6579                                 kprintf("M_LASTFRAG ");
6580 #ifdef M_VLANTAG
6581                         if (mp->m_flags & M_VLANTAG)
6582                                 kprintf("M_VLANTAG ");
6583 #endif
6584 #ifdef M_PROMISC
6585                         if (mp->m_flags & M_PROMISC)
6586                                 kprintf("M_PROMISC ");
6587 #endif
6588                         kprintf(") csum_flags = ( ");
6589                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6590                                 kprintf("CSUM_IP ");
6591                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6592                                 kprintf("CSUM_TCP ");
6593                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6594                                 kprintf("CSUM_UDP ");
6595                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6596                                 kprintf("CSUM_IP_FRAGS ");
6597                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6598                                 kprintf("CSUM_FRAGMENT ");
6599 #ifdef CSUM_TSO
6600                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6601                                 kprintf("CSUM_TSO ");
6602 #endif
6603                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6604                                 kprintf("CSUM_IP_CHECKED ");
6605                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6606                                 kprintf("CSUM_IP_VALID ");
6607                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6608                                 kprintf("CSUM_DATA_VALID ");
6609                         kprintf(")\n");
6610                 }
6611
6612                 if (mp->m_flags & M_EXT) {
6613                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6614                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6615                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6616                                   "ext_size = %d\n",
6617                                   val_hi, val_lo, mp->m_ext.ext_size);
6618                 }
6619                 mp = mp->m_next;
6620         }
6621 }
6622
6623
6624 /****************************************************************************/
6625 /* Prints out the mbufs in the RX mbuf chain.                               */
6626 /*                                                                          */
6627 /* Returns:                                                                 */
6628 /*   Nothing.                                                               */
6629 /****************************************************************************/
6630 static void
6631 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6632 {
6633         struct ifnet *ifp = &sc->arpcom.ac_if;
6634         int i;
6635
6636         if_printf(ifp,
6637         "----------------------------"
6638         "  rx mbuf data  "
6639         "----------------------------\n");
6640
6641         for (i = 0; i < count; i++) {
6642                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6643                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6644                 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6645         }
6646
6647         if_printf(ifp,
6648         "----------------------------"
6649         "----------------"
6650         "----------------------------\n");
6651 }
6652
6653
6654 /****************************************************************************/
6655 /* Prints out a tx_bd structure.                                            */
6656 /*                                                                          */
6657 /* Returns:                                                                 */
6658 /*   Nothing.                                                               */
6659 /****************************************************************************/
6660 static void
6661 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6662 {
6663         struct ifnet *ifp = &sc->arpcom.ac_if;
6664
6665         if (idx > MAX_TX_BD(sc)) {
6666                 /* Index out of range. */
6667                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6668         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6669                 /* TX Chain page pointer. */
6670                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6671                           "chain page pointer\n",
6672                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6673         } else {
6674                 /* Normal tx_bd entry. */
6675                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6676                           "nbytes = 0x%08X, "
6677                           "vlan tag= 0x%04X, flags = 0x%04X (",
6678                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6679                           txbd->tx_bd_mss_nbytes,
6680                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6681
6682                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6683                         kprintf(" CONN_FAULT");
6684
6685                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6686                         kprintf(" TCP_UDP_CKSUM");
6687
6688                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6689                         kprintf(" IP_CKSUM");
6690
6691                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6692                         kprintf("  VLAN");
6693
6694                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6695                         kprintf(" COAL_NOW");
6696
6697                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6698                         kprintf(" DONT_GEN_CRC");
6699
6700                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6701                         kprintf(" START");
6702
6703                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6704                         kprintf(" END");
6705
6706                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6707                         kprintf(" LSO");
6708
6709                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6710                         kprintf(" OPTION_WORD");
6711
6712                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6713                         kprintf(" FLAGS");
6714
6715                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6716                         kprintf(" SNAP");
6717
6718                 kprintf(" )\n");
6719         }
6720 }
6721
6722
6723 /****************************************************************************/
6724 /* Prints out a rx_bd structure.                                            */
6725 /*                                                                          */
6726 /* Returns:                                                                 */
6727 /*   Nothing.                                                               */
6728 /****************************************************************************/
6729 static void
6730 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6731 {
6732         struct ifnet *ifp = &sc->arpcom.ac_if;
6733
6734         if (idx > MAX_RX_BD(sc)) {
6735                 /* Index out of range. */
6736                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6737         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6738                 /* TX Chain page pointer. */
6739                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6740                           "chain page pointer\n",
6741                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6742         } else {
6743                 /* Normal tx_bd entry. */
6744                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6745                           "nbytes = 0x%08X, flags = 0x%08X\n",
6746                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6747                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6748         }
6749 }
6750
6751
6752 /****************************************************************************/
6753 /* Prints out a l2_fhdr structure.                                          */
6754 /*                                                                          */
6755 /* Returns:                                                                 */
6756 /*   Nothing.                                                               */
6757 /****************************************************************************/
6758 static void
6759 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6760 {
6761         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6762                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6763                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6764                   idx, l2fhdr->l2_fhdr_status,
6765                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6766                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6767 }
6768
6769
6770 /****************************************************************************/
6771 /* Prints out the tx chain.                                                 */
6772 /*                                                                          */
6773 /* Returns:                                                                 */
6774 /*   Nothing.                                                               */
6775 /****************************************************************************/
6776 static void
6777 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6778 {
6779         struct ifnet *ifp = &sc->arpcom.ac_if;
6780         int i;
6781
6782         /* First some info about the tx_bd chain structure. */
6783         if_printf(ifp,
6784         "----------------------------"
6785         "  tx_bd  chain  "
6786         "----------------------------\n");
6787
6788         if_printf(ifp, "page size      = 0x%08X, "
6789                   "tx chain pages        = 0x%08X\n",
6790                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
6791
6792         if_printf(ifp, "tx_bd per page = 0x%08X, "
6793                   "usable tx_bd per page = 0x%08X\n",
6794                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6795                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6796
6797         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
6798
6799         if_printf(ifp,
6800         "----------------------------"
6801         "  tx_bd data    "
6802         "----------------------------\n");
6803
6804         /* Now print out the tx_bd's themselves. */
6805         for (i = 0; i < count; i++) {
6806                 struct tx_bd *txbd;
6807
6808                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6809                 bce_dump_txbd(sc, tx_prod, txbd);
6810                 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
6811         }
6812
6813         if_printf(ifp,
6814         "----------------------------"
6815         "----------------"
6816         "----------------------------\n");
6817 }
6818
6819
6820 /****************************************************************************/
6821 /* Prints out the rx chain.                                                 */
6822 /*                                                                          */
6823 /* Returns:                                                                 */
6824 /*   Nothing.                                                               */
6825 /****************************************************************************/
6826 static void
6827 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6828 {
6829         struct ifnet *ifp = &sc->arpcom.ac_if;
6830         int i;
6831
6832         /* First some info about the tx_bd chain structure. */
6833         if_printf(ifp,
6834         "----------------------------"
6835         "  rx_bd  chain  "
6836         "----------------------------\n");
6837
6838         if_printf(ifp, "page size      = 0x%08X, "
6839                   "rx chain pages        = 0x%08X\n",
6840                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
6841
6842         if_printf(ifp, "rx_bd per page = 0x%08X, "
6843                   "usable rx_bd per page = 0x%08X\n",
6844                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6845                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6846
6847         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
6848
6849         if_printf(ifp,
6850         "----------------------------"
6851         "   rx_bd data   "
6852         "----------------------------\n");
6853
6854         /* Now print out the rx_bd's themselves. */
6855         for (i = 0; i < count; i++) {
6856                 struct rx_bd *rxbd;
6857
6858                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6859                 bce_dump_rxbd(sc, rx_prod, rxbd);
6860                 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
6861         }
6862
6863         if_printf(ifp,
6864         "----------------------------"
6865         "----------------"
6866         "----------------------------\n");
6867 }
6868
6869
6870 /****************************************************************************/
6871 /* Prints out the status block from host memory.                            */
6872 /*                                                                          */
6873 /* Returns:                                                                 */
6874 /*   Nothing.                                                               */
6875 /****************************************************************************/
6876 static void
6877 bce_dump_status_block(struct bce_softc *sc)
6878 {
6879         struct status_block *sblk = sc->status_block;
6880         struct ifnet *ifp = &sc->arpcom.ac_if;
6881
6882         if_printf(ifp,
6883         "----------------------------"
6884         "  Status Block  "
6885         "----------------------------\n");
6886
6887         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6888
6889         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6890                   sblk->status_attn_bits_ack);
6891
6892         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6893             sblk->status_rx_quick_consumer_index0,
6894             (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
6895
6896         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6897             sblk->status_tx_quick_consumer_index0,
6898             (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
6899
6900         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6901
6902         /* Theses indices are not used for normal L2 drivers. */
6903         if (sblk->status_rx_quick_consumer_index1) {
6904                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6905                 sblk->status_rx_quick_consumer_index1,
6906                 (uint16_t)RX_CHAIN_IDX(sc,
6907                     sblk->status_rx_quick_consumer_index1));
6908         }
6909
6910         if (sblk->status_tx_quick_consumer_index1) {
6911                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6912                 sblk->status_tx_quick_consumer_index1,
6913                 (uint16_t)TX_CHAIN_IDX(sc,
6914                     sblk->status_tx_quick_consumer_index1));
6915         }
6916
6917         if (sblk->status_rx_quick_consumer_index2) {
6918                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6919                 sblk->status_rx_quick_consumer_index2,
6920                 (uint16_t)RX_CHAIN_IDX(sc,
6921                     sblk->status_rx_quick_consumer_index2));
6922         }
6923
6924         if (sblk->status_tx_quick_consumer_index2) {
6925                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6926                 sblk->status_tx_quick_consumer_index2,
6927                 (uint16_t)TX_CHAIN_IDX(sc,
6928                     sblk->status_tx_quick_consumer_index2));
6929         }
6930
6931         if (sblk->status_rx_quick_consumer_index3) {
6932                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6933                 sblk->status_rx_quick_consumer_index3,
6934                 (uint16_t)RX_CHAIN_IDX(sc,
6935                     sblk->status_rx_quick_consumer_index3));
6936         }
6937
6938         if (sblk->status_tx_quick_consumer_index3) {
6939                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6940                 sblk->status_tx_quick_consumer_index3,
6941                 (uint16_t)TX_CHAIN_IDX(sc,
6942                     sblk->status_tx_quick_consumer_index3));
6943         }
6944
6945         if (sblk->status_rx_quick_consumer_index4 ||
6946             sblk->status_rx_quick_consumer_index5) {
6947                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6948                           sblk->status_rx_quick_consumer_index4,
6949                           sblk->status_rx_quick_consumer_index5);
6950         }
6951
6952         if (sblk->status_rx_quick_consumer_index6 ||
6953             sblk->status_rx_quick_consumer_index7) {
6954                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6955                           sblk->status_rx_quick_consumer_index6,
6956                           sblk->status_rx_quick_consumer_index7);
6957         }
6958
6959         if (sblk->status_rx_quick_consumer_index8 ||
6960             sblk->status_rx_quick_consumer_index9) {
6961                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6962                           sblk->status_rx_quick_consumer_index8,
6963                           sblk->status_rx_quick_consumer_index9);
6964         }
6965
6966         if (sblk->status_rx_quick_consumer_index10 ||
6967             sblk->status_rx_quick_consumer_index11) {
6968                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6969                           sblk->status_rx_quick_consumer_index10,
6970                           sblk->status_rx_quick_consumer_index11);
6971         }
6972
6973         if (sblk->status_rx_quick_consumer_index12 ||
6974             sblk->status_rx_quick_consumer_index13) {
6975                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6976                           sblk->status_rx_quick_consumer_index12,
6977                           sblk->status_rx_quick_consumer_index13);
6978         }
6979
6980         if (sblk->status_rx_quick_consumer_index14 ||
6981             sblk->status_rx_quick_consumer_index15) {
6982                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6983                           sblk->status_rx_quick_consumer_index14,
6984                           sblk->status_rx_quick_consumer_index15);
6985         }
6986
6987         if (sblk->status_completion_producer_index ||
6988             sblk->status_cmd_consumer_index) {
6989                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6990                           sblk->status_completion_producer_index,
6991                           sblk->status_cmd_consumer_index);
6992         }
6993
6994         if_printf(ifp,
6995         "----------------------------"
6996         "----------------"
6997         "----------------------------\n");
6998 }
6999
7000
7001 /****************************************************************************/
7002 /* Prints out the statistics block.                                         */
7003 /*                                                                          */
7004 /* Returns:                                                                 */
7005 /*   Nothing.                                                               */
7006 /****************************************************************************/
7007 static void
7008 bce_dump_stats_block(struct bce_softc *sc)
7009 {
7010         struct statistics_block *sblk = sc->stats_block;
7011         struct ifnet *ifp = &sc->arpcom.ac_if;
7012
7013         if_printf(ifp,
7014         "---------------"
7015         " Stats Block  (All Stats Not Shown Are 0) "
7016         "---------------\n");
7017
7018         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7019                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7020                           sblk->stat_IfHCInOctets_hi,
7021                           sblk->stat_IfHCInOctets_lo);
7022         }
7023
7024         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7025                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7026                           sblk->stat_IfHCInBadOctets_hi,
7027                           sblk->stat_IfHCInBadOctets_lo);
7028         }
7029
7030         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7031                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7032                           sblk->stat_IfHCOutOctets_hi,
7033                           sblk->stat_IfHCOutOctets_lo);
7034         }
7035
7036         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7037                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7038                           sblk->stat_IfHCOutBadOctets_hi,
7039                           sblk->stat_IfHCOutBadOctets_lo);
7040         }
7041
7042         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7043                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7044                           sblk->stat_IfHCInUcastPkts_hi,
7045                           sblk->stat_IfHCInUcastPkts_lo);
7046         }
7047
7048         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7049             sblk->stat_IfHCInBroadcastPkts_lo) {
7050                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7051                           sblk->stat_IfHCInBroadcastPkts_hi,
7052                           sblk->stat_IfHCInBroadcastPkts_lo);
7053         }
7054
7055         if (sblk->stat_IfHCInMulticastPkts_hi ||
7056             sblk->stat_IfHCInMulticastPkts_lo) {
7057                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7058                           sblk->stat_IfHCInMulticastPkts_hi,
7059                           sblk->stat_IfHCInMulticastPkts_lo);
7060         }
7061
7062         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7063                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7064                           sblk->stat_IfHCOutUcastPkts_hi,
7065                           sblk->stat_IfHCOutUcastPkts_lo);
7066         }
7067
7068         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7069             sblk->stat_IfHCOutBroadcastPkts_lo) {
7070                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7071                           sblk->stat_IfHCOutBroadcastPkts_hi,
7072                           sblk->stat_IfHCOutBroadcastPkts_lo);
7073         }
7074
7075         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7076             sblk->stat_IfHCOutMulticastPkts_lo) {
7077                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7078                           sblk->stat_IfHCOutMulticastPkts_hi,
7079                           sblk->stat_IfHCOutMulticastPkts_lo);
7080         }
7081
7082         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7083                 if_printf(ifp, "         0x%08X : "
7084                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7085                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7086         }
7087
7088         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7089                 if_printf(ifp, "         0x%08X : "
7090                           "Dot3StatsCarrierSenseErrors\n",
7091                           sblk->stat_Dot3StatsCarrierSenseErrors);
7092         }
7093
7094         if (sblk->stat_Dot3StatsFCSErrors) {
7095                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7096                           sblk->stat_Dot3StatsFCSErrors);
7097         }
7098
7099         if (sblk->stat_Dot3StatsAlignmentErrors) {
7100                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7101                           sblk->stat_Dot3StatsAlignmentErrors);
7102         }
7103
7104         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7105                 if_printf(ifp, "         0x%08X : "
7106                           "Dot3StatsSingleCollisionFrames\n",
7107                           sblk->stat_Dot3StatsSingleCollisionFrames);
7108         }
7109
7110         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7111                 if_printf(ifp, "         0x%08X : "
7112                           "Dot3StatsMultipleCollisionFrames\n",
7113                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7114         }
7115
7116         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7117                 if_printf(ifp, "         0x%08X : "
7118                           "Dot3StatsDeferredTransmissions\n",
7119                           sblk->stat_Dot3StatsDeferredTransmissions);
7120         }
7121
7122         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7123                 if_printf(ifp, "         0x%08X : "
7124                           "Dot3StatsExcessiveCollisions\n",
7125                           sblk->stat_Dot3StatsExcessiveCollisions);
7126         }
7127
7128         if (sblk->stat_Dot3StatsLateCollisions) {
7129                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7130                           sblk->stat_Dot3StatsLateCollisions);
7131         }
7132
7133         if (sblk->stat_EtherStatsCollisions) {
7134                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7135                           sblk->stat_EtherStatsCollisions);
7136         }
7137
7138         if (sblk->stat_EtherStatsFragments)  {
7139                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7140                           sblk->stat_EtherStatsFragments);
7141         }
7142
7143         if (sblk->stat_EtherStatsJabbers) {
7144                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7145                           sblk->stat_EtherStatsJabbers);
7146         }
7147
7148         if (sblk->stat_EtherStatsUndersizePkts) {
7149                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7150                           sblk->stat_EtherStatsUndersizePkts);
7151         }
7152
7153         if (sblk->stat_EtherStatsOverrsizePkts) {
7154                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7155                           sblk->stat_EtherStatsOverrsizePkts);
7156         }
7157
7158         if (sblk->stat_EtherStatsPktsRx64Octets) {
7159                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7160                           sblk->stat_EtherStatsPktsRx64Octets);
7161         }
7162
7163         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7164                 if_printf(ifp, "         0x%08X : "
7165                           "EtherStatsPktsRx65Octetsto127Octets\n",
7166                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7167         }
7168
7169         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7170                 if_printf(ifp, "         0x%08X : "
7171                           "EtherStatsPktsRx128Octetsto255Octets\n",
7172                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7173         }
7174
7175         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7176                 if_printf(ifp, "         0x%08X : "
7177                           "EtherStatsPktsRx256Octetsto511Octets\n",
7178                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7179         }
7180
7181         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7182                 if_printf(ifp, "         0x%08X : "
7183                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7184                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7185         }
7186
7187         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7188                 if_printf(ifp, "         0x%08X : "
7189                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7190                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7191         }
7192
7193         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7194                 if_printf(ifp, "         0x%08X : "
7195                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7196                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7197         }
7198
7199         if (sblk->stat_EtherStatsPktsTx64Octets) {
7200                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7201                           sblk->stat_EtherStatsPktsTx64Octets);
7202         }
7203
7204         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7205                 if_printf(ifp, "         0x%08X : "
7206                           "EtherStatsPktsTx65Octetsto127Octets\n",
7207                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7208         }
7209
7210         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7211                 if_printf(ifp, "         0x%08X : "
7212                           "EtherStatsPktsTx128Octetsto255Octets\n",
7213                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7214         }
7215
7216         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7217                 if_printf(ifp, "         0x%08X : "
7218                           "EtherStatsPktsTx256Octetsto511Octets\n",
7219                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7220         }
7221
7222         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7223                 if_printf(ifp, "         0x%08X : "
7224                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7225                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7226         }
7227
7228         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7229                 if_printf(ifp, "         0x%08X : "
7230                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7231                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7232         }
7233
7234         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7235                 if_printf(ifp, "         0x%08X : "
7236                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7237                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7238         }
7239
7240         if (sblk->stat_XonPauseFramesReceived) {
7241                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7242                           sblk->stat_XonPauseFramesReceived);
7243         }
7244
7245         if (sblk->stat_XoffPauseFramesReceived) {
7246                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7247                           sblk->stat_XoffPauseFramesReceived);
7248         }
7249
7250         if (sblk->stat_OutXonSent) {
7251                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7252                           sblk->stat_OutXonSent);
7253         }
7254
7255         if (sblk->stat_OutXoffSent) {
7256                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7257                           sblk->stat_OutXoffSent);
7258         }
7259
7260         if (sblk->stat_FlowControlDone) {
7261                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7262                           sblk->stat_FlowControlDone);
7263         }
7264
7265         if (sblk->stat_MacControlFramesReceived) {
7266                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7267                           sblk->stat_MacControlFramesReceived);
7268         }
7269
7270         if (sblk->stat_XoffStateEntered) {
7271                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7272                           sblk->stat_XoffStateEntered);
7273         }
7274
7275         if (sblk->stat_IfInFramesL2FilterDiscards) {
7276                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7277         }
7278
7279         if (sblk->stat_IfInRuleCheckerDiscards) {
7280                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7281                           sblk->stat_IfInRuleCheckerDiscards);
7282         }
7283
7284         if (sblk->stat_IfInFTQDiscards) {
7285                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7286                           sblk->stat_IfInFTQDiscards);
7287         }
7288
7289         if (sblk->stat_IfInMBUFDiscards) {
7290                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7291                           sblk->stat_IfInMBUFDiscards);
7292         }
7293
7294         if (sblk->stat_IfInRuleCheckerP4Hit) {
7295                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7296                           sblk->stat_IfInRuleCheckerP4Hit);
7297         }
7298
7299         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7300                 if_printf(ifp, "         0x%08X : "
7301                           "CatchupInRuleCheckerDiscards\n",
7302                           sblk->stat_CatchupInRuleCheckerDiscards);
7303         }
7304
7305         if (sblk->stat_CatchupInFTQDiscards) {
7306                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7307                           sblk->stat_CatchupInFTQDiscards);
7308         }
7309
7310         if (sblk->stat_CatchupInMBUFDiscards) {
7311                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7312                           sblk->stat_CatchupInMBUFDiscards);
7313         }
7314
7315         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7316                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7317                           sblk->stat_CatchupInRuleCheckerP4Hit);
7318         }
7319
7320         if_printf(ifp,
7321         "----------------------------"
7322         "----------------"
7323         "----------------------------\n");
7324 }
7325
7326
7327 /****************************************************************************/
7328 /* Prints out a summary of the driver state.                                */
7329 /*                                                                          */
7330 /* Returns:                                                                 */
7331 /*   Nothing.                                                               */
7332 /****************************************************************************/
7333 static void
7334 bce_dump_driver_state(struct bce_softc *sc)
7335 {
7336         struct ifnet *ifp = &sc->arpcom.ac_if;
7337         uint32_t val_hi, val_lo;
7338
7339         if_printf(ifp,
7340         "-----------------------------"
7341         " Driver State "
7342         "-----------------------------\n");
7343
7344         val_hi = BCE_ADDR_HI(sc);
7345         val_lo = BCE_ADDR_LO(sc);
7346         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7347                   "virtual address\n", val_hi, val_lo);
7348
7349         val_hi = BCE_ADDR_HI(sc->status_block);
7350         val_lo = BCE_ADDR_LO(sc->status_block);
7351         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7352                   "virtual address\n", val_hi, val_lo);
7353
7354         val_hi = BCE_ADDR_HI(sc->stats_block);
7355         val_lo = BCE_ADDR_LO(sc->stats_block);
7356         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7357                   "virtual address\n", val_hi, val_lo);
7358
7359         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7360         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7361         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7362                   "virtual adddress\n", val_hi, val_lo);
7363
7364         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7365         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7366         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7367                   "virtual address\n", val_hi, val_lo);
7368
7369         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7370         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7371         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7372                   "virtual address\n", val_hi, val_lo);
7373
7374         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7375         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7376         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7377                   "virtual address\n", val_hi, val_lo);
7378
7379         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7380                   "h/w intrs\n", sc->interrupts_generated);
7381
7382         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7383                   "rx interrupts handled\n", sc->rx_interrupts);
7384
7385         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7386                   "tx interrupts handled\n", sc->tx_interrupts);
7387
7388         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7389                   "status block index\n", sc->last_status_idx);
7390
7391         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7392                   "tx producer index\n",
7393                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7394
7395         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7396                   "tx consumer index\n",
7397                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7398
7399         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7400                   "tx producer bseq index\n", sc->tx_prod_bseq);
7401
7402         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7403                   "rx producer index\n",
7404                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7405
7406         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7407                   "rx consumer index\n",
7408                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7409
7410         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7411                   "rx producer bseq index\n", sc->rx_prod_bseq);
7412
7413         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7414                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7415
7416         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7417                   "free rx_bd's\n", sc->free_rx_bd);
7418
7419         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7420                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7421
7422         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7423                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7424
7425         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7426                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7427
7428         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7429                   sc->used_tx_bd);
7430
7431         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7432                   sc->tx_hi_watermark, sc->max_tx_bd);
7433
7434         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7435                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7436
7437         if_printf(ifp,
7438         "----------------------------"
7439         "----------------"
7440         "----------------------------\n");
7441 }
7442
7443
7444 /****************************************************************************/
7445 /* Prints out the hardware state through a summary of important registers,  */
7446 /* followed by a complete register dump.                                    */
7447 /*                                                                          */
7448 /* Returns:                                                                 */
7449 /*   Nothing.                                                               */
7450 /****************************************************************************/
7451 static void
7452 bce_dump_hw_state(struct bce_softc *sc)
7453 {
7454         struct ifnet *ifp = &sc->arpcom.ac_if;
7455         uint32_t val1;
7456         int i;
7457
7458         if_printf(ifp,
7459         "----------------------------"
7460         " Hardware State "
7461         "----------------------------\n");
7462
7463         if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7464
7465         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7466         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7467                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7468
7469         val1 = REG_RD(sc, BCE_DMA_STATUS);
7470         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7471
7472         val1 = REG_RD(sc, BCE_CTX_STATUS);
7473         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7474
7475         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7476         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7477                   val1, BCE_EMAC_STATUS);
7478
7479         val1 = REG_RD(sc, BCE_RPM_STATUS);
7480         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7481
7482         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7483         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7484                   val1, BCE_TBDR_STATUS);
7485
7486         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7487         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7488                   val1, BCE_TDMA_STATUS);
7489
7490         val1 = REG_RD(sc, BCE_HC_STATUS);
7491         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7492
7493         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7494         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7495                   val1, BCE_TXP_CPU_STATE);
7496
7497         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7498         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7499                   val1, BCE_TPAT_CPU_STATE);
7500
7501         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7502         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7503                   val1, BCE_RXP_CPU_STATE);
7504
7505         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7506         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7507                   val1, BCE_COM_CPU_STATE);
7508
7509         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7510         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7511                   val1, BCE_MCP_CPU_STATE);
7512
7513         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7514         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7515                   val1, BCE_CP_CPU_STATE);
7516
7517         if_printf(ifp,
7518         "----------------------------"
7519         "----------------"
7520         "----------------------------\n");
7521
7522         if_printf(ifp,
7523         "----------------------------"
7524         " Register  Dump "
7525         "----------------------------\n");
7526
7527         for (i = 0x400; i < 0x8000; i += 0x10) {
7528                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7529                           REG_RD(sc, i),
7530                           REG_RD(sc, i + 0x4),
7531                           REG_RD(sc, i + 0x8),
7532                           REG_RD(sc, i + 0xc));
7533         }
7534
7535         if_printf(ifp,
7536         "----------------------------"
7537         "----------------"
7538         "----------------------------\n");
7539 }
7540
7541
7542 /****************************************************************************/
7543 /* Prints out the TXP state.                                                */
7544 /*                                                                          */
7545 /* Returns:                                                                 */
7546 /*   Nothing.                                                               */
7547 /****************************************************************************/
7548 static void
7549 bce_dump_txp_state(struct bce_softc *sc)
7550 {
7551         struct ifnet *ifp = &sc->arpcom.ac_if;
7552         uint32_t val1;
7553         int i;
7554
7555         if_printf(ifp,
7556         "----------------------------"
7557         "   TXP  State   "
7558         "----------------------------\n");
7559
7560         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7561         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7562                   val1, BCE_TXP_CPU_MODE);
7563
7564         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7565         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7566                   val1, BCE_TXP_CPU_STATE);
7567
7568         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7569         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7570                   val1, BCE_TXP_CPU_EVENT_MASK);
7571
7572         if_printf(ifp,
7573         "----------------------------"
7574         " Register  Dump "
7575         "----------------------------\n");
7576
7577         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7578                 /* Skip the big blank spaces */
7579                 if (i < 0x454000 && i > 0x5ffff) {
7580                         if_printf(ifp, "0x%04X: "
7581                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7582                                   REG_RD_IND(sc, i),
7583                                   REG_RD_IND(sc, i + 0x4),
7584                                   REG_RD_IND(sc, i + 0x8),
7585                                   REG_RD_IND(sc, i + 0xc));
7586                 }
7587         }
7588
7589         if_printf(ifp,
7590         "----------------------------"
7591         "----------------"
7592         "----------------------------\n");
7593 }
7594
7595
7596 /****************************************************************************/
7597 /* Prints out the RXP state.                                                */
7598 /*                                                                          */
7599 /* Returns:                                                                 */
7600 /*   Nothing.                                                               */
7601 /****************************************************************************/
7602 static void
7603 bce_dump_rxp_state(struct bce_softc *sc)
7604 {
7605         struct ifnet *ifp = &sc->arpcom.ac_if;
7606         uint32_t val1;
7607         int i;
7608
7609         if_printf(ifp,
7610         "----------------------------"
7611         "   RXP  State   "
7612         "----------------------------\n");
7613
7614         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7615         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7616                   val1, BCE_RXP_CPU_MODE);
7617
7618         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7619         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7620                   val1, BCE_RXP_CPU_STATE);
7621
7622         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7623         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7624                   val1, BCE_RXP_CPU_EVENT_MASK);
7625
7626         if_printf(ifp,
7627         "----------------------------"
7628         " Register  Dump "
7629         "----------------------------\n");
7630
7631         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7632                 /* Skip the big blank sapces */
7633                 if (i < 0xc5400 && i > 0xdffff) {
7634                         if_printf(ifp, "0x%04X: "
7635                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7636                                   REG_RD_IND(sc, i),
7637                                   REG_RD_IND(sc, i + 0x4),
7638                                   REG_RD_IND(sc, i + 0x8),
7639                                   REG_RD_IND(sc, i + 0xc));
7640                 }
7641         }
7642
7643         if_printf(ifp,
7644         "----------------------------"
7645         "----------------"
7646         "----------------------------\n");
7647 }
7648
7649
7650 /****************************************************************************/
7651 /* Prints out the TPAT state.                                               */
7652 /*                                                                          */
7653 /* Returns:                                                                 */
7654 /*   Nothing.                                                               */
7655 /****************************************************************************/
7656 static void
7657 bce_dump_tpat_state(struct bce_softc *sc)
7658 {
7659         struct ifnet *ifp = &sc->arpcom.ac_if;
7660         uint32_t val1;
7661         int i;
7662
7663         if_printf(ifp,
7664         "----------------------------"
7665         "   TPAT State   "
7666         "----------------------------\n");
7667
7668         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7669         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7670                   val1, BCE_TPAT_CPU_MODE);
7671
7672         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7673         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7674                   val1, BCE_TPAT_CPU_STATE);
7675
7676         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7677         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7678                   val1, BCE_TPAT_CPU_EVENT_MASK);
7679
7680         if_printf(ifp,
7681         "----------------------------"
7682         " Register  Dump "
7683         "----------------------------\n");
7684
7685         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7686                 /* Skip the big blank spaces */
7687                 if (i < 0x854000 && i > 0x9ffff) {
7688                         if_printf(ifp, "0x%04X: "
7689                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7690                                   REG_RD_IND(sc, i),
7691                                   REG_RD_IND(sc, i + 0x4),
7692                                   REG_RD_IND(sc, i + 0x8),
7693                                   REG_RD_IND(sc, i + 0xc));
7694                 }
7695         }
7696
7697         if_printf(ifp,
7698         "----------------------------"
7699         "----------------"
7700         "----------------------------\n");
7701 }
7702
7703
7704 /****************************************************************************/
7705 /* Prints out the driver state and then enters the debugger.                */
7706 /*                                                                          */
7707 /* Returns:                                                                 */
7708 /*   Nothing.                                                               */
7709 /****************************************************************************/
7710 static void
7711 bce_breakpoint(struct bce_softc *sc)
7712 {
7713 #if 0
7714         bce_freeze_controller(sc);
7715 #endif
7716
7717         bce_dump_driver_state(sc);
7718         bce_dump_status_block(sc);
7719         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7720         bce_dump_hw_state(sc);
7721         bce_dump_txp_state(sc);
7722
7723 #if 0
7724         bce_unfreeze_controller(sc);
7725 #endif
7726
7727         /* Call the debugger. */
7728         breakpoint();
7729 }
7730
7731 #endif  /* BCE_DEBUG */
7732
7733 static int
7734 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7735 {
7736         struct bce_softc *sc = arg1;
7737
7738         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7739                         &sc->bce_tx_quick_cons_trip_int,
7740                         BCE_COALMASK_TX_BDS_INT);
7741 }
7742
7743 static int
7744 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7745 {
7746         struct bce_softc *sc = arg1;
7747
7748         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7749                         &sc->bce_tx_quick_cons_trip,
7750                         BCE_COALMASK_TX_BDS);
7751 }
7752
7753 static int
7754 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7755 {
7756         struct bce_softc *sc = arg1;
7757
7758         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7759                         &sc->bce_tx_ticks_int,
7760                         BCE_COALMASK_TX_TICKS_INT);
7761 }
7762
7763 static int
7764 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7765 {
7766         struct bce_softc *sc = arg1;
7767
7768         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7769                         &sc->bce_tx_ticks,
7770                         BCE_COALMASK_TX_TICKS);
7771 }
7772
7773 static int
7774 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7775 {
7776         struct bce_softc *sc = arg1;
7777
7778         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7779                         &sc->bce_rx_quick_cons_trip_int,
7780                         BCE_COALMASK_RX_BDS_INT);
7781 }
7782
7783 static int
7784 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7785 {
7786         struct bce_softc *sc = arg1;
7787
7788         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7789                         &sc->bce_rx_quick_cons_trip,
7790                         BCE_COALMASK_RX_BDS);
7791 }
7792
7793 static int
7794 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7795 {
7796         struct bce_softc *sc = arg1;
7797
7798         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7799                         &sc->bce_rx_ticks_int,
7800                         BCE_COALMASK_RX_TICKS_INT);
7801 }
7802
7803 static int
7804 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7805 {
7806         struct bce_softc *sc = arg1;
7807
7808         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7809                         &sc->bce_rx_ticks,
7810                         BCE_COALMASK_RX_TICKS);
7811 }
7812
7813 static int
7814 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7815                        uint32_t coalchg_mask)
7816 {
7817         struct bce_softc *sc = arg1;
7818         struct ifnet *ifp = &sc->arpcom.ac_if;
7819         int error = 0, v;
7820
7821         lwkt_serialize_enter(ifp->if_serializer);
7822
7823         v = *coal;
7824         error = sysctl_handle_int(oidp, &v, 0, req);
7825         if (!error && req->newptr != NULL) {
7826                 if (v < 0) {
7827                         error = EINVAL;
7828                 } else {
7829                         *coal = v;
7830                         sc->bce_coalchg_mask |= coalchg_mask;
7831                 }
7832         }
7833
7834         lwkt_serialize_exit(ifp->if_serializer);
7835         return error;
7836 }
7837
7838 static void
7839 bce_coal_change(struct bce_softc *sc)
7840 {
7841         struct ifnet *ifp = &sc->arpcom.ac_if;
7842
7843         ASSERT_SERIALIZED(ifp->if_serializer);
7844
7845         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7846                 sc->bce_coalchg_mask = 0;
7847                 return;
7848         }
7849
7850         if (sc->bce_coalchg_mask &
7851             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7852                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7853                        (sc->bce_tx_quick_cons_trip_int << 16) |
7854                        sc->bce_tx_quick_cons_trip);
7855                 if (bootverbose) {
7856                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7857                                   sc->bce_tx_quick_cons_trip,
7858                                   sc->bce_tx_quick_cons_trip_int);
7859                 }
7860         }
7861
7862         if (sc->bce_coalchg_mask &
7863             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7864                 REG_WR(sc, BCE_HC_TX_TICKS,
7865                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7866                 if (bootverbose) {
7867                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7868                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7869                 }
7870         }
7871
7872         if (sc->bce_coalchg_mask &
7873             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7874                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7875                        (sc->bce_rx_quick_cons_trip_int << 16) |
7876                        sc->bce_rx_quick_cons_trip);
7877                 if (bootverbose) {
7878                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7879                                   sc->bce_rx_quick_cons_trip,
7880                                   sc->bce_rx_quick_cons_trip_int);
7881                 }
7882         }
7883
7884         if (sc->bce_coalchg_mask &
7885             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7886                 REG_WR(sc, BCE_HC_RX_TICKS,
7887                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7888                 if (bootverbose) {
7889                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7890                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7891                 }
7892         }
7893
7894         sc->bce_coalchg_mask = 0;
7895 }
7896
7897 static int
7898 bce_tso_setup(struct bce_softc *sc, struct mbuf **mp,
7899     uint16_t *flags0, uint16_t *mss0)
7900 {
7901         struct mbuf *m;
7902         uint16_t flags;
7903         int thoff, iphlen, hoff;
7904
7905         m = *mp;
7906         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
7907
7908         hoff = m->m_pkthdr.csum_lhlen;
7909         iphlen = m->m_pkthdr.csum_iphlen;
7910         thoff = m->m_pkthdr.csum_thlen;
7911
7912         KASSERT(hoff >= sizeof(struct ether_header),
7913             ("invalid ether header len %d", hoff));
7914         KASSERT(iphlen >= sizeof(struct ip),
7915             ("invalid ip header len %d", iphlen));
7916         KASSERT(thoff >= sizeof(struct tcphdr),
7917             ("invalid tcp header len %d", thoff));
7918
7919         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
7920                 m = m_pullup(m, hoff + iphlen + thoff);
7921                 if (m == NULL) {
7922                         *mp = NULL;
7923                         return ENOBUFS;
7924                 }
7925                 *mp = m;
7926         }
7927
7928         /* Set the LSO flag in the TX BD */
7929         flags = TX_BD_FLAGS_SW_LSO;
7930
7931         /* Set the length of IP + TCP options (in 32 bit words) */
7932         flags |= (((iphlen + thoff -
7933             sizeof(struct ip) - sizeof(struct tcphdr)) >> 2) << 8);
7934
7935         *mss0 = htole16(m->m_pkthdr.tso_segsz);
7936         *flags0 = flags;
7937
7938         return 0;
7939 }