1 @c Copyright (C) 2009-2014 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
20 * AArch64 Options:: Options
21 * AArch64 Extensions:: Extensions
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @option{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @option{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @option{-mabi=} command line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
53 @cindex @option{-mcpu=} command line option, AArch64
54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
55 This option specifies the target processor. The assembler will issue an error
56 message if an attempt is made to assemble an instruction which will not execute
57 on the target processor. The following processor names are recognized:
65 The special name @code{all} may be used to allow the assembler to accept
66 instructions valid for any supported processor, including all optional
69 In addition to the basic instruction set, the assembler can be told to
70 accept, or restrict, various extension mnemonics that extend the
71 processor. @xref{AArch64 Extensions}.
73 If some implementations of a particular processor can have an
74 extension, then then those extensions are automatically enabled.
75 Consequently, you will not normally have to specify any additional
78 @cindex @option{-march=} command line option, AArch64
79 @item -march=@var{architecture}[+@var{extension}@dots{}]
80 This option specifies the target architecture. The assembler will
81 issue an error message if an attempt is made to assemble an
82 instruction which will not execute on the target architecture. The
83 only value for @var{architecture} is @code{armv8-a}.
85 If both @option{-mcpu} and @option{-march} are specified, the
86 assembler will use the setting for @option{-mcpu}. If neither are
87 specified, the assembler will default to @option{-mcpu=all}.
89 The architecture option can be extended with the same instruction set
90 extension options as the @option{-mcpu} option. Unlike
91 @option{-mcpu}, extensions are not always enabled by default,
92 @xref{AArch64 Extensions}.
94 @cindex @code{-mverbose-error} command line option, AArch64
96 This option enables verbose error messages for AArch64 gas. This option
97 is enabled by default.
99 @cindex @code{-mno-verbose-error} command line option, AArch64
100 @item -mno-verbose-error
101 This option disables verbose error messages in AArch64 gas.
106 @node AArch64 Extensions
107 @section Architecture Extensions
109 The table below lists the permitted architecture extensions that are
110 supported by the assembler and the conditions under which they are
111 automatically enabled.
113 Multiple extensions may be specified, separated by a @code{+}.
114 Extension mnemonics may also be removed from those the assembler
115 accepts. This is done by prepending @code{no} to the option that adds
116 the extension. Extensions that are removed must be listed after all
117 extensions that have been added.
119 Enabling an extension that requires other extensions will
120 automatically cause those extensions to be enabled. Similarly,
121 disabling an extension that is required by other extensions will
122 automatically cause those extensions to be disabled.
124 @multitable @columnfractions .12 .17 .17 .54
125 @headitem Extension @tab Minimum Architecture @tab Enabled by default
127 @item @code{crc} @tab ARMv8-A @tab No
128 @tab Enable CRC instructions.
129 @item @code{crypto} @tab ARMv8-A @tab No
130 @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
131 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
132 @tab Enable floating-point extensions.
133 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
134 @tab Enable Advanced SIMD extensions. This implies @code{fp}.
140 * AArch64-Chars:: Special Characters
141 * AArch64-Regs:: Register Names
142 * AArch64-Relocations:: Relocations
146 @subsection Special Characters
148 @cindex line comment character, AArch64
149 @cindex AArch64 line comment character
150 The presence of a @samp{//} on a line indicates the start of a comment
151 that extends to the end of the current line. If a @samp{#} appears as
152 the first character of a line, the whole line is treated as a comment.
154 @cindex line separator, AArch64
155 @cindex statement separator, AArch64
156 @cindex AArch64 line separator
157 The @samp{;} character can be used instead of a newline to separate
160 @cindex immediate character, AArch64
161 @cindex AArch64 immediate character
162 The @samp{#} can be optionally used to indicate immediate operands.
165 @subsection Register Names
167 @cindex AArch64 register names
168 @cindex register names, AArch64
169 Please refer to the section @samp{4.4 Register Names} of
170 @samp{ARMv8 Instruction Set Overview}, which is available at
171 @uref{http://infocenter.arm.com}.
173 @node AArch64-Relocations
174 @subsection Relocations
176 @cindex relocations, AArch64
177 @cindex AArch64 relocations
178 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
179 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
180 by prefixing the label with @samp{#:abs_g2:} etc.
181 For example to load the 48-bit absolute address of @var{foo} into x0:
184 movz x0, #:abs_g2:foo // bits 32-47, overflow check
185 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
186 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
189 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
190 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
191 instructions can be generated by prefixing the label with
192 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
194 For example to use 33-bit (+/-4GB) pc-relative addressing to
195 load the address of @var{foo} into x0:
198 adrp x0, :pg_hi21:foo
199 add x0, x0, #:lo12:foo
202 Or to load the value of @var{foo} into x0:
205 adrp x0, :pg_hi21:foo
206 ldr x0, [x0, #:lo12:foo]
209 Note that @samp{:pg_hi21:} is optional.
218 adrp x0, :pg_hi21:foo
221 @node AArch64 Floating Point
222 @section Floating Point
224 @cindex floating point, AArch64 (@sc{ieee})
225 @cindex AArch64 floating point (@sc{ieee})
226 The AArch64 architecture uses @sc{ieee} floating-point numbers.
228 @node AArch64 Directives
229 @section AArch64 Machine Directives
231 @cindex machine directives, AArch64
232 @cindex AArch64 machine directives
235 @c AAAAAAAAAAAAAAAAAAAAAAAAA
236 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
238 @cindex @code{.bss} directive, AArch64
240 This directive switches to the @code{.bss} section.
242 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
243 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
244 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
245 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
246 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
247 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
248 @c IIIIIIIIIIIIIIIIIIIIIIIIII
249 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
250 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
251 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
253 @cindex @code{.ltorg} directive, AArch64
255 This directive causes the current contents of the literal pool to be
256 dumped into the current section (which is assumed to be the .text
257 section) at the current location (aligned to a word boundary).
258 GAS maintains a separate literal pool for each section and each
259 sub-section. The @code{.ltorg} directive will only affect the literal
260 pool of the current section and sub-section. At the end of assembly
261 all remaining, un-empty literal pools will automatically be dumped.
263 Note - older versions of GAS would dump the current literal
264 pool any time a section change occurred. This is no longer done, since
265 it prevents accurate control of the placement of literal pools.
267 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
269 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
270 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
272 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
274 @cindex @code{.pool} directive, AArch64
276 This is a synonym for .ltorg.
278 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
279 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
281 @cindex @code{.req} directive, AArch64
282 @item @var{name} .req @var{register name}
283 This creates an alias for @var{register name} called @var{name}. For
290 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
292 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
294 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
296 @cindex @code{.unreq} directive, AArch64
297 @item .unreq @var{alias-name}
298 This undefines a register alias which was previously defined using the
299 @code{req} directive. For example:
306 An error occurs if the name is undefined. Note - this pseudo op can
307 be used to delete builtin in register name aliases (eg 'w0'). This
308 should only be done if it is really necessary.
310 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
312 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
313 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
314 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
315 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
319 @node AArch64 Opcodes
322 @cindex AArch64 opcodes
323 @cindex opcodes for AArch64
324 GAS implements all the standard AArch64 opcodes. It also
325 implements several pseudo opcodes, including several synthetic load
330 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
333 ldr <register> , =<expression>
336 The constant expression will be placed into the nearest literal pool (if it not
337 already there) and a PC-relative LDR instruction will be generated.
341 For more information on the AArch64 instruction set and assembly language
342 notation, see @samp{ARMv8 Instruction Set Overview} available at
343 @uref{http://infocenter.arm.com}.
346 @node AArch64 Mapping Symbols
347 @section Mapping Symbols
349 The AArch64 ELF specification requires that special symbols be inserted
350 into object files to mark certain features:
356 At the start of a region of code containing AArch64 instructions.
360 At the start of a region of data.