sys/dev/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/delay.h>
  31 #include <linux/hdmi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  40 {
  41         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  42 }
  43
  44 static void
  45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  46 {
  47         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         uint32_t enabled_bits;
  50
  51         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  52
  53         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  54              "HDMI port enabled, expecting disabled\n");
  55 }
  56
  57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  58 {
  59         struct intel_digital_port *intel_dig_port =
  60                 container_of(encoder, struct intel_digital_port, base.base);
  61         return &intel_dig_port->hdmi;
  62 }
  63
  64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  65 {
  66         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  67 }
  68
  69 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  70 {
  71         switch (type) {
  72         case HDMI_INFOFRAME_TYPE_AVI:
  73                 return VIDEO_DIP_SELECT_AVI;
  74         case HDMI_INFOFRAME_TYPE_SPD:
  75                 return VIDEO_DIP_SELECT_SPD;
  76         case HDMI_INFOFRAME_TYPE_VENDOR:
  77                 return VIDEO_DIP_SELECT_VENDOR;
  78         default:
  79                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  80                 return 0;
  81         }
  82 }
  83
  84 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  85 {
  86         switch (type) {
  87         case HDMI_INFOFRAME_TYPE_AVI:
  88                 return VIDEO_DIP_ENABLE_AVI;
  89         case HDMI_INFOFRAME_TYPE_SPD:
  90                 return VIDEO_DIP_ENABLE_SPD;
  91         case HDMI_INFOFRAME_TYPE_VENDOR:
  92                 return VIDEO_DIP_ENABLE_VENDOR;
  93         default:
  94                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  95                 return 0;
  96         }
  97 }
  98
  99 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 100 {
 101         switch (type) {
 102         case HDMI_INFOFRAME_TYPE_AVI:
 103                 return VIDEO_DIP_ENABLE_AVI_HSW;
 104         case HDMI_INFOFRAME_TYPE_SPD:
 105                 return VIDEO_DIP_ENABLE_SPD_HSW;
 106         case HDMI_INFOFRAME_TYPE_VENDOR:
 107                 return VIDEO_DIP_ENABLE_VS_HSW;
 108         default:
 109                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 110                 return 0;
 111         }
 112 }
 113
 114 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 115                                   enum transcoder cpu_transcoder,
 116                                   struct drm_i915_private *dev_priv)
 117 {
 118         switch (type) {
 119         case HDMI_INFOFRAME_TYPE_AVI:
 120                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 121         case HDMI_INFOFRAME_TYPE_SPD:
 122                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_VENDOR:
 124                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 127                 return 0;
 128         }
 129 }
 130
 131 static void g4x_write_infoframe(struct drm_encoder *encoder,
 132                                 enum hdmi_infoframe_type type,
 133                                 const void *frame, ssize_t len)
 134 {
 135         const uint32_t *data = frame;
 136         struct drm_device *dev = encoder->dev;
 137         struct drm_i915_private *dev_priv = dev->dev_private;
 138         u32 val = I915_READ(VIDEO_DIP_CTL);
 139         int i;
 140
 141         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 142
 143         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 144         val |= g4x_infoframe_index(type);
 145
 146         val &= ~g4x_infoframe_enable(type);
 147
 148         I915_WRITE(VIDEO_DIP_CTL, val);
 149
 150         mmiowb();
 151         for (i = 0; i < len; i += 4) {
 152                 I915_WRITE(VIDEO_DIP_DATA, *data);
 153                 data++;
 154         }
 155         /* Write every possible data byte to force correct ECC calculation. */
 156         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 157                 I915_WRITE(VIDEO_DIP_DATA, 0);
 158         mmiowb();
 159
 160         val |= g4x_infoframe_enable(type);
 161         val &= ~VIDEO_DIP_FREQ_MASK;
 162         val |= VIDEO_DIP_FREQ_VSYNC;
 163
 164         I915_WRITE(VIDEO_DIP_CTL, val);
 165         POSTING_READ(VIDEO_DIP_CTL);
 166 }
 167
 168 static void ibx_write_infoframe(struct drm_encoder *encoder,
 169                                 enum hdmi_infoframe_type type,
 170                                 const void *frame, ssize_t len)
 171 {
 172         const uint32_t *data = frame;
 173         struct drm_device *dev = encoder->dev;
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 176         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 177         u32 val = I915_READ(reg);
 178
 179         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 180
 181         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 182         val |= g4x_infoframe_index(type);
 183
 184         val &= ~g4x_infoframe_enable(type);
 185
 186         I915_WRITE(reg, val);
 187
 188         mmiowb();
 189         for (i = 0; i < len; i += 4) {
 190                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 191                 data++;
 192         }
 193         /* Write every possible data byte to force correct ECC calculation. */
 194         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 196         mmiowb();
 197
 198         val |= g4x_infoframe_enable(type);
 199         val &= ~VIDEO_DIP_FREQ_MASK;
 200         val |= VIDEO_DIP_FREQ_VSYNC;
 201
 202         I915_WRITE(reg, val);
 203         POSTING_READ(reg);
 204 }
 205
 206 static void cpt_write_infoframe(struct drm_encoder *encoder,
 207                                 enum hdmi_infoframe_type type,
 208                                 const void *frame, ssize_t len)
 209 {
 210         const uint32_t *data = frame;
 211         struct drm_device *dev = encoder->dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 214         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 215         u32 val = I915_READ(reg);
 216
 217         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 218
 219         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 220         val |= g4x_infoframe_index(type);
 221
 222         /* The DIP control register spec says that we need to update the AVI
 223          * infoframe without clearing its enable bit */
 224         if (type != HDMI_INFOFRAME_TYPE_AVI)
 225                 val &= ~g4x_infoframe_enable(type);
 226
 227         I915_WRITE(reg, val);
 228
 229         mmiowb();
 230         for (i = 0; i < len; i += 4) {
 231                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 232                 data++;
 233         }
 234         /* Write every possible data byte to force correct ECC calculation. */
 235         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 236                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 237         mmiowb();
 238
 239         val |= g4x_infoframe_enable(type);
 240         val &= ~VIDEO_DIP_FREQ_MASK;
 241         val |= VIDEO_DIP_FREQ_VSYNC;
 242
 243         I915_WRITE(reg, val);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void vlv_write_infoframe(struct drm_encoder *encoder,
 248                                 enum hdmi_infoframe_type type,
 249                                 const void *frame, ssize_t len)
 250 {
 251         const uint32_t *data = frame;
 252         struct drm_device *dev = encoder->dev;
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 255         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 256         u32 val = I915_READ(reg);
 257
 258         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 259
 260         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 261         val |= g4x_infoframe_index(type);
 262
 263         val &= ~g4x_infoframe_enable(type);
 264
 265         I915_WRITE(reg, val);
 266
 267         mmiowb();
 268         for (i = 0; i < len; i += 4) {
 269                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 270                 data++;
 271         }
 272         /* Write every possible data byte to force correct ECC calculation. */
 273         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 274                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 275         mmiowb();
 276
 277         val |= g4x_infoframe_enable(type);
 278         val &= ~VIDEO_DIP_FREQ_MASK;
 279         val |= VIDEO_DIP_FREQ_VSYNC;
 280
 281         I915_WRITE(reg, val);
 282         POSTING_READ(reg);
 283 }
 284
 285 static void hsw_write_infoframe(struct drm_encoder *encoder,
 286                                 enum hdmi_infoframe_type type,
 287                                 const void *frame, ssize_t len)
 288 {
 289         const uint32_t *data = frame;
 290         struct drm_device *dev = encoder->dev;
 291         struct drm_i915_private *dev_priv = dev->dev_private;
 292         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 293         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 294         u32 data_reg;
 295         int i;
 296         u32 val = I915_READ(ctl_reg);
 297
 298         data_reg = hsw_infoframe_data_reg(type,
 299                                           intel_crtc->config.cpu_transcoder,
 300                                           dev_priv);
 301         if (data_reg == 0)
 302                 return;
 303
 304         val &= ~hsw_infoframe_enable(type);
 305         I915_WRITE(ctl_reg, val);
 306
 307         mmiowb();
 308         for (i = 0; i < len; i += 4) {
 309                 I915_WRITE(data_reg + i, *data);
 310                 data++;
 311         }
 312         /* Write every possible data byte to force correct ECC calculation. */
 313         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 314                 I915_WRITE(data_reg + i, 0);
 315         mmiowb();
 316
 317         val |= hsw_infoframe_enable(type);
 318         I915_WRITE(ctl_reg, val);
 319         POSTING_READ(ctl_reg);
 320 }
 321
 322 /*
 323  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 324  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 325  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 326  * used for both technologies.
 327  *
 328  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 329  * DW1:       DB3       | DB2 | DB1 | DB0
 330  * DW2:       DB7       | DB6 | DB5 | DB4
 331  * DW3: ...
 332  *
 333  * (HB is Header Byte, DB is Data Byte)
 334  *
 335  * The hdmi pack() functions don't know about that hardware specific hole so we
 336  * trick them by giving an offset into the buffer and moving back the header
 337  * bytes by one.
 338  */
 339 static void intel_write_infoframe(struct drm_encoder *encoder,
 340                                   union hdmi_infoframe *frame)
 341 {
 342         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 343         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 344         ssize_t len;
 345
 346         /* see comment above for the reason for this offset */
 347         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 348         if (len < 0)
 349                 return;
 350
 351         /* Insert the 'hole' (see big comment above) at position 3 */
 352         buffer[0] = buffer[1];
 353         buffer[1] = buffer[2];
 354         buffer[2] = buffer[3];
 355         buffer[3] = 0;
 356         len++;
 357
 358         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 359 }
 360
 361 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 362                                          struct drm_display_mode *adjusted_mode)
 363 {
 364         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 365         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 366         union hdmi_infoframe frame;
 367         int ret;
 368
 369         /* Set user selected PAR to incoming mode's member */
 370         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 371
 372         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 373                                                        adjusted_mode);
 374         if (ret < 0) {
 375                 DRM_ERROR("couldn't fill AVI infoframe\n");
 376                 return;
 377         }
 378
 379         if (intel_hdmi->rgb_quant_range_selectable) {
 380                 if (intel_crtc->config.limited_color_range)
 381                         frame.avi.quantization_range =
 382                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 383                 else
 384                         frame.avi.quantization_range =
 385                                 HDMI_QUANTIZATION_RANGE_FULL;
 386         }
 387
 388         intel_write_infoframe(encoder, &frame);
 389 }
 390
 391 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 392 {
 393         union hdmi_infoframe frame;
 394         int ret;
 395
 396         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 397         if (ret < 0) {
 398                 DRM_ERROR("couldn't fill SPD infoframe\n");
 399                 return;
 400         }
 401
 402         frame.spd.sdi = HDMI_SPD_SDI_PC;
 403
 404         intel_write_infoframe(encoder, &frame);
 405 }
 406
 407 static void
 408 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 409                               struct drm_display_mode *adjusted_mode)
 410 {
 411         union hdmi_infoframe frame;
 412         int ret;
 413
 414         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 415                                                           adjusted_mode);
 416         if (ret < 0)
 417                 return;
 418
 419         intel_write_infoframe(encoder, &frame);
 420 }
 421
 422 static void g4x_set_infoframes(struct drm_encoder *encoder,
 423                                bool enable,
 424                                struct drm_display_mode *adjusted_mode)
 425 {
 426         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 427         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 428         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 429         u32 reg = VIDEO_DIP_CTL;
 430         u32 val = I915_READ(reg);
 431         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 432
 433         assert_hdmi_port_disabled(intel_hdmi);
 434
 435         /* If the registers were not initialized yet, they might be zeroes,
 436          * which means we're selecting the AVI DIP and we're setting its
 437          * frequency to once. This seems to really confuse the HW and make
 438          * things stop working (the register spec says the AVI always needs to
 439          * be sent every VSync). So here we avoid writing to the register more
 440          * than we need and also explicitly select the AVI DIP and explicitly
 441          * set its frequency to every VSync. Avoiding to write it twice seems to
 442          * be enough to solve the problem, but being defensive shouldn't hurt us
 443          * either. */
 444         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 445
 446         if (!enable) {
 447                 if (!(val & VIDEO_DIP_ENABLE))
 448                         return;
 449                 val &= ~VIDEO_DIP_ENABLE;
 450                 I915_WRITE(reg, val);
 451                 POSTING_READ(reg);
 452                 return;
 453         }
 454
 455         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 456                 if (val & VIDEO_DIP_ENABLE) {
 457                         val &= ~VIDEO_DIP_ENABLE;
 458                         I915_WRITE(reg, val);
 459                         POSTING_READ(reg);
 460                 }
 461                 val &= ~VIDEO_DIP_PORT_MASK;
 462                 val |= port;
 463         }
 464
 465         val |= VIDEO_DIP_ENABLE;
 466         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 467
 468         I915_WRITE(reg, val);
 469         POSTING_READ(reg);
 470
 471         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 472         intel_hdmi_set_spd_infoframe(encoder);
 473         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 474 }
 475
 476 static void ibx_set_infoframes(struct drm_encoder *encoder,
 477                                bool enable,
 478                                struct drm_display_mode *adjusted_mode)
 479 {
 480         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 481         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 482         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 483         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 484         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 485         u32 val = I915_READ(reg);
 486         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 487
 488         assert_hdmi_port_disabled(intel_hdmi);
 489
 490         /* See the big comment in g4x_set_infoframes() */
 491         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 492
 493         if (!enable) {
 494                 if (!(val & VIDEO_DIP_ENABLE))
 495                         return;
 496                 val &= ~VIDEO_DIP_ENABLE;
 497                 I915_WRITE(reg, val);
 498                 POSTING_READ(reg);
 499                 return;
 500         }
 501
 502         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 503                 if (val & VIDEO_DIP_ENABLE) {
 504                         val &= ~VIDEO_DIP_ENABLE;
 505                         I915_WRITE(reg, val);
 506                         POSTING_READ(reg);
 507                 }
 508                 val &= ~VIDEO_DIP_PORT_MASK;
 509                 val |= port;
 510         }
 511
 512         val |= VIDEO_DIP_ENABLE;
 513         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 514                  VIDEO_DIP_ENABLE_GCP);
 515
 516         I915_WRITE(reg, val);
 517         POSTING_READ(reg);
 518
 519         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 520         intel_hdmi_set_spd_infoframe(encoder);
 521         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 522 }
 523
 524 static void cpt_set_infoframes(struct drm_encoder *encoder,
 525                                bool enable,
 526                                struct drm_display_mode *adjusted_mode)
 527 {
 528         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 529         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 530         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 531         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 532         u32 val = I915_READ(reg);
 533
 534         assert_hdmi_port_disabled(intel_hdmi);
 535
 536         /* See the big comment in g4x_set_infoframes() */
 537         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 538
 539         if (!enable) {
 540                 if (!(val & VIDEO_DIP_ENABLE))
 541                         return;
 542                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 543                 I915_WRITE(reg, val);
 544                 POSTING_READ(reg);
 545                 return;
 546         }
 547
 548         /* Set both together, unset both together: see the spec. */
 549         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 550         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 551                  VIDEO_DIP_ENABLE_GCP);
 552
 553         I915_WRITE(reg, val);
 554         POSTING_READ(reg);
 555
 556         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 557         intel_hdmi_set_spd_infoframe(encoder);
 558         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 559 }
 560
 561 static void vlv_set_infoframes(struct drm_encoder *encoder,
 562                                bool enable,
 563                                struct drm_display_mode *adjusted_mode)
 564 {
 565         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 566         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 567         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 568         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 569         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 570         u32 val = I915_READ(reg);
 571         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 572
 573         assert_hdmi_port_disabled(intel_hdmi);
 574
 575         /* See the big comment in g4x_set_infoframes() */
 576         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 577
 578         if (!enable) {
 579                 if (!(val & VIDEO_DIP_ENABLE))
 580                         return;
 581                 val &= ~VIDEO_DIP_ENABLE;
 582                 I915_WRITE(reg, val);
 583                 POSTING_READ(reg);
 584                 return;
 585         }
 586
 587         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 588                 if (val & VIDEO_DIP_ENABLE) {
 589                         val &= ~VIDEO_DIP_ENABLE;
 590                         I915_WRITE(reg, val);
 591                         POSTING_READ(reg);
 592                 }
 593                 val &= ~VIDEO_DIP_PORT_MASK;
 594                 val |= port;
 595         }
 596
 597         val |= VIDEO_DIP_ENABLE;
 598         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 599                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 600
 601         I915_WRITE(reg, val);
 602         POSTING_READ(reg);
 603
 604         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 605         intel_hdmi_set_spd_infoframe(encoder);
 606         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 607 }
 608
 609 static void hsw_set_infoframes(struct drm_encoder *encoder,
 610                                bool enable,
 611                                struct drm_display_mode *adjusted_mode)
 612 {
 613         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 614         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 615         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 616         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 617         u32 val = I915_READ(reg);
 618
 619         assert_hdmi_port_disabled(intel_hdmi);
 620
 621         if (!enable) {
 622                 I915_WRITE(reg, 0);
 623                 POSTING_READ(reg);
 624                 return;
 625         }
 626
 627         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 628                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 629
 630         I915_WRITE(reg, val);
 631         POSTING_READ(reg);
 632
 633         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 634         intel_hdmi_set_spd_infoframe(encoder);
 635         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 636 }
 637
 638 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 639 {
 640         struct drm_device *dev = encoder->base.dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 643         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 644         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 645         u32 hdmi_val;
 646
 647         hdmi_val = SDVO_ENCODING_HDMI;
 648         if (!HAS_PCH_SPLIT(dev))
 649                 hdmi_val |= intel_hdmi->color_range;
 650         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 651                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 652         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 653                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 654
 655         if (crtc->config.pipe_bpp > 24)
 656                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 657         else
 658                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 659
 660         if (crtc->config.has_hdmi_sink)
 661                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 662
 663         if (crtc->config.has_audio) {
 664                 WARN_ON(!crtc->config.has_hdmi_sink);
 665                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 666                                  pipe_name(crtc->pipe));
 667                 hdmi_val |= SDVO_AUDIO_ENABLE;
 668                 intel_write_eld(&encoder->base, adjusted_mode);
 669         }
 670
 671         if (HAS_PCH_CPT(dev))
 672                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 673         else if (IS_CHERRYVIEW(dev))
 674                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 675         else
 676                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 677
 678         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 679         POSTING_READ(intel_hdmi->hdmi_reg);
 680 }
 681
 682 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 683                                     enum i915_pipe *pipe)
 684 {
 685         struct drm_device *dev = encoder->base.dev;
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 688         enum intel_display_power_domain power_domain;
 689         u32 tmp;
 690
 691         power_domain = intel_display_port_power_domain(encoder);
 692         if (!intel_display_power_enabled(dev_priv, power_domain))
 693                 return false;
 694
 695         tmp = I915_READ(intel_hdmi->hdmi_reg);
 696
 697         if (!(tmp & SDVO_ENABLE))
 698                 return false;
 699
 700         if (HAS_PCH_CPT(dev))
 701                 *pipe = PORT_TO_PIPE_CPT(tmp);
 702         else if (IS_CHERRYVIEW(dev))
 703                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 704         else
 705                 *pipe = PORT_TO_PIPE(tmp);
 706
 707         return true;
 708 }
 709
 710 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 711                                   struct intel_crtc_config *pipe_config)
 712 {
 713         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 714         struct drm_device *dev = encoder->base.dev;
 715         struct drm_i915_private *dev_priv = dev->dev_private;
 716         u32 tmp, flags = 0;
 717         int dotclock;
 718
 719         tmp = I915_READ(intel_hdmi->hdmi_reg);
 720
 721         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 722                 flags |= DRM_MODE_FLAG_PHSYNC;
 723         else
 724                 flags |= DRM_MODE_FLAG_NHSYNC;
 725
 726         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 727                 flags |= DRM_MODE_FLAG_PVSYNC;
 728         else
 729                 flags |= DRM_MODE_FLAG_NVSYNC;
 730
 731         if (tmp & HDMI_MODE_SELECT_HDMI)
 732                 pipe_config->has_hdmi_sink = true;
 733
 734         if (tmp & SDVO_AUDIO_ENABLE)
 735                 pipe_config->has_audio = true;
 736
 737         if (!HAS_PCH_SPLIT(dev) &&
 738             tmp & HDMI_COLOR_RANGE_16_235)
 739                 pipe_config->limited_color_range = true;
 740
 741         pipe_config->adjusted_mode.flags |= flags;
 742
 743         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 744                 dotclock = pipe_config->port_clock * 2 / 3;
 745         else
 746                 dotclock = pipe_config->port_clock;
 747
 748         if (HAS_PCH_SPLIT(dev_priv->dev))
 749                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 750
 751         pipe_config->adjusted_mode.crtc_clock = dotclock;
 752 }
 753
 754 static void intel_enable_hdmi(struct intel_encoder *encoder)
 755 {
 756         struct drm_device *dev = encoder->base.dev;
 757         struct drm_i915_private *dev_priv = dev->dev_private;
 758         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 759         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 760         u32 temp;
 761         u32 enable_bits = SDVO_ENABLE;
 762
 763         if (intel_crtc->config.has_audio)
 764                 enable_bits |= SDVO_AUDIO_ENABLE;
 765
 766         temp = I915_READ(intel_hdmi->hdmi_reg);
 767
 768         /* HW workaround for IBX, we need to move the port to transcoder A
 769          * before disabling it, so restore the transcoder select bit here. */
 770         if (HAS_PCH_IBX(dev))
 771                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 772
 773         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 774          * we do this anyway which shows more stable in testing.
 775          */
 776         if (HAS_PCH_SPLIT(dev)) {
 777                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 778                 POSTING_READ(intel_hdmi->hdmi_reg);
 779         }
 780
 781         temp |= enable_bits;
 782
 783         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 784         POSTING_READ(intel_hdmi->hdmi_reg);
 785
 786         /* HW workaround, need to write this twice for issue that may result
 787          * in first write getting masked.
 788          */
 789         if (HAS_PCH_SPLIT(dev)) {
 790                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 791                 POSTING_READ(intel_hdmi->hdmi_reg);
 792         }
 793 }
 794
 795 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 796 {
 797 }
 798
 799 static void intel_disable_hdmi(struct intel_encoder *encoder)
 800 {
 801         struct drm_device *dev = encoder->base.dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 804         u32 temp;
 805         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 806
 807         temp = I915_READ(intel_hdmi->hdmi_reg);
 808
 809         /* HW workaround for IBX, we need to move the port to transcoder A
 810          * before disabling it. */
 811         if (HAS_PCH_IBX(dev)) {
 812                 struct drm_crtc *crtc = encoder->base.crtc;
 813                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 814
 815                 if (temp & SDVO_PIPE_B_SELECT) {
 816                         temp &= ~SDVO_PIPE_B_SELECT;
 817                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 818                         POSTING_READ(intel_hdmi->hdmi_reg);
 819
 820                         /* Again we need to write this twice. */
 821                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 822                         POSTING_READ(intel_hdmi->hdmi_reg);
 823
 824                         /* Transcoder selection bits only update
 825                          * effectively on vblank. */
 826                         if (crtc)
 827                                 intel_wait_for_vblank(dev, pipe);
 828                         else
 829                                 msleep(50);
 830                 }
 831         }
 832
 833         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 834          * we do this anyway which shows more stable in testing.
 835          */
 836         if (HAS_PCH_SPLIT(dev)) {
 837                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 838                 POSTING_READ(intel_hdmi->hdmi_reg);
 839         }
 840
 841         temp &= ~enable_bits;
 842
 843         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 844         POSTING_READ(intel_hdmi->hdmi_reg);
 845
 846         /* HW workaround, need to write this twice for issue that may result
 847          * in first write getting masked.
 848          */
 849         if (HAS_PCH_SPLIT(dev)) {
 850                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 851                 POSTING_READ(intel_hdmi->hdmi_reg);
 852         }
 853 }
 854
 855 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 856 {
 857         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 858
 859         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 860                 return 165000;
 861         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 862                 return 300000;
 863         else
 864                 return 225000;
 865 }
 866
 867 static enum drm_mode_status
 868 intel_hdmi_mode_valid(struct drm_connector *connector,
 869                       struct drm_display_mode *mode)
 870 {
 871         int clock = mode->clock;
 872
 873         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 874                 clock *= 2;
 875
 876         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 877                                          true))
 878                 return MODE_CLOCK_HIGH;
 879         if (clock < 20000)
 880                 return MODE_CLOCK_LOW;
 881
 882         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 883                 return MODE_NO_DBLESCAN;
 884
 885         return MODE_OK;
 886 }
 887
 888 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 889 {
 890         struct drm_device *dev = crtc->base.dev;
 891         struct intel_encoder *encoder;
 892         int count = 0, count_hdmi = 0;
 893
 894         if (HAS_GMCH_DISPLAY(dev))
 895                 return false;
 896
 897         for_each_intel_encoder(dev, encoder) {
 898                 if (encoder->new_crtc != crtc)
 899                         continue;
 900
 901                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 902                 count++;
 903         }
 904
 905         /*
 906          * HDMI 12bpc affects the clocks, so it's only possible
 907          * when not cloning with other encoder types.
 908          */
 909         return count_hdmi > 0 && count_hdmi == count;
 910 }
 911
 912 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 913                                struct intel_crtc_config *pipe_config)
 914 {
 915         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 916         struct drm_device *dev = encoder->base.dev;
 917         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 918         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 919         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 920         int desired_bpp;
 921
 922         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 923
 924         if (intel_hdmi->color_range_auto) {
 925                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 926                 if (pipe_config->has_hdmi_sink &&
 927                     drm_match_cea_mode(adjusted_mode) > 1)
 928                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 929                 else
 930                         intel_hdmi->color_range = 0;
 931         }
 932
 933         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
 934                 pipe_config->pixel_multiplier = 2;
 935         }
 936
 937         if (intel_hdmi->color_range)
 938                 pipe_config->limited_color_range = true;
 939
 940         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 941                 pipe_config->has_pch_encoder = true;
 942
 943         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
 944                 pipe_config->has_audio = true;
 945
 946         /*
 947          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 948          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 949          * outputs. We also need to check that the higher clock still fits
 950          * within limits.
 951          */
 952         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
 953             clock_12bpc <= portclock_limit &&
 954             hdmi_12bpc_possible(encoder->new_crtc)) {
 955                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 956                 desired_bpp = 12*3;
 957
 958                 /* Need to adjust the port link by 1.5x for 12bpc. */
 959                 pipe_config->port_clock = clock_12bpc;
 960         } else {
 961                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 962                 desired_bpp = 8*3;
 963         }
 964
 965         if (!pipe_config->bw_constrained) {
 966                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 967                 pipe_config->pipe_bpp = desired_bpp;
 968         }
 969
 970         if (adjusted_mode->crtc_clock > portclock_limit) {
 971                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 972                 return false;
 973         }
 974
 975         return true;
 976 }
 977
 978 static void
 979 intel_hdmi_unset_edid(struct drm_connector *connector)
 980 {
 981         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 982
 983         intel_hdmi->has_hdmi_sink = false;
 984         intel_hdmi->has_audio = false;
 985         intel_hdmi->rgb_quant_range_selectable = false;
 986
 987         kfree(to_intel_connector(connector)->detect_edid);
 988         to_intel_connector(connector)->detect_edid = NULL;
 989 }
 990
 991 static bool
 992 intel_hdmi_set_edid(struct drm_connector *connector)
 993 {
 994         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 995         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 996         struct intel_encoder *intel_encoder =
 997                 &hdmi_to_dig_port(intel_hdmi)->base;
 998         enum intel_display_power_domain power_domain;
 999         struct edid *edid;
1000         bool connected = false;
1001
1002         power_domain = intel_display_port_power_domain(intel_encoder);
1003         intel_display_power_get(dev_priv, power_domain);
1004
1005         edid = drm_get_edid(connector,
1006                             intel_gmbus_get_adapter(dev_priv,
1007                                                     intel_hdmi->ddc_bus));
1008
1009         intel_display_power_put(dev_priv, power_domain);
1010
1011         to_intel_connector(connector)->detect_edid = edid;
1012         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1013                 intel_hdmi->rgb_quant_range_selectable =
1014                         drm_rgb_quant_range_selectable(edid);
1015
1016                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1017                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1018                         intel_hdmi->has_audio =
1019                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1020
1021                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1022                         intel_hdmi->has_hdmi_sink =
1023                                 drm_detect_hdmi_monitor(edid);
1024
1025                 connected = true;
1026         }
1027
1028         return connected;
1029 }
1030
1031 static enum drm_connector_status
1032 intel_hdmi_detect(struct drm_connector *connector, bool force)
1033 {
1034         enum drm_connector_status status;
1035
1036         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1037                       connector->base.id, connector->name);
1038
1039         intel_hdmi_unset_edid(connector);
1040
1041         if (intel_hdmi_set_edid(connector)) {
1042                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1043
1044                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1045                 status = connector_status_connected;
1046         } else
1047                 status = connector_status_disconnected;
1048
1049         return status;
1050 }
1051
1052 static void
1053 intel_hdmi_force(struct drm_connector *connector)
1054 {
1055         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1056
1057         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1058                       connector->base.id, connector->name);
1059
1060         intel_hdmi_unset_edid(connector);
1061
1062         if (connector->status != connector_status_connected)
1063                 return;
1064
1065         intel_hdmi_set_edid(connector);
1066         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1067 }
1068
1069 static int intel_hdmi_get_modes(struct drm_connector *connector)
1070 {
1071         struct edid *edid;
1072
1073         edid = to_intel_connector(connector)->detect_edid;
1074         if (edid == NULL)
1075                 return 0;
1076
1077         return intel_connector_update_modes(connector, edid);
1078 }
1079
1080 static bool
1081 intel_hdmi_detect_audio(struct drm_connector *connector)
1082 {
1083         bool has_audio = false;
1084         struct edid *edid;
1085
1086         edid = to_intel_connector(connector)->detect_edid;
1087         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1088                 has_audio = drm_detect_monitor_audio(edid);
1089
1090         return has_audio;
1091 }
1092
1093 static int
1094 intel_hdmi_set_property(struct drm_connector *connector,
1095                         struct drm_property *property,
1096                         uint64_t val)
1097 {
1098         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1099         struct intel_digital_port *intel_dig_port =
1100                 hdmi_to_dig_port(intel_hdmi);
1101         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1102         int ret;
1103
1104         ret = drm_object_property_set_value(&connector->base, property, val);
1105         if (ret)
1106                 return ret;
1107
1108         if (property == dev_priv->force_audio_property) {
1109                 enum hdmi_force_audio i = val;
1110                 bool has_audio;
1111
1112                 if (i == intel_hdmi->force_audio)
1113                         return 0;
1114
1115                 intel_hdmi->force_audio = i;
1116
1117                 if (i == HDMI_AUDIO_AUTO)
1118                         has_audio = intel_hdmi_detect_audio(connector);
1119                 else
1120                         has_audio = (i == HDMI_AUDIO_ON);
1121
1122                 if (i == HDMI_AUDIO_OFF_DVI)
1123                         intel_hdmi->has_hdmi_sink = 0;
1124
1125                 intel_hdmi->has_audio = has_audio;
1126                 goto done;
1127         }
1128
1129         if (property == dev_priv->broadcast_rgb_property) {
1130                 bool old_auto = intel_hdmi->color_range_auto;
1131                 uint32_t old_range = intel_hdmi->color_range;
1132
1133                 switch (val) {
1134                 case INTEL_BROADCAST_RGB_AUTO:
1135                         intel_hdmi->color_range_auto = true;
1136                         break;
1137                 case INTEL_BROADCAST_RGB_FULL:
1138                         intel_hdmi->color_range_auto = false;
1139                         intel_hdmi->color_range = 0;
1140                         break;
1141                 case INTEL_BROADCAST_RGB_LIMITED:
1142                         intel_hdmi->color_range_auto = false;
1143                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1144                         break;
1145                 default:
1146                         return -EINVAL;
1147                 }
1148
1149                 if (old_auto == intel_hdmi->color_range_auto &&
1150                     old_range == intel_hdmi->color_range)
1151                         return 0;
1152
1153                 goto done;
1154         }
1155
1156         if (property == connector->dev->mode_config.aspect_ratio_property) {
1157                 switch (val) {
1158                 case DRM_MODE_PICTURE_ASPECT_NONE:
1159                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1160                         break;
1161                 case DRM_MODE_PICTURE_ASPECT_4_3:
1162                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1163                         break;
1164                 case DRM_MODE_PICTURE_ASPECT_16_9:
1165                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1166                         break;
1167                 default:
1168                         return -EINVAL;
1169                 }
1170                 goto done;
1171         }
1172
1173         return -EINVAL;
1174
1175 done:
1176         if (intel_dig_port->base.base.crtc)
1177                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1178
1179         return 0;
1180 }
1181
1182 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1183 {
1184         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1185         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1186         struct drm_display_mode *adjusted_mode =
1187                 &intel_crtc->config.adjusted_mode;
1188
1189         intel_hdmi_prepare(encoder);
1190
1191         intel_hdmi->set_infoframes(&encoder->base,
1192                                    intel_crtc->config.has_hdmi_sink,
1193                                    adjusted_mode);
1194 }
1195
1196 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1197 {
1198         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1199         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1200         struct drm_device *dev = encoder->base.dev;
1201         struct drm_i915_private *dev_priv = dev->dev_private;
1202         struct intel_crtc *intel_crtc =
1203                 to_intel_crtc(encoder->base.crtc);
1204         struct drm_display_mode *adjusted_mode =
1205                 &intel_crtc->config.adjusted_mode;
1206         enum dpio_channel port = vlv_dport_to_channel(dport);
1207         int pipe = intel_crtc->pipe;
1208         u32 val;
1209
1210         /* Enable clock channels for this port */
1211         mutex_lock(&dev_priv->dpio_lock);
1212         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1213         val = 0;
1214         if (pipe)
1215                 val |= (1<<21);
1216         else
1217                 val &= ~(1<<21);
1218         val |= 0x001000c4;
1219         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1220
1221         /* HDMI 1.0V-2dB */
1222         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1223         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1224         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1225         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1226         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1227         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1228         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1229         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1230
1231         /* Program lane clock */
1232         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1233         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1234         mutex_unlock(&dev_priv->dpio_lock);
1235
1236         intel_hdmi->set_infoframes(&encoder->base,
1237                                    intel_crtc->config.has_hdmi_sink,
1238                                    adjusted_mode);
1239
1240         intel_enable_hdmi(encoder);
1241
1242         vlv_wait_port_ready(dev_priv, dport);
1243 }
1244
1245 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1246 {
1247         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1248         struct drm_device *dev = encoder->base.dev;
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250         struct intel_crtc *intel_crtc =
1251                 to_intel_crtc(encoder->base.crtc);
1252         enum dpio_channel port = vlv_dport_to_channel(dport);
1253         int pipe = intel_crtc->pipe;
1254
1255         intel_hdmi_prepare(encoder);
1256
1257         /* Program Tx lane resets to default */
1258         mutex_lock(&dev_priv->dpio_lock);
1259         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1260                          DPIO_PCS_TX_LANE2_RESET |
1261                          DPIO_PCS_TX_LANE1_RESET);
1262         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1263                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1264                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1265                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1266                          DPIO_PCS_CLK_SOFT_RESET);
1267
1268         /* Fix up inter-pair skew failure */
1269         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1270         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1271         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1272
1273         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1274         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1275         mutex_unlock(&dev_priv->dpio_lock);
1276 }
1277
1278 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1279 {
1280         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1281         struct drm_device *dev = encoder->base.dev;
1282         struct drm_i915_private *dev_priv = dev->dev_private;
1283         struct intel_crtc *intel_crtc =
1284                 to_intel_crtc(encoder->base.crtc);
1285         enum dpio_channel ch = vlv_dport_to_channel(dport);
1286         enum i915_pipe pipe = intel_crtc->pipe;
1287         u32 val;
1288
1289         intel_hdmi_prepare(encoder);
1290
1291         mutex_lock(&dev_priv->dpio_lock);
1292
1293         /* program left/right clock distribution */
1294         if (pipe != PIPE_B) {
1295                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1296                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1297                 if (ch == DPIO_CH0)
1298                         val |= CHV_BUFLEFTENA1_FORCE;
1299                 if (ch == DPIO_CH1)
1300                         val |= CHV_BUFRIGHTENA1_FORCE;
1301                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1302         } else {
1303                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1304                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1305                 if (ch == DPIO_CH0)
1306                         val |= CHV_BUFLEFTENA2_FORCE;
1307                 if (ch == DPIO_CH1)
1308                         val |= CHV_BUFRIGHTENA2_FORCE;
1309                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1310         }
1311
1312         /* program clock channel usage */
1313         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1314         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1315         if (pipe != PIPE_B)
1316                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1317         else
1318                 val |= CHV_PCS_USEDCLKCHANNEL;
1319         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1320
1321         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1322         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1323         if (pipe != PIPE_B)
1324                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1325         else
1326                 val |= CHV_PCS_USEDCLKCHANNEL;
1327         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1328
1329         /*
1330          * This a a bit weird since generally CL
1331          * matches the pipe, but here we need to
1332          * pick the CL based on the port.
1333          */
1334         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1335         if (pipe != PIPE_B)
1336                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1337         else
1338                 val |= CHV_CMN_USEDCLKCHANNEL;
1339         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1340
1341         mutex_unlock(&dev_priv->dpio_lock);
1342 }
1343
1344 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1345 {
1346         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1347         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1348         struct intel_crtc *intel_crtc =
1349                 to_intel_crtc(encoder->base.crtc);
1350         enum dpio_channel port = vlv_dport_to_channel(dport);
1351         int pipe = intel_crtc->pipe;
1352
1353         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1354         mutex_lock(&dev_priv->dpio_lock);
1355         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1356         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1357         mutex_unlock(&dev_priv->dpio_lock);
1358 }
1359
1360 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1361 {
1362         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1363         struct drm_device *dev = encoder->base.dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         struct intel_crtc *intel_crtc =
1366                 to_intel_crtc(encoder->base.crtc);
1367         enum dpio_channel ch = vlv_dport_to_channel(dport);
1368         enum i915_pipe pipe = intel_crtc->pipe;
1369         u32 val;
1370
1371         mutex_lock(&dev_priv->dpio_lock);
1372
1373         /* Propagate soft reset to data lane reset */
1374         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1375         val |= CHV_PCS_REQ_SOFTRESET_EN;
1376         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1377
1378         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1379         val |= CHV_PCS_REQ_SOFTRESET_EN;
1380         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1381
1382         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1383         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1384         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1385
1386         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1387         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1388         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1389
1390         mutex_unlock(&dev_priv->dpio_lock);
1391 }
1392
1393 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1394 {
1395         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1396         struct drm_device *dev = encoder->base.dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         struct intel_crtc *intel_crtc =
1399                 to_intel_crtc(encoder->base.crtc);
1400         enum dpio_channel ch = vlv_dport_to_channel(dport);
1401         int pipe = intel_crtc->pipe;
1402         int data, i;
1403         u32 val;
1404
1405         mutex_lock(&dev_priv->dpio_lock);
1406
1407         /* Deassert soft data lane reset*/
1408         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1409         val |= CHV_PCS_REQ_SOFTRESET_EN;
1410         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1411
1412         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1413         val |= CHV_PCS_REQ_SOFTRESET_EN;
1414         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1415
1416         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1417         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1418         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1419
1420         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1421         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1422         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1423
1424         /* Program Tx latency optimal setting */
1425         for (i = 0; i < 4; i++) {
1426                 /* Set the latency optimal bit */
1427                 data = (i == 1) ? 0x0 : 0x6;
1428                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1429                                 data << DPIO_FRC_LATENCY_SHFIT);
1430
1431                 /* Set the upar bit */
1432                 data = (i == 1) ? 0x0 : 0x1;
1433                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1434                                 data << DPIO_UPAR_SHIFT);
1435         }
1436
1437         /* Data lane stagger programming */
1438         /* FIXME: Fix up value only after power analysis */
1439
1440         /* Clear calc init */
1441         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1442         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1443         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1444
1445         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1446         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1447         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1448
1449         /* FIXME: Program the support xxx V-dB */
1450         /* Use 800mV-0dB */
1451         for (i = 0; i < 4; i++) {
1452                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1453                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1454                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1455                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1456         }
1457
1458         for (i = 0; i < 4; i++) {
1459                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1460                 val &= ~DPIO_SWING_MARGIN000_MASK;
1461                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1462                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1463         }
1464
1465         /* Disable unique transition scale */
1466         for (i = 0; i < 4; i++) {
1467                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1468                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1469                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1470         }
1471
1472         /* Additional steps for 1200mV-0dB */
1473 #if 0
1474         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1475         if (ch)
1476                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1477         else
1478                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1479         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1480
1481         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1482                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1483                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1484 #endif
1485         /* Start swing calculation */
1486         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1487         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1488         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1489
1490         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1491         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1492         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1493
1494         /* LRC Bypass */
1495         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1496         val |= DPIO_LRC_BYPASS;
1497         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1498
1499         mutex_unlock(&dev_priv->dpio_lock);
1500
1501         intel_enable_hdmi(encoder);
1502
1503         vlv_wait_port_ready(dev_priv, dport);
1504 }
1505
1506 static void intel_hdmi_destroy(struct drm_connector *connector)
1507 {
1508         kfree(to_intel_connector(connector)->detect_edid);
1509         drm_connector_cleanup(connector);
1510         kfree(connector);
1511 }
1512
1513 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1514         .dpms = intel_connector_dpms,
1515         .detect = intel_hdmi_detect,
1516         .force = intel_hdmi_force,
1517         .fill_modes = drm_helper_probe_single_connector_modes,
1518         .set_property = intel_hdmi_set_property,
1519         .destroy = intel_hdmi_destroy,
1520 };
1521
1522 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1523         .get_modes = intel_hdmi_get_modes,
1524         .mode_valid = intel_hdmi_mode_valid,
1525         .best_encoder = intel_best_encoder,
1526 };
1527
1528 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1529         .destroy = intel_encoder_destroy,
1530 };
1531
1532 static void
1533 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1534 {
1535         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1536                 drm_object_attach_property(&connector->base,
1537                         connector->dev->mode_config.aspect_ratio_property,
1538                         DRM_MODE_PICTURE_ASPECT_NONE);
1539 }
1540
1541 static void
1542 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1543 {
1544         intel_attach_force_audio_property(connector);
1545         intel_attach_broadcast_rgb_property(connector);
1546         intel_hdmi->color_range_auto = true;
1547         intel_attach_aspect_ratio_property(connector);
1548         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1549 }
1550
1551 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1552                                struct intel_connector *intel_connector)
1553 {
1554         struct drm_connector *connector = &intel_connector->base;
1555         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1556         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1557         struct drm_device *dev = intel_encoder->base.dev;
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         enum port port = intel_dig_port->port;
1560
1561         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1562                            DRM_MODE_CONNECTOR_HDMIA);
1563         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1564
1565         connector->interlace_allowed = 1;
1566         connector->doublescan_allowed = 0;
1567         connector->stereo_allowed = 1;
1568
1569         switch (port) {
1570         case PORT_B:
1571                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1572                 intel_encoder->hpd_pin = HPD_PORT_B;
1573                 break;
1574         case PORT_C:
1575                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1576                 intel_encoder->hpd_pin = HPD_PORT_C;
1577                 break;
1578         case PORT_D:
1579                 if (IS_CHERRYVIEW(dev))
1580                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1581                 else
1582                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1583                 intel_encoder->hpd_pin = HPD_PORT_D;
1584                 break;
1585         case PORT_A:
1586                 intel_encoder->hpd_pin = HPD_PORT_A;
1587                 /* Internal port only for eDP. */
1588         default:
1589                 BUG();
1590         }
1591
1592         if (IS_VALLEYVIEW(dev)) {
1593                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1594                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1595         } else if (IS_G4X(dev)) {
1596                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1597                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1598         } else if (HAS_DDI(dev)) {
1599                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1600                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1601         } else if (HAS_PCH_IBX(dev)) {
1602                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1603                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1604         } else {
1605                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1606                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1607         }
1608
1609         if (HAS_DDI(dev))
1610                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1611         else
1612                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1613         intel_connector->unregister = intel_connector_unregister;
1614
1615         intel_hdmi_add_properties(intel_hdmi, connector);
1616
1617         intel_connector_attach_encoder(intel_connector, intel_encoder);
1618         drm_connector_register(connector);
1619
1620         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1621          * 0xd.  Failure to do so will result in spurious interrupts being
1622          * generated on the port when a cable is not attached.
1623          */
1624         if (IS_G4X(dev) && !IS_GM45(dev)) {
1625                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1626                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1627         }
1628 }
1629
1630 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1631 {
1632         struct intel_digital_port *intel_dig_port;
1633         struct intel_encoder *intel_encoder;
1634         struct intel_connector *intel_connector;
1635
1636         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1637         if (!intel_dig_port)
1638                 return;
1639
1640         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1641         if (!intel_connector) {
1642                 kfree(intel_dig_port);
1643                 return;
1644         }
1645
1646         intel_encoder = &intel_dig_port->base;
1647
1648         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1649                          DRM_MODE_ENCODER_TMDS);
1650
1651         intel_encoder->compute_config = intel_hdmi_compute_config;
1652         intel_encoder->disable = intel_disable_hdmi;
1653         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1654         intel_encoder->get_config = intel_hdmi_get_config;
1655         if (IS_CHERRYVIEW(dev)) {
1656                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1657                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1658                 intel_encoder->enable = vlv_enable_hdmi;
1659                 intel_encoder->post_disable = chv_hdmi_post_disable;
1660         } else if (IS_VALLEYVIEW(dev)) {
1661                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1662                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1663                 intel_encoder->enable = vlv_enable_hdmi;
1664                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1665         } else {
1666                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1667                 intel_encoder->enable = intel_enable_hdmi;
1668         }
1669
1670         intel_encoder->type = INTEL_OUTPUT_HDMI;
1671         if (IS_CHERRYVIEW(dev)) {
1672                 if (port == PORT_D)
1673                         intel_encoder->crtc_mask = 1 << 2;
1674                 else
1675                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1676         } else {
1677                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1678         }
1679         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1680         /*
1681          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1682          * to work on real hardware. And since g4x can send infoframes to
1683          * only one port anyway, nothing is lost by allowing it.
1684          */
1685         if (IS_G4X(dev))
1686                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1687
1688         intel_dig_port->port = port;
1689         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1690         intel_dig_port->dp.output_reg = 0;
1691
1692         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1693 }