2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
4 * Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $DragonFly: src/sys/bus/pci/pci_pcib.c,v 1.4 2005/01/17 20:24:46 joerg Exp $
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
38 #include <sys/systm.h>
40 #include <machine/resource.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
45 #include "pcib_private.h"
48 * Attach a pci bus device to a motherboard or pci-to-pci bridge bus.
49 * Due to probe recursion it is possible for pci-to-pci bridges (such as
50 * on the DELL2550) to attach before all the motherboard bridges have
51 * attached. We must call device_add_child() with the secondary id
52 * rather then -1 in order to ensure that we do not accidently use
53 * a motherboard PCI id, otherwise the device probe will believe that
54 * the later motherboard bridge bus has already been probed and refuse
55 * to probe it. The result: disappearing busses!
57 * Bridges will cause recursions or duplicate attach attempts. If
58 * we have already attached this bus we don't do it again!
62 pcib_attach_common(device_t dev)
64 struct pcib_softc *sc;
67 sc = device_get_softc(dev);
71 * Get current bridge configuration.
73 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
74 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
75 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
76 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
77 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
78 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
81 * Determine current I/O decode.
83 if (sc->command & PCIM_CMD_PORTEN) {
84 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
85 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
86 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
87 pci_read_config(dev, PCIR_IOBASEL_1, 1));
89 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
92 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
93 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
94 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
95 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
97 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
102 * Determine current memory decode.
104 if (sc->command & PCIM_CMD_MEMEN) {
105 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
106 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
107 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
108 pci_read_config(dev, PCIR_PMBASEL_1, 2));
109 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
110 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
116 switch (pci_get_devid(dev)) {
117 case 0x12258086: /* Intel 82454KX/GX (Orion) */
121 supbus = pci_read_config(dev, 0x41, 1);
122 if (supbus != 0xff) {
123 sc->secbus = supbus + 1;
124 sc->subbus = supbus + 1;
130 * The i82380FB mobile docking controller is a PCI-PCI bridge,
131 * and it is a subtractive bridge. However, the ProgIf is wrong
132 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
133 * happen. There's also a Toshiba bridge that behaves this
136 case 0x124b8086: /* Intel 82380FB Mobile */
137 case 0x060513d7: /* Toshiba ???? */
138 sc->flags |= PCIB_SUBTRACTIVE;
143 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
144 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
145 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
146 * This means they act as if they were subtractively decoding
147 * bridges and pass all transactions. Mark them and real ProgIf 1
148 * parts as subtractive.
150 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
151 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
152 sc->flags |= PCIB_SUBTRACTIVE;
155 device_printf(dev, " secondary bus %d\n", sc->secbus);
156 device_printf(dev, " subordinate bus %d\n", sc->subbus);
157 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
158 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
159 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
160 if (sc->flags & PCIB_SUBTRACTIVE)
161 device_printf(dev, " Subtractively decoded bridge.\n");
165 * XXX If the secondary bus number is zero, we should assign a bus number
166 * since the BIOS hasn't, then initialise the bridge.
170 * XXX If the subordinate bus number is less than the secondary bus number,
171 * we should pick a better value. One sensible alternative would be to
172 * pick 255; the only tradeoff here is that configuration transactions
173 * would be more widely routed than absolutely necessary.
178 pcib_match(device_t dev)
180 switch (pci_get_devid(dev)) {
181 /* Intel -- vendor 0x8086 */
183 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
185 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
187 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
189 return ("Intel 82454NX PCI Expander Bridge");
191 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
193 return ("Intel 82380FB mobile PCI to PCI bridge");
195 return ("Intel 82801AA (ICH) Hub to PCI bridge");
197 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
199 return ("Intel 82801BA/CA/DB/EB/FB (ICH2/3/4/5/6) Hub to PCI bridge");
201 return ("Intel 82845 PCI-PCI (AGP) bridge");
203 /* VLSI -- vendor 0x1004 */
205 return ("VLSI 82C534 Eagle II PCI Bus bridge");
207 return ("VLSI 82C538 Eagle II PCI Docking bridge");
209 /* VIA Technologies -- vendor 0x1106 */
211 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
213 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
214 /* Exclude the ACPI function of VT82Cxxx series */
220 /* AcerLabs -- vendor 0x10b9 */
221 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
222 /* id is '10b9" but the register always shows "10b9". -Foxfair */
224 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
225 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
226 return ("AcerLabs M5243 PCI-PCI bridge");
228 /* AMD -- vendor 0x1022 */
230 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
232 return ("AMD-761 PCI-PCI (4x AGP) bridge");
234 /* DEC -- vendor 0x1011 */
236 return ("DEC 21050 PCI-PCI bridge");
238 return ("DEC 21052 PCI-PCI bridge");
240 return ("DEC 21150 PCI-PCI bridge");
242 return ("DEC 21152 PCI-PCI bridge");
244 return ("DEC 21153 PCI-PCI bridge");
246 return ("DEC 21154 PCI-PCI bridge");
248 /* NVIDIA -- vendor 0x10de */
251 return ("NVIDIA nForce2 PCI-PCI bridge");
255 return ("IBM 82351 PCI-PCI bridge");
256 /* UMC United Microelectronics 0x1060 */
258 return ("UMC UM8881 HB4 486 PCI Chipset");
261 if (pci_get_class(dev) == PCIC_BRIDGE
262 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI)
263 return pci_bridge_type(dev);
268 static int pcib_probe(device_t dev)
272 desc = pcib_match(dev);
274 device_set_desc_copy(dev, desc);
282 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
284 struct pcib_softc *sc = device_get_softc(dev);
288 *result = sc->secbus;
295 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
297 struct pcib_softc *sc = device_get_softc(dev);
308 pcib_attach(device_t dev)
310 struct pcib_softc *sc;
313 pcib_attach_common(dev);
314 sc = device_get_softc(dev);
315 /*chipset_attach(dev, device_get_unit(dev));*/
317 if (sc->secbus != 0) {
318 child = device_add_child(dev, "pci", sc->secbus);
320 return bus_generic_attach(dev);
326 * Is the prefetch window open (eg, can we allocate memory in it?)
329 pcib_is_prefetch_open(struct pcib_softc *sc)
331 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
335 * Is the nonprefetch window open (eg, can we allocate memory in it?)
338 pcib_is_nonprefetch_open(struct pcib_softc *sc)
340 return (sc->membase > 0 && sc->membase < sc->memlimit);
344 * Is the io window open (eg, can we allocate ports in it?)
347 pcib_is_io_open(struct pcib_softc *sc)
349 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
353 * We have to trap resource allocation requests and ensure that the bridge
354 * is set up to, or capable of handling them.
357 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
358 u_long start, u_long end, u_long count, u_int flags)
360 struct pcib_softc *sc = device_get_softc(dev);
364 * Fail the allocation for this range if it's not supported.
369 if (!pcib_is_io_open(sc))
371 ok = (start >= sc->iobase && end <= sc->iolimit);
372 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
374 if (start < sc->iobase)
376 if (end > sc->iolimit)
382 if (start < sc->iobase && end > sc->iolimit) {
389 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
395 device_printf(dev, "device %s requested unsupported I/O "
396 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
397 device_get_nameunit(child), start, end,
398 sc->iobase, sc->iolimit);
402 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
403 device_get_nameunit(child), start, end);
408 if (pcib_is_nonprefetch_open(sc))
409 ok = ok || (start >= sc->membase && end <= sc->memlimit);
410 if (pcib_is_prefetch_open(sc))
411 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
412 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
415 if (flags & RF_PREFETCHABLE) {
416 if (pcib_is_prefetch_open(sc)) {
417 if (start < sc->pmembase)
418 start = sc->pmembase;
419 if (end > sc->pmemlimit)
424 } else { /* non-prefetchable */
425 if (pcib_is_nonprefetch_open(sc)) {
426 if (start < sc->membase)
428 if (end > sc->memlimit)
436 ok = 1; /* subtractive bridge: always ok */
438 if (pcib_is_nonprefetch_open(sc)) {
439 if (start < sc->membase && end > sc->memlimit) {
444 if (pcib_is_prefetch_open(sc)) {
445 if (start < sc->pmembase && end > sc->pmemlimit) {
446 start = sc->pmembase;
453 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
458 if (!ok && bootverbose)
460 "device %s requested unsupported memory range "
461 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
462 device_get_nameunit(child), start, end,
463 sc->membase, sc->memlimit, sc->pmembase,
468 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
469 device_get_nameunit(child), start, end);
476 * Bridge is OK decoding this resource, so pass it up.
478 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
483 pcib_maxslots(device_t dev)
489 pcib_read_config(device_t dev, int b, int s, int f,
493 * Pass through to the next ppb up the chain (i.e. our
496 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
497 b, s, f, reg, width);
501 pcib_write_config(device_t dev, int b, int s, int f,
502 int reg, uint32_t val, int width)
505 * Pass through to the next ppb up the chain (i.e. our
508 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
509 b, s, f, reg, val, width);
513 * Route an interrupt across a PCI bridge.
516 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
522 device_printf(pcib, "Hi!\n");
526 * The PCI standard defines a swizzle of the child-side device/intpin
527 * to the parent-side intpin as follows.
529 * device = device on child bus
530 * child_intpin = intpin on child bus slot (0-3)
531 * parent_intpin = intpin on parent bus slot (0-3)
533 * parent_intpin = (device + child_intpin) % 4
535 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
538 * Our parent is a PCI bus. Its parent must export the pci interface
539 * which includes the ability to route interrupts.
541 bus = device_get_parent(pcib);
542 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
544 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
545 pci_get_slot(dev), 'A' + pin - 1, intnum);
550 * Try to read the bus number of a host-PCI bridge using appropriate config
554 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
559 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
560 if (id == 0xffffffff)
566 /* XXX This is a guess */
567 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
571 /* Intel 82454KX/GX (Orion) */
572 *busnum = read_config(bus, slot, func, 0x4a, 1);
576 * For the 450nx chipset, there is a whole bundle of
577 * things pretending to be host bridges. The MIOC will
578 * be seen first and isn't really a pci bridge (the
579 * actual busses are attached to the PXB's). We need to
580 * read the registers of the MIOC to figure out the
581 * bus numbers for the PXB channels.
583 * Since the MIOC doesn't have a pci bus attached, we
584 * pretend it wasn't there.
590 /* Intel 82454NX PXB#0, Bus#A */
591 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
594 /* Intel 82454NX PXB#0, Bus#B */
595 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
598 /* Intel 82454NX PXB#1, Bus#A */
599 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
602 /* Intel 82454NX PXB#1, Bus#B */
603 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
608 /* ServerWorks -- vendor 0x1166 */
620 *busnum = read_config(bus, slot, func, 0x44, 1);
623 /* Don't know how to read bus number. */
630 static device_method_t pcib_methods[] = {
631 /* Device interface */
632 DEVMETHOD(device_probe, pcib_probe),
633 DEVMETHOD(device_attach, pcib_attach),
634 DEVMETHOD(device_shutdown, bus_generic_shutdown),
635 DEVMETHOD(device_suspend, bus_generic_suspend),
636 DEVMETHOD(device_resume, bus_generic_resume),
639 DEVMETHOD(bus_print_child, bus_generic_print_child),
640 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
641 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
642 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
643 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
644 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
645 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
646 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
647 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
650 DEVMETHOD(pcib_maxslots, pcib_maxslots),
651 DEVMETHOD(pcib_read_config, pcib_read_config),
652 DEVMETHOD(pcib_write_config, pcib_write_config),
653 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
658 static driver_t pcib_driver = {
661 sizeof(struct pcib_softc)
664 devclass_t pcib_devclass;
666 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);