sys/dev/raid/arcmsr/arcmsr.c

   1 /*
   2 *****************************************************************************************
   3 **        O.S   : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) SATA/SAS RAID HOST Adapter
   8 **                ARCMSR RAID Host adapter
   9 **                [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
  10 ******************************************************************************************
  11 ************************************************************************
  12 **
  13 ** Copyright (c) 2004-2010 ARECA Co. Ltd.
  14 **        Erich Chen, Taipei Taiwan All rights reserved.
  15 **
  16 ** Redistribution and use in source and binary forms, with or without
  17 ** modification, are permitted provided that the following conditions
  18 ** are met:
  19 ** 1. Redistributions of source code must retain the above copyright
  20 **    notice, this list of conditions and the following disclaimer.
  21 ** 2. Redistributions in binary form must reproduce the above copyright
  22 **    notice, this list of conditions and the following disclaimer in the
  23 **    documentation and/or other materials provided with the distribution.
  24 ** 3. The name of the author may not be used to endorse or promote products
  25 **    derived from this software without specific prior written permission.
  26 **
  27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 **************************************************************************
  38 ** History
  39 **
  40 **        REV#         DATE                 NAME                 DESCRIPTION
  41 **     1.00.00.00    3/31/2004         Erich Chen        First release
  42 **     1.20.00.02   11/29/2004         Erich Chen        bug fix with arcmsr_bus_reset when PHY error
  43 **     1.20.00.03    4/19/2005         Erich Chen        add SATA 24 Ports adapter type support
  44 **                                                       clean unused function
  45 **     1.20.00.12    9/12/2005         Erich Chen        bug fix with abort command handling,
  46 **                                                       firmware version check
  47 **                                                       and firmware update notify for hardware bug fix
  48 **                                                       handling if none zero high part physical address
  49 **                                                       of srb resource
  50 **     1.20.00.13    8/18/2006         Erich Chen        remove pending srb and report busy
  51 **                                                       add iop message xfer
  52 **                                                       with scsi pass-through command
  53 **                                                       add new device id of sas raid adapters
  54 **                                                       code fit for SPARC64 & PPC
  55 **     1.20.00.14   02/05/2007         Erich Chen        bug fix for incorrect ccb_h.status report
  56 **                                                       and cause g_vfs_done() read write error
  57 **     1.20.00.15   10/10/2007         Erich Chen        support new RAID adapter type ARC120x
  58 **     1.20.00.16   10/10/2009         Erich Chen        Bug fix for RAID adapter type ARC120x
  59 **                                                       bus_dmamem_alloc() with BUS_DMA_ZERO
  60 **     1.20.00.17   07/15/2010         Ching Huang       Added support ARC1880
  61 **                                                       report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  62 **                                                       prevent cam_periph_error removing all LUN devices of one Target id
  63 **                                                       for any one LUN device failed
  64 **     1.20.00.18   10/14/2010         Ching Huang       Fixed "inquiry data fails comparion at DV1 step"
  65 **                  10/25/2010         Ching Huang       Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  66 **     1.20.00.19   11/11/2010         Ching Huang       Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  67 ******************************************************************************************
  68 * $FreeBSD: src/sys/dev/arcmsr/arcmsr.c,v 1.35 2010/11/13 08:58:36 delphij Exp $
  69 */
  70 #include <sys/param.h>
  71 #include <sys/systm.h>
  72 #include <sys/malloc.h>
  73 #include <sys/kernel.h>
  74 #include <sys/bus.h>
  75 #include <sys/queue.h>
  76 #include <sys/stat.h>
  77 #include <sys/devicestat.h>
  78 #include <sys/kthread.h>
  79 #include <sys/module.h>
  80 #include <sys/proc.h>
  81 #include <sys/lock.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/thread2.h>
  84 #include <sys/poll.h>
  85 #include <sys/device.h>
  86 #include <vm/vm.h>
  87 #include <vm/vm_param.h>
  88 #include <vm/pmap.h>
  89
  90 #include <machine/atomic.h>
  91 #include <sys/conf.h>
  92 #include <sys/rman.h>
  93
  94 #include <bus/cam/cam.h>
  95 #include <bus/cam/cam_ccb.h>
  96 #include <bus/cam/cam_sim.h>
  97 #include <bus/cam/cam_periph.h>
  98 #include <bus/cam/cam_xpt_periph.h>
  99 #include <bus/cam/cam_xpt_sim.h>
 100 #include <bus/cam/cam_debug.h>
 101 #include <bus/cam/scsi/scsi_all.h>
 102 #include <bus/cam/scsi/scsi_message.h>
 103 /*
 104 **************************************************************************
 105 **************************************************************************
 106 */
 107 #include <sys/endian.h>
 108 #include <bus/pci/pcivar.h>
 109 #include <bus/pci/pcireg.h>
 110 #define ARCMSR_LOCK_INIT(l, s)  lockinit(l, s, 0, LK_CANRECURSE)
 111 #define ARCMSR_LOCK_DESTROY(l)  lockuninit(l)
 112 #define ARCMSR_LOCK_ACQUIRE(l)  lockmgr(l, LK_EXCLUSIVE)
 113 #define ARCMSR_LOCK_RELEASE(l)  lockmgr(l, LK_RELEASE)
 114 #define ARCMSR_LOCK_TRY(l)      lockmgr(&l, LK_EXCLUSIVE|LK_NOWAIT);
 115 #define arcmsr_htole32(x)       htole32(x)
 116 typedef struct lock             arcmsr_lock_t;
 117
 118 #if !defined(CAM_NEW_TRAN_CODE)
 119 #define CAM_NEW_TRAN_CODE       1
 120 #endif
 121
 122 #define ARCMSR_DRIVER_VERSION                   "Driver Version 1.20.00.19 2010-11-11"
 123 #include <dev/raid/arcmsr/arcmsr.h>
 124 #define ARCMSR_SRBS_POOL_SIZE           ((sizeof(struct CommandControlBlock) * ARCMSR_MAX_FREESRB_NUM))
 125 /*
 126 **************************************************************************
 127 **************************************************************************
 128 */
 129 #define CHIP_REG_READ32(s, b, r)        bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
 130 #define CHIP_REG_WRITE32(s, b, r, d)    bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
 131 /*
 132 **************************************************************************
 133 **************************************************************************
 134 */
 135 static struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 136 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb);
 137 static int arcmsr_probe(device_t dev);
 138 static int arcmsr_attach(device_t dev);
 139 static int arcmsr_detach(device_t dev);
 140 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 141 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 142 static int arcmsr_shutdown(device_t dev);
 143 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 144 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 145 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 146 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 147 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 148 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 149 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 150 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 151 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb);
 152 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 153 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 154 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 155 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 156 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t * dm_segs, u_int32_t nseg);
 157 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb);
 158 static int arcmsr_resume(device_t dev);
 159 static int arcmsr_suspend(device_t dev);
 160 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 161 static void     arcmsr_polling_devmap(void* arg);
 162 /*
 163 **************************************************************************
 164 **************************************************************************
 165 */
 166 static void UDELAY(u_int32_t us) { DELAY(us); }
 167 /*
 168 **************************************************************************
 169 **************************************************************************
 170 */
 171 static bus_dmamap_callback_t arcmsr_map_free_srb;
 172 static bus_dmamap_callback_t arcmsr_execute_srb;
 173 /*
 174 **************************************************************************
 175 **************************************************************************
 176 */
 177 static d_open_t arcmsr_open;
 178 static d_close_t arcmsr_close;
 179 static d_ioctl_t arcmsr_ioctl;
 180
 181 static device_method_t arcmsr_methods[]={
 182         DEVMETHOD(device_probe,         arcmsr_probe),
 183         DEVMETHOD(device_attach,        arcmsr_attach),
 184         DEVMETHOD(device_detach,        arcmsr_detach),
 185         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 186         DEVMETHOD(device_suspend,       arcmsr_suspend),
 187         DEVMETHOD(device_resume,        arcmsr_resume),
 188         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 189         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 190         { 0, 0 }
 191 };
 192
 193 static driver_t arcmsr_driver={
 194         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 195 };
 196
 197 static devclass_t arcmsr_devclass;
 198 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, NULL, NULL);
 199 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 200 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 201 #ifndef BUS_DMA_COHERENT
 202         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 203 #endif
 204
 205 static struct dev_ops arcmsr_ops = {
 206         { "arcmsr", 0, 0 },
 207         .d_open =       arcmsr_open,                    /* open     */
 208         .d_close =      arcmsr_close,                   /* close    */
 209         .d_ioctl =      arcmsr_ioctl,                   /* ioctl    */
 210 };
 211
 212 static int      arcmsr_msi_enable = 1;
 213 TUNABLE_INT("hw.arcmsr.msi.enable", &arcmsr_msi_enable);
 214
 215
 216 /*
 217 **************************************************************************
 218 **************************************************************************
 219 */
 220
 221 static int
 222 arcmsr_open(struct dev_open_args *ap)
 223 {
 224         cdev_t dev = ap->a_head.a_dev;
 225         struct AdapterControlBlock *acb=dev->si_drv1;
 226
 227         if(acb==NULL) {
 228                 return ENXIO;
 229         }
 230         return 0;
 231 }
 232
 233 /*
 234 **************************************************************************
 235 **************************************************************************
 236 */
 237
 238 static int
 239 arcmsr_close(struct dev_close_args *ap)
 240 {
 241         cdev_t dev = ap->a_head.a_dev;
 242         struct AdapterControlBlock *acb=dev->si_drv1;
 243
 244         if(acb==NULL) {
 245                 return ENXIO;
 246         }
 247         return 0;
 248 }
 249
 250 /*
 251 **************************************************************************
 252 **************************************************************************
 253 */
 254
 255 static int
 256 arcmsr_ioctl(struct dev_ioctl_args *ap)
 257 {
 258         cdev_t dev = ap->a_head.a_dev;
 259         u_long ioctl_cmd = ap->a_cmd;
 260         caddr_t arg = ap->a_data;
 261         struct AdapterControlBlock *acb=dev->si_drv1;
 262
 263         if(acb==NULL) {
 264                 return ENXIO;
 265         }
 266         return(arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 267 }
 268
 269 /*
 270 **********************************************************************
 271 **********************************************************************
 272 */
 273 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 274 {
 275         u_int32_t intmask_org=0;
 276
 277         switch (acb->adapter_type) {
 278         case ACB_ADAPTER_TYPE_A: {
 279                         /* disable all outbound interrupt */
 280                         intmask_org=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 281                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 282                 }
 283                 break;
 284         case ACB_ADAPTER_TYPE_B: {
 285                         /* disable all outbound interrupt */
 286                         intmask_org=CHIP_REG_READ32(HBB_DOORBELL,
 287                         0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 288                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
 289                 }
 290                 break;
 291         case ACB_ADAPTER_TYPE_C: {
 292                         /* disable all outbound interrupt */
 293                         intmask_org=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)  ; /* disable outbound message0 int */
 294                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 295                 }
 296                 break;
 297         }
 298         return(intmask_org);
 299 }
 300 /*
 301 **********************************************************************
 302 **********************************************************************
 303 */
 304 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 305 {
 306         u_int32_t mask;
 307
 308         switch (acb->adapter_type) {
 309         case ACB_ADAPTER_TYPE_A: {
 310                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 311                         mask=~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 312                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 313                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 314                 }
 315                 break;
 316         case ACB_ADAPTER_TYPE_B: {
 317                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 318                         mask=(ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 319                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 320                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 321                 }
 322                 break;
 323         case ACB_ADAPTER_TYPE_C: {
 324                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 325                         mask=~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 326                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 327                         acb->outbound_int_enable= ~(intmask_org & mask) & 0x0000000f;
 328                 }
 329                 break;
 330         }
 331         return;
 332 }
 333 /*
 334 **********************************************************************
 335 **********************************************************************
 336 */
 337 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 338 {
 339         u_int32_t Index;
 340         u_int8_t Retries=0x00;
 341
 342         do {
 343                 for(Index=0; Index < 100; Index++) {
 344                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 345                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 346                                 return TRUE;
 347                         }
 348                         UDELAY(10000);
 349                 }/*max 1 seconds*/
 350         }while(Retries++ < 20);/*max 20 sec*/
 351         return FALSE;
 352 }
 353 /*
 354 **********************************************************************
 355 **********************************************************************
 356 */
 357 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 358 {
 359         u_int32_t Index;
 360         u_int8_t Retries=0x00;
 361
 362         do {
 363                 for(Index=0; Index < 100; Index++) {
 364                         if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 365                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 366                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 367                                 return TRUE;
 368                         }
 369                         UDELAY(10000);
 370                 }/*max 1 seconds*/
 371         }while(Retries++ < 20);/*max 20 sec*/
 372         return FALSE;
 373 }
 374 /*
 375 **********************************************************************
 376 **********************************************************************
 377 */
 378 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 379 {
 380         u_int32_t Index;
 381         u_int8_t Retries=0x00;
 382
 383         do {
 384                 for(Index=0; Index < 100; Index++) {
 385                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 386                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 387                                 return TRUE;
 388                         }
 389                         UDELAY(10000);
 390                 }/*max 1 seconds*/
 391         }while(Retries++ < 20);/*max 20 sec*/
 392         return FALSE;
 393 }
 394 /*
 395 ************************************************************************
 396 ************************************************************************
 397 */
 398 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 399 {
 400         int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
 401
 402         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 403         do {
 404                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 405                         break;
 406                 } else {
 407                         retry_count--;
 408                 }
 409         }while(retry_count!=0);
 410         return;
 411 }
 412 /*
 413 ************************************************************************
 414 ************************************************************************
 415 */
 416 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 417 {
 418         int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
 419
 420         CHIP_REG_WRITE32(HBB_DOORBELL,
 421         0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 422         do {
 423                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 424                         break;
 425                 } else {
 426                         retry_count--;
 427                 }
 428         }while(retry_count!=0);
 429         return;
 430 }
 431 /*
 432 ************************************************************************
 433 ************************************************************************
 434 */
 435 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 436 {
 437         int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
 438
 439         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 440         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 441         do {
 442                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 443                         break;
 444                 } else {
 445                         retry_count--;
 446                 }
 447         }while(retry_count!=0);
 448         return;
 449 }
 450 /*
 451 ************************************************************************
 452 ************************************************************************
 453 */
 454 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 455 {
 456         switch (acb->adapter_type) {
 457         case ACB_ADAPTER_TYPE_A: {
 458                         arcmsr_flush_hba_cache(acb);
 459                 }
 460                 break;
 461         case ACB_ADAPTER_TYPE_B: {
 462                         arcmsr_flush_hbb_cache(acb);
 463                 }
 464                 break;
 465         case ACB_ADAPTER_TYPE_C: {
 466                         arcmsr_flush_hbc_cache(acb);
 467                 }
 468                 break;
 469         }
 470         return;
 471 }
 472 /*
 473 *******************************************************************************
 474 *******************************************************************************
 475 */
 476 static int arcmsr_suspend(device_t dev)
 477 {
 478         struct AdapterControlBlock      *acb = device_get_softc(dev);
 479
 480         /* flush controller */
 481         arcmsr_iop_parking(acb);
 482         /* disable all outbound interrupt */
 483         arcmsr_disable_allintr(acb);
 484         return(0);
 485 }
 486 /*
 487 *******************************************************************************
 488 *******************************************************************************
 489 */
 490 static int arcmsr_resume(device_t dev)
 491 {
 492         struct AdapterControlBlock      *acb = device_get_softc(dev);
 493
 494         arcmsr_iop_init(acb);
 495         return(0);
 496 }
 497 /*
 498 *********************************************************************************
 499 *********************************************************************************
 500 */
 501 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 502 {
 503         struct AdapterControlBlock *acb;
 504         u_int8_t target_id, target_lun;
 505         struct cam_sim * sim;
 506
 507         sim=(struct cam_sim *) cb_arg;
 508         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 509         switch (code) {
 510         case AC_LOST_DEVICE:
 511                 target_id=xpt_path_target_id(path);
 512                 target_lun=xpt_path_lun_id(path);
 513                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 514                         break;
 515                 }
 516                 kprintf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 517                 break;
 518         default:
 519                 break;
 520         }
 521 }
 522 /*
 523 **********************************************************************
 524 **********************************************************************
 525 */
 526 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 527 {
 528         struct AdapterControlBlock *acb=srb->acb;
 529         union ccb * pccb=srb->pccb;
 530
 531         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 532                 bus_dmasync_op_t op;
 533
 534                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 535                         op = BUS_DMASYNC_POSTREAD;
 536                 } else {
 537                         op = BUS_DMASYNC_POSTWRITE;
 538                 }
 539                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 540                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 541         }
 542         if(stand_flag==1) {
 543                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 544                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 545                 acb->srboutstandingcount < ARCMSR_RELEASE_SIMQ_LEVEL)) {
 546                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 547                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 548                 }
 549         }
 550         srb->startdone=ARCMSR_SRB_DONE;
 551         srb->srb_flags=0;
 552         acb->srbworkingQ[acb->workingsrb_doneindex]=srb;
 553         acb->workingsrb_doneindex++;
 554         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
 555         xpt_done(pccb);
 556         return;
 557 }
 558 /*
 559 **********************************************************************
 560 **********************************************************************
 561 */
 562 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 563 {
 564         union ccb * pccb=srb->pccb;
 565
 566         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 567         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 568         if(&pccb->csio.sense_data) {
 569                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 570                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 571                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 572                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 573                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 574         }
 575         return;
 576 }
 577 /*
 578 *********************************************************************
 579 *********************************************************************
 580 */
 581 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 582 {
 583         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 584         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 585                 kprintf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 586         }
 587         return;
 588 }
 589 /*
 590 *********************************************************************
 591 *********************************************************************
 592 */
 593 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 594 {
 595         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 596         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 597                 kprintf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 598         }
 599         return;
 600 }
 601 /*
 602 *********************************************************************
 603 *********************************************************************
 604 */
 605 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 606 {
 607         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 608         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 609         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 610                 kprintf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 611         }
 612         return;
 613 }
 614 /*
 615 *********************************************************************
 616 *********************************************************************
 617 */
 618 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 619 {
 620         switch (acb->adapter_type) {
 621         case ACB_ADAPTER_TYPE_A: {
 622                         arcmsr_abort_hba_allcmd(acb);
 623                 }
 624                 break;
 625         case ACB_ADAPTER_TYPE_B: {
 626                         arcmsr_abort_hbb_allcmd(acb);
 627                 }
 628                 break;
 629         case ACB_ADAPTER_TYPE_C: {
 630                         arcmsr_abort_hbc_allcmd(acb);
 631                 }
 632                 break;
 633         }
 634         return;
 635 }
 636 /*
 637 **************************************************************************
 638 **************************************************************************
 639 */
 640 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 641 {
 642         int target, lun;
 643
 644         target=srb->pccb->ccb_h.target_id;
 645         lun=srb->pccb->ccb_h.target_lun;
 646         if(error == FALSE) {
 647                 if(acb->devstate[target][lun]==ARECA_RAID_GONE) {
 648                         acb->devstate[target][lun]=ARECA_RAID_GOOD;
 649                 }
 650                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 651                 arcmsr_srb_complete(srb, 1);
 652         } else {
 653                 switch(srb->arcmsr_cdb.DeviceStatus) {
 654                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 655                                 if(acb->devstate[target][lun]==ARECA_RAID_GOOD) {
 656                                         kprintf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 657                                 }
 658                                 acb->devstate[target][lun]=ARECA_RAID_GONE;
 659                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 660                                 arcmsr_srb_complete(srb, 1);
 661                         }
 662                         break;
 663                 case ARCMSR_DEV_ABORTED:
 664                 case ARCMSR_DEV_INIT_FAIL: {
 665                                 acb->devstate[target][lun]=ARECA_RAID_GONE;
 666                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 667                                 arcmsr_srb_complete(srb, 1);
 668                         }
 669                         break;
 670                 case SCSISTAT_CHECK_CONDITION: {
 671                                 acb->devstate[target][lun]=ARECA_RAID_GOOD;
 672                                 arcmsr_report_sense_info(srb);
 673                                 arcmsr_srb_complete(srb, 1);
 674                         }
 675                         break;
 676                 default:
 677                         kprintf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n"
 678                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 679                         acb->devstate[target][lun]=ARECA_RAID_GONE;
 680                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 681                         /*unknow error or crc error just for retry*/
 682                         arcmsr_srb_complete(srb, 1);
 683                         break;
 684                 }
 685         }
 686         return;
 687 }
 688 /*
 689 **************************************************************************
 690 **************************************************************************
 691 */
 692 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 693 {
 694         struct CommandControlBlock *srb;
 695
 696         /* check if command done with no error*/
 697         switch (acb->adapter_type) {
 698         case ACB_ADAPTER_TYPE_C:
 699                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFF0));/*frame must be 32 bytes aligned*/
 700                 break;
 701         case ACB_ADAPTER_TYPE_A:
 702         case ACB_ADAPTER_TYPE_B:
 703         default:
 704                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 705                 break;
 706         }
 707         if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) {
 708                 if(srb->startdone==ARCMSR_SRB_ABORTED) {
 709                         kprintf("arcmsr%d: srb='%p' isr got aborted command \n", acb->pci_unit, srb);
 710                         srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 711                         arcmsr_srb_complete(srb, 1);
 712                         return;
 713                 }
 714                 kprintf("arcmsr%d: isr get an illegal srb command done"
 715                         "acb='%p' srb='%p' srbacb='%p' startdone=0x%xsrboutstandingcount=%d \n",
 716                         acb->pci_unit, acb, srb, srb->acb,srb->startdone, acb->srboutstandingcount);
 717                 return;
 718         }
 719         arcmsr_report_srb_state(acb, srb, error);
 720         return;
 721 }
 722 /*
 723 **********************************************************************
 724 **********************************************************************
 725 */
 726 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 727 {
 728         int i=0;
 729         u_int32_t flag_srb;
 730         u_int16_t error;
 731
 732         switch (acb->adapter_type) {
 733         case ACB_ADAPTER_TYPE_A: {
 734                         u_int32_t outbound_intstatus;
 735
 736                         /*clear and abort all outbound posted Q*/
 737                         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 738                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 739                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 740                 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 741                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 742                         }
 743                 }
 744                 break;
 745         case ACB_ADAPTER_TYPE_B: {
 746                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 747
 748                         /*clear all outbound posted Q*/
 749                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 750                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 751                                 if((flag_srb=phbbmu->done_qbuffer[i])!=0) {
 752                                         phbbmu->done_qbuffer[i]=0;
 753                         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 754                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 755                                 }
 756                                 phbbmu->post_qbuffer[i]=0;
 757                         }/*drain reply FIFO*/
 758                         phbbmu->doneq_index=0;
 759                         phbbmu->postq_index=0;
 760                 }
 761                 break;
 762         case ACB_ADAPTER_TYPE_C: {
 763
 764                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 765                                 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 766                 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
 767                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 768                         }
 769                 }
 770                 break;
 771         }
 772         return;
 773 }
 774 /*
 775 ****************************************************************************
 776 ****************************************************************************
 777 */
 778 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 779 {
 780         struct CommandControlBlock *srb;
 781         u_int32_t intmask_org;
 782         u_int32_t i=0;
 783
 784         if(acb->srboutstandingcount>0) {
 785                 /* disable all outbound interrupt */
 786                 intmask_org=arcmsr_disable_allintr(acb);
 787                 /*clear and abort all outbound posted Q*/
 788                 arcmsr_done4abort_postqueue(acb);
 789                 /* talk to iop 331 outstanding command aborted*/
 790                 arcmsr_abort_allcmd(acb);
 791                 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
 792                         srb=acb->psrb_pool[i];
 793                         if(srb->startdone==ARCMSR_SRB_START) {
 794                                 srb->startdone=ARCMSR_SRB_ABORTED;
 795                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 796                                 arcmsr_srb_complete(srb, 1);
 797                         }
 798                 }
 799                 /* enable all outbound interrupt */
 800                 arcmsr_enable_allintr(acb, intmask_org);
 801         }
 802         atomic_set_int(&acb->srboutstandingcount, 0);
 803         acb->workingsrb_doneindex=0;
 804         acb->workingsrb_startindex=0;
 805         return;
 806 }
 807 /*
 808 **********************************************************************
 809 **********************************************************************
 810 */
 811 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 812                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 813 {
 814         struct ARCMSR_CDB * arcmsr_cdb= &srb->arcmsr_cdb;
 815         u_int8_t * psge=(u_int8_t *)&arcmsr_cdb->u;
 816         u_int32_t address_lo, address_hi;
 817         union ccb * pccb=srb->pccb;
 818         struct ccb_scsiio * pcsio= &pccb->csio;
 819         u_int32_t arccdbsize=0x30;
 820
 821         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
 822         arcmsr_cdb->Bus=0;
 823         arcmsr_cdb->TargetID=pccb->ccb_h.target_id;
 824         arcmsr_cdb->LUN=pccb->ccb_h.target_lun;
 825         arcmsr_cdb->Function=1;
 826         arcmsr_cdb->CdbLength=(u_int8_t)pcsio->cdb_len;
 827         arcmsr_cdb->Context=0;
 828         bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
 829         if(nseg != 0) {
 830                 struct AdapterControlBlock *acb=srb->acb;
 831                 bus_dmasync_op_t op;
 832                 u_int32_t length, i, cdb_sgcount=0;
 833
 834                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 835                         op=BUS_DMASYNC_PREREAD;
 836                 } else {
 837                         op=BUS_DMASYNC_PREWRITE;
 838                         arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_WRITE;
 839                         srb->srb_flags|=SRB_FLAG_WRITE;
 840                 }
 841                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 842                 for(i=0;i<nseg;i++) {
 843                         /* Get the physical address of the current data pointer */
 844                         length=arcmsr_htole32(dm_segs[i].ds_len);
 845                         address_lo=arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
 846                         address_hi=arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
 847                         if(address_hi==0) {
 848                                 struct SG32ENTRY * pdma_sg=(struct SG32ENTRY *)psge;
 849                                 pdma_sg->address=address_lo;
 850                                 pdma_sg->length=length;
 851                                 psge += sizeof(struct SG32ENTRY);
 852                                 arccdbsize += sizeof(struct SG32ENTRY);
 853                         } else {
 854                                 u_int32_t sg64s_size=0, tmplength=length;
 855
 856                                 while(1) {
 857                                         u_int64_t span4G, length0;
 858                                         struct SG64ENTRY * pdma_sg=(struct SG64ENTRY *)psge;
 859
 860                                         span4G=(u_int64_t)address_lo + tmplength;
 861                                         pdma_sg->addresshigh=address_hi;
 862                                         pdma_sg->address=address_lo;
 863                                         if(span4G > 0x100000000) {
 864                                                 /*see if cross 4G boundary*/
 865                                                 length0=0x100000000-address_lo;
 866                                                 pdma_sg->length=(u_int32_t)length0|IS_SG64_ADDR;
 867                                                 address_hi=address_hi+1;
 868                                                 address_lo=0;
 869                                                 tmplength=tmplength-(u_int32_t)length0;
 870                                                 sg64s_size += sizeof(struct SG64ENTRY);
 871                                                 psge += sizeof(struct SG64ENTRY);
 872                                                 cdb_sgcount++;
 873                                         } else {
 874                                                 pdma_sg->length=tmplength|IS_SG64_ADDR;
 875                                                 sg64s_size += sizeof(struct SG64ENTRY);
 876                                                 psge += sizeof(struct SG64ENTRY);
 877                                                 break;
 878                                         }
 879                                 }
 880                                 arccdbsize += sg64s_size;
 881                         }
 882                         cdb_sgcount++;
 883                 }
 884                 arcmsr_cdb->sgcount=(u_int8_t)cdb_sgcount;
 885                 arcmsr_cdb->DataLength=pcsio->dxfer_len;
 886                 if( arccdbsize > 256) {
 887                         arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_SGL_BSIZE;
 888                 }
 889         } else {
 890                 arcmsr_cdb->DataLength = 0;
 891         }
 892     srb->arc_cdb_size=arccdbsize;
 893         return;
 894 }
 895 /*
 896 **************************************************************************
 897 **************************************************************************
 898 */
 899 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
 900 {
 901         u_int32_t cdb_shifted_phyaddr=(u_int32_t) srb->cdb_shifted_phyaddr;
 902         struct ARCMSR_CDB * arcmsr_cdb=(struct ARCMSR_CDB *)&srb->arcmsr_cdb;
 903
 904         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
 905         atomic_add_int(&acb->srboutstandingcount, 1);
 906         srb->startdone=ARCMSR_SRB_START;
 907
 908         switch (acb->adapter_type) {
 909         case ACB_ADAPTER_TYPE_A: {
 910                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
 911                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
 912                         } else {
 913                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr);
 914                         }
 915                 }
 916                 break;
 917         case ACB_ADAPTER_TYPE_B: {
 918                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 919                         int ending_index, index;
 920
 921                         index=phbbmu->postq_index;
 922                         ending_index=((index+1)%ARCMSR_MAX_HBB_POSTQUEUE);
 923                         phbbmu->post_qbuffer[ending_index]=0;
 924                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
 925                                 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
 926                         } else {
 927                                 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr;
 928                         }
 929                         index++;
 930                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
 931                         phbbmu->postq_index=index;
 932                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
 933                 }
 934                 break;
 935     case ACB_ADAPTER_TYPE_C:
 936         {
 937             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
 938
 939             arc_cdb_size=(srb->arc_cdb_size>0x300)?0x300:srb->arc_cdb_size;
 940             ccb_post_stamp=(cdb_shifted_phyaddr | ((arc_cdb_size-1) >> 6) | 1);
 941                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
 942             if(cdb_phyaddr_hi32)
 943             {
 944                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
 945                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
 946             }
 947             else
 948             {
 949                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
 950             }
 951         }
 952         break;
 953         }
 954         return;
 955 }
 956 /*
 957 ************************************************************************
 958 ************************************************************************
 959 */
 960 static struct QBUFFER * arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
 961 {
 962         struct QBUFFER *qbuffer=NULL;
 963
 964         switch (acb->adapter_type) {
 965         case ACB_ADAPTER_TYPE_A: {
 966                         struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu;
 967
 968                         qbuffer=(struct QBUFFER *)&phbamu->message_rbuffer;
 969                 }
 970                 break;
 971         case ACB_ADAPTER_TYPE_B: {
 972                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 973
 974                         qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
 975                 }
 976                 break;
 977         case ACB_ADAPTER_TYPE_C: {
 978                         struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu;
 979
 980                         qbuffer=(struct QBUFFER *)&phbcmu->message_rbuffer;
 981                 }
 982                 break;
 983         }
 984         return(qbuffer);
 985 }
 986 /*
 987 ************************************************************************
 988 ************************************************************************
 989 */
 990 static struct QBUFFER * arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
 991 {
 992         struct QBUFFER *qbuffer=NULL;
 993
 994         switch (acb->adapter_type) {
 995         case ACB_ADAPTER_TYPE_A: {
 996                         struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu;
 997
 998                         qbuffer=(struct QBUFFER *)&phbamu->message_wbuffer;
 999                 }
1000                 break;
1001         case ACB_ADAPTER_TYPE_B: {
1002                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
1003
1004                         qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1005                 }
1006                 break;
1007         case ACB_ADAPTER_TYPE_C: {
1008                         struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu;
1009
1010                         qbuffer=(struct QBUFFER *)&phbcmu->message_wbuffer;
1011                 }
1012                 break;
1013         }
1014         return(qbuffer);
1015 }
1016 /*
1017 **************************************************************************
1018 **************************************************************************
1019 */
1020 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1021 {
1022         switch (acb->adapter_type) {
1023         case ACB_ADAPTER_TYPE_A: {
1024                         /* let IOP know data has been read */
1025                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1026                 }
1027                 break;
1028         case ACB_ADAPTER_TYPE_B: {
1029                         /* let IOP know data has been read */
1030                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1031                 }
1032                 break;
1033         case ACB_ADAPTER_TYPE_C: {
1034                         /* let IOP know data has been read */
1035                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1036                 }
1037         }
1038         return;
1039 }
1040 /*
1041 **************************************************************************
1042 **************************************************************************
1043 */
1044 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1045 {
1046         switch (acb->adapter_type) {
1047         case ACB_ADAPTER_TYPE_A: {
1048                         /*
1049                         ** push inbound doorbell tell iop, driver data write ok
1050                         ** and wait reply on next hwinterrupt for next Qbuffer post
1051                         */
1052                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1053                 }
1054                 break;
1055         case ACB_ADAPTER_TYPE_B: {
1056                         /*
1057                         ** push inbound doorbell tell iop, driver data write ok
1058                         ** and wait reply on next hwinterrupt for next Qbuffer post
1059                         */
1060                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1061                 }
1062                 break;
1063         case ACB_ADAPTER_TYPE_C: {
1064                         /*
1065                         ** push inbound doorbell tell iop, driver data write ok
1066                         ** and wait reply on next hwinterrupt for next Qbuffer post
1067                         */
1068                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1069                 }
1070                 break;
1071         }
1072 }
1073 /*
1074 **********************************************************************
1075 **********************************************************************
1076 */
1077 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
1078 {
1079         u_int8_t *pQbuffer;
1080         struct QBUFFER *pwbuffer;
1081         u_int8_t * iop_data;
1082         int32_t allxfer_len=0;
1083
1084         pwbuffer=arcmsr_get_iop_wqbuffer(acb);
1085         iop_data=(u_int8_t *)pwbuffer->data;
1086         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1087                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1088                 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex)
1089                         && (allxfer_len<124)) {
1090                         pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex];
1091                         memcpy(iop_data, pQbuffer, 1);
1092                         acb->wqbuf_firstindex++;
1093                         acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */
1094                         iop_data++;
1095                         allxfer_len++;
1096                 }
1097                 pwbuffer->data_len=allxfer_len;
1098                 /*
1099                 ** push inbound doorbell and wait reply at hwinterrupt routine for next Qbuffer post
1100                 */
1101                 arcmsr_iop_message_wrote(acb);
1102         }
1103         return;
1104 }
1105 /*
1106 ************************************************************************
1107 ************************************************************************
1108 */
1109 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1110 {
1111         acb->acb_flags &=~ACB_F_MSG_START_BGRB;
1112         CHIP_REG_WRITE32(HBA_MessageUnit,
1113         0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1114         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1115                 kprintf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1116                         , acb->pci_unit);
1117         }
1118         return;
1119 }
1120 /*
1121 ************************************************************************
1122 ************************************************************************
1123 */
1124 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1125 {
1126         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1127         CHIP_REG_WRITE32(HBB_DOORBELL,
1128         0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1129         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1130                 kprintf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1131                         , acb->pci_unit);
1132         }
1133         return;
1134 }
1135 /*
1136 ************************************************************************
1137 ************************************************************************
1138 */
1139 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1140 {
1141         acb->acb_flags &=~ACB_F_MSG_START_BGRB;
1142         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1143         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1144         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1145                 kprintf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1146         }
1147         return;
1148 }
1149 /*
1150 ************************************************************************
1151 ************************************************************************
1152 */
1153 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1154 {
1155         switch (acb->adapter_type) {
1156         case ACB_ADAPTER_TYPE_A: {
1157                         arcmsr_stop_hba_bgrb(acb);
1158                 }
1159                 break;
1160         case ACB_ADAPTER_TYPE_B: {
1161                         arcmsr_stop_hbb_bgrb(acb);
1162                 }
1163                 break;
1164         case ACB_ADAPTER_TYPE_C: {
1165                         arcmsr_stop_hbc_bgrb(acb);
1166                 }
1167                 break;
1168         }
1169         return;
1170 }
1171 /*
1172 ************************************************************************
1173 ************************************************************************
1174 */
1175 static void arcmsr_poll(struct cam_sim * psim)
1176 {
1177         struct AdapterControlBlock *acb;
1178
1179         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1180         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1181         arcmsr_interrupt(acb);
1182         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1183         return;
1184 }
1185 /*
1186 **************************************************************************
1187 **************************************************************************
1188 */
1189 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1190 {
1191         struct QBUFFER *prbuffer;
1192         u_int8_t *pQbuffer;
1193         u_int8_t *iop_data;
1194         int my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
1195
1196         /*check this iop data if overflow my rqbuffer*/
1197         rqbuf_lastindex=acb->rqbuf_lastindex;
1198         rqbuf_firstindex=acb->rqbuf_firstindex;
1199         prbuffer=arcmsr_get_iop_rqbuffer(acb);
1200         iop_data=(u_int8_t *)prbuffer->data;
1201         iop_len=prbuffer->data_len;
1202         my_empty_len=(rqbuf_firstindex-rqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1);
1203         if(my_empty_len>=iop_len) {
1204                 while(iop_len > 0) {
1205                         pQbuffer=&acb->rqbuffer[rqbuf_lastindex];
1206                         memcpy(pQbuffer, iop_data, 1);
1207                         rqbuf_lastindex++;
1208                         rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;/*if last index number set it to 0 */
1209                         iop_data++;
1210                         iop_len--;
1211                 }
1212                 acb->rqbuf_lastindex=rqbuf_lastindex;
1213                 arcmsr_iop_message_read(acb);
1214                 /*signature, let IOP know data has been read */
1215         } else {
1216                 acb->acb_flags|=ACB_F_IOPDATA_OVERFLOW;
1217         }
1218         return;
1219 }
1220 /*
1221 **************************************************************************
1222 **************************************************************************
1223 */
1224 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1225 {
1226         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1227         /*
1228         *****************************************************************
1229         **   check if there are any mail packages from user space program
1230         **   in my post bag, now is the time to send them into Areca's firmware
1231         *****************************************************************
1232         */
1233         if(acb->wqbuf_firstindex!=acb->wqbuf_lastindex) {
1234                 u_int8_t *pQbuffer;
1235                 struct QBUFFER *pwbuffer;
1236                 u_int8_t *iop_data;
1237                 int allxfer_len=0;
1238
1239                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1240                 pwbuffer=arcmsr_get_iop_wqbuffer(acb);
1241                 iop_data=(u_int8_t *)pwbuffer->data;
1242                 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex)
1243                         && (allxfer_len<124)) {
1244                         pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex];
1245                         memcpy(iop_data, pQbuffer, 1);
1246                         acb->wqbuf_firstindex++;
1247                         acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */
1248                         iop_data++;
1249                         allxfer_len++;
1250                 }
1251                 pwbuffer->data_len=allxfer_len;
1252                 /*
1253                 ** push inbound doorbell tell iop driver data write ok
1254                 ** and wait reply on next hwinterrupt for next Qbuffer post
1255                 */
1256                 arcmsr_iop_message_wrote(acb);
1257         }
1258         if(acb->wqbuf_firstindex==acb->wqbuf_lastindex) {
1259                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1260         }
1261         return;
1262 }
1263
1264 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1265 {
1266 /*
1267         if (ccb->ccb_h.status != CAM_REQ_CMP)
1268                 kprintf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x, failure status=%x\n",ccb->ccb_h.target_id,ccb->ccb_h.target_lun,ccb->ccb_h.status);
1269         else
1270                 kprintf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1271 */
1272         xpt_free_path(ccb->ccb_h.path);
1273 }
1274
1275 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1276 {
1277         struct cam_path     *path;
1278         union ccb            ccb;
1279
1280         if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1281                 return;
1282 /*      kprintf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1283         bzero(&ccb, sizeof(union ccb));
1284         xpt_setup_ccb(&ccb.ccb_h, path, 5);
1285         ccb.ccb_h.func_code = XPT_SCAN_LUN;
1286         ccb.ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1287         ccb.crcn.flags = CAM_FLAG_NONE;
1288         xpt_action(&ccb);
1289         return;
1290 }
1291
1292
1293 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1294 {
1295         struct CommandControlBlock *srb;
1296         u_int32_t intmask_org;
1297         int i;
1298
1299         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1300         /* disable all outbound interrupts */
1301         intmask_org = arcmsr_disable_allintr(acb);
1302         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1303         {
1304                 srb = acb->psrb_pool[i];
1305                 if (srb->startdone == ARCMSR_SRB_START)
1306                 {
1307                 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1308             {
1309                         srb->startdone = ARCMSR_SRB_ABORTED;
1310                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1311                         arcmsr_srb_complete(srb, 1);
1312                 }
1313                 }
1314         }
1315         /* enable outbound Post Queue, outbound doorbell Interrupt */
1316         arcmsr_enable_allintr(acb, intmask_org);
1317         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1318 }
1319
1320
1321 /*
1322 **************************************************************************
1323 **************************************************************************
1324 */
1325 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1326         u_int32_t       devicemap;
1327         u_int32_t       target, lun;
1328     u_int32_t   deviceMapCurrent[4]={0};
1329     u_int8_t    *pDevMap;
1330
1331         switch (acb->adapter_type) {
1332         case ACB_ADAPTER_TYPE_A:
1333                         devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1334                         for (target= 0; target < 4; target++)
1335                         {
1336                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1337                 devicemap += 4;
1338                         }
1339                         break;
1340
1341         case ACB_ADAPTER_TYPE_B:
1342                         devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1343                         for (target= 0; target < 4; target++)
1344                         {
1345                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1346                 devicemap += 4;
1347                         }
1348                         break;
1349
1350         case ACB_ADAPTER_TYPE_C:
1351                         devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1352                         for (target= 0; target < 4; target++)
1353                         {
1354                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1355                 devicemap += 4;
1356                         }
1357                         break;
1358         }
1359                 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1360                 {
1361                         acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1362                 }
1363                 /*
1364                 ** adapter posted CONFIG message
1365                 ** copy the new map, note if there are differences with the current map
1366                 */
1367                 pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1368                 for (target= 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1369                 {
1370                         if (*pDevMap != acb->device_map[target])
1371                         {
1372                 u_int8_t difference, bit_check;
1373
1374                 difference= *pDevMap ^ acb->device_map[target];
1375                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1376                 {
1377                     bit_check=(1 << lun);                                               /*check bit from 0....31*/
1378                     if(difference & bit_check)
1379                     {
1380                         if(acb->device_map[target] & bit_check)
1381                         {/* unit departed */
1382                                                         kprintf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1383                                                         arcmsr_abort_dr_ccbs(acb, target, lun);
1384                                 arcmsr_rescan_lun(acb, target, lun);
1385                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1386                         }
1387                         else
1388                         {/* unit arrived */
1389                                                         kprintf("arcmsr_dr_handle: Target=%x, lun=%x, ARRIVING!!!\n",target,lun);
1390                                 arcmsr_rescan_lun(acb, target, lun);
1391                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1392                         }
1393                     }
1394                 }
1395 /*                              kprintf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1396                                 acb->device_map[target]= *pDevMap;
1397                         }
1398                         pDevMap++;
1399                 }
1400 }
1401 /*
1402 **************************************************************************
1403 **************************************************************************
1404 */
1405 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1406         u_int32_t outbound_message;
1407
1408         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1409         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1410         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1411                 arcmsr_dr_handle( acb );
1412 }
1413 /*
1414 **************************************************************************
1415 **************************************************************************
1416 */
1417 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1418         u_int32_t outbound_message;
1419
1420         /* clear interrupts */
1421         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1422         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1423         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1424                 arcmsr_dr_handle( acb );
1425 }
1426 /*
1427 **************************************************************************
1428 **************************************************************************
1429 */
1430 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1431         u_int32_t outbound_message;
1432
1433         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1434         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1435         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1436                 arcmsr_dr_handle( acb );
1437 }
1438 /*
1439 **************************************************************************
1440 **************************************************************************
1441 */
1442 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1443 {
1444         u_int32_t outbound_doorbell;
1445
1446         /*
1447         *******************************************************************
1448         **  Maybe here we need to check wrqbuffer_lock is lock or not
1449         **  DOORBELL: din! don!
1450         **  check if there are any mail need to pack from firmware
1451         *******************************************************************
1452         */
1453         outbound_doorbell=CHIP_REG_READ32(HBA_MessageUnit,
1454         0, outbound_doorbell);
1455         CHIP_REG_WRITE32(HBA_MessageUnit,
1456         0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
1457         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1458                 arcmsr_iop2drv_data_wrote_handle(acb);
1459         }
1460         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1461                 arcmsr_iop2drv_data_read_handle(acb);
1462         }
1463         return;
1464 }
1465 /*
1466 **************************************************************************
1467 **************************************************************************
1468 */
1469 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1470 {
1471         u_int32_t outbound_doorbell;
1472
1473         /*
1474         *******************************************************************
1475         **  Maybe here we need to check wrqbuffer_lock is lock or not
1476         **  DOORBELL: din! don!
1477         **  check if there are any mail need to pack from firmware
1478         *******************************************************************
1479         */
1480         outbound_doorbell=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1481         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
1482         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1483                 arcmsr_iop2drv_data_wrote_handle(acb);
1484         }
1485         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1486                 arcmsr_iop2drv_data_read_handle(acb);
1487         }
1488         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1489                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1490         }
1491         return;
1492 }
1493 /*
1494 **************************************************************************
1495 **************************************************************************
1496 */
1497 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1498 {
1499         u_int32_t flag_srb;
1500         u_int16_t error;
1501
1502         /*
1503         *****************************************************************************
1504         **               areca cdb command done
1505         *****************************************************************************
1506         */
1507         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1508                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1509         while((flag_srb=CHIP_REG_READ32(HBA_MessageUnit,
1510                 0, outbound_queueport)) != 0xFFFFFFFF) {
1511                 /* check if command done with no error*/
1512         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1513                 arcmsr_drain_donequeue(acb, flag_srb, error);
1514         }       /*drain reply FIFO*/
1515         return;
1516 }
1517 /*
1518 **************************************************************************
1519 **************************************************************************
1520 */
1521 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1522 {
1523         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
1524         u_int32_t flag_srb;
1525         int index;
1526         u_int16_t error;
1527
1528         /*
1529         *****************************************************************************
1530         **               areca cdb command done
1531         *****************************************************************************
1532         */
1533         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1534                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1535         index=phbbmu->doneq_index;
1536         while((flag_srb=phbbmu->done_qbuffer[index]) != 0) {
1537                 phbbmu->done_qbuffer[index]=0;
1538                 index++;
1539                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1540                 phbbmu->doneq_index=index;
1541                 /* check if command done with no error*/
1542         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1543                 arcmsr_drain_donequeue(acb, flag_srb, error);
1544         }       /*drain reply FIFO*/
1545         return;
1546 }
1547 /*
1548 **************************************************************************
1549 **************************************************************************
1550 */
1551 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1552 {
1553         u_int32_t flag_srb,throttling=0;
1554         u_int16_t error;
1555
1556         /*
1557         *****************************************************************************
1558         **               areca cdb command done
1559         *****************************************************************************
1560         */
1561         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1562
1563         while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1564
1565                 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1566                 /* check if command done with no error*/
1567         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1568                 arcmsr_drain_donequeue(acb, flag_srb, error);
1569         if(throttling==ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1570             CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1571             break;
1572         }
1573         throttling++;
1574         }       /*drain reply FIFO*/
1575         return;
1576 }
1577 /*
1578 **********************************************************************
1579 **********************************************************************
1580 */
1581 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
1582 {
1583         u_int32_t outbound_intstatus;
1584         /*
1585         *********************************************
1586         **   check outbound intstatus
1587         *********************************************
1588         */
1589         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
1590         if(!outbound_intstatus) {
1591                 /*it must be share irq*/
1592                 return;
1593         }
1594         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
1595         /* MU doorbell interrupts*/
1596         if(outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
1597                 arcmsr_hba_doorbell_isr(acb);
1598         }
1599         /* MU post queue interrupts*/
1600         if(outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
1601                 arcmsr_hba_postqueue_isr(acb);
1602         }
1603         if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
1604                 arcmsr_hba_message_isr(acb);
1605         }
1606         return;
1607 }
1608 /*
1609 **********************************************************************
1610 **********************************************************************
1611 */
1612 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
1613 {
1614         u_int32_t outbound_doorbell;
1615         /*
1616         *********************************************
1617         **   check outbound intstatus
1618         *********************************************
1619         */
1620         outbound_doorbell=CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
1621         if(!outbound_doorbell) {
1622                 /*it must be share irq*/
1623                 return;
1624         }
1625         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
1626         CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
1627         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
1628         /* MU ioctl transfer doorbell interrupts*/
1629         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
1630                 arcmsr_iop2drv_data_wrote_handle(acb);
1631         }
1632         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
1633                 arcmsr_iop2drv_data_read_handle(acb);
1634         }
1635         /* MU post queue interrupts*/
1636         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
1637                 arcmsr_hbb_postqueue_isr(acb);
1638         }
1639         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
1640                 arcmsr_hbb_message_isr(acb);
1641         }
1642         return;
1643 }
1644 /*
1645 **********************************************************************
1646 **********************************************************************
1647 */
1648 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
1649 {
1650         u_int32_t host_interrupt_status;
1651         /*
1652         *********************************************
1653         **   check outbound intstatus
1654         *********************************************
1655         */
1656         host_interrupt_status=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
1657         if(!host_interrupt_status) {
1658                 /*it must be share irq*/
1659                 return;
1660         }
1661         /* MU doorbell interrupts*/
1662         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
1663                 arcmsr_hbc_doorbell_isr(acb);
1664         }
1665         /* MU post queue interrupts*/
1666         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1667                 arcmsr_hbc_postqueue_isr(acb);
1668         }
1669         return;
1670 }
1671 /*
1672 ******************************************************************************
1673 ******************************************************************************
1674 */
1675 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
1676 {
1677         switch (acb->adapter_type) {
1678         case ACB_ADAPTER_TYPE_A:
1679                 arcmsr_handle_hba_isr(acb);
1680                 break;
1681         case ACB_ADAPTER_TYPE_B:
1682                 arcmsr_handle_hbb_isr(acb);
1683                 break;
1684         case ACB_ADAPTER_TYPE_C:
1685                 arcmsr_handle_hbc_isr(acb);
1686                 break;
1687         default:
1688                 kprintf("arcmsr%d: interrupt service,"
1689                 " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type);
1690                 break;
1691         }
1692         return;
1693 }
1694 /*
1695 **********************************************************************
1696 **********************************************************************
1697 */
1698 static void arcmsr_intr_handler(void *arg)
1699 {
1700         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)arg;
1701
1702         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1703         arcmsr_interrupt(acb);
1704         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1705 }
1706 /*
1707 ******************************************************************************
1708 ******************************************************************************
1709 */
1710 static void     arcmsr_polling_devmap(void* arg)
1711 {
1712         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
1713         switch (acb->adapter_type) {
1714         case ACB_ADAPTER_TYPE_A:
1715                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
1716                 break;
1717
1718         case ACB_ADAPTER_TYPE_B:
1719                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
1720                 break;
1721
1722         case ACB_ADAPTER_TYPE_C:
1723                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
1724                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1725                 break;
1726         }
1727
1728         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
1729         {
1730                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
1731         }
1732 }
1733
1734 /*
1735 *******************************************************************************
1736 **
1737 *******************************************************************************
1738 */
1739 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
1740 {
1741         u_int32_t intmask_org;
1742
1743         if(acb!=NULL) {
1744                 /* stop adapter background rebuild */
1745                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
1746                         intmask_org = arcmsr_disable_allintr(acb);
1747                         arcmsr_stop_adapter_bgrb(acb);
1748                         arcmsr_flush_adapter_cache(acb);
1749                         arcmsr_enable_allintr(acb, intmask_org);
1750                 }
1751         }
1752 }
1753 /*
1754 ***********************************************************************
1755 **
1756 ************************************************************************
1757 */
1758 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
1759 {
1760         struct CMD_MESSAGE_FIELD * pcmdmessagefld;
1761         u_int32_t retvalue=EINVAL;
1762
1763         pcmdmessagefld=(struct CMD_MESSAGE_FIELD *) arg;
1764         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
1765                 return retvalue;
1766         }
1767         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1768         switch(ioctl_cmd) {
1769         case ARCMSR_MESSAGE_READ_RQBUFFER: {
1770                         u_int8_t * pQbuffer;
1771                         u_int8_t * ptmpQbuffer=pcmdmessagefld->messagedatabuffer;
1772                         u_int32_t allxfer_len=0;
1773
1774                         while((acb->rqbuf_firstindex!=acb->rqbuf_lastindex)
1775                                 && (allxfer_len<1031)) {
1776                                 /*copy READ QBUFFER to srb*/
1777                                 pQbuffer= &acb->rqbuffer[acb->rqbuf_firstindex];
1778                                 memcpy(ptmpQbuffer, pQbuffer, 1);
1779                                 acb->rqbuf_firstindex++;
1780                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1781                                 /*if last index number set it to 0 */
1782                                 ptmpQbuffer++;
1783                                 allxfer_len++;
1784                         }
1785                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1786                                 struct QBUFFER * prbuffer;
1787                                 u_int8_t * iop_data;
1788                                 u_int32_t iop_len;
1789
1790                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1791                                 prbuffer=arcmsr_get_iop_rqbuffer(acb);
1792                                 iop_data=(u_int8_t *)prbuffer->data;
1793                                 iop_len=(u_int32_t)prbuffer->data_len;
1794                                 /*this iop data does no chance to make me overflow again here, so just do it*/
1795                                 while(iop_len>0) {
1796                                         pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex];
1797                                         memcpy(pQbuffer, iop_data, 1);
1798                                         acb->rqbuf_lastindex++;
1799                                         acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1800                                         /*if last index number set it to 0 */
1801                                         iop_data++;
1802                                         iop_len--;
1803                                 }
1804                                 arcmsr_iop_message_read(acb);
1805                                 /*signature, let IOP know data has been readed */
1806                         }
1807                         pcmdmessagefld->cmdmessage.Length=allxfer_len;
1808                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1809                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1810                 }
1811                 break;
1812         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
1813                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
1814                         u_int8_t * pQbuffer;
1815                         u_int8_t * ptmpuserbuffer=pcmdmessagefld->messagedatabuffer;
1816
1817                         user_len=pcmdmessagefld->cmdmessage.Length;
1818                         /*check if data xfer length of this request will overflow my array qbuffer */
1819                         wqbuf_lastindex=acb->wqbuf_lastindex;
1820                         wqbuf_firstindex=acb->wqbuf_firstindex;
1821                         if(wqbuf_lastindex!=wqbuf_firstindex) {
1822                                 arcmsr_post_ioctldata2iop(acb);
1823                                 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
1824                         } else {
1825                                 my_empty_len=(wqbuf_firstindex-wqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1);
1826                                 if(my_empty_len>=user_len) {
1827                                         while(user_len>0) {
1828                                                 /*copy srb data to wqbuffer*/
1829                                                 pQbuffer= &acb->wqbuffer[acb->wqbuf_lastindex];
1830                                                 memcpy(pQbuffer, ptmpuserbuffer, 1);
1831                                                 acb->wqbuf_lastindex++;
1832                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1833                                                 /*if last index number set it to 0 */
1834                                                 ptmpuserbuffer++;
1835                                                 user_len--;
1836                                         }
1837                                         /*post fist Qbuffer*/
1838                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
1839                                                 acb->acb_flags &=~ACB_F_MESSAGE_WQBUFFER_CLEARED;
1840                                                 arcmsr_post_ioctldata2iop(acb);
1841                                         }
1842                                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1843                                 } else {
1844                                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
1845                                 }
1846                         }
1847                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1848                 }
1849                 break;
1850         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1851                         u_int8_t * pQbuffer=acb->rqbuffer;
1852
1853                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1854                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1855                                 arcmsr_iop_message_read(acb);
1856                                 /*signature, let IOP know data has been readed */
1857                         }
1858                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
1859                         acb->rqbuf_firstindex=0;
1860                         acb->rqbuf_lastindex=0;
1861                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1862                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1863                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1864                 }
1865                 break;
1866         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
1867                 {
1868                         u_int8_t * pQbuffer=acb->wqbuffer;
1869
1870                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1871                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1872                 arcmsr_iop_message_read(acb);
1873                                 /*signature, let IOP know data has been readed */
1874                         }
1875                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
1876                         acb->wqbuf_firstindex=0;
1877                         acb->wqbuf_lastindex=0;
1878                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1879                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1880                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1881                 }
1882                 break;
1883         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1884                         u_int8_t * pQbuffer;
1885
1886                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1887                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1888                 arcmsr_iop_message_read(acb);
1889                                 /*signature, let IOP know data has been readed */
1890                         }
1891                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
1892                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
1893                                         |ACB_F_MESSAGE_WQBUFFER_READ);
1894                         acb->rqbuf_firstindex=0;
1895                         acb->rqbuf_lastindex=0;
1896                         acb->wqbuf_firstindex=0;
1897                         acb->wqbuf_lastindex=0;
1898                         pQbuffer=acb->rqbuffer;
1899                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
1900                         pQbuffer=acb->wqbuffer;
1901                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
1902                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1903                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1904                 }
1905                 break;
1906         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
1907                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_3F;
1908                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1909                 }
1910                 break;
1911         case ARCMSR_MESSAGE_SAY_HELLO: {
1912                         u_int8_t * hello_string="Hello! I am ARCMSR";
1913                         u_int8_t * puserbuffer=(u_int8_t *)pcmdmessagefld->messagedatabuffer;
1914
1915                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
1916                                 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
1917                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1918                                 return ENOIOCTL;
1919                         }
1920                         pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
1921                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1922                 }
1923                 break;
1924         case ARCMSR_MESSAGE_SAY_GOODBYE: {
1925                         arcmsr_iop_parking(acb);
1926                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1927                 }
1928                 break;
1929         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
1930                         arcmsr_flush_adapter_cache(acb);
1931                         retvalue=ARCMSR_MESSAGE_SUCCESS;
1932                 }
1933                 break;
1934         }
1935         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1936         return retvalue;
1937 }
1938 /*
1939 **************************************************************************
1940 **************************************************************************
1941 */
1942 struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb)
1943 {
1944         struct CommandControlBlock *srb=NULL;
1945         u_int32_t workingsrb_startindex, workingsrb_doneindex;
1946
1947         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1948         workingsrb_doneindex=acb->workingsrb_doneindex;
1949         workingsrb_startindex=acb->workingsrb_startindex;
1950         srb=acb->srbworkingQ[workingsrb_startindex];
1951         workingsrb_startindex++;
1952         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
1953         if(workingsrb_doneindex!=workingsrb_startindex) {
1954                 acb->workingsrb_startindex=workingsrb_startindex;
1955         } else {
1956                 srb=NULL;
1957         }
1958         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1959         return(srb);
1960 }
1961 /*
1962 **************************************************************************
1963 **************************************************************************
1964 */
1965 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb)
1966 {
1967         struct CMD_MESSAGE_FIELD * pcmdmessagefld;
1968         int retvalue = 0, transfer_len = 0;
1969         char *buffer;
1970         u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
1971                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
1972                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
1973                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
1974                                         /* 4 bytes: Areca io control code */
1975         if((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
1976                 buffer = pccb->csio.data_ptr;
1977                 transfer_len = pccb->csio.dxfer_len;
1978         } else {
1979                 retvalue = ARCMSR_MESSAGE_FAIL;
1980                 goto message_out;
1981         }
1982         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
1983                 retvalue = ARCMSR_MESSAGE_FAIL;
1984                 goto message_out;
1985         }
1986         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
1987         switch(controlcode) {
1988         case ARCMSR_MESSAGE_READ_RQBUFFER: {
1989                         u_int8_t *pQbuffer;
1990                         u_int8_t *ptmpQbuffer=pcmdmessagefld->messagedatabuffer;
1991                         int32_t allxfer_len = 0;
1992
1993                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
1994                                 && (allxfer_len < 1031)) {
1995                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
1996                                 memcpy(ptmpQbuffer, pQbuffer, 1);
1997                                 acb->rqbuf_firstindex++;
1998                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1999                                 ptmpQbuffer++;
2000                                 allxfer_len++;
2001                         }
2002                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2003                                 struct QBUFFER  *prbuffer;
2004                                 u_int8_t  *iop_data;
2005                                 int32_t iop_len;
2006
2007                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2008                                 prbuffer=arcmsr_get_iop_rqbuffer(acb);
2009                                 iop_data = (u_int8_t *)prbuffer->data;
2010                                 iop_len =(u_int32_t)prbuffer->data_len;
2011                                 while (iop_len > 0) {
2012                                 pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex];
2013                                         memcpy(pQbuffer, iop_data, 1);
2014                                         acb->rqbuf_lastindex++;
2015                                         acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2016                                         iop_data++;
2017                                         iop_len--;
2018                                 }
2019                                 arcmsr_iop_message_read(acb);
2020                         }
2021                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2022                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2023                         retvalue=ARCMSR_MESSAGE_SUCCESS;
2024                 }
2025                 break;
2026         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2027                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2028                         u_int8_t *pQbuffer;
2029                         u_int8_t *ptmpuserbuffer=pcmdmessagefld->messagedatabuffer;
2030
2031                         user_len = pcmdmessagefld->cmdmessage.Length;
2032                         wqbuf_lastindex = acb->wqbuf_lastindex;
2033                         wqbuf_firstindex = acb->wqbuf_firstindex;
2034                         if (wqbuf_lastindex != wqbuf_firstindex) {
2035                                 arcmsr_post_ioctldata2iop(acb);
2036                                 /* has error report sensedata */
2037                             if(&pccb->csio.sense_data) {
2038                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2039                                 /* Valid,ErrorCode */
2040                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2041                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2042                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2043                                 /* AdditionalSenseLength */
2044                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2045                                 /* AdditionalSenseCode */
2046                                 }
2047                                 retvalue = ARCMSR_MESSAGE_FAIL;
2048                         } else {
2049                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2050                                                 &(ARCMSR_MAX_QBUFFER - 1);
2051                                 if (my_empty_len >= user_len) {
2052                                         while (user_len > 0) {
2053                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2054                                                 memcpy(pQbuffer, ptmpuserbuffer, 1);
2055                                                 acb->wqbuf_lastindex++;
2056                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2057                                                 ptmpuserbuffer++;
2058                                                 user_len--;
2059                                         }
2060                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2061                                                 acb->acb_flags &=
2062                                                 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2063                                                 arcmsr_post_ioctldata2iop(acb);
2064                                         }
2065                                 } else {
2066                                         /* has error report sensedata */
2067                                         if(&pccb->csio.sense_data) {
2068                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2069                                         /* Valid,ErrorCode */
2070                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2071                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2072                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2073                                         /* AdditionalSenseLength */
2074                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2075                                         /* AdditionalSenseCode */
2076                                         }
2077                                         retvalue = ARCMSR_MESSAGE_FAIL;
2078                                 }
2079                         }
2080                 }
2081                 break;
2082         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2083                         u_int8_t *pQbuffer = acb->rqbuffer;
2084
2085                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2086                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2087                                 arcmsr_iop_message_read(acb);
2088                         }
2089                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2090                         acb->rqbuf_firstindex = 0;
2091                         acb->rqbuf_lastindex = 0;
2092                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2093                         pcmdmessagefld->cmdmessage.ReturnCode =
2094                         ARCMSR_MESSAGE_RETURNCODE_OK;
2095                 }
2096                 break;
2097         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2098                         u_int8_t *pQbuffer = acb->wqbuffer;
2099
2100                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2101                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2102                                 arcmsr_iop_message_read(acb);
2103                         }
2104                         acb->acb_flags |=
2105                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2106                                         ACB_F_MESSAGE_WQBUFFER_READ);
2107                         acb->wqbuf_firstindex = 0;
2108                         acb->wqbuf_lastindex = 0;
2109                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2110                         pcmdmessagefld->cmdmessage.ReturnCode =
2111                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2112                 }
2113                 break;
2114         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2115                         u_int8_t *pQbuffer;
2116
2117                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2118                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2119                                 arcmsr_iop_message_read(acb);
2120                         }
2121                         acb->acb_flags |=
2122                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2123                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2124                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2125                         acb->rqbuf_firstindex = 0;
2126                         acb->rqbuf_lastindex = 0;
2127                         acb->wqbuf_firstindex = 0;
2128                         acb->wqbuf_lastindex = 0;
2129                         pQbuffer = acb->rqbuffer;
2130                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2131                         pQbuffer = acb->wqbuffer;
2132                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2133                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2134                 }
2135                 break;
2136         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2137                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2138                 }
2139                 break;
2140         case ARCMSR_MESSAGE_SAY_HELLO: {
2141                         int8_t * hello_string = "Hello! I am ARCMSR";
2142
2143                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2144                                 , (int16_t)strlen(hello_string));
2145                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2146                 }
2147                 break;
2148         case ARCMSR_MESSAGE_SAY_GOODBYE:
2149                 arcmsr_iop_parking(acb);
2150                 break;
2151         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2152                 arcmsr_flush_adapter_cache(acb);
2153                 break;
2154         default:
2155                 retvalue = ARCMSR_MESSAGE_FAIL;
2156         }
2157 message_out:
2158         return retvalue;
2159 }
2160 /*
2161 *********************************************************************
2162 *********************************************************************
2163 */
2164 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2165 {
2166         struct CommandControlBlock *srb=(struct CommandControlBlock *)arg;
2167         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)srb->acb;
2168         union ccb * pccb;
2169         int target, lun;
2170
2171         pccb=srb->pccb;
2172         target=pccb->ccb_h.target_id;
2173         lun=pccb->ccb_h.target_lun;
2174         if(error != 0) {
2175                 if(error != EFBIG) {
2176                         kprintf("arcmsr%d: unexpected error %x"
2177                                 " returned from 'bus_dmamap_load' \n"
2178                                 , acb->pci_unit, error);
2179                 }
2180                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2181                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2182                 }
2183                 arcmsr_srb_complete(srb, 0);
2184                 return;
2185         }
2186         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2187                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2188                 arcmsr_srb_complete(srb, 0);
2189                 return;
2190         }
2191         if(acb->acb_flags & ACB_F_BUS_RESET) {
2192                 kprintf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2193                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2194                 arcmsr_srb_complete(srb, 0);
2195                 return;
2196         }
2197         if(acb->devstate[target][lun]==ARECA_RAID_GONE) {
2198                 u_int8_t block_cmd;
2199
2200                 block_cmd=pccb->csio.cdb_io.cdb_bytes[0] & 0x0f;
2201                 if(block_cmd==0x08 || block_cmd==0x0a) {
2202                         kprintf("arcmsr%d:block 'read/write' command "
2203                                 "with gone raid volume Cmd=%2x, TargetId=%d, Lun=%d \n"
2204                                 , acb->pci_unit, block_cmd, target, lun);
2205                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2206                         arcmsr_srb_complete(srb, 0);
2207                         return;
2208                 }
2209         }
2210         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2211                 if(nseg != 0) {
2212                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2213                 }
2214                 arcmsr_srb_complete(srb, 0);
2215                 return;
2216         }
2217         if(acb->srboutstandingcount >= ARCMSR_MAX_OUTSTANDING_CMD) {
2218                 xpt_freeze_simq(acb->psim, 1);
2219                 pccb->ccb_h.status = CAM_REQUEUE_REQ;
2220                 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2221                 arcmsr_srb_complete(srb, 0);
2222                 return;
2223         }
2224         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2225         arcmsr_build_srb(srb, dm_segs, nseg);
2226 /*      if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2227                 callout_reset(&srb->ccb_callout, (pccb->ccb_h.timeout * hz) / 1000, arcmsr_srb_timeout, srb);
2228 */
2229         arcmsr_post_srb(acb, srb);
2230         return;
2231 }
2232 /*
2233 *****************************************************************************************
2234 *****************************************************************************************
2235 */
2236 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb)
2237 {
2238         struct CommandControlBlock *srb;
2239         struct AdapterControlBlock *acb=(struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2240         u_int32_t intmask_org;
2241         int i=0;
2242
2243         acb->num_aborts++;
2244         /*
2245         ***************************************************************************
2246         ** It is the upper layer do abort command this lock just prior to calling us.
2247         ** First determine if we currently own this command.
2248         ** Start by searching the device queue. If not found
2249         ** at all, and the system wanted us to just abort the
2250         ** command return success.
2251         ***************************************************************************
2252         */
2253         if(acb->srboutstandingcount!=0) {
2254                 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
2255                         srb=acb->psrb_pool[i];
2256                         if(srb->startdone==ARCMSR_SRB_START) {
2257                                 if(srb->pccb==abortccb) {
2258                                         srb->startdone=ARCMSR_SRB_ABORTED;
2259                                         kprintf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
2260                                                 "outstanding command \n"
2261                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2262                                                 , abortccb->ccb_h.target_lun, srb);
2263                                         goto abort_outstanding_cmd;
2264                                 }
2265                         }
2266                 }
2267         }
2268         return(FALSE);
2269 abort_outstanding_cmd:
2270         /* disable all outbound interrupt */
2271         intmask_org=arcmsr_disable_allintr(acb);
2272         arcmsr_polling_srbdone(acb, srb);
2273         /* enable outbound Post Queue, outbound doorbell Interrupt */
2274         arcmsr_enable_allintr(acb, intmask_org);
2275         return (TRUE);
2276 }
2277 /*
2278 ****************************************************************************
2279 ****************************************************************************
2280 */
2281 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2282 {
2283         int retry=0;
2284
2285         acb->num_resets++;
2286         acb->acb_flags |=ACB_F_BUS_RESET;
2287         while(acb->srboutstandingcount!=0 && retry < 400) {
2288                 arcmsr_interrupt(acb);
2289                 UDELAY(25000);
2290                 retry++;
2291         }
2292         arcmsr_iop_reset(acb);
2293         acb->acb_flags &= ~ACB_F_BUS_RESET;
2294         return;
2295 }
2296 /*
2297 **************************************************************************
2298 **************************************************************************
2299 */
2300 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2301                 union ccb * pccb)
2302 {
2303         pccb->ccb_h.status |= CAM_REQ_CMP;
2304         switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2305         case INQUIRY: {
2306                 unsigned char inqdata[36];
2307                 char *buffer=pccb->csio.data_ptr;
2308
2309                 if (pccb->ccb_h.target_lun) {
2310                         pccb->ccb_h.status |= CAM_SEL_TIMEOUT;
2311                         xpt_done(pccb);
2312                         return;
2313                 }
2314                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2315                 inqdata[1] = 0;                         /* rem media bit & Dev Type Modifier */
2316                 inqdata[2] = 0;                         /* ISO, ECMA, & ANSI versions */
2317                 inqdata[3] = 0;
2318                 inqdata[4] = 31;                        /* length of additional data */
2319                 inqdata[5] = 0;
2320                 inqdata[6] = 0;
2321                 inqdata[7] = 0;
2322                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
2323                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
2324                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2325                 memcpy(buffer, inqdata, sizeof(inqdata));
2326                 xpt_done(pccb);
2327         }
2328         break;
2329         case WRITE_BUFFER:
2330         case READ_BUFFER: {
2331                 if (arcmsr_iop_message_xfer(acb, pccb)) {
2332                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2333                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2334                 }
2335                 xpt_done(pccb);
2336         }
2337         break;
2338         default:
2339                 xpt_done(pccb);
2340         }
2341 }
2342 /*
2343 *********************************************************************
2344 *********************************************************************
2345 */
2346 static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
2347 {
2348         struct AdapterControlBlock *  acb;
2349
2350         acb=(struct AdapterControlBlock *) cam_sim_softc(psim);
2351         if(acb==NULL) {
2352                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2353                 xpt_done(pccb);
2354                 return;
2355         }
2356         switch (pccb->ccb_h.func_code) {
2357         case XPT_SCSI_IO: {
2358                         struct CommandControlBlock *srb;
2359                         int target=pccb->ccb_h.target_id;
2360
2361                         if(target == 16) {
2362                                 /* virtual device for iop message transfer */
2363                                 arcmsr_handle_virtual_command(acb, pccb);
2364                                 return;
2365                         }
2366                         if((srb=arcmsr_get_freesrb(acb)) == NULL) {
2367                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2368                                 xpt_done(pccb);
2369                                 return;
2370                         }
2371                         pccb->ccb_h.arcmsr_ccbsrb_ptr=srb;
2372                         pccb->ccb_h.arcmsr_ccbacb_ptr=acb;
2373                         srb->pccb=pccb;
2374                         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2375                                 if(!(pccb->ccb_h.flags & CAM_SCATTER_VALID)) {
2376                                         /* Single buffer */
2377                                         if(!(pccb->ccb_h.flags & CAM_DATA_PHYS)) {
2378                                                 /* Buffer is virtual */
2379                                                 u_int32_t error;
2380
2381                                                 crit_enter();
2382                                                 error = bus_dmamap_load(acb->dm_segs_dmat
2383                                                         , srb->dm_segs_dmamap
2384                                                         , pccb->csio.data_ptr
2385                                                         , pccb->csio.dxfer_len
2386                                                         , arcmsr_execute_srb, srb, /*flags*/0);
2387                                                 if(error == EINPROGRESS) {
2388                                                         xpt_freeze_simq(acb->psim, 1);
2389                                                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2390                                                 }
2391                                                 crit_exit();
2392                                         }
2393                                         else {          /* Buffer is physical */
2394                                                 struct bus_dma_segment seg;
2395
2396                                                 seg.ds_addr = (bus_addr_t)pccb->csio.data_ptr;
2397                                                 seg.ds_len = pccb->csio.dxfer_len;
2398                                                 arcmsr_execute_srb(srb, &seg, 1, 0);
2399                                         }
2400                                 } else {
2401                                         /* Scatter/gather list */
2402                                         struct bus_dma_segment *segs;
2403
2404                                         if((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0
2405                                         || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) {
2406                                                 pccb->ccb_h.status |= CAM_PROVIDE_FAIL;
2407                                                 xpt_done(pccb);
2408                                                 kfree(srb, M_DEVBUF);
2409                                                 return;
2410                                         }
2411                                         segs=(struct bus_dma_segment *)pccb->csio.data_ptr;
2412                                         arcmsr_execute_srb(srb, segs, pccb->csio.sglist_cnt, 0);
2413                                 }
2414                         } else {
2415                                 arcmsr_execute_srb(srb, NULL, 0, 0);
2416                         }
2417                         break;
2418                 }
2419         case XPT_TARGET_IO: {
2420                         /* target mode not yet support vendor specific commands. */
2421                         pccb->ccb_h.status |= CAM_REQ_CMP;
2422                         xpt_done(pccb);
2423                         break;
2424                 }
2425         case XPT_PATH_INQ: {
2426                         struct ccb_pathinq *cpi= &pccb->cpi;
2427
2428                         cpi->version_num=1;
2429                         cpi->hba_inquiry=PI_SDTR_ABLE | PI_TAG_ABLE;
2430                         cpi->target_sprt=0;
2431                         cpi->hba_misc=0;
2432                         cpi->hba_eng_cnt=0;
2433                         cpi->max_target=ARCMSR_MAX_TARGETID;        /* 0-16 */
2434                         cpi->max_lun=ARCMSR_MAX_TARGETLUN;          /* 0-7 */
2435                         cpi->initiator_id=ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2436                         cpi->bus_id=cam_sim_bus(psim);
2437                         strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2438                         strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2439                         strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2440                         cpi->unit_number=cam_sim_unit(psim);
2441                 #ifdef  CAM_NEW_TRAN_CODE
2442                         cpi->transport = XPORT_SPI;
2443                         cpi->transport_version = 2;
2444                         cpi->protocol = PROTO_SCSI;
2445                         cpi->protocol_version = SCSI_REV_2;
2446                 #endif
2447                         cpi->ccb_h.status |= CAM_REQ_CMP;
2448                         xpt_done(pccb);
2449                         break;
2450                 }
2451         case XPT_ABORT: {
2452                         union ccb *pabort_ccb;
2453
2454                         pabort_ccb=pccb->cab.abort_ccb;
2455                         switch (pabort_ccb->ccb_h.func_code) {
2456                         case XPT_ACCEPT_TARGET_IO:
2457                         case XPT_IMMED_NOTIFY:
2458                         case XPT_CONT_TARGET_IO:
2459                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2460                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2461                                         xpt_done(pabort_ccb);
2462                                         pccb->ccb_h.status |= CAM_REQ_CMP;
2463                                 } else {
2464                                         xpt_print_path(pabort_ccb->ccb_h.path);
2465                                         kprintf("Not found\n");
2466                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
2467                                 }
2468                                 break;
2469                         case XPT_SCSI_IO:
2470                                 pccb->ccb_h.status |= CAM_UA_ABORT;
2471                                 break;
2472                         default:
2473                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2474                                 break;
2475                         }
2476                         xpt_done(pccb);
2477                         break;
2478                 }
2479         case XPT_RESET_BUS:
2480         case XPT_RESET_DEV: {
2481                         u_int32_t     i;
2482
2483                         arcmsr_bus_reset(acb);
2484                         for (i=0; i < 500; i++) {
2485                                 DELAY(1000);
2486                         }
2487                         pccb->ccb_h.status |= CAM_REQ_CMP;
2488                         xpt_done(pccb);
2489                         break;
2490                 }
2491         case XPT_TERM_IO: {
2492                         pccb->ccb_h.status |= CAM_REQ_INVALID;
2493                         xpt_done(pccb);
2494                         break;
2495                 }
2496         case XPT_GET_TRAN_SETTINGS: {
2497                         struct ccb_trans_settings *cts;
2498
2499                         if(pccb->ccb_h.target_id == 16) {
2500                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2501                                 xpt_done(pccb);
2502                                 break;
2503                         }
2504                         cts= &pccb->cts;
2505                 #ifdef  CAM_NEW_TRAN_CODE
2506                         {
2507                                 struct ccb_trans_settings_scsi *scsi;
2508                                 struct ccb_trans_settings_spi *spi;
2509
2510                                 scsi = &cts->proto_specific.scsi;
2511                                 spi = &cts->xport_specific.spi;
2512                                 cts->protocol = PROTO_SCSI;
2513                                 cts->protocol_version = SCSI_REV_2;
2514                                 cts->transport = XPORT_SPI;
2515                                 cts->transport_version = 2;
2516                                 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
2517                                 spi->sync_period=3;
2518                                 spi->sync_offset=32;
2519                                 spi->bus_width=MSG_EXT_WDTR_BUS_16_BIT;
2520                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2521                                 spi->valid = CTS_SPI_VALID_DISC
2522                                         | CTS_SPI_VALID_SYNC_RATE
2523                                         | CTS_SPI_VALID_SYNC_OFFSET
2524                                         | CTS_SPI_VALID_BUS_WIDTH;
2525                                 scsi->valid = CTS_SCSI_VALID_TQ;
2526                         }
2527                 #else
2528                         {
2529                                 cts->flags=(CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
2530                                 cts->sync_period=3;
2531                                 cts->sync_offset=32;
2532                                 cts->bus_width=MSG_EXT_WDTR_BUS_16_BIT;
2533                                 cts->valid=CCB_TRANS_SYNC_RATE_VALID |
2534                                 CCB_TRANS_SYNC_OFFSET_VALID |
2535                                 CCB_TRANS_BUS_WIDTH_VALID |
2536                                 CCB_TRANS_DISC_VALID |
2537                                 CCB_TRANS_TQ_VALID;
2538                         }
2539                 #endif
2540                         pccb->ccb_h.status |= CAM_REQ_CMP;
2541                         xpt_done(pccb);
2542                         break;
2543                 }
2544         case XPT_SET_TRAN_SETTINGS: {
2545                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2546                         xpt_done(pccb);
2547                         break;
2548                 }
2549         case XPT_CALC_GEOMETRY: {
2550                         struct ccb_calc_geometry *ccg;
2551                         u_int32_t size_mb;
2552                         u_int32_t secs_per_cylinder;
2553
2554                         if(pccb->ccb_h.target_id == 16) {
2555                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2556                                 xpt_done(pccb);
2557                                 break;
2558                         }
2559                         ccg= &pccb->ccg;
2560                         if (ccg->block_size == 0) {
2561                                 pccb->ccb_h.status = CAM_REQ_INVALID;
2562                                 xpt_done(pccb);
2563                                 break;
2564                         }
2565                         if(((1024L * 1024L)/ccg->block_size) < 0) {
2566                                 pccb->ccb_h.status = CAM_REQ_INVALID;
2567                                 xpt_done(pccb);
2568                                 break;
2569                         }
2570                         size_mb=ccg->volume_size/((1024L * 1024L)/ccg->block_size);
2571                         if(size_mb > 1024 ) {
2572                                 ccg->heads=255;
2573                                 ccg->secs_per_track=63;
2574                         } else {
2575                                 ccg->heads=64;
2576                                 ccg->secs_per_track=32;
2577                         }
2578                         secs_per_cylinder=ccg->heads * ccg->secs_per_track;
2579                         ccg->cylinders=ccg->volume_size / secs_per_cylinder;
2580                         pccb->ccb_h.status |= CAM_REQ_CMP;
2581                         xpt_done(pccb);
2582                         break;
2583                 }
2584         default:
2585                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2586                 xpt_done(pccb);
2587                 break;
2588         }
2589         return;
2590 }
2591 /*
2592 **********************************************************************
2593 **********************************************************************
2594 */
2595 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
2596 {
2597         acb->acb_flags |= ACB_F_MSG_START_BGRB;
2598         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
2599         if(!arcmsr_hba_wait_msgint_ready(acb)) {
2600                 kprintf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
2601         }
2602         return;
2603 }
2604 /*
2605 **********************************************************************
2606 **********************************************************************
2607 */
2608 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
2609 {
2610         acb->acb_flags |= ACB_F_MSG_START_BGRB;
2611         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,  ARCMSR_MESSAGE_START_BGRB);
2612         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
2613                 kprintf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
2614         }
2615         return;
2616 }
2617 /*
2618 **********************************************************************
2619 **********************************************************************
2620 */
2621 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
2622 {
2623         acb->acb_flags |= ACB_F_MSG_START_BGRB;
2624         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
2625         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2626         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
2627                 kprintf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
2628         }
2629         return;
2630 }
2631 /*
2632 **********************************************************************
2633 **********************************************************************
2634 */
2635 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
2636 {
2637         switch (acb->adapter_type) {
2638         case ACB_ADAPTER_TYPE_A:
2639                 arcmsr_start_hba_bgrb(acb);
2640                 break;
2641         case ACB_ADAPTER_TYPE_B:
2642                 arcmsr_start_hbb_bgrb(acb);
2643                 break;
2644         case ACB_ADAPTER_TYPE_C:
2645                 arcmsr_start_hbc_bgrb(acb);
2646                 break;
2647         }
2648         return;
2649 }
2650 /*
2651 **********************************************************************
2652 **
2653 **********************************************************************
2654 */
2655 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
2656 {
2657         struct CommandControlBlock *srb;
2658         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
2659         u_int16_t       error;
2660
2661 polling_ccb_retry:
2662         poll_count++;
2663         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2664         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
2665         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2666         while(1) {
2667                 if((flag_srb=CHIP_REG_READ32(HBA_MessageUnit,
2668                         0, outbound_queueport))==0xFFFFFFFF) {
2669                         if(poll_srb_done) {
2670                                 break;/*chip FIFO no ccb for completion already*/
2671                         } else {
2672                                 UDELAY(25000);
2673                                 if ((poll_count > 100) && (poll_srb != NULL)) {
2674                                         break;
2675                                 }
2676                                 goto polling_ccb_retry;
2677                         }
2678                 }
2679                 /* check if command done with no error*/
2680                 srb=(struct CommandControlBlock *)
2681                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
2682         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2683                 poll_srb_done = (srb==poll_srb) ? 1:0;
2684                 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) {
2685                         if(srb->startdone==ARCMSR_SRB_ABORTED) {
2686                                 kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
2687                                         "poll command abort successfully \n"
2688                                         , acb->pci_unit
2689                                         , srb->pccb->ccb_h.target_id
2690                                         , srb->pccb->ccb_h.target_lun, srb);
2691                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
2692                                 arcmsr_srb_complete(srb, 1);
2693                                 continue;
2694                         }
2695                         kprintf("arcmsr%d: polling get an illegal srb command done srb='%p'"
2696                                 "srboutstandingcount=%d \n"
2697                                 , acb->pci_unit
2698                                 , srb, acb->srboutstandingcount);
2699                         continue;
2700                 }
2701                 arcmsr_report_srb_state(acb, srb, error);
2702         }       /*drain reply FIFO*/
2703         return;
2704 }
2705 /*
2706 **********************************************************************
2707 **
2708 **********************************************************************
2709 */
2710 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
2711 {
2712         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
2713         struct CommandControlBlock *srb;
2714         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
2715         int index;
2716         u_int16_t       error;
2717
2718 polling_ccb_retry:
2719         poll_count++;
2720         CHIP_REG_WRITE32(HBB_DOORBELL,
2721         0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
2722         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2723         while(1) {
2724                 index=phbbmu->doneq_index;
2725                 if((flag_srb=phbbmu->done_qbuffer[index]) == 0) {
2726                         if(poll_srb_done) {
2727                                 break;/*chip FIFO no ccb for completion already*/
2728                         } else {
2729                                 UDELAY(25000);
2730                             if ((poll_count > 100) && (poll_srb != NULL)) {
2731                                         break;
2732                                 }
2733                                 goto polling_ccb_retry;
2734                         }
2735                 }
2736                 phbbmu->done_qbuffer[index]=0;
2737                 index++;
2738                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
2739                 phbbmu->doneq_index=index;
2740                 /* check if command done with no error*/
2741                 srb=(struct CommandControlBlock *)
2742                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
2743         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2744                 poll_srb_done = (srb==poll_srb) ? 1:0;
2745                 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) {
2746                         if(srb->startdone==ARCMSR_SRB_ABORTED) {
2747                                 kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
2748                                         "poll command abort successfully \n"
2749                                         , acb->pci_unit
2750                                         , srb->pccb->ccb_h.target_id
2751                                         , srb->pccb->ccb_h.target_lun, srb);
2752                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
2753                                 arcmsr_srb_complete(srb, 1);
2754                                 continue;
2755                         }
2756                         kprintf("arcmsr%d: polling get an illegal srb command done srb='%p'"
2757                                 "srboutstandingcount=%d \n"
2758                                 , acb->pci_unit
2759                                 , srb, acb->srboutstandingcount);
2760                         continue;
2761                 }
2762                 arcmsr_report_srb_state(acb, srb, error);
2763         }       /*drain reply FIFO*/
2764         return;
2765 }
2766 /*
2767 **********************************************************************
2768 **
2769 **********************************************************************
2770 */
2771 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
2772 {
2773         struct CommandControlBlock *srb;
2774         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
2775         u_int16_t       error;
2776
2777 polling_ccb_retry:
2778         poll_count++;
2779         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2780         while(1) {
2781                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
2782                         if(poll_srb_done) {
2783                                 break;/*chip FIFO no ccb for completion already*/
2784                         } else {
2785                                 UDELAY(25000);
2786                             if ((poll_count > 100) && (poll_srb != NULL)) {
2787                                         break;
2788                                 }
2789                             if (acb->srboutstandingcount == 0) {
2790                                     break;
2791                             }
2792                                 goto polling_ccb_retry;
2793                         }
2794                 }
2795                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2796                 /* check if command done with no error*/
2797                 srb=(struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFF0));/*frame must be 32 bytes aligned*/
2798         error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2799                 if (poll_srb != NULL)
2800                         poll_srb_done = (srb==poll_srb) ? 1:0;
2801                 if((srb->acb!=acb) || (srb->startdone!=ARCMSR_SRB_START)) {
2802                         if(srb->startdone==ARCMSR_SRB_ABORTED) {
2803                                 kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
2804                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
2805                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
2806                                 arcmsr_srb_complete(srb, 1);
2807                                 continue;
2808                         }
2809                         kprintf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
2810                                         , acb->pci_unit, srb, acb->srboutstandingcount);
2811                         continue;
2812                 }
2813                 arcmsr_report_srb_state(acb, srb, error);
2814         }       /*drain reply FIFO*/
2815         return;
2816 }
2817 /*
2818 **********************************************************************
2819 **********************************************************************
2820 */
2821 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
2822 {
2823         switch (acb->adapter_type) {
2824         case ACB_ADAPTER_TYPE_A: {
2825                         arcmsr_polling_hba_srbdone(acb, poll_srb);
2826                 }
2827                 break;
2828         case ACB_ADAPTER_TYPE_B: {
2829                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
2830                 }
2831                 break;
2832         case ACB_ADAPTER_TYPE_C: {
2833                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
2834                 }
2835                 break;
2836         }
2837 }
2838 /*
2839 **********************************************************************
2840 **********************************************************************
2841 */
2842 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
2843 {
2844         char *acb_firm_model=acb->firm_model;
2845         char *acb_firm_version=acb->firm_version;
2846         char *acb_device_map = acb->device_map;
2847         size_t iop_firm_model=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
2848         size_t iop_firm_version=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
2849         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
2850         int i;
2851
2852         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2853         if(!arcmsr_hba_wait_msgint_ready(acb)) {
2854                 kprintf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
2855         }
2856         i=0;
2857         while(i<8) {
2858                 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
2859                 /* 8 bytes firm_model, 15, 60-67*/
2860                 acb_firm_model++;
2861                 i++;
2862         }
2863         i=0;
2864         while(i<16) {
2865                 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
2866                 /* 16 bytes firm_version, 17, 68-83*/
2867                 acb_firm_version++;
2868                 i++;
2869         }
2870         i=0;
2871         while(i<16) {
2872                 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
2873                 acb_device_map++;
2874                 i++;
2875         }
2876         kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
2877         kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
2878         acb->firm_request_len=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
2879         acb->firm_numbers_queue=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
2880         acb->firm_sdram_size=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
2881         acb->firm_ide_channels=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
2882         acb->firm_cfg_version=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);   /*firm_cfg_version,  25,          */
2883         return;
2884 }
2885 /*
2886 **********************************************************************
2887 **********************************************************************
2888 */
2889 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
2890 {
2891         char *acb_firm_model=acb->firm_model;
2892         char *acb_firm_version=acb->firm_version;
2893         char *acb_device_map = acb->device_map;
2894         size_t iop_firm_model=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);  /*firm_model,15,60-67*/
2895         size_t iop_firm_version=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
2896         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
2897         int i;
2898
2899         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2900         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
2901                 kprintf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
2902         }
2903         i=0;
2904         while(i<8) {
2905                 *acb_firm_model=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
2906                 /* 8 bytes firm_model, 15, 60-67*/
2907                 acb_firm_model++;
2908                 i++;
2909         }
2910         i=0;
2911         while(i<16) {
2912                 *acb_firm_version=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
2913                 /* 16 bytes firm_version, 17, 68-83*/
2914                 acb_firm_version++;
2915                 i++;
2916         }
2917         i=0;
2918         while(i<16) {
2919                 *acb_device_map=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
2920                 acb_device_map++;
2921                 i++;
2922         }
2923         kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
2924         kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
2925         acb->firm_request_len=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
2926         acb->firm_numbers_queue=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
2927         acb->firm_sdram_size=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
2928         acb->firm_ide_channels=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
2929         acb->firm_cfg_version=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);      /*firm_cfg_version,  25,          */
2930         return;
2931 }
2932 /*
2933 **********************************************************************
2934 **********************************************************************
2935 */
2936 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
2937 {
2938         char *acb_firm_model=acb->firm_model;
2939         char *acb_firm_version=acb->firm_version;
2940         char *acb_device_map = acb->device_map;
2941         size_t iop_firm_model=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
2942         size_t iop_firm_version=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
2943         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
2944         int i;
2945
2946         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2947         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2948         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
2949                 kprintf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
2950         }
2951         i=0;
2952         while(i<8) {
2953                 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
2954                 /* 8 bytes firm_model, 15, 60-67*/
2955                 acb_firm_model++;
2956                 i++;
2957         }
2958         i=0;
2959         while(i<16) {
2960                 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
2961                 /* 16 bytes firm_version, 17, 68-83*/
2962                 acb_firm_version++;
2963                 i++;
2964         }
2965         i=0;
2966         while(i<16) {
2967                 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
2968                 acb_device_map++;
2969                 i++;
2970         }
2971         kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
2972         kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
2973         acb->firm_request_len   =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);      /*firm_request_len,   1, 04-07*/
2974         acb->firm_numbers_queue =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);      /*firm_numbers_queue, 2, 08-11*/
2975         acb->firm_sdram_size    =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);      /*firm_sdram_size,    3, 12-15*/
2976         acb->firm_ide_channels  =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);      /*firm_ide_channels,  4, 16-19*/
2977         acb->firm_cfg_version   =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);        /*firm_cfg_version,  25,          */
2978         return;
2979 }
2980 /*
2981 **********************************************************************
2982 **********************************************************************
2983 */
2984 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
2985 {
2986         switch (acb->adapter_type) {
2987         case ACB_ADAPTER_TYPE_A: {
2988                         arcmsr_get_hba_config(acb);
2989                 }
2990                 break;
2991         case ACB_ADAPTER_TYPE_B: {
2992                         arcmsr_get_hbb_config(acb);
2993                 }
2994                 break;
2995         case ACB_ADAPTER_TYPE_C: {
2996                         arcmsr_get_hbc_config(acb);
2997                 }
2998                 break;
2999         }
3000         return;
3001 }
3002 /*
3003 **********************************************************************
3004 **********************************************************************
3005 */
3006 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3007 {
3008         int     timeout=0;
3009
3010         switch (acb->adapter_type) {
3011         case ACB_ADAPTER_TYPE_A: {
3012                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3013                         {
3014                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3015                                 {
3016                                         kprintf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3017                                         return;
3018                                 }
3019                                 UDELAY(15000); /* wait 15 milli-seconds */
3020                         }
3021                 }
3022                 break;
3023         case ACB_ADAPTER_TYPE_B: {
3024                         while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3025                         {
3026                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3027                                 {
3028                                         kprintf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3029                                         return;
3030                                 }
3031                                 UDELAY(15000); /* wait 15 milli-seconds */
3032                         }
3033                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3034                 }
3035                 break;
3036         case ACB_ADAPTER_TYPE_C: {
3037                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3038                         {
3039                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3040                                 {
3041                                         kprintf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3042                                         return;
3043                                 }
3044                                 UDELAY(15000); /* wait 15 milli-seconds */
3045                         }
3046                 }
3047                 break;
3048         }
3049         return;
3050 }
3051 /*
3052 **********************************************************************
3053 **********************************************************************
3054 */
3055 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3056 {
3057         u_int32_t outbound_doorbell;
3058
3059         switch (acb->adapter_type) {
3060         case ACB_ADAPTER_TYPE_A: {
3061                         /* empty doorbell Qbuffer if door bell ringed */
3062                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3063                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3064                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3065
3066                 }
3067                 break;
3068         case ACB_ADAPTER_TYPE_B: {
3069                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3070                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3071                         /* let IOP know data has been read */
3072                 }
3073                 break;
3074         case ACB_ADAPTER_TYPE_C: {
3075                         /* empty doorbell Qbuffer if door bell ringed */
3076                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3077                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
3078                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3079
3080                 }
3081                 break;
3082         }
3083         return;
3084 }
3085 /*
3086 ************************************************************************
3087 ************************************************************************
3088 */
3089 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3090 {
3091         unsigned long srb_phyaddr;
3092         u_int32_t srb_phyaddr_hi32;
3093
3094         /*
3095         ********************************************************************
3096         ** here we need to tell iop 331 our freesrb.HighPart
3097         ** if freesrb.HighPart is not zero
3098         ********************************************************************
3099         */
3100         srb_phyaddr= (unsigned long) acb->srb_phyaddr.phyaddr;
3101 //      srb_phyaddr_hi32=(u_int32_t) ((srb_phyaddr>>16)>>16);
3102         srb_phyaddr_hi32=acb->srb_phyaddr.B.phyadd_high;
3103         switch (acb->adapter_type) {
3104         case ACB_ADAPTER_TYPE_A: {
3105                         if(srb_phyaddr_hi32!=0) {
3106                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3107                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3108                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3109                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3110                                         kprintf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3111                                         return FALSE;
3112                                 }
3113                         }
3114                 }
3115                 break;
3116                 /*
3117                 ***********************************************************************
3118                 **    if adapter type B, set window of "post command Q"
3119                 ***********************************************************************
3120                 */
3121         case ACB_ADAPTER_TYPE_B: {
3122                         u_int32_t post_queue_phyaddr;
3123                         struct HBB_MessageUnit *phbbmu;
3124
3125                         phbbmu=(struct HBB_MessageUnit *)acb->pmu;
3126                         phbbmu->postq_index=0;
3127                         phbbmu->doneq_index=0;
3128                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3129                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3130                                 kprintf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3131                                 return FALSE;
3132                         }
3133                         post_queue_phyaddr = srb_phyaddr + ARCMSR_MAX_FREESRB_NUM*sizeof(struct CommandControlBlock)
3134                         + offsetof(struct HBB_MessageUnit, post_qbuffer);
3135                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3136                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3137                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3138                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3139                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3140                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3141                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3142                                 kprintf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3143                                 return FALSE;
3144                         }
3145                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3146                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3147                                 kprintf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3148                                 return FALSE;
3149                         }
3150                 }
3151                 break;
3152         case ACB_ADAPTER_TYPE_C: {
3153                         if(srb_phyaddr_hi32!=0) {
3154                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3155                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3156                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3157                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3158                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3159                                         kprintf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3160                                         return FALSE;
3161                                 }
3162                         }
3163                 }
3164                 break;
3165         }
3166         return TRUE;
3167 }
3168 /*
3169 ************************************************************************
3170 ************************************************************************
3171 */
3172 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3173 {
3174         switch (acb->adapter_type)
3175         {
3176         case ACB_ADAPTER_TYPE_A:
3177         case ACB_ADAPTER_TYPE_C:
3178                 break;
3179         case ACB_ADAPTER_TYPE_B: {
3180                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3181                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3182                                 kprintf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3183
3184                                 return;
3185                         }
3186                 }
3187                 break;
3188         }
3189         return;
3190 }
3191 /*
3192 **********************************************************************
3193 **********************************************************************
3194 */
3195 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3196 {
3197         u_int32_t intmask_org;
3198
3199         /* disable all outbound interrupt */
3200         intmask_org=arcmsr_disable_allintr(acb);
3201         arcmsr_wait_firmware_ready(acb);
3202         arcmsr_iop_confirm(acb);
3203         arcmsr_get_firmware_spec(acb);
3204         /*start background rebuild*/
3205         arcmsr_start_adapter_bgrb(acb);
3206         /* empty doorbell Qbuffer if door bell ringed */
3207         arcmsr_clear_doorbell_queue_buffer(acb);
3208         arcmsr_enable_eoi_mode(acb);
3209         /* enable outbound Post Queue, outbound doorbell Interrupt */
3210         arcmsr_enable_allintr(acb, intmask_org);
3211         acb->acb_flags |=ACB_F_IOP_INITED;
3212         return;
3213 }
3214 /*
3215 **********************************************************************
3216 **********************************************************************
3217 */
3218 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3219 {
3220         struct AdapterControlBlock *acb=arg;
3221         struct CommandControlBlock *srb_tmp;
3222         u_int8_t * dma_memptr;
3223         u_int32_t i;
3224         unsigned long srb_phyaddr=(unsigned long)segs->ds_addr;
3225
3226         dma_memptr=acb->uncacheptr;
3227         acb->srb_phyaddr.phyaddr=srb_phyaddr;
3228         srb_tmp=(struct CommandControlBlock *)dma_memptr;
3229         for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
3230                 if(bus_dmamap_create(acb->dm_segs_dmat,
3231                          /*flags*/0, &srb_tmp->dm_segs_dmamap)!=0) {
3232                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3233                         kprintf("arcmsr%d:"
3234                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3235                         return;
3236                 }
3237                 srb_tmp->cdb_shifted_phyaddr=(acb->adapter_type==ACB_ADAPTER_TYPE_C)?srb_phyaddr:(srb_phyaddr >> 5);
3238                 srb_tmp->acb=acb;
3239                 acb->srbworkingQ[i]=acb->psrb_pool[i]=srb_tmp;
3240                 srb_phyaddr=srb_phyaddr+sizeof(struct CommandControlBlock);
3241                 srb_tmp++;
3242         }
3243         acb->vir2phy_offset=(unsigned long)srb_tmp-(unsigned long)srb_phyaddr;
3244         return;
3245 }
3246 /*
3247 ************************************************************************
3248 **
3249 **
3250 ************************************************************************
3251 */
3252 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3253 {
3254         /* remove the control device */
3255         if(acb->ioctl_dev != NULL) {
3256                 destroy_dev(acb->ioctl_dev);
3257         }
3258         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3259         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3260         bus_dma_tag_destroy(acb->srb_dmat);
3261         bus_dma_tag_destroy(acb->dm_segs_dmat);
3262         bus_dma_tag_destroy(acb->parent_dmat);
3263         return;
3264 }
3265 /*
3266 ************************************************************************
3267 ************************************************************************
3268 */
3269 static u_int32_t arcmsr_initialize(device_t dev)
3270 {
3271         struct AdapterControlBlock *acb=device_get_softc(dev);
3272         u_int16_t pci_command;
3273         int i, j,max_coherent_size;
3274
3275         switch (pci_get_devid(dev)) {
3276         case PCIDevVenIDARC1880: {
3277                         acb->adapter_type=ACB_ADAPTER_TYPE_C;
3278                         max_coherent_size=ARCMSR_SRBS_POOL_SIZE;
3279                 }
3280                 break;
3281         case PCIDevVenIDARC1200:
3282         case PCIDevVenIDARC1201: {
3283                         acb->adapter_type=ACB_ADAPTER_TYPE_B;
3284                         max_coherent_size=ARCMSR_SRBS_POOL_SIZE+(sizeof(struct HBB_MessageUnit));
3285                 }
3286                 break;
3287         case PCIDevVenIDARC1110:
3288         case PCIDevVenIDARC1120:
3289         case PCIDevVenIDARC1130:
3290         case PCIDevVenIDARC1160:
3291         case PCIDevVenIDARC1170:
3292         case PCIDevVenIDARC1210:
3293         case PCIDevVenIDARC1220:
3294         case PCIDevVenIDARC1230:
3295         case PCIDevVenIDARC1231:
3296         case PCIDevVenIDARC1260:
3297         case PCIDevVenIDARC1261:
3298         case PCIDevVenIDARC1270:
3299         case PCIDevVenIDARC1280:
3300         case PCIDevVenIDARC1212:
3301         case PCIDevVenIDARC1222:
3302         case PCIDevVenIDARC1380:
3303         case PCIDevVenIDARC1381:
3304         case PCIDevVenIDARC1680:
3305         case PCIDevVenIDARC1681: {
3306                         acb->adapter_type=ACB_ADAPTER_TYPE_A;
3307                         max_coherent_size=ARCMSR_SRBS_POOL_SIZE;
3308                 }
3309                 break;
3310         default: {
3311                         kprintf("arcmsr%d:"
3312                         " unknown RAID adapter type \n", device_get_unit(dev));
3313                         return ENOMEM;
3314                 }
3315         }
3316         if(bus_dma_tag_create(  /*parent*/      NULL,
3317                                 /*alignemnt*/   1,
3318                                 /*boundary*/    0,
3319                                 /*lowaddr*/     BUS_SPACE_MAXADDR,
3320                                 /*highaddr*/    BUS_SPACE_MAXADDR,
3321                                 /*filter*/      NULL,
3322                                 /*filterarg*/   NULL,
3323                                 /*maxsize*/     BUS_SPACE_MAXSIZE_32BIT,
3324                                 /*nsegments*/   BUS_SPACE_UNRESTRICTED,
3325                                 /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
3326                                 /*flags*/       0,
3327                                                 &acb->parent_dmat) != 0)
3328         {
3329                 kprintf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
3330                 return ENOMEM;
3331         }
3332         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
3333         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
3334                                 /*alignment*/   1,
3335                                 /*boundary*/    0,
3336                                 /*lowaddr*/     BUS_SPACE_MAXADDR,
3337                                 /*highaddr*/    BUS_SPACE_MAXADDR,
3338                                 /*filter*/      NULL,
3339                                 /*filterarg*/   NULL,
3340                                 /*maxsize*/     ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
3341                                 /*nsegments*/   ARCMSR_MAX_SG_ENTRIES,
3342                                 /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
3343                                 /*flags*/       0,
3344                                                 &acb->dm_segs_dmat) != 0)
3345         {
3346                 bus_dma_tag_destroy(acb->parent_dmat);
3347                 kprintf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
3348                 return ENOMEM;
3349         }
3350         /* DMA tag for our srb structures.... Allocate the freesrb memory */
3351         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
3352                                 /*alignment*/   0x20,
3353                                 /*boundary*/    0,
3354                                 /*lowaddr*/     BUS_SPACE_MAXADDR_32BIT,
3355                                 /*highaddr*/    BUS_SPACE_MAXADDR,
3356                                 /*filter*/      NULL,
3357                                 /*filterarg*/   NULL,
3358                                 /*maxsize*/     max_coherent_size,
3359                                 /*nsegments*/   1,
3360                                 /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
3361                                 /*flags*/       0,
3362                                                 &acb->srb_dmat) != 0)
3363         {
3364                 bus_dma_tag_destroy(acb->dm_segs_dmat);
3365                 bus_dma_tag_destroy(acb->parent_dmat);
3366                 kprintf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
3367                 return ENXIO;
3368         }
3369         /* Allocation for our srbs */
3370         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
3371                 bus_dma_tag_destroy(acb->srb_dmat);
3372                 bus_dma_tag_destroy(acb->dm_segs_dmat);
3373                 bus_dma_tag_destroy(acb->parent_dmat);
3374                 kprintf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
3375                 return ENXIO;
3376         }
3377         /* And permanently map them */
3378         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
3379                 bus_dma_tag_destroy(acb->srb_dmat);
3380                 bus_dma_tag_destroy(acb->dm_segs_dmat);
3381                 bus_dma_tag_destroy(acb->parent_dmat);
3382                 kprintf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
3383                 return ENXIO;
3384         }
3385         pci_command=pci_read_config(dev, PCIR_COMMAND, 2);
3386         pci_command |= PCIM_CMD_BUSMASTEREN;
3387         pci_command |= PCIM_CMD_PERRESPEN;
3388         pci_command |= PCIM_CMD_MWRICEN;
3389         /* Enable Busmaster/Mem */
3390         pci_command |= PCIM_CMD_MEMEN;
3391         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
3392         switch(acb->adapter_type) {
3393         case ACB_ADAPTER_TYPE_A: {
3394                         u_int32_t rid0=PCIR_BAR(0);
3395                         vm_offset_t     mem_base0;
3396
3397                         acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
3398                         if(acb->sys_res_arcmsr[0] == NULL) {
3399                                 arcmsr_free_resource(acb);
3400                                 kprintf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
3401                                 return ENOMEM;
3402                         }
3403                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
3404                                 arcmsr_free_resource(acb);
3405                                 kprintf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
3406                                 return ENXIO;
3407                         }
3408                         mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
3409                         if(mem_base0==0) {
3410                                 arcmsr_free_resource(acb);
3411                                 kprintf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
3412                                 return ENXIO;
3413                         }
3414                         acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]);
3415                         acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]);
3416                         acb->pmu=(struct MessageUnit_UNION *)mem_base0;
3417                 }
3418                 break;
3419         case ACB_ADAPTER_TYPE_B: {
3420                         struct HBB_MessageUnit *phbbmu;
3421                         struct CommandControlBlock *freesrb;
3422                         u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
3423                         vm_offset_t     mem_base[]={0,0};
3424                         for(i=0; i<2; i++) {
3425                                 if(i==0) {
3426                                         acb->sys_res_arcmsr[i]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
3427                                                                                         0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
3428                                 } else {
3429                                         acb->sys_res_arcmsr[i]=bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
3430                                                                                         0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
3431                                 }
3432                                 if(acb->sys_res_arcmsr[i] == NULL) {
3433                                         arcmsr_free_resource(acb);
3434                                         kprintf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
3435                                         return ENOMEM;
3436                                 }
3437                                 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
3438                                         arcmsr_free_resource(acb);
3439                                         kprintf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
3440                                         return ENXIO;
3441                                 }
3442                                 mem_base[i]=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
3443                                 if(mem_base[i]==0) {
3444                                         arcmsr_free_resource(acb);
3445                                         kprintf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
3446                                         return ENXIO;
3447                                 }
3448                                 acb->btag[i]=rman_get_bustag(acb->sys_res_arcmsr[i]);
3449                                 acb->bhandle[i]=rman_get_bushandle(acb->sys_res_arcmsr[i]);
3450                         }
3451                         freesrb=(struct CommandControlBlock *)acb->uncacheptr;
3452                         acb->pmu=(struct MessageUnit_UNION *)&freesrb[ARCMSR_MAX_FREESRB_NUM];
3453                         phbbmu=(struct HBB_MessageUnit *)acb->pmu;
3454                         phbbmu->hbb_doorbell=(struct HBB_DOORBELL *)mem_base[0];
3455                         phbbmu->hbb_rwbuffer=(struct HBB_RWBUFFER *)mem_base[1];
3456                 }
3457                 break;
3458         case ACB_ADAPTER_TYPE_C: {
3459                         u_int32_t rid0=PCIR_BAR(1);
3460                         vm_offset_t     mem_base0;
3461
3462                         acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
3463                         if(acb->sys_res_arcmsr[0] == NULL) {
3464                                 arcmsr_free_resource(acb);
3465                                 kprintf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
3466                                 return ENOMEM;
3467                         }
3468                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
3469                                 arcmsr_free_resource(acb);
3470                                 kprintf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
3471                                 return ENXIO;
3472                         }
3473                         mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
3474                         if(mem_base0==0) {
3475                                 arcmsr_free_resource(acb);
3476                                 kprintf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
3477                                 return ENXIO;
3478                         }
3479                         acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]);
3480                         acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]);
3481                         acb->pmu=(struct MessageUnit_UNION *)mem_base0;
3482                 }
3483                 break;
3484         }
3485         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
3486                 arcmsr_free_resource(acb);
3487                 kprintf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
3488                 return ENXIO;
3489         }
3490         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
3491         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
3492         /*
3493         ********************************************************************
3494         ** init raid volume state
3495         ********************************************************************
3496         */
3497         for(i=0;i<ARCMSR_MAX_TARGETID;i++) {
3498                 for(j=0;j<ARCMSR_MAX_TARGETLUN;j++) {
3499                         acb->devstate[i][j]=ARECA_RAID_GONE;
3500                 }
3501         }
3502         arcmsr_iop_init(acb);
3503         return(0);
3504 }
3505 /*
3506 ************************************************************************
3507 ************************************************************************
3508 */
3509 static int arcmsr_attach(device_t dev)
3510 {
3511         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
3512         u_int32_t unit=device_get_unit(dev);
3513         struct ccb_setasync csa;
3514         struct cam_devq *devq;  /* Device Queue to use for this SIM */
3515         struct resource *irqres;
3516         int     rid;
3517         u_int irq_flags;
3518
3519         if(acb == NULL) {
3520                 kprintf("arcmsr%d: cannot allocate softc\n", unit);
3521                 return (ENOMEM);
3522         }
3523         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr Q buffer lock");
3524         if(arcmsr_initialize(dev)) {
3525                 kprintf("arcmsr%d: initialize failure!\n", unit);
3526                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3527                 return ENXIO;
3528         }
3529         /* After setting up the adapter, map our interrupt */
3530         rid=0;
3531         acb->irq_type = pci_alloc_1intr(dev, arcmsr_msi_enable, &rid,
3532             &irq_flags);
3533         irqres=bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
3534             irq_flags);
3535         if(irqres == NULL ||
3536                 bus_setup_intr(dev, irqres, INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih, NULL)) {
3537                 arcmsr_free_resource(acb);
3538                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3539                 kprintf("arcmsr%d: unable to register interrupt handler!\n", unit);
3540                 return ENXIO;
3541         }
3542         acb->irqres=irqres;
3543         acb->pci_dev=dev;
3544         acb->pci_unit=unit;
3545         /*
3546          * Now let the CAM generic SCSI layer find the SCSI devices on
3547          * the bus *  start queue to reset to the idle loop. *
3548          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
3549          * max_sim_transactions
3550         */
3551         devq=cam_simq_alloc(ARCMSR_MAX_START_JOB);
3552         if(devq == NULL) {
3553             arcmsr_free_resource(acb);
3554                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
3555                 if (acb->irq_type == PCI_INTR_TYPE_MSI)
3556                         pci_release_msi(acb->pci_dev);
3557                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3558                 kprintf("arcmsr%d: cam_simq_alloc failure!\n", unit);
3559                 return ENXIO;
3560         }
3561         acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->qbuffer_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
3562         if(acb->psim == NULL) {
3563                 arcmsr_free_resource(acb);
3564                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
3565                 if (acb->irq_type == PCI_INTR_TYPE_MSI)
3566                         pci_release_msi(acb->pci_dev);
3567                 cam_simq_release(devq);
3568                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3569                 kprintf("arcmsr%d: cam_sim_alloc failure!\n", unit);
3570                 return ENXIO;
3571         }
3572         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
3573         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
3574                 arcmsr_free_resource(acb);
3575                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
3576                 if (acb->irq_type == PCI_INTR_TYPE_MSI)
3577                         pci_release_msi(acb->pci_dev);
3578                 cam_sim_free(acb->psim);
3579                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3580                 kprintf("arcmsr%d: xpt_bus_register failure!\n", unit);
3581                 return ENXIO;
3582         }
3583         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3584                 arcmsr_free_resource(acb);
3585                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
3586                 if (acb->irq_type == PCI_INTR_TYPE_MSI)
3587                         pci_release_msi(acb->pci_dev);
3588                 xpt_bus_deregister(cam_sim_path(acb->psim));
3589                 cam_sim_free(acb->psim);
3590                 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3591                 kprintf("arcmsr%d: xpt_create_path failure!\n", unit);
3592                 return ENXIO;
3593         }
3594         /*
3595         ****************************************************
3596         */
3597         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
3598         csa.ccb_h.func_code=XPT_SASYNC_CB;
3599         csa.event_enable=AC_FOUND_DEVICE|AC_LOST_DEVICE;
3600         csa.callback=arcmsr_async;
3601         csa.callback_arg=acb->psim;
3602         xpt_action((union ccb *)&csa);
3603         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
3604         /* Create the control device.  */
3605         acb->ioctl_dev=make_dev(&arcmsr_ops, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
3606
3607         acb->ioctl_dev->si_drv1=acb;
3608         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
3609         callout_init(&acb->devmap_callout);
3610         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
3611         return 0;
3612 }
3613 /*
3614 ************************************************************************
3615 ************************************************************************
3616 */
3617 static int arcmsr_probe(device_t dev)
3618 {
3619         u_int32_t id;
3620         static char buf[256];
3621         char x_type[]={"X-TYPE"};
3622         char *type;
3623         int raid6 = 1;
3624
3625         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
3626                 return (ENXIO);
3627         }
3628         switch(id=pci_get_devid(dev)) {
3629         case PCIDevVenIDARC1110:
3630         case PCIDevVenIDARC1200:
3631         case PCIDevVenIDARC1201:
3632         case PCIDevVenIDARC1210:
3633                 raid6 = 0;
3634                 /*FALLTHRU*/
3635         case PCIDevVenIDARC1120:
3636         case PCIDevVenIDARC1130:
3637         case PCIDevVenIDARC1160:
3638         case PCIDevVenIDARC1170:
3639         case PCIDevVenIDARC1220:
3640         case PCIDevVenIDARC1230:
3641         case PCIDevVenIDARC1231:
3642         case PCIDevVenIDARC1260:
3643         case PCIDevVenIDARC1261:
3644         case PCIDevVenIDARC1270:
3645         case PCIDevVenIDARC1280:
3646                 type = "SATA";
3647                 break;
3648         case PCIDevVenIDARC1212:
3649         case PCIDevVenIDARC1222:
3650         case PCIDevVenIDARC1380:
3651         case PCIDevVenIDARC1381:
3652         case PCIDevVenIDARC1680:
3653         case PCIDevVenIDARC1681:
3654                 type = "SAS 3G";
3655                 break;
3656         case PCIDevVenIDARC1880:
3657                 type = "SAS 6G";
3658                 break;
3659         default:
3660                 type = x_type;
3661                 break;
3662         }
3663         if(type == x_type)
3664                 return(ENXIO);
3665         ksprintf(buf, "Areca %s Host Adapter RAID Controller%s", type, raid6 ? " (RAID6 capable)" : "");
3666         device_set_desc_copy(dev, buf);
3667         return 0;
3668 }
3669 /*
3670 ************************************************************************
3671 ************************************************************************
3672 */
3673 static int arcmsr_shutdown(device_t dev)
3674 {
3675         u_int32_t  i;
3676         u_int32_t intmask_org;
3677         struct CommandControlBlock *srb;
3678         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
3679
3680         /* stop adapter background rebuild */
3681         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
3682         /* disable all outbound interrupt */
3683         intmask_org=arcmsr_disable_allintr(acb);
3684         arcmsr_stop_adapter_bgrb(acb);
3685         arcmsr_flush_adapter_cache(acb);
3686         /* abort all outstanding command */
3687         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
3688         acb->acb_flags &= ~ACB_F_IOP_INITED;
3689         if(acb->srboutstandingcount!=0) {
3690                 /*clear and abort all outbound posted Q*/
3691                 arcmsr_done4abort_postqueue(acb);
3692                 /* talk to iop 331 outstanding command aborted*/
3693                 arcmsr_abort_allcmd(acb);
3694                 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
3695                         srb=acb->psrb_pool[i];
3696                         if(srb->startdone==ARCMSR_SRB_START) {
3697                                 srb->startdone=ARCMSR_SRB_ABORTED;
3698                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3699                                 arcmsr_srb_complete(srb, 1);
3700                         }
3701                 }
3702         }
3703         atomic_set_int(&acb->srboutstandingcount, 0);
3704         acb->workingsrb_doneindex=0;
3705         acb->workingsrb_startindex=0;
3706         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
3707         return (0);
3708 }
3709 /*
3710 ************************************************************************
3711 ************************************************************************
3712 */
3713 static int arcmsr_detach(device_t dev)
3714 {
3715         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
3716         int i;
3717
3718         callout_stop(&acb->devmap_callout);
3719         bus_teardown_intr(dev, acb->irqres, acb->ih);
3720         arcmsr_shutdown(dev);
3721         arcmsr_free_resource(acb);
3722         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
3723                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
3724         }
3725         bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
3726         if (acb->irq_type == PCI_INTR_TYPE_MSI)
3727                 pci_release_msi(acb->pci_dev);
3728         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
3729         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
3730         xpt_free_path(acb->ppath);
3731         xpt_bus_deregister(cam_sim_path(acb->psim));
3732         cam_sim_free(acb->psim);
3733         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
3734         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3735         return (0);
3736 }