2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.17 2004/09/14 22:44:46 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
40 * series chips and several workalikes including the following:
42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
44 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
45 * ASIX Electronics AX88140A (www.asix.com.tw)
46 * ASIX Electronics AX88141 (www.asix.com.tw)
47 * ADMtek AL981 (www.admtek.com.tw)
48 * ADMtek AN985 (www.admtek.com.tw)
49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
50 * Accton EN1217 (www.accton.com)
51 * Conexant LANfinity (www.conexant.com)
53 * Datasheets for the 21143 are available at developer.intel.com.
54 * Datasheets for the clone parts can be found at their respective sites.
55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
56 * The PNIC II is essentially a Macronix 98715A chip; the only difference
57 * worth noting is that its multicast hash table is only 128 bits wide
60 * Written by Bill Paul <wpaul@ee.columbia.edu>
61 * Electrical Engineering Department
62 * Columbia University, New York City
66 * The Intel 21143 is the successor to the DEC 21140. It is basically
67 * the same as the 21140 but with a few new features. The 21143 supports
68 * three kinds of media attachments:
70 * o MII port, for 10Mbps and 100Mbps support and NWAY
71 * autonegotiation provided by an external PHY.
72 * o SYM port, for symbol mode 100Mbps support.
76 * The 100Mbps SYM port and 10baseT port can be used together in
77 * combination with the internal NWAY support to create a 10/100
78 * autosensing configuration.
80 * Note that not all tulip workalikes are handled in this driver: we only
81 * deal with those which are relatively well behaved. The Winbond is
82 * handled separately due to its different register offsets and the
83 * special handling needed for its various bugs. The PNIC is handled
84 * here, but I'm not thrilled about it.
86 * All of the workalike chips use some form of MII transceiver support
87 * with the exception of the Macronix chips, which also have a SYM port.
88 * The ASIX AX88140A is also documented to have a SYM port, but all
89 * the cards I've seen use an MII transceiver, probably because the
90 * AX88140A doesn't support internal NWAY.
93 #include <sys/param.h>
94 #include <sys/systm.h>
95 #include <sys/sockio.h>
97 #include <sys/malloc.h>
98 #include <sys/kernel.h>
99 #include <sys/socket.h>
100 #include <sys/sysctl.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108 #include <net/vlan/if_vlan_var.h>
112 #include <vm/vm.h> /* for vtophys */
113 #include <vm/pmap.h> /* for vtophys */
114 #include <machine/clock.h> /* for DELAY */
115 #include <machine/bus_pio.h>
116 #include <machine/bus_memio.h>
117 #include <machine/bus.h>
118 #include <machine/resource.h>
120 #include <sys/rman.h>
122 #include "../mii_layer/mii.h"
123 #include "../mii_layer/miivar.h"
125 #include <bus/pci/pcireg.h>
126 #include <bus/pci/pcivar.h>
128 #define DC_USEIOSPACE
133 #include "if_dcreg.h"
135 /* "controller miibus0" required. See GENERIC if you get errors here. */
136 #include "miibus_if.h"
139 * Various supported device vendors/types and their names.
141 static struct dc_type dc_devs[] = {
142 { DC_VENDORID_DEC, DC_DEVICEID_21143,
143 "Intel 21143 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
145 "Davicom DM9009 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
147 "Davicom DM9100 10/100BaseTX" },
148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
149 "Davicom DM9102 10/100BaseTX" },
150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
151 "Davicom DM9102A 10/100BaseTX" },
152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
153 "ADMtek AL981 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
155 "ADMtek AN985 10/100BaseTX" },
156 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
157 "ASIX AX88140A 10/100BaseTX" },
158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
159 "ASIX AX88141 10/100BaseTX" },
160 { DC_VENDORID_MX, DC_DEVICEID_98713,
161 "Macronix 98713 10/100BaseTX" },
162 { DC_VENDORID_MX, DC_DEVICEID_98713,
163 "Macronix 98713A 10/100BaseTX" },
164 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
165 "Compex RL100-TX 10/100BaseTX" },
166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
167 "Compex RL100-TX 10/100BaseTX" },
168 { DC_VENDORID_MX, DC_DEVICEID_987x5,
169 "Macronix 98715/98715A 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_987x5,
171 "Macronix 98715AEC-C 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98725 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_98727,
175 "Macronix 98727/98732 10/100BaseTX" },
176 { DC_VENDORID_LO, DC_DEVICEID_82C115,
177 "LC82C115 PNIC II 10/100BaseTX" },
178 { DC_VENDORID_LO, DC_DEVICEID_82C168,
179 "82c168 PNIC 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C168,
181 "82c169 PNIC 10/100BaseTX" },
182 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
183 "Accton EN1217 10/100BaseTX" },
184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
185 "Accton EN2242 MiniPCI 10/100BaseTX" },
186 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
187 "Conexant LANfinity MiniPCI 10/100BaseTX" },
188 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
189 "3Com OfficeConnect 10/100B" },
193 static int dc_probe (device_t);
194 static int dc_attach (device_t);
195 static int dc_detach (device_t);
196 static int dc_suspend (device_t);
197 static int dc_resume (device_t);
198 static void dc_acpi (device_t);
199 static struct dc_type *dc_devtype (device_t);
200 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
201 static int dc_encap (struct dc_softc *, struct mbuf *,
203 static int dc_coal (struct dc_softc *, struct mbuf **);
204 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
205 static int dc_rx_resync (struct dc_softc *);
206 static void dc_rxeof (struct dc_softc *);
207 static void dc_txeof (struct dc_softc *);
208 static void dc_tick (void *);
209 static void dc_tx_underrun (struct dc_softc *);
210 static void dc_intr (void *);
211 static void dc_start (struct ifnet *);
212 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
214 static void dc_init (void *);
215 static void dc_stop (struct dc_softc *);
216 static void dc_watchdog (struct ifnet *);
217 static void dc_shutdown (device_t);
218 static int dc_ifmedia_upd (struct ifnet *);
219 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
221 static void dc_delay (struct dc_softc *);
222 static void dc_eeprom_idle (struct dc_softc *);
223 static void dc_eeprom_putbyte (struct dc_softc *, int);
224 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
225 static void dc_eeprom_getword_pnic
226 (struct dc_softc *, int, u_int16_t *);
227 static void dc_eeprom_width (struct dc_softc *);
228 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
231 static void dc_mii_writebit (struct dc_softc *, int);
232 static int dc_mii_readbit (struct dc_softc *);
233 static void dc_mii_sync (struct dc_softc *);
234 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
235 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
236 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
237 static int dc_miibus_readreg (device_t, int, int);
238 static int dc_miibus_writereg (device_t, int, int, int);
239 static void dc_miibus_statchg (device_t);
240 static void dc_miibus_mediainit (device_t);
242 static void dc_setcfg (struct dc_softc *, int);
243 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t);
244 static u_int32_t dc_crc_be (caddr_t);
245 static void dc_setfilt_21143 (struct dc_softc *);
246 static void dc_setfilt_asix (struct dc_softc *);
247 static void dc_setfilt_admtek (struct dc_softc *);
249 static void dc_setfilt (struct dc_softc *);
251 static void dc_reset (struct dc_softc *);
252 static int dc_list_rx_init (struct dc_softc *);
253 static int dc_list_tx_init (struct dc_softc *);
255 static void dc_read_srom (struct dc_softc *, int);
256 static void dc_parse_21143_srom (struct dc_softc *);
257 static void dc_decode_leaf_sia (struct dc_softc *,
258 struct dc_eblock_sia *);
259 static void dc_decode_leaf_mii (struct dc_softc *,
260 struct dc_eblock_mii *);
261 static void dc_decode_leaf_sym (struct dc_softc *,
262 struct dc_eblock_sym *);
263 static void dc_apply_fixup (struct dc_softc *, int);
266 #define DC_RES SYS_RES_IOPORT
267 #define DC_RID DC_PCI_CFBIO
269 #define DC_RES SYS_RES_MEMORY
270 #define DC_RID DC_PCI_CFBMA
273 static device_method_t dc_methods[] = {
274 /* Device interface */
275 DEVMETHOD(device_probe, dc_probe),
276 DEVMETHOD(device_attach, dc_attach),
277 DEVMETHOD(device_detach, dc_detach),
278 DEVMETHOD(device_suspend, dc_suspend),
279 DEVMETHOD(device_resume, dc_resume),
280 DEVMETHOD(device_shutdown, dc_shutdown),
283 DEVMETHOD(bus_print_child, bus_generic_print_child),
284 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
287 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
288 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
289 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
290 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
295 static driver_t dc_driver = {
298 sizeof(struct dc_softc)
301 static devclass_t dc_devclass;
304 static int dc_quick=1;
305 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
306 &dc_quick,0,"do not mdevget in dc driver");
309 DECLARE_DUMMY_MODULE(if_dc);
310 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
311 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
313 #define DC_SETBIT(sc, reg, x) \
314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
316 #define DC_CLRBIT(sc, reg, x) \
317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
319 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
320 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
322 static void dc_delay(sc)
327 for (idx = (300 / 33) + 1; idx > 0; idx--)
328 CSR_READ_4(sc, DC_BUSCTL);
331 static void dc_eeprom_width(sc)
336 /* Force EEPROM to idle state. */
339 /* Enter EEPROM access mode. */
340 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
342 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
346 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
351 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
353 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 for (i = 1; i <= 12; i++) {
362 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
364 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
373 /* Turn off EEPROM access mode. */
381 /* Enter EEPROM access mode. */
382 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
384 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
391 /* Turn off EEPROM access mode. */
395 static void dc_eeprom_idle(sc)
400 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
402 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
409 for (i = 0; i < 25; i++) {
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
420 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
426 * Send a read command and address to the EEPROM, check for ACK.
428 static void dc_eeprom_putbyte(sc, addr)
434 d = DC_EECMD_READ >> 6;
437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
448 * Feed in each bit and strobe the clock.
450 for (i = sc->dc_romwidth; i--;) {
451 if (addr & (1 << i)) {
452 SIO_SET(DC_SIO_EE_DATAIN);
454 SIO_CLR(DC_SIO_EE_DATAIN);
457 SIO_SET(DC_SIO_EE_CLK);
459 SIO_CLR(DC_SIO_EE_CLK);
467 * Read a word of data stored in the EEPROM at address 'addr.'
468 * The PNIC 82c168/82c169 has its own non-standard way to read
471 static void dc_eeprom_getword_pnic(sc, addr, dest)
479 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
481 for (i = 0; i < DC_TIMEOUT; i++) {
483 r = CSR_READ_4(sc, DC_SIO);
484 if (!(r & DC_PN_SIOCTL_BUSY)) {
485 *dest = (u_int16_t)(r & 0xFFFF);
494 * Read a word of data stored in the EEPROM at address 'addr.'
496 static void dc_eeprom_getword(sc, addr, dest)
504 /* Force EEPROM to idle state. */
507 /* Enter EEPROM access mode. */
508 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
510 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
512 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
514 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
518 * Send address of word we want to read.
520 dc_eeprom_putbyte(sc, addr);
523 * Start reading bits from EEPROM.
525 for (i = 0x8000; i; i >>= 1) {
526 SIO_SET(DC_SIO_EE_CLK);
528 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
531 SIO_CLR(DC_SIO_EE_CLK);
535 /* Turn off EEPROM access mode. */
544 * Read a sequence of words from the EEPROM.
546 static void dc_read_eeprom(sc, dest, off, cnt, swap)
554 u_int16_t word = 0, *ptr;
556 for (i = 0; i < cnt; i++) {
558 dc_eeprom_getword_pnic(sc, off + i, &word);
560 dc_eeprom_getword(sc, off + i, &word);
561 ptr = (u_int16_t *)(dest + (i * 2));
572 * The following two routines are taken from the Macronix 98713
573 * Application Notes pp.19-21.
576 * Write a bit to the MII bus.
578 static void dc_mii_writebit(sc, bit)
583 CSR_WRITE_4(sc, DC_SIO,
584 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
586 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
588 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
589 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
595 * Read a bit from the MII bus.
597 static int dc_mii_readbit(sc)
600 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
601 CSR_READ_4(sc, DC_SIO);
602 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
603 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
604 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
611 * Sync the PHYs by setting data bit and strobing the clock 32 times.
613 static void dc_mii_sync(sc)
618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
620 for (i = 0; i < 32; i++)
621 dc_mii_writebit(sc, 1);
627 * Clock a series of bits through the MII.
629 static void dc_mii_send(sc, bits, cnt)
636 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
637 dc_mii_writebit(sc, bits & i);
641 * Read an PHY register through the MII.
643 static int dc_mii_readreg(sc, frame)
645 struct dc_mii_frame *frame;
653 * Set up frame for RX.
655 frame->mii_stdelim = DC_MII_STARTDELIM;
656 frame->mii_opcode = DC_MII_READOP;
657 frame->mii_turnaround = 0;
666 * Send command/address info.
668 dc_mii_send(sc, frame->mii_stdelim, 2);
669 dc_mii_send(sc, frame->mii_opcode, 2);
670 dc_mii_send(sc, frame->mii_phyaddr, 5);
671 dc_mii_send(sc, frame->mii_regaddr, 5);
675 dc_mii_writebit(sc, 1);
676 dc_mii_writebit(sc, 0);
680 ack = dc_mii_readbit(sc);
683 * Now try reading data bits. If the ack failed, we still
684 * need to clock through 16 cycles to keep the PHY(s) in sync.
687 for(i = 0; i < 16; i++) {
693 for (i = 0x8000; i; i >>= 1) {
695 if (dc_mii_readbit(sc))
696 frame->mii_data |= i;
702 dc_mii_writebit(sc, 0);
703 dc_mii_writebit(sc, 0);
713 * Write to a PHY register through the MII.
715 static int dc_mii_writereg(sc, frame)
717 struct dc_mii_frame *frame;
724 * Set up frame for TX.
727 frame->mii_stdelim = DC_MII_STARTDELIM;
728 frame->mii_opcode = DC_MII_WRITEOP;
729 frame->mii_turnaround = DC_MII_TURNAROUND;
736 dc_mii_send(sc, frame->mii_stdelim, 2);
737 dc_mii_send(sc, frame->mii_opcode, 2);
738 dc_mii_send(sc, frame->mii_phyaddr, 5);
739 dc_mii_send(sc, frame->mii_regaddr, 5);
740 dc_mii_send(sc, frame->mii_turnaround, 2);
741 dc_mii_send(sc, frame->mii_data, 16);
744 dc_mii_writebit(sc, 0);
745 dc_mii_writebit(sc, 0);
752 static int dc_miibus_readreg(dev, phy, reg)
756 struct dc_mii_frame frame;
758 int i, rval, phy_reg = 0;
760 sc = device_get_softc(dev);
761 bzero((char *)&frame, sizeof(frame));
764 * Note: both the AL981 and AN985 have internal PHYs,
765 * however the AL981 provides direct access to the PHY
766 * registers while the AN985 uses a serial MII interface.
767 * The AN985's MII interface is also buggy in that you
768 * can read from any MII address (0 to 31), but only address 1
769 * behaves normally. To deal with both cases, we pretend
770 * that the PHY is at MII address 1.
772 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
776 * Note: the ukphy probes of the RS7112 report a PHY at
777 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
778 * so we only respond to correct one.
780 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
783 if (sc->dc_pmode != DC_PMODE_MII) {
784 if (phy == (MII_NPHY - 1)) {
788 * Fake something to make the probe
789 * code think there's a PHY here.
791 return(BMSR_MEDIAMASK);
795 return(DC_VENDORID_LO);
796 return(DC_VENDORID_DEC);
800 return(DC_DEVICEID_82C168);
801 return(DC_DEVICEID_21143);
811 if (DC_IS_PNIC(sc)) {
812 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
813 (phy << 23) | (reg << 18));
814 for (i = 0; i < DC_TIMEOUT; i++) {
816 rval = CSR_READ_4(sc, DC_PN_MII);
817 if (!(rval & DC_PN_MII_BUSY)) {
819 return(rval == 0xFFFF ? 0 : rval);
825 if (DC_IS_COMET(sc)) {
828 phy_reg = DC_AL_BMCR;
831 phy_reg = DC_AL_BMSR;
834 phy_reg = DC_AL_VENID;
837 phy_reg = DC_AL_DEVID;
840 phy_reg = DC_AL_ANAR;
843 phy_reg = DC_AL_LPAR;
846 phy_reg = DC_AL_ANER;
849 printf("dc%d: phy_read: bad phy register %x\n",
855 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
862 frame.mii_phyaddr = phy;
863 frame.mii_regaddr = reg;
864 if (sc->dc_type == DC_TYPE_98713) {
865 phy_reg = CSR_READ_4(sc, DC_NETCFG);
866 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
868 dc_mii_readreg(sc, &frame);
869 if (sc->dc_type == DC_TYPE_98713)
870 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
872 return(frame.mii_data);
875 static int dc_miibus_writereg(dev, phy, reg, data)
880 struct dc_mii_frame frame;
883 sc = device_get_softc(dev);
884 bzero((char *)&frame, sizeof(frame));
886 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
889 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
892 if (DC_IS_PNIC(sc)) {
893 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
894 (phy << 23) | (reg << 10) | data);
895 for (i = 0; i < DC_TIMEOUT; i++) {
896 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
902 if (DC_IS_COMET(sc)) {
905 phy_reg = DC_AL_BMCR;
908 phy_reg = DC_AL_BMSR;
911 phy_reg = DC_AL_VENID;
914 phy_reg = DC_AL_DEVID;
917 phy_reg = DC_AL_ANAR;
920 phy_reg = DC_AL_LPAR;
923 phy_reg = DC_AL_ANER;
926 printf("dc%d: phy_write: bad phy register %x\n",
932 CSR_WRITE_4(sc, phy_reg, data);
936 frame.mii_phyaddr = phy;
937 frame.mii_regaddr = reg;
938 frame.mii_data = data;
940 if (sc->dc_type == DC_TYPE_98713) {
941 phy_reg = CSR_READ_4(sc, DC_NETCFG);
942 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
944 dc_mii_writereg(sc, &frame);
945 if (sc->dc_type == DC_TYPE_98713)
946 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
951 static void dc_miibus_statchg(dev)
955 struct mii_data *mii;
958 sc = device_get_softc(dev);
959 if (DC_IS_ADMTEK(sc))
962 mii = device_get_softc(sc->dc_miibus);
963 ifm = &mii->mii_media;
964 if (DC_IS_DAVICOM(sc) &&
965 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
966 dc_setcfg(sc, ifm->ifm_media);
967 sc->dc_if_media = ifm->ifm_media;
969 dc_setcfg(sc, mii->mii_media_active);
970 sc->dc_if_media = mii->mii_media_active;
977 * Special support for DM9102A cards with HomePNA PHYs. Note:
978 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
979 * to be impossible to talk to the management interface of the DM9801
980 * PHY (its MDIO pin is not connected to anything). Consequently,
981 * the driver has to just 'know' about the additional mode and deal
982 * with it itself. *sigh*
984 static void dc_miibus_mediainit(dev)
988 struct mii_data *mii;
992 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
994 sc = device_get_softc(dev);
995 mii = device_get_softc(sc->dc_miibus);
996 ifm = &mii->mii_media;
998 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
999 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL);
1004 #define DC_POLY 0xEDB88320
1005 #define DC_BITS_512 9
1006 #define DC_BITS_128 7
1007 #define DC_BITS_64 6
1009 static u_int32_t dc_crc_le(sc, addr)
1010 struct dc_softc *sc;
1013 u_int32_t idx, bit, data, crc;
1015 /* Compute CRC for the address value. */
1016 crc = 0xFFFFFFFF; /* initial value */
1018 for (idx = 0; idx < 6; idx++) {
1019 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1020 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1024 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1025 * chips is only 128 bits wide.
1027 if (sc->dc_flags & DC_128BIT_HASH)
1028 return (crc & ((1 << DC_BITS_128) - 1));
1030 /* The hash table on the MX98715BEC is only 64 bits wide. */
1031 if (sc->dc_flags & DC_64BIT_HASH)
1032 return (crc & ((1 << DC_BITS_64) - 1));
1034 return (crc & ((1 << DC_BITS_512) - 1));
1038 * Calculate CRC of a multicast group address, return the lower 6 bits.
1040 static u_int32_t dc_crc_be(addr)
1043 u_int32_t crc, carry;
1047 /* Compute CRC for the address value. */
1048 crc = 0xFFFFFFFF; /* initial value */
1050 for (i = 0; i < 6; i++) {
1052 for (j = 0; j < 8; j++) {
1053 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1057 crc = (crc ^ 0x04c11db6) | carry;
1061 /* return the filter bit position */
1062 return((crc >> 26) & 0x0000003F);
1066 * 21143-style RX filter setup routine. Filter programming is done by
1067 * downloading a special setup frame into the TX engine. 21143, Macronix,
1068 * PNIC, PNIC II and Davicom chips are programmed this way.
1070 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1071 * address (our node address) and a 512-bit hash filter for multicast
1072 * frames. We also sneak the broadcast address into the hash filter since
1075 void dc_setfilt_21143(sc)
1076 struct dc_softc *sc;
1078 struct dc_desc *sframe;
1080 struct ifmultiaddr *ifma;
1084 ifp = &sc->arpcom.ac_if;
1086 i = sc->dc_cdata.dc_tx_prod;
1087 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1088 sc->dc_cdata.dc_tx_cnt++;
1089 sframe = &sc->dc_ldata->dc_tx_list[i];
1090 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1091 bzero((char *)sp, DC_SFRAME_LEN);
1093 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1094 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1095 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1097 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1099 /* If we want promiscuous mode, set the allframes bit. */
1100 if (ifp->if_flags & IFF_PROMISC)
1101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1103 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1105 if (ifp->if_flags & IFF_ALLMULTI)
1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1110 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1111 ifma = ifma->ifma_link.le_next) {
1112 if (ifma->ifma_addr->sa_family != AF_LINK)
1115 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1116 sp[h >> 4] |= 1 << (h & 0xF);
1119 if (ifp->if_flags & IFF_BROADCAST) {
1120 h = dc_crc_le(sc, ifp->if_broadcastaddr);
1121 sp[h >> 4] |= 1 << (h & 0xF);
1124 /* Set our MAC address */
1125 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1126 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1127 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1129 sframe->dc_status = DC_TXSTAT_OWN;
1130 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1133 * The PNIC takes an exceedingly long time to process its
1134 * setup frame; wait 10ms after posting the setup frame
1135 * before proceeding, just so it has time to swallow its
1145 void dc_setfilt_admtek(sc)
1146 struct dc_softc *sc;
1150 u_int32_t hashes[2] = { 0, 0 };
1151 struct ifmultiaddr *ifma;
1153 ifp = &sc->arpcom.ac_if;
1155 /* Init our MAC address */
1156 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1157 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1159 /* If we want promiscuous mode, set the allframes bit. */
1160 if (ifp->if_flags & IFF_PROMISC)
1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1165 if (ifp->if_flags & IFF_ALLMULTI)
1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1170 /* first, zot all the existing hash bits */
1171 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1172 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1175 * If we're already in promisc or allmulti mode, we
1176 * don't have to bother programming the multicast filter.
1178 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1181 /* now program new ones */
1182 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1183 ifma = ifma->ifma_link.le_next) {
1184 if (ifma->ifma_addr->sa_family != AF_LINK)
1186 if (DC_IS_CENTAUR(sc))
1187 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1189 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1191 hashes[0] |= (1 << h);
1193 hashes[1] |= (1 << (h - 32));
1196 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1197 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1202 void dc_setfilt_asix(sc)
1203 struct dc_softc *sc;
1207 u_int32_t hashes[2] = { 0, 0 };
1208 struct ifmultiaddr *ifma;
1210 ifp = &sc->arpcom.ac_if;
1212 /* Init our MAC address */
1213 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1214 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1215 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1217 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1218 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1220 /* If we want promiscuous mode, set the allframes bit. */
1221 if (ifp->if_flags & IFF_PROMISC)
1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1226 if (ifp->if_flags & IFF_ALLMULTI)
1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1232 * The ASIX chip has a special bit to enable reception
1233 * of broadcast frames.
1235 if (ifp->if_flags & IFF_BROADCAST)
1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1240 /* first, zot all the existing hash bits */
1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1247 * If we're already in promisc or allmulti mode, we
1248 * don't have to bother programming the multicast filter.
1250 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1253 /* now program new ones */
1254 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1255 ifma = ifma->ifma_link.le_next) {
1256 if (ifma->ifma_addr->sa_family != AF_LINK)
1258 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1260 hashes[0] |= (1 << h);
1262 hashes[1] |= (1 << (h - 32));
1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1273 static void dc_setfilt(sc)
1274 struct dc_softc *sc;
1276 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1277 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1278 dc_setfilt_21143(sc);
1281 dc_setfilt_asix(sc);
1283 if (DC_IS_ADMTEK(sc))
1284 dc_setfilt_admtek(sc);
1290 * In order to fiddle with the
1291 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1292 * first have to put the transmit and/or receive logic in the idle state.
1294 static void dc_setcfg(sc, media)
1295 struct dc_softc *sc;
1301 if (IFM_SUBTYPE(media) == IFM_NONE)
1304 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1306 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1308 for (i = 0; i < DC_TIMEOUT; i++) {
1309 isr = CSR_READ_4(sc, DC_ISR);
1310 if (isr & DC_ISR_TX_IDLE ||
1311 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1316 if (i == DC_TIMEOUT)
1317 printf("dc%d: failed to force tx and "
1318 "rx to idle state\n", sc->dc_unit);
1321 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1322 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1324 if (sc->dc_pmode == DC_PMODE_MII) {
1327 if (DC_IS_INTEL(sc)) {
1328 /* there's a write enable bit here that reads as 1 */
1329 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1330 watchdogreg &= ~DC_WDOG_CTLWREN;
1331 watchdogreg |= DC_WDOG_JABBERDIS;
1332 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1334 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1336 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1337 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1338 if (sc->dc_type == DC_TYPE_98713)
1339 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1340 DC_NETCFG_SCRAMBLER));
1341 if (!DC_IS_DAVICOM(sc))
1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1343 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1344 if (DC_IS_INTEL(sc))
1345 dc_apply_fixup(sc, IFM_AUTO);
1347 if (DC_IS_PNIC(sc)) {
1348 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1350 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1353 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1355 if (DC_IS_INTEL(sc))
1357 (media & IFM_GMASK) == IFM_FDX ?
1358 IFM_100_TX|IFM_FDX : IFM_100_TX);
1362 if (IFM_SUBTYPE(media) == IFM_10_T) {
1363 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1364 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1365 if (sc->dc_pmode == DC_PMODE_MII) {
1368 /* there's a write enable bit here that reads as 1 */
1369 if (DC_IS_INTEL(sc)) {
1370 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1371 watchdogreg &= ~DC_WDOG_CTLWREN;
1372 watchdogreg |= DC_WDOG_JABBERDIS;
1373 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1375 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1378 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1379 if (sc->dc_type == DC_TYPE_98713)
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1381 if (!DC_IS_DAVICOM(sc))
1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1383 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1384 if (DC_IS_INTEL(sc))
1385 dc_apply_fixup(sc, IFM_AUTO);
1387 if (DC_IS_PNIC(sc)) {
1388 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1389 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1390 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1393 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1395 if (DC_IS_INTEL(sc)) {
1396 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1397 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1398 if ((media & IFM_GMASK) == IFM_FDX)
1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1401 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1402 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1403 DC_CLRBIT(sc, DC_10BTCTRL,
1404 DC_TCTL_AUTONEGENBL);
1406 (media & IFM_GMASK) == IFM_FDX ?
1407 IFM_10_T|IFM_FDX : IFM_10_T);
1414 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1415 * PHY and we want HomePNA mode, set the portsel bit to turn
1416 * on the external MII port.
1418 if (DC_IS_DAVICOM(sc)) {
1419 if (IFM_SUBTYPE(media) == IFM_homePNA) {
1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1423 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1427 if ((media & IFM_GMASK) == IFM_FDX) {
1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1429 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1430 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1433 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1434 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1443 static void dc_reset(sc)
1444 struct dc_softc *sc;
1448 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1450 for (i = 0; i < DC_TIMEOUT; i++) {
1452 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1456 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1458 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1462 if (i == DC_TIMEOUT)
1463 printf("dc%d: reset never completed!\n", sc->dc_unit);
1465 /* Wait a little while for the chip to get its brains in order. */
1468 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1469 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1470 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1473 * Bring the SIA out of reset. In some cases, it looks
1474 * like failing to unreset the SIA soon enough gets it
1475 * into a state where it will never come out of reset
1476 * until we reset the whole chip again.
1478 if (DC_IS_INTEL(sc)) {
1479 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1480 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1481 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1487 static struct dc_type *dc_devtype(dev)
1495 while(t->dc_name != NULL) {
1496 if ((pci_get_vendor(dev) == t->dc_vid) &&
1497 (pci_get_device(dev) == t->dc_did)) {
1498 /* Check the PCI revision */
1499 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1500 if (t->dc_did == DC_DEVICEID_98713 &&
1501 rev >= DC_REVISION_98713A)
1503 if (t->dc_did == DC_DEVICEID_98713_CP &&
1504 rev >= DC_REVISION_98713A)
1506 if (t->dc_did == DC_DEVICEID_987x5 &&
1507 rev >= DC_REVISION_98715AEC_C)
1509 if (t->dc_did == DC_DEVICEID_987x5 &&
1510 rev >= DC_REVISION_98725)
1512 if (t->dc_did == DC_DEVICEID_AX88140A &&
1513 rev >= DC_REVISION_88141)
1515 if (t->dc_did == DC_DEVICEID_82C168 &&
1516 rev >= DC_REVISION_82C169)
1518 if (t->dc_did == DC_DEVICEID_DM9102 &&
1519 rev >= DC_REVISION_DM9102A)
1530 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1531 * IDs against our list and return a device name if we find a match.
1532 * We do a little bit of extra work to identify the exact type of
1533 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1534 * but different revision IDs. The same is true for 98715/98715A
1535 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1536 * cases, the exact chip revision affects driver behavior.
1538 static int dc_probe(dev)
1543 t = dc_devtype(dev);
1546 device_set_desc(dev, t->dc_name);
1553 static void dc_acpi(dev)
1559 unit = device_get_unit(dev);
1561 /* Find the location of the capabilities block */
1562 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1564 r = pci_read_config(dev, cptr, 4) & 0xFF;
1567 r = pci_read_config(dev, cptr + 4, 4);
1568 if (r & DC_PSTATE_D3) {
1569 u_int32_t iobase, membase, irq;
1571 /* Save important PCI config data. */
1572 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1573 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1574 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1576 /* Reset the power state. */
1577 printf("dc%d: chip is in D%d power mode "
1578 "-- setting to D0\n", unit, r & DC_PSTATE_D3);
1580 pci_write_config(dev, cptr + 4, r, 4);
1582 /* Restore PCI config data. */
1583 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1584 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1585 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1591 static void dc_apply_fixup(sc, media)
1592 struct dc_softc *sc;
1595 struct dc_mediainfo *m;
1603 if (m->dc_media == media)
1611 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1612 reg = (p[0] | (p[1] << 8)) << 16;
1613 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1616 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1617 reg = (p[0] | (p[1] << 8)) << 16;
1618 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1624 static void dc_decode_leaf_sia(sc, l)
1625 struct dc_softc *sc;
1626 struct dc_eblock_sia *l;
1628 struct dc_mediainfo *m;
1630 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1631 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1632 m->dc_media = IFM_10_T;
1634 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1635 m->dc_media = IFM_10_T|IFM_FDX;
1637 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1638 m->dc_media = IFM_10_2;
1640 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1641 m->dc_media = IFM_10_5;
1644 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1646 m->dc_next = sc->dc_mi;
1649 sc->dc_pmode = DC_PMODE_SIA;
1654 static void dc_decode_leaf_sym(sc, l)
1655 struct dc_softc *sc;
1656 struct dc_eblock_sym *l;
1658 struct dc_mediainfo *m;
1660 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1661 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1662 m->dc_media = IFM_100_TX;
1664 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1665 m->dc_media = IFM_100_TX|IFM_FDX;
1668 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1670 m->dc_next = sc->dc_mi;
1673 sc->dc_pmode = DC_PMODE_SYM;
1678 static void dc_decode_leaf_mii(sc, l)
1679 struct dc_softc *sc;
1680 struct dc_eblock_mii *l;
1683 struct dc_mediainfo *m;
1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1686 /* We abuse IFM_AUTO to represent MII. */
1687 m->dc_media = IFM_AUTO;
1688 m->dc_gp_len = l->dc_gpr_len;
1691 p += sizeof(struct dc_eblock_mii);
1693 p += 2 * l->dc_gpr_len;
1694 m->dc_reset_len = *p;
1696 m->dc_reset_ptr = p;
1698 m->dc_next = sc->dc_mi;
1704 static void dc_read_srom(sc, bits)
1705 struct dc_softc *sc;
1711 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1712 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1715 static void dc_parse_21143_srom(sc)
1716 struct dc_softc *sc;
1718 struct dc_leaf_hdr *lhdr;
1719 struct dc_eblock_hdr *hdr;
1725 loff = sc->dc_srom[27];
1726 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1729 ptr += sizeof(struct dc_leaf_hdr) - 1;
1731 * Look if we got a MII media block.
1733 for (i = 0; i < lhdr->dc_mcnt; i++) {
1734 hdr = (struct dc_eblock_hdr *)ptr;
1735 if (hdr->dc_type == DC_EBLOCK_MII)
1738 ptr += (hdr->dc_len & 0x7F);
1743 * Do the same thing again. Only use SIA and SYM media
1744 * blocks if no MII media block is available.
1747 ptr += sizeof(struct dc_leaf_hdr) - 1;
1748 for (i = 0; i < lhdr->dc_mcnt; i++) {
1749 hdr = (struct dc_eblock_hdr *)ptr;
1750 switch(hdr->dc_type) {
1752 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1756 dc_decode_leaf_sia(sc,
1757 (struct dc_eblock_sia *)hdr);
1761 dc_decode_leaf_sym(sc,
1762 (struct dc_eblock_sym *)hdr);
1765 /* Don't care. Yet. */
1768 ptr += (hdr->dc_len & 0x7F);
1776 * Attach the interface. Allocate softc structures, do ifmedia
1777 * setup and ethernet/BPF attach.
1779 static int dc_attach(dev)
1783 u_char eaddr[ETHER_ADDR_LEN];
1785 struct dc_softc *sc;
1788 int unit, error = 0, rid, mac_offset;
1792 sc = device_get_softc(dev);
1793 unit = device_get_unit(dev);
1794 bzero(sc, sizeof(struct dc_softc));
1795 callout_init(&sc->dc_stat_timer);
1798 * Handle power management nonsense.
1803 * Map control/status registers.
1805 command = pci_read_config(dev, PCIR_COMMAND, 4);
1806 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1807 pci_write_config(dev, PCIR_COMMAND, command, 4);
1808 command = pci_read_config(dev, PCIR_COMMAND, 4);
1810 #ifdef DC_USEIOSPACE
1811 if (!(command & PCIM_CMD_PORTEN)) {
1812 printf("dc%d: failed to enable I/O ports!\n", unit);
1817 if (!(command & PCIM_CMD_MEMEN)) {
1818 printf("dc%d: failed to enable memory mapping!\n", unit);
1825 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1826 0, ~0, 1, RF_ACTIVE);
1828 if (sc->dc_res == NULL) {
1829 printf("dc%d: couldn't map ports/memory\n", unit);
1834 sc->dc_btag = rman_get_bustag(sc->dc_res);
1835 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1837 /* Allocate interrupt */
1839 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1840 RF_SHAREABLE | RF_ACTIVE);
1842 if (sc->dc_irq == NULL) {
1843 printf("dc%d: couldn't map interrupt\n", unit);
1844 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1849 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
1850 dc_intr, sc, &sc->dc_intrhand);
1853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1854 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1855 printf("dc%d: couldn't set up irq\n", unit);
1859 /* Need this info to decide on a chip type. */
1860 sc->dc_info = dc_devtype(dev);
1861 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1863 /* Get the eeprom width, but PNIC has diff eeprom */
1864 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1865 dc_eeprom_width(sc);
1867 switch(sc->dc_info->dc_did) {
1868 case DC_DEVICEID_21143:
1869 sc->dc_type = DC_TYPE_21143;
1870 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1871 sc->dc_flags |= DC_REDUCED_MII_POLL;
1872 /* Save EEPROM contents so we can parse them later. */
1873 dc_read_srom(sc, sc->dc_romwidth);
1875 case DC_DEVICEID_DM9009:
1876 case DC_DEVICEID_DM9100:
1877 case DC_DEVICEID_DM9102:
1878 sc->dc_type = DC_TYPE_DM9102;
1879 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1880 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1881 sc->dc_pmode = DC_PMODE_MII;
1882 /* Increase the latency timer value. */
1883 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1884 command &= 0xFFFF00FF;
1885 command |= 0x00008000;
1886 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1888 case DC_DEVICEID_AL981:
1889 sc->dc_type = DC_TYPE_AL981;
1890 sc->dc_flags |= DC_TX_USE_TX_INTR;
1891 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1892 sc->dc_pmode = DC_PMODE_MII;
1893 dc_read_srom(sc, sc->dc_romwidth);
1895 case DC_DEVICEID_AN985:
1896 case DC_DEVICEID_EN2242:
1897 case DC_DEVICEID_3CSOHOB:
1898 sc->dc_type = DC_TYPE_AN985;
1899 sc->dc_flags |= DC_64BIT_HASH;
1900 sc->dc_flags |= DC_TX_USE_TX_INTR;
1901 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1902 sc->dc_pmode = DC_PMODE_MII;
1903 dc_read_srom(sc, sc->dc_romwidth);
1905 case DC_DEVICEID_98713:
1906 case DC_DEVICEID_98713_CP:
1907 if (revision < DC_REVISION_98713A) {
1908 sc->dc_type = DC_TYPE_98713;
1910 if (revision >= DC_REVISION_98713A) {
1911 sc->dc_type = DC_TYPE_98713A;
1912 sc->dc_flags |= DC_21143_NWAY;
1914 sc->dc_flags |= DC_REDUCED_MII_POLL;
1915 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1917 case DC_DEVICEID_987x5:
1918 case DC_DEVICEID_EN1217:
1920 * Macronix MX98715AEC-C/D/E parts have only a
1921 * 128-bit hash table. We need to deal with these
1922 * in the same manner as the PNIC II so that we
1923 * get the right number of bits out of the
1926 if (revision >= DC_REVISION_98715AEC_C &&
1927 revision < DC_REVISION_98725)
1928 sc->dc_flags |= DC_128BIT_HASH;
1929 sc->dc_type = DC_TYPE_987x5;
1930 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1931 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1933 case DC_DEVICEID_98727:
1934 sc->dc_type = DC_TYPE_987x5;
1935 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1936 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1938 case DC_DEVICEID_82C115:
1939 sc->dc_type = DC_TYPE_PNICII;
1940 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1941 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1943 case DC_DEVICEID_82C168:
1944 sc->dc_type = DC_TYPE_PNIC;
1945 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1946 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1947 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1948 if (revision < DC_REVISION_82C169)
1949 sc->dc_pmode = DC_PMODE_SYM;
1951 case DC_DEVICEID_AX88140A:
1952 sc->dc_type = DC_TYPE_ASIX;
1953 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1954 sc->dc_flags |= DC_REDUCED_MII_POLL;
1955 sc->dc_pmode = DC_PMODE_MII;
1957 case DC_DEVICEID_RS7112:
1958 sc->dc_type = DC_TYPE_CONEXANT;
1959 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1960 sc->dc_flags |= DC_REDUCED_MII_POLL;
1961 sc->dc_pmode = DC_PMODE_MII;
1962 dc_read_srom(sc, sc->dc_romwidth);
1965 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1966 sc->dc_info->dc_did);
1970 /* Save the cache line size. */
1971 if (DC_IS_DAVICOM(sc))
1972 sc->dc_cachesize = 0;
1974 sc->dc_cachesize = pci_read_config(dev,
1975 DC_PCI_CFLT, 4) & 0xFF;
1977 /* Reset the adapter. */
1980 /* Take 21143 out of snooze mode */
1981 if (DC_IS_INTEL(sc)) {
1982 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1983 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1984 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1988 * Try to learn something about the supported media.
1989 * We know that ASIX and ADMtek and Davicom devices
1990 * will *always* be using MII media, so that's a no-brainer.
1991 * The tricky ones are the Macronix/PNIC II and the
1994 if (DC_IS_INTEL(sc))
1995 dc_parse_21143_srom(sc);
1996 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1997 if (sc->dc_type == DC_TYPE_98713)
1998 sc->dc_pmode = DC_PMODE_MII;
2000 sc->dc_pmode = DC_PMODE_SYM;
2001 } else if (!sc->dc_pmode)
2002 sc->dc_pmode = DC_PMODE_MII;
2005 * Get station address from the EEPROM.
2007 switch(sc->dc_type) {
2009 case DC_TYPE_98713A:
2011 case DC_TYPE_PNICII:
2012 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2013 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2014 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2017 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2019 case DC_TYPE_DM9102:
2022 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2026 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2028 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2030 case DC_TYPE_CONEXANT:
2031 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2034 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2040 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2041 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2043 if (sc->dc_ldata == NULL) {
2044 printf("dc%d: no memory for list buffers!\n", unit);
2045 if (sc->dc_pnic_rx_buf != NULL)
2046 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2047 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2049 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2054 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2056 ifp = &sc->arpcom.ac_if;
2058 if_initname(ifp, "dc", unit);
2059 ifp->if_mtu = ETHERMTU;
2060 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2061 ifp->if_ioctl = dc_ioctl;
2062 ifp->if_start = dc_start;
2063 ifp->if_watchdog = dc_watchdog;
2064 ifp->if_init = dc_init;
2065 ifp->if_baudrate = 10000000;
2066 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2069 * Do MII setup. If this is a 21143, check for a PHY on the
2070 * MII bus after applying any necessary fixups to twiddle the
2071 * GPIO bits. If we don't end up finding a PHY, restore the
2072 * old selection (SIA only or SIA/SYM) and attach the dcphy
2075 if (DC_IS_INTEL(sc)) {
2076 dc_apply_fixup(sc, IFM_AUTO);
2078 sc->dc_pmode = DC_PMODE_MII;
2081 error = mii_phy_probe(dev, &sc->dc_miibus,
2082 dc_ifmedia_upd, dc_ifmedia_sts);
2084 if (error && DC_IS_INTEL(sc)) {
2086 if (sc->dc_pmode != DC_PMODE_SIA)
2087 sc->dc_pmode = DC_PMODE_SYM;
2088 sc->dc_flags |= DC_21143_NWAY;
2089 mii_phy_probe(dev, &sc->dc_miibus,
2090 dc_ifmedia_upd, dc_ifmedia_sts);
2092 * For non-MII cards, we need to have the 21143
2093 * drive the LEDs. Except there are some systems
2094 * like the NEC VersaPro NoteBook PC which have no
2095 * LEDs, and twiddling these bits has adverse effects
2096 * on them. (I.e. you suddenly can't get a link.)
2098 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2099 sc->dc_flags |= DC_TULIP_LEDS;
2104 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2105 contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2107 if (sc->dc_pnic_rx_buf != NULL)
2108 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2109 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2110 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2111 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2117 * Call MI attach routine.
2119 ether_ifattach(ifp, eaddr);
2121 if (DC_IS_ADMTEK(sc)) {
2123 * Set automatic TX underrun recovery for the ADMtek chips
2125 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2129 * Tell the upper layer(s) we support long frames.
2131 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2134 sc->dc_srm_media = 0;
2136 /* Remember the SRM console media setting */
2137 if (DC_IS_INTEL(sc)) {
2138 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2139 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2140 switch ((command >> 8) & 0xff) {
2142 sc->dc_srm_media = IFM_10_T;
2145 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2148 sc->dc_srm_media = IFM_100_TX;
2151 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2154 if (sc->dc_srm_media)
2155 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2166 static int dc_detach(dev)
2169 struct dc_softc *sc;
2172 struct dc_mediainfo *m;
2176 sc = device_get_softc(dev);
2177 ifp = &sc->arpcom.ac_if;
2180 ether_ifdetach(ifp);
2182 bus_generic_detach(dev);
2183 device_delete_child(dev, sc->dc_miibus);
2185 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2186 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2187 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2189 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2190 if (sc->dc_pnic_rx_buf != NULL)
2191 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2193 while(sc->dc_mi != NULL) {
2194 m = sc->dc_mi->dc_next;
2195 free(sc->dc_mi, M_DEVBUF);
2198 free(sc->dc_srom, M_DEVBUF);
2206 * Initialize the transmit descriptors.
2208 static int dc_list_tx_init(sc)
2209 struct dc_softc *sc;
2211 struct dc_chain_data *cd;
2212 struct dc_list_data *ld;
2217 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2218 if (i == (DC_TX_LIST_CNT - 1)) {
2219 ld->dc_tx_list[i].dc_next =
2220 vtophys(&ld->dc_tx_list[0]);
2222 ld->dc_tx_list[i].dc_next =
2223 vtophys(&ld->dc_tx_list[i + 1]);
2225 cd->dc_tx_chain[i] = NULL;
2226 ld->dc_tx_list[i].dc_data = 0;
2227 ld->dc_tx_list[i].dc_ctl = 0;
2230 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2237 * Initialize the RX descriptors and allocate mbufs for them. Note that
2238 * we arrange the descriptors in a closed ring, so that the last descriptor
2239 * points back to the first.
2241 static int dc_list_rx_init(sc)
2242 struct dc_softc *sc;
2244 struct dc_chain_data *cd;
2245 struct dc_list_data *ld;
2251 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2252 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2254 if (i == (DC_RX_LIST_CNT - 1)) {
2255 ld->dc_rx_list[i].dc_next =
2256 vtophys(&ld->dc_rx_list[0]);
2258 ld->dc_rx_list[i].dc_next =
2259 vtophys(&ld->dc_rx_list[i + 1]);
2269 * Initialize an RX descriptor and attach an MBUF cluster.
2271 static int dc_newbuf(sc, i, m)
2272 struct dc_softc *sc;
2276 struct mbuf *m_new = NULL;
2279 c = &sc->dc_ldata->dc_rx_list[i];
2282 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
2286 MCLGET(m_new, MB_DONTWAIT);
2287 if (!(m_new->m_flags & M_EXT)) {
2291 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2294 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2295 m_new->m_data = m_new->m_ext.ext_buf;
2298 m_adj(m_new, sizeof(u_int64_t));
2301 * If this is a PNIC chip, zero the buffer. This is part
2302 * of the workaround for the receive bug in the 82c168 and
2305 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2306 bzero((char *)mtod(m_new, char *), m_new->m_len);
2308 sc->dc_cdata.dc_rx_chain[i] = m_new;
2309 c->dc_data = vtophys(mtod(m_new, caddr_t));
2310 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2311 c->dc_status = DC_RXSTAT_OWN;
2318 * The PNIC chip has a terrible bug in it that manifests itself during
2319 * periods of heavy activity. The exact mode of failure if difficult to
2320 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2321 * will happen on slow machines. The bug is that sometimes instead of
2322 * uploading one complete frame during reception, it uploads what looks
2323 * like the entire contents of its FIFO memory. The frame we want is at
2324 * the end of the whole mess, but we never know exactly how much data has
2325 * been uploaded, so salvaging the frame is hard.
2327 * There is only one way to do it reliably, and it's disgusting.
2328 * Here's what we know:
2330 * - We know there will always be somewhere between one and three extra
2331 * descriptors uploaded.
2333 * - We know the desired received frame will always be at the end of the
2334 * total data upload.
2336 * - We know the size of the desired received frame because it will be
2337 * provided in the length field of the status word in the last descriptor.
2339 * Here's what we do:
2341 * - When we allocate buffers for the receive ring, we bzero() them.
2342 * This means that we know that the buffer contents should be all
2343 * zeros, except for data uploaded by the chip.
2345 * - We also force the PNIC chip to upload frames that include the
2346 * ethernet CRC at the end.
2348 * - We gather all of the bogus frame data into a single buffer.
2350 * - We then position a pointer at the end of this buffer and scan
2351 * backwards until we encounter the first non-zero byte of data.
2352 * This is the end of the received frame. We know we will encounter
2353 * some data at the end of the frame because the CRC will always be
2354 * there, so even if the sender transmits a packet of all zeros,
2355 * we won't be fooled.
2357 * - We know the size of the actual received frame, so we subtract
2358 * that value from the current pointer location. This brings us
2359 * to the start of the actual received packet.
2361 * - We copy this into an mbuf and pass it on, along with the actual
2364 * The performance hit is tremendous, but it beats dropping frames all
2368 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2369 static void dc_pnic_rx_bug_war(sc, idx)
2370 struct dc_softc *sc;
2373 struct dc_desc *cur_rx;
2374 struct dc_desc *c = NULL;
2375 struct mbuf *m = NULL;
2378 u_int32_t rxstat = 0;
2380 i = sc->dc_pnic_rx_bug_save;
2381 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2382 ptr = sc->dc_pnic_rx_buf;
2383 bzero(ptr, DC_RXLEN * 5);
2385 /* Copy all the bytes from the bogus buffers. */
2387 c = &sc->dc_ldata->dc_rx_list[i];
2388 rxstat = c->dc_status;
2389 m = sc->dc_cdata.dc_rx_chain[i];
2390 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2392 /* If this is the last buffer, break out. */
2393 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2395 dc_newbuf(sc, i, m);
2396 DC_INC(i, DC_RX_LIST_CNT);
2399 /* Find the length of the actual receive frame. */
2400 total_len = DC_RXBYTES(rxstat);
2402 /* Scan backwards until we hit a non-zero byte. */
2407 if ((uintptr_t)(ptr) & 0x3)
2410 /* Now find the start of the frame. */
2412 if (ptr < sc->dc_pnic_rx_buf)
2413 ptr = sc->dc_pnic_rx_buf;
2416 * Now copy the salvaged frame to the last mbuf and fake up
2417 * the status word to make it look like a successful
2420 dc_newbuf(sc, i, m);
2421 bcopy(ptr, mtod(m, char *), total_len);
2422 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2428 * This routine searches the RX ring for dirty descriptors in the
2429 * event that the rxeof routine falls out of sync with the chip's
2430 * current descriptor pointer. This may happen sometimes as a result
2431 * of a "no RX buffer available" condition that happens when the chip
2432 * consumes all of the RX buffers before the driver has a chance to
2433 * process the RX ring. This routine may need to be called more than
2434 * once to bring the driver back in sync with the chip, however we
2435 * should still be getting RX DONE interrupts to drive the search
2436 * for new packets in the RX ring, so we should catch up eventually.
2438 static int dc_rx_resync(sc)
2439 struct dc_softc *sc;
2442 struct dc_desc *cur_rx;
2444 pos = sc->dc_cdata.dc_rx_prod;
2446 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2447 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2448 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2450 DC_INC(pos, DC_RX_LIST_CNT);
2453 /* If the ring really is empty, then just return. */
2454 if (i == DC_RX_LIST_CNT)
2457 /* We've fallen behing the chip: catch it. */
2458 sc->dc_cdata.dc_rx_prod = pos;
2464 * A frame has been uploaded: pass the resulting mbuf chain up to
2465 * the higher level protocols.
2467 static void dc_rxeof(sc)
2468 struct dc_softc *sc;
2472 struct dc_desc *cur_rx;
2473 int i, total_len = 0;
2476 ifp = &sc->arpcom.ac_if;
2477 i = sc->dc_cdata.dc_rx_prod;
2479 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2481 #ifdef DEVICE_POLLING
2482 if (ifp->if_flags & IFF_POLLING) {
2483 if (sc->rxcycles <= 0)
2487 #endif /* DEVICE_POLLING */
2488 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2489 rxstat = cur_rx->dc_status;
2490 m = sc->dc_cdata.dc_rx_chain[i];
2491 total_len = DC_RXBYTES(rxstat);
2493 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2494 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2495 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2496 sc->dc_pnic_rx_bug_save = i;
2497 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2498 DC_INC(i, DC_RX_LIST_CNT);
2501 dc_pnic_rx_bug_war(sc, i);
2502 rxstat = cur_rx->dc_status;
2503 total_len = DC_RXBYTES(rxstat);
2507 sc->dc_cdata.dc_rx_chain[i] = NULL;
2510 * If an error occurs, update stats, clear the
2511 * status word and leave the mbuf cluster in place:
2512 * it should simply get re-used next time this descriptor
2513 * comes up in the ring. However, don't report long
2514 * frames as errors since they could be vlans
2516 if ((rxstat & DC_RXSTAT_RXERR)){
2517 if (!(rxstat & DC_RXSTAT_GIANT) ||
2518 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2519 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2520 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2522 if (rxstat & DC_RXSTAT_COLLSEEN)
2523 ifp->if_collisions++;
2524 dc_newbuf(sc, i, m);
2525 if (rxstat & DC_RXSTAT_CRCERR) {
2526 DC_INC(i, DC_RX_LIST_CNT);
2535 /* No errors; receive the packet. */
2536 total_len -= ETHER_CRC_LEN;
2540 * On the x86 we do not have alignment problems, so try to
2541 * allocate a new buffer for the receive ring, and pass up
2542 * the one where the packet is already, saving the expensive
2543 * copy done in m_devget().
2544 * If we are on an architecture with alignment problems, or
2545 * if the allocation fails, then use m_devget and leave the
2546 * existing buffer in the receive ring.
2548 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2549 m->m_pkthdr.rcvif = ifp;
2550 m->m_pkthdr.len = m->m_len = total_len;
2551 DC_INC(i, DC_RX_LIST_CNT);
2557 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2558 total_len + ETHER_ALIGN, 0, ifp, NULL);
2559 dc_newbuf(sc, i, m);
2560 DC_INC(i, DC_RX_LIST_CNT);
2565 m_adj(m0, ETHER_ALIGN);
2570 (*ifp->if_input)(ifp, m);
2573 sc->dc_cdata.dc_rx_prod = i;
2577 * A frame was downloaded to the chip. It's safe for us to clean up
2583 struct dc_softc *sc;
2585 struct dc_desc *cur_tx = NULL;
2589 ifp = &sc->arpcom.ac_if;
2592 * Go through our tx list and free mbufs for those
2593 * frames that have been transmitted.
2595 idx = sc->dc_cdata.dc_tx_cons;
2596 while(idx != sc->dc_cdata.dc_tx_prod) {
2599 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2600 txstat = cur_tx->dc_status;
2602 if (txstat & DC_TXSTAT_OWN)
2605 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2606 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2607 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2609 * Yes, the PNIC is so brain damaged
2610 * that it will sometimes generate a TX
2611 * underrun error while DMAing the RX
2612 * filter setup frame. If we detect this,
2613 * we have to send the setup frame again,
2614 * or else the filter won't be programmed
2617 if (DC_IS_PNIC(sc)) {
2618 if (txstat & DC_TXSTAT_ERRSUM)
2621 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2623 sc->dc_cdata.dc_tx_cnt--;
2624 DC_INC(idx, DC_TX_LIST_CNT);
2628 if (DC_IS_CONEXANT(sc)) {
2630 * For some reason Conexant chips like
2631 * setting the CARRLOST flag even when
2632 * the carrier is there. In CURRENT we
2633 * have the same problem for Xircom
2636 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2637 sc->dc_pmode == DC_PMODE_MII &&
2638 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2639 DC_TXSTAT_NOCARRIER)))
2640 txstat &= ~DC_TXSTAT_ERRSUM;
2642 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2643 sc->dc_pmode == DC_PMODE_MII &&
2644 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2645 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2646 txstat &= ~DC_TXSTAT_ERRSUM;
2649 if (txstat & DC_TXSTAT_ERRSUM) {
2651 if (txstat & DC_TXSTAT_EXCESSCOLL)
2652 ifp->if_collisions++;
2653 if (txstat & DC_TXSTAT_LATECOLL)
2654 ifp->if_collisions++;
2655 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2661 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2664 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2665 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2666 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2669 sc->dc_cdata.dc_tx_cnt--;
2670 DC_INC(idx, DC_TX_LIST_CNT);
2673 if (idx != sc->dc_cdata.dc_tx_cons) {
2674 /* some buffers have been freed */
2675 sc->dc_cdata.dc_tx_cons = idx;
2676 ifp->if_flags &= ~IFF_OACTIVE;
2678 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2683 static void dc_tick(xsc)
2686 struct dc_softc *sc;
2687 struct mii_data *mii;
2695 ifp = &sc->arpcom.ac_if;
2696 mii = device_get_softc(sc->dc_miibus);
2698 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2699 if (sc->dc_flags & DC_21143_NWAY) {
2700 r = CSR_READ_4(sc, DC_10BTSTAT);
2701 if (IFM_SUBTYPE(mii->mii_media_active) ==
2702 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2706 if (IFM_SUBTYPE(mii->mii_media_active) ==
2707 IFM_10_T && (r & DC_TSTAT_LS10)) {
2711 if (sc->dc_link == 0)
2714 r = CSR_READ_4(sc, DC_ISR);
2715 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2716 sc->dc_cdata.dc_tx_cnt == 0)
2718 if (!(mii->mii_media_status & IFM_ACTIVE))
2725 * When the init routine completes, we expect to be able to send
2726 * packets right away, and in fact the network code will send a
2727 * gratuitous ARP the moment the init routine marks the interface
2728 * as running. However, even though the MAC may have been initialized,
2729 * there may be a delay of a few seconds before the PHY completes
2730 * autonegotiation and the link is brought up. Any transmissions
2731 * made during that delay will be lost. Dealing with this is tricky:
2732 * we can't just pause in the init routine while waiting for the
2733 * PHY to come ready since that would bring the whole system to
2734 * a screeching halt for several seconds.
2736 * What we do here is prevent the TX start routine from sending
2737 * any packets until a link has been established. After the
2738 * interface has been initialized, the tick routine will poll
2739 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2740 * that time, packets will stay in the send queue, and once the
2741 * link comes up, they will be flushed out to the wire.
2745 if (mii->mii_media_status & IFM_ACTIVE &&
2746 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2748 if (ifp->if_snd.ifq_head != NULL)
2753 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2754 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2756 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2764 * A transmit underrun has occurred. Back off the transmit threshold,
2765 * or switch to store and forward mode if we have to.
2767 static void dc_tx_underrun(sc)
2768 struct dc_softc *sc;
2773 if (DC_IS_DAVICOM(sc))
2776 if (DC_IS_INTEL(sc)) {
2778 * The real 21143 requires that the transmitter be idle
2779 * in order to change the transmit threshold or store
2780 * and forward state.
2782 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2784 for (i = 0; i < DC_TIMEOUT; i++) {
2785 isr = CSR_READ_4(sc, DC_ISR);
2786 if (isr & DC_ISR_TX_IDLE)
2790 if (i == DC_TIMEOUT) {
2791 printf("dc%d: failed to force tx to idle state\n",
2797 printf("dc%d: TX underrun -- ", sc->dc_unit);
2798 sc->dc_txthresh += DC_TXTHRESH_INC;
2799 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2800 printf("using store and forward mode\n");
2801 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2803 printf("increasing TX threshold\n");
2804 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2805 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2808 if (DC_IS_INTEL(sc))
2809 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2814 #ifdef DEVICE_POLLING
2815 static poll_handler_t dc_poll;
2818 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2820 struct dc_softc *sc = ifp->if_softc;
2822 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2823 /* Re-enable interrupts. */
2824 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2827 sc->rxcycles = count;
2830 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
2833 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2836 status = CSR_READ_4(sc, DC_ISR);
2837 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2838 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2842 /* ack what we have */
2843 CSR_WRITE_4(sc, DC_ISR, status);
2845 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2846 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2847 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2849 if (dc_rx_resync(sc))
2852 /* restart transmit unit if necessary */
2853 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2854 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2856 if (status & DC_ISR_TX_UNDERRUN)
2859 if (status & DC_ISR_BUS_ERR) {
2860 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
2866 #endif /* DEVICE_POLLING */
2868 static void dc_intr(arg)
2871 struct dc_softc *sc;
2877 if (sc->suspended) {
2881 ifp = &sc->arpcom.ac_if;
2883 #ifdef DEVICE_POLLING
2884 if (ifp->if_flags & IFF_POLLING)
2886 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
2887 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2890 #endif /* DEVICE_POLLING */
2892 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2895 /* Suppress unwanted interrupts */
2896 if (!(ifp->if_flags & IFF_UP)) {
2897 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2902 /* Disable interrupts. */
2903 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2905 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2907 CSR_WRITE_4(sc, DC_ISR, status);
2909 if (status & DC_ISR_RX_OK) {
2911 curpkts = ifp->if_ipackets;
2913 if (curpkts == ifp->if_ipackets) {
2914 while(dc_rx_resync(sc))
2919 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2922 if (status & DC_ISR_TX_IDLE) {
2924 if (sc->dc_cdata.dc_tx_cnt) {
2925 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2926 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2930 if (status & DC_ISR_TX_UNDERRUN)
2933 if ((status & DC_ISR_RX_WATDOGTIMEO)
2934 || (status & DC_ISR_RX_NOBUF)) {
2936 curpkts = ifp->if_ipackets;
2938 if (curpkts == ifp->if_ipackets) {
2939 while(dc_rx_resync(sc))
2944 if (status & DC_ISR_BUS_ERR) {
2950 /* Re-enable interrupts. */
2951 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2953 if (ifp->if_snd.ifq_head != NULL)
2960 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2961 * pointers to the fragment pointers.
2963 static int dc_encap(sc, m_head, txidx)
2964 struct dc_softc *sc;
2965 struct mbuf *m_head;
2968 struct dc_desc *f = NULL;
2970 int frag, cur, cnt = 0;
2973 * Start packing the mbufs in this chain into
2974 * the fragment pointers. Stop when we run out
2975 * of fragments or hit the end of the mbuf chain.
2978 cur = frag = *txidx;
2980 for (m = m_head; m != NULL; m = m->m_next) {
2981 if (m->m_len != 0) {
2982 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2983 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2984 frag == (DC_TX_LIST_CNT - 1))
2987 if ((DC_TX_LIST_CNT -
2988 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2991 f = &sc->dc_ldata->dc_tx_list[frag];
2992 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2995 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2997 f->dc_status = DC_TXSTAT_OWN;
2998 f->dc_data = vtophys(mtod(m, vm_offset_t));
3000 DC_INC(frag, DC_TX_LIST_CNT);
3008 sc->dc_cdata.dc_tx_cnt += cnt;
3009 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3010 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3011 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3012 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3013 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3014 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3015 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3016 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3017 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3024 * Coalesce an mbuf chain into a single mbuf cluster buffer.
3025 * Needed for some really badly behaved chips that just can't
3026 * do scatter/gather correctly.
3028 static int dc_coal(sc, m_head)
3029 struct dc_softc *sc;
3030 struct mbuf **m_head;
3032 struct mbuf *m_new, *m;
3035 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
3038 if (m->m_pkthdr.len > MHLEN) {
3039 MCLGET(m_new, MB_DONTWAIT);
3040 if (!(m_new->m_flags & M_EXT)) {
3045 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3046 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3054 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3055 * to the mbuf data regions directly in the transmit lists. We also save a
3056 * copy of the pointers since the transmit list fragment pointers are
3057 * physical addresses.
3060 static void dc_start(ifp)
3063 struct dc_softc *sc;
3064 struct mbuf *m_head = NULL;
3069 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3072 if (ifp->if_flags & IFF_OACTIVE)
3075 idx = sc->dc_cdata.dc_tx_prod;
3077 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3078 IF_DEQUEUE(&ifp->if_snd, m_head);
3082 if (sc->dc_flags & DC_TX_COALESCE &&
3083 m_head->m_next != NULL) {
3084 /* only coalesce if have >1 mbufs */
3085 if (dc_coal(sc, &m_head)) {
3086 IF_PREPEND(&ifp->if_snd, m_head);
3087 ifp->if_flags |= IFF_OACTIVE;
3092 if (dc_encap(sc, m_head, &idx)) {
3093 IF_PREPEND(&ifp->if_snd, m_head);
3094 ifp->if_flags |= IFF_OACTIVE;
3099 * If there's a BPF listener, bounce a copy of this frame
3103 bpf_mtap(ifp, m_head);
3105 if (sc->dc_flags & DC_TX_ONE) {
3106 ifp->if_flags |= IFF_OACTIVE;
3112 sc->dc_cdata.dc_tx_prod = idx;
3113 if (!(sc->dc_flags & DC_TX_POLL))
3114 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3117 * Set a timeout in case the chip goes out to lunch.
3124 static void dc_init(xsc)
3127 struct dc_softc *sc = xsc;
3128 struct ifnet *ifp = &sc->arpcom.ac_if;
3129 struct mii_data *mii;
3134 mii = device_get_softc(sc->dc_miibus);
3137 * Cancel pending I/O and free all RX/TX buffers.
3143 * Set cache alignment and burst length.
3145 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3146 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3148 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3150 * Evenly share the bus between receive and transmit process.
3152 if (DC_IS_INTEL(sc))
3153 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3154 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3155 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3157 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3159 if (sc->dc_flags & DC_TX_POLL)
3160 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3161 switch(sc->dc_cachesize) {
3163 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3166 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3169 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3173 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3177 if (sc->dc_flags & DC_TX_STORENFWD)
3178 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3180 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3181 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3183 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3184 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3188 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3189 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3191 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3193 * The app notes for the 98713 and 98715A say that
3194 * in order to have the chips operate properly, a magic
3195 * number must be written to CSR16. Macronix does not
3196 * document the meaning of these bits so there's no way
3197 * to know exactly what they do. The 98713 has a magic
3198 * number all its own; the rest all use a different one.
3200 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3201 if (sc->dc_type == DC_TYPE_98713)
3202 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3204 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3208 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3210 /* Init circular RX list. */
3211 if (dc_list_rx_init(sc) == ENOBUFS) {
3212 printf("dc%d: initialization failed: no "
3213 "memory for rx buffers\n", sc->dc_unit);
3220 * Init tx descriptors.
3222 dc_list_tx_init(sc);
3225 * Load the address of the RX list.
3227 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3228 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3231 * Enable interrupts.
3233 #ifdef DEVICE_POLLING
3235 * ... but only if we are not polling, and make sure they are off in
3236 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3239 if (ifp->if_flags & IFF_POLLING)
3240 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3243 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3244 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3246 /* Enable transmitter. */
3247 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3250 * If this is an Intel 21143 and we're not using the
3251 * MII port, program the LED control pins so we get
3252 * link and activity indications.
3254 if (sc->dc_flags & DC_TULIP_LEDS) {
3255 CSR_WRITE_4(sc, DC_WATCHDOG,
3256 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3257 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3261 * Load the RX/multicast filter. We do this sort of late
3262 * because the filter programming scheme on the 21143 and
3263 * some clones requires DMAing a setup frame via the TX
3264 * engine, and we need the transmitter enabled for that.
3268 /* Enable receiver. */
3269 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3270 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3273 dc_setcfg(sc, sc->dc_if_media);
3275 ifp->if_flags |= IFF_RUNNING;
3276 ifp->if_flags &= ~IFF_OACTIVE;
3280 /* Don't start the ticker if this is a homePNA link. */
3281 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3284 if (sc->dc_flags & DC_21143_NWAY)
3285 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3287 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3291 if(sc->dc_srm_media) {
3294 ifr.ifr_media = sc->dc_srm_media;
3295 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3296 sc->dc_srm_media = 0;
3303 * Set media options.
3305 static int dc_ifmedia_upd(ifp)
3308 struct dc_softc *sc;
3309 struct mii_data *mii;
3310 struct ifmedia *ifm;
3313 mii = device_get_softc(sc->dc_miibus);
3315 ifm = &mii->mii_media;
3317 if (DC_IS_DAVICOM(sc) &&
3318 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3319 dc_setcfg(sc, ifm->ifm_media);
3327 * Report current media status.
3329 static void dc_ifmedia_sts(ifp, ifmr)
3331 struct ifmediareq *ifmr;
3333 struct dc_softc *sc;
3334 struct mii_data *mii;
3335 struct ifmedia *ifm;
3338 mii = device_get_softc(sc->dc_miibus);
3340 ifm = &mii->mii_media;
3341 if (DC_IS_DAVICOM(sc)) {
3342 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3343 ifmr->ifm_active = ifm->ifm_media;
3344 ifmr->ifm_status = 0;
3348 ifmr->ifm_active = mii->mii_media_active;
3349 ifmr->ifm_status = mii->mii_media_status;
3354 static int dc_ioctl(ifp, command, data, cr)
3360 struct dc_softc *sc = ifp->if_softc;
3361 struct ifreq *ifr = (struct ifreq *) data;
3362 struct mii_data *mii;
3371 error = ether_ioctl(ifp, command, data);
3374 if (ifp->if_flags & IFF_UP) {
3375 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3376 (IFF_PROMISC | IFF_ALLMULTI);
3377 if (ifp->if_flags & IFF_RUNNING) {
3381 sc->dc_txthresh = 0;
3385 if (ifp->if_flags & IFF_RUNNING)
3388 sc->dc_if_flags = ifp->if_flags;
3398 mii = device_get_softc(sc->dc_miibus);
3399 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3401 if (sc->dc_srm_media)
3402 sc->dc_srm_media = 0;
3415 static void dc_watchdog(ifp)
3418 struct dc_softc *sc;
3423 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3429 if (ifp->if_snd.ifq_head != NULL)
3436 * Stop the adapter and free any mbufs allocated to the
3439 static void dc_stop(sc)
3440 struct dc_softc *sc;
3445 ifp = &sc->arpcom.ac_if;
3448 callout_stop(&sc->dc_stat_timer);
3450 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3451 #ifdef DEVICE_POLLING
3452 ether_poll_deregister(ifp);
3455 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3456 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3457 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3458 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3462 * Free data in the RX lists.
3464 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3465 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3466 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3467 sc->dc_cdata.dc_rx_chain[i] = NULL;
3470 bzero((char *)&sc->dc_ldata->dc_rx_list,
3471 sizeof(sc->dc_ldata->dc_rx_list));
3474 * Free the TX list buffers.
3476 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3477 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3478 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3480 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3481 DC_TXCTL_LASTFRAG)) {
3482 sc->dc_cdata.dc_tx_chain[i] = NULL;
3485 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3486 sc->dc_cdata.dc_tx_chain[i] = NULL;
3490 bzero((char *)&sc->dc_ldata->dc_tx_list,
3491 sizeof(sc->dc_ldata->dc_tx_list));
3497 * Stop all chip I/O so that the kernel's probe routines don't
3498 * get confused by errant DMAs when rebooting.
3500 static void dc_shutdown(dev)
3503 struct dc_softc *sc;
3505 sc = device_get_softc(dev);
3513 * Device suspend routine. Stop the interface and save some PCI
3514 * settings in case the BIOS doesn't restore them properly on
3517 static int dc_suspend(dev)
3522 struct dc_softc *sc;
3526 sc = device_get_softc(dev);
3530 for (i = 0; i < 5; i++)
3531 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3532 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3533 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3534 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3535 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3544 * Device resume routine. Restore some PCI settings in case the BIOS
3545 * doesn't, re-enable busmastering, and restart the interface if
3548 static int dc_resume(dev)
3553 struct dc_softc *sc;
3558 sc = device_get_softc(dev);
3559 ifp = &sc->arpcom.ac_if;
3563 /* better way to do this? */
3564 for (i = 0; i < 5; i++)
3565 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3566 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3567 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3568 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3569 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3571 /* reenable busmastering */
3572 pci_enable_busmaster(dev);
3573 pci_enable_io(dev, DC_RES);
3575 /* reinitialize interface if necessary */
3576 if (ifp->if_flags & IFF_UP)
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