2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.26 2005/09/29 12:52:51 sephe Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/sockio.h>
65 #include <sys/malloc.h>
66 #include <sys/kernel.h>
67 #include <sys/socket.h>
68 #include <sys/sysctl.h>
69 #include <sys/thread2.h>
72 #include <net/ifq_var.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/vlan/if_vlan_var.h>
82 #include <machine/bus_pio.h>
83 #include <machine/bus_memio.h>
84 #include <machine/bus.h>
85 #include <machine/resource.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include <bus/pci/pcireg.h>
93 #include <bus/pci/pcivar.h>
95 #define SIS_USEIOSPACE
97 #include "if_sisreg.h"
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
103 * Various supported device vendors/types and their names.
105 static struct sis_type sis_devs[] = {
106 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
107 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
108 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
112 static int sis_probe(device_t);
113 static int sis_attach(device_t);
114 static int sis_detach(device_t);
116 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
118 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
119 static void sis_rxeof(struct sis_softc *);
120 static void sis_rxeoc(struct sis_softc *);
121 static void sis_txeof(struct sis_softc *);
122 static void sis_intr(void *);
123 static void sis_tick(void *);
124 static void sis_start(struct ifnet *);
125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
126 static void sis_init(void *);
127 static void sis_stop(struct sis_softc *);
128 static void sis_watchdog(struct ifnet *);
129 static void sis_shutdown(device_t);
130 static int sis_ifmedia_upd(struct ifnet *);
131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static uint16_t sis_reverse(uint16_t);
134 static void sis_delay(struct sis_softc *);
135 static void sis_eeprom_idle(struct sis_softc *);
136 static void sis_eeprom_putbyte(struct sis_softc *, int);
137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
142 static device_t sis_find_bridge(device_t);
145 static void sis_mii_sync(struct sis_softc *);
146 static void sis_mii_send(struct sis_softc *, uint32_t, int);
147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
149 static int sis_miibus_readreg(device_t, int, int);
150 static int sis_miibus_writereg(device_t, int, int, int);
151 static void sis_miibus_statchg(device_t);
153 static void sis_setmulti_sis(struct sis_softc *);
154 static void sis_setmulti_ns(struct sis_softc *);
155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
156 static void sis_reset(struct sis_softc *);
157 static int sis_list_rx_init(struct sis_softc *);
158 static int sis_list_tx_init(struct sis_softc *);
160 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
161 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
162 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
163 #ifdef DEVICE_POLLING
164 static poll_handler_t sis_poll;
166 #ifdef SIS_USEIOSPACE
167 #define SIS_RES SYS_RES_IOPORT
168 #define SIS_RID SIS_PCI_LOIO
170 #define SIS_RES SYS_RES_MEMORY
171 #define SIS_RID SIS_PCI_LOMEM
174 static device_method_t sis_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, sis_probe),
177 DEVMETHOD(device_attach, sis_attach),
178 DEVMETHOD(device_detach, sis_detach),
179 DEVMETHOD(device_shutdown, sis_shutdown),
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
186 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
187 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
188 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
193 static driver_t sis_driver = {
196 sizeof(struct sis_softc)
199 static devclass_t sis_devclass;
201 DECLARE_DUMMY_MODULE(if_sis);
202 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
205 #define SIS_SETBIT(sc, reg, x) \
206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
208 #define SIS_CLRBIT(sc, reg, x) \
209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
218 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
223 r->sis_next = segs->ds_addr;
227 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
232 r->sis_ptr = segs->ds_addr;
236 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
245 * Routine to reverse the bits in a word. Stolen almost
246 * verbatim from /usr/games/fortune.
249 sis_reverse(uint16_t n)
251 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
252 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
253 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
254 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
260 sis_delay(struct sis_softc *sc)
264 for (idx = (300 / 33) + 1; idx > 0; idx--)
265 CSR_READ_4(sc, SIS_CSR);
269 sis_eeprom_idle(struct sis_softc *sc)
273 SIO_SET(SIS_EECTL_CSEL);
275 SIO_SET(SIS_EECTL_CLK);
278 for (i = 0; i < 25; i++) {
279 SIO_CLR(SIS_EECTL_CLK);
281 SIO_SET(SIS_EECTL_CLK);
285 SIO_CLR(SIS_EECTL_CLK);
287 SIO_CLR(SIS_EECTL_CSEL);
289 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
293 * Send a read command and address to the EEPROM, check for ACK.
296 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
300 d = addr | SIS_EECMD_READ;
303 * Feed in each bit and stobe the clock.
305 for (i = 0x400; i; i >>= 1) {
307 SIO_SET(SIS_EECTL_DIN);
309 SIO_CLR(SIS_EECTL_DIN);
311 SIO_SET(SIS_EECTL_CLK);
313 SIO_CLR(SIS_EECTL_CLK);
319 * Read a word of data stored in the EEPROM at address 'addr.'
322 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
327 /* Force EEPROM to idle state. */
330 /* Enter EEPROM access mode. */
332 SIO_CLR(SIS_EECTL_CLK);
334 SIO_SET(SIS_EECTL_CSEL);
338 * Send address of word we want to read.
340 sis_eeprom_putbyte(sc, addr);
343 * Start reading bits from EEPROM.
345 for (i = 0x8000; i; i >>= 1) {
346 SIO_SET(SIS_EECTL_CLK);
348 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
351 SIO_CLR(SIS_EECTL_CLK);
355 /* Turn off EEPROM access mode. */
362 * Read a sequence of words from the EEPROM.
365 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
368 uint16_t word = 0, *ptr;
370 for (i = 0; i < cnt; i++) {
371 sis_eeprom_getword(sc, off + i, &word);
372 ptr = (uint16_t *)(dest + (i * 2));
382 sis_find_bridge(device_t dev)
384 devclass_t pci_devclass;
385 device_t *pci_devices;
387 device_t *pci_children;
388 int pci_childcount = 0;
389 device_t *busp, *childp;
390 device_t child = NULL;
393 if ((pci_devclass = devclass_find("pci")) == NULL)
396 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
398 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
400 device_get_children(*busp, &pci_children, &pci_childcount);
401 for (j = 0, childp = pci_children; j < pci_childcount;
403 if (pci_get_vendor(*childp) == SIS_VENDORID &&
404 pci_get_device(*childp) == 0x0008) {
412 free(pci_devices, M_TEMP);
413 free(pci_children, M_TEMP);
418 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
424 bus_space_tag_t btag;
426 bridge = sis_find_bridge(dev);
429 reg = pci_read_config(bridge, 0x48, 1);
430 pci_write_config(bridge, 0x48, reg|0x40, 1);
433 btag = I386_BUS_SPACE_IO;
435 for (i = 0; i < cnt; i++) {
436 bus_space_write_1(btag, 0x0, 0x70, i + off);
437 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
440 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
444 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
446 uint32_t filtsave, csrsave;
448 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
449 csrsave = CSR_READ_4(sc, SIS_CSR);
451 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
452 CSR_WRITE_4(sc, SIS_CSR, 0);
454 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
456 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
457 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
458 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
459 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
461 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
463 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
464 CSR_WRITE_4(sc, SIS_CSR, csrsave);
469 * Sync the PHYs by setting data bit and strobing the clock 32 times.
472 sis_mii_sync(struct sis_softc *sc)
476 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
478 for (i = 0; i < 32; i++) {
479 SIO_SET(SIS_MII_CLK);
481 SIO_CLR(SIS_MII_CLK);
487 * Clock a series of bits through the MII.
490 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
494 SIO_CLR(SIS_MII_CLK);
496 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
498 SIO_SET(SIS_MII_DATA);
500 SIO_CLR(SIS_MII_DATA);
502 SIO_CLR(SIS_MII_CLK);
504 SIO_SET(SIS_MII_CLK);
509 * Read an PHY register through the MII.
512 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
519 * Set up frame for RX.
521 frame->mii_stdelim = SIS_MII_STARTDELIM;
522 frame->mii_opcode = SIS_MII_READOP;
523 frame->mii_turnaround = 0;
529 SIO_SET(SIS_MII_DIR);
534 * Send command/address info.
536 sis_mii_send(sc, frame->mii_stdelim, 2);
537 sis_mii_send(sc, frame->mii_opcode, 2);
538 sis_mii_send(sc, frame->mii_phyaddr, 5);
539 sis_mii_send(sc, frame->mii_regaddr, 5);
542 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
544 SIO_SET(SIS_MII_CLK);
548 SIO_CLR(SIS_MII_DIR);
551 SIO_CLR(SIS_MII_CLK);
553 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
554 SIO_SET(SIS_MII_CLK);
558 * Now try reading data bits. If the ack failed, we still
559 * need to clock through 16 cycles to keep the PHY(s) in sync.
562 for(i = 0; i < 16; i++) {
563 SIO_CLR(SIS_MII_CLK);
565 SIO_SET(SIS_MII_CLK);
571 for (i = 0x8000; i; i >>= 1) {
572 SIO_CLR(SIS_MII_CLK);
575 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
576 frame->mii_data |= i;
579 SIO_SET(SIS_MII_CLK);
585 SIO_CLR(SIS_MII_CLK);
587 SIO_SET(SIS_MII_CLK);
598 * Write to a PHY register through the MII.
601 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
606 * Set up frame for TX.
609 frame->mii_stdelim = SIS_MII_STARTDELIM;
610 frame->mii_opcode = SIS_MII_WRITEOP;
611 frame->mii_turnaround = SIS_MII_TURNAROUND;
614 * Turn on data output.
616 SIO_SET(SIS_MII_DIR);
620 sis_mii_send(sc, frame->mii_stdelim, 2);
621 sis_mii_send(sc, frame->mii_opcode, 2);
622 sis_mii_send(sc, frame->mii_phyaddr, 5);
623 sis_mii_send(sc, frame->mii_regaddr, 5);
624 sis_mii_send(sc, frame->mii_turnaround, 2);
625 sis_mii_send(sc, frame->mii_data, 16);
628 SIO_SET(SIS_MII_CLK);
630 SIO_CLR(SIS_MII_CLK);
636 SIO_CLR(SIS_MII_DIR);
644 sis_miibus_readreg(device_t dev, int phy, int reg)
646 struct sis_softc *sc;
647 struct sis_mii_frame frame;
649 sc = device_get_softc(dev);
651 if (sc->sis_type == SIS_TYPE_83815) {
655 * The NatSemi chip can take a while after
656 * a reset to come ready, during which the BMSR
657 * returns a value of 0. This is *never* supposed
658 * to happen: some of the BMSR bits are meant to
659 * be hardwired in the on position, and this can
660 * confuse the miibus code a bit during the probe
661 * and attach phase. So we make an effort to check
662 * for this condition and wait for it to clear.
664 if (!CSR_READ_4(sc, NS_BMSR))
666 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
669 * Chipsets < SIS_635 seem not to be able to read/write
670 * through mdio. Use the enhanced PHY access register
673 if (sc->sis_type == SIS_TYPE_900 &&
674 sc->sis_rev < SIS_REV_635) {
680 CSR_WRITE_4(sc, SIS_PHYCTL,
681 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
682 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
684 for (i = 0; i < SIS_TIMEOUT; i++) {
685 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
689 if (i == SIS_TIMEOUT) {
690 device_printf(dev, "PHY failed to come ready\n");
694 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
701 bzero((char *)&frame, sizeof(frame));
703 frame.mii_phyaddr = phy;
704 frame.mii_regaddr = reg;
705 sis_mii_readreg(sc, &frame);
707 return(frame.mii_data);
712 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
714 struct sis_softc *sc;
715 struct sis_mii_frame frame;
717 sc = device_get_softc(dev);
719 if (sc->sis_type == SIS_TYPE_83815) {
722 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
726 if (sc->sis_type == SIS_TYPE_900 &&
727 sc->sis_rev < SIS_REV_635) {
733 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
734 (reg << 6) | SIS_PHYOP_WRITE);
735 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
737 for (i = 0; i < SIS_TIMEOUT; i++) {
738 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
742 if (i == SIS_TIMEOUT)
743 device_printf(dev, "PHY failed to come ready\n");
745 bzero((char *)&frame, sizeof(frame));
747 frame.mii_phyaddr = phy;
748 frame.mii_regaddr = reg;
749 frame.mii_data = data;
750 sis_mii_writereg(sc, &frame);
755 static void sis_miibus_statchg(device_t dev)
757 struct sis_softc *sc;
759 sc = device_get_softc(dev);
764 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
770 /* Compute CRC for the address value. */
771 crc = 0xFFFFFFFF; /* initial value */
773 for (i = 0; i < 6; i++) {
775 for (j = 0; j < 8; j++) {
776 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
780 crc = (crc ^ 0x04c11db6) | carry;
785 * return the filter bit position
787 * The NatSemi chip has a 512-bit filter, which is
788 * different than the SiS, so we special-case it.
790 if (sc->sis_type == SIS_TYPE_83815)
792 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
799 sis_setmulti_ns(struct sis_softc *sc)
802 struct ifmultiaddr *ifma;
803 uint32_t h = 0, i, filtsave;
806 ifp = &sc->arpcom.ac_if;
808 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
809 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
810 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
815 * We have to explicitly enable the multicast hash table
816 * on the NatSemi chip if we want to use it, which we do.
818 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
819 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
821 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
823 /* first, zot all the existing hash bits */
824 for (i = 0; i < 32; i++) {
825 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
826 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
829 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
830 if (ifma->ifma_addr->sa_family != AF_LINK)
833 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
836 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
839 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
842 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
846 sis_setmulti_sis(struct sis_softc *sc)
849 struct ifmultiaddr *ifma;
850 uint32_t h, i, n, ctl;
853 ifp = &sc->arpcom.ac_if;
855 /* hash table size */
856 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
861 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
863 if (ifp->if_flags & IFF_BROADCAST)
864 ctl |= SIS_RXFILTCTL_BROAD;
866 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
867 ctl |= SIS_RXFILTCTL_ALLMULTI;
868 if (ifp->if_flags & IFF_PROMISC)
869 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
870 for (i = 0; i < n; i++)
873 for (i = 0; i < n; i++)
876 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
877 if (ifma->ifma_addr->sa_family != AF_LINK)
880 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
881 hashes[h >> 4] |= 1 << (h & 0xf);
885 ctl |= SIS_RXFILTCTL_ALLMULTI;
886 for (i = 0; i < n; i++)
891 for (i = 0; i < n; i++) {
892 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
893 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
896 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
900 sis_reset(struct sis_softc *sc)
902 struct ifnet *ifp = &sc->arpcom.ac_if;
905 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
907 for (i = 0; i < SIS_TIMEOUT; i++) {
908 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
912 if (i == SIS_TIMEOUT)
913 if_printf(ifp, "reset never completed\n");
915 /* Wait a little while for the chip to get its brains in order. */
919 * If this is a NetSemi chip, make sure to clear
922 if (sc->sis_type == SIS_TYPE_83815) {
923 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
924 CSR_WRITE_4(sc, NS_CLKRUN, 0);
929 * Probe for an SiS chip. Check the PCI vendor and device
930 * IDs against our list and return a device name if we find a match.
933 sis_probe(device_t dev)
939 while(t->sis_name != NULL) {
940 if ((pci_get_vendor(dev) == t->sis_vid) &&
941 (pci_get_device(dev) == t->sis_did)) {
942 device_set_desc(dev, t->sis_name);
952 * Attach the interface. Allocate softc structures, do ifmedia
953 * setup and ethernet/BPF attach.
956 sis_attach(device_t dev)
958 uint8_t eaddr[ETHER_ADDR_LEN];
960 struct sis_softc *sc;
962 int error, rid, waittime;
964 error = waittime = 0;
965 sc = device_get_softc(dev);
967 if (pci_get_device(dev) == SIS_DEVICEID_900)
968 sc->sis_type = SIS_TYPE_900;
969 if (pci_get_device(dev) == SIS_DEVICEID_7016)
970 sc->sis_type = SIS_TYPE_7016;
971 if (pci_get_vendor(dev) == NS_VENDORID)
972 sc->sis_type = SIS_TYPE_83815;
974 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
977 * Handle power management nonsense.
980 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
981 if (command == 0x01) {
983 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
984 if (command & SIS_PSTATE_MASK) {
985 uint32_t iobase, membase, irq;
987 /* Save important PCI config data. */
988 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
989 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
990 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
992 /* Reset the power state. */
993 device_printf(dev, "chip is in D%d power mode "
994 "-- setting to D0\n", command & SIS_PSTATE_MASK);
995 command &= 0xFFFFFFFC;
996 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
998 /* Restore PCI config data. */
999 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
1000 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
1001 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1006 * Map control/status registers.
1008 command = pci_read_config(dev, PCIR_COMMAND, 4);
1009 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1010 pci_write_config(dev, PCIR_COMMAND, command, 4);
1011 command = pci_read_config(dev, PCIR_COMMAND, 4);
1013 #ifdef SIS_USEIOSPACE
1014 if (!(command & PCIM_CMD_PORTEN)) {
1015 device_printf(dev, "failed to enable I/O ports!\n");
1020 if (!(command & PCIM_CMD_MEMEN)) {
1021 device_printf(dev, "failed to enable memory mapping!\n");
1028 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
1030 if (sc->sis_res == NULL) {
1031 device_printf(dev, "couldn't map ports/memory\n");
1036 sc->sis_btag = rman_get_bustag(sc->sis_res);
1037 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1039 /* Allocate interrupt */
1041 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1042 RF_SHAREABLE | RF_ACTIVE);
1044 if (sc->sis_irq == NULL) {
1045 device_printf(dev, "couldn't map interrupt\n");
1050 /* Reset the adapter. */
1053 if (sc->sis_type == SIS_TYPE_900 &&
1054 (sc->sis_rev == SIS_REV_635 ||
1055 sc->sis_rev == SIS_REV_900B)) {
1056 SIO_SET(SIS_CFG_RND_CNT);
1057 SIO_SET(SIS_CFG_PERR_DETECT);
1061 * Get station address from the EEPROM.
1063 switch (pci_get_vendor(dev)) {
1066 * Reading the MAC address out of the EEPROM on
1067 * the NatSemi chip takes a bit more work than
1068 * you'd expect. The address spans 4 16-bit words,
1069 * with the first word containing only a single bit.
1070 * You have to shift everything over one bit to
1071 * get it aligned properly. Also, the bits are
1072 * stored backwards (the LSB is really the MSB,
1073 * and so on) so you have to reverse them in order
1074 * to get the MAC address into the form we want.
1075 * Why? Who the hell knows.
1080 sis_read_eeprom(sc, (caddr_t)&tmp,
1081 NS_EE_NODEADDR, 4, 0);
1083 /* Shift everything over one bit. */
1084 tmp[3] = tmp[3] >> 1;
1085 tmp[3] |= tmp[2] << 15;
1086 tmp[2] = tmp[2] >> 1;
1087 tmp[2] |= tmp[1] << 15;
1088 tmp[1] = tmp[1] >> 1;
1089 tmp[1] |= tmp[0] << 15;
1091 /* Now reverse all the bits. */
1092 tmp[3] = sis_reverse(tmp[3]);
1093 tmp[2] = sis_reverse(tmp[2]);
1094 tmp[1] = sis_reverse(tmp[1]);
1096 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1103 * If this is a SiS 630E chipset with an embedded
1104 * SiS 900 controller, we have to read the MAC address
1105 * from the APC CMOS RAM. Our method for doing this
1106 * is very ugly since we have to reach out and grab
1107 * ahold of hardware for which we cannot properly
1108 * allocate resources. This code is only compiled on
1109 * the i386 architecture since the SiS 630E chipset
1110 * is for x86 motherboards only. Note that there are
1111 * a lot of magic numbers in this hack. These are
1112 * taken from SiS's Linux driver. I'd like to replace
1113 * them with proper symbolic definitions, but that
1114 * requires some datasheets that I don't have access
1117 if (sc->sis_rev == SIS_REV_630S ||
1118 sc->sis_rev == SIS_REV_630E ||
1119 sc->sis_rev == SIS_REV_630EA1)
1120 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1122 else if (sc->sis_rev == SIS_REV_635 ||
1123 sc->sis_rev == SIS_REV_630ET)
1124 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1125 else if (sc->sis_rev == SIS_REV_96x) {
1127 * Allow to read EEPROM from LAN. It is shared
1128 * between a 1394 controller and the NIC and each
1129 * time we access it, we need to set SIS_EECMD_REQ.
1131 SIO_SET(SIS_EECMD_REQ);
1132 for (waittime = 0; waittime < SIS_TIMEOUT;
1134 /* Force EEPROM to idle state. */
1135 sis_eeprom_idle(sc);
1136 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1137 sis_read_eeprom(sc, (caddr_t)&eaddr,
1138 SIS_EE_NODEADDR, 3, 0);
1144 * Set SIS_EECTL_CLK to high, so a other master
1145 * can operate on the i2c bus.
1147 SIO_SET(SIS_EECTL_CLK);
1148 /* Refuse EEPROM access by LAN */
1149 SIO_SET(SIS_EECMD_DONE);
1152 sis_read_eeprom(sc, (caddr_t)&eaddr,
1153 SIS_EE_NODEADDR, 3, 0);
1157 callout_init(&sc->sis_timer);
1160 * Allocate the parent bus DMA tag appropriate for PCI.
1162 #define SIS_NSEG_NEW 32
1163 error = bus_dma_tag_create(NULL, /* parent */
1164 1, 0, /* alignment, boundary */
1165 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1166 BUS_SPACE_MAXADDR, /* highaddr */
1167 NULL, NULL, /* filter, filterarg */
1168 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1169 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1170 BUS_DMA_ALLOCNOW, /* flags */
1171 &sc->sis_parent_tag);
1176 * Now allocate a tag for the DMA descriptor lists and a chunk
1177 * of DMA-able memory based on the tag. Also obtain the physical
1178 * addresses of the RX and TX ring, which we'll need later.
1179 * All of our lists are allocated as a contiguous block of memory.
1181 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1182 1, 0, /* alignment, boundary */
1183 BUS_SPACE_MAXADDR, /* lowaddr */
1184 BUS_SPACE_MAXADDR, /* highaddr */
1185 NULL, NULL, /* filter, filterarg */
1186 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1187 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1189 &sc->sis_ldata.sis_rx_tag);
1193 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1194 (void **)&sc->sis_ldata.sis_rx_list,
1195 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1196 &sc->sis_ldata.sis_rx_dmamap);
1199 device_printf(dev, "no memory for rx list buffers!\n");
1200 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1201 sc->sis_ldata.sis_rx_tag = NULL;
1205 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1206 sc->sis_ldata.sis_rx_dmamap,
1207 sc->sis_ldata.sis_rx_list,
1208 sizeof(struct sis_desc), sis_dma_map_ring,
1209 &sc->sis_cdata.sis_rx_paddr, 0);
1212 device_printf(dev, "cannot get address of the rx ring!\n");
1213 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1214 sc->sis_ldata.sis_rx_list,
1215 sc->sis_ldata.sis_rx_dmamap);
1216 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1217 sc->sis_ldata.sis_rx_tag = NULL;
1221 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1222 1, 0, /* alignment, boundary */
1223 BUS_SPACE_MAXADDR, /* lowaddr */
1224 BUS_SPACE_MAXADDR, /* highaddr */
1225 NULL, NULL, /* filter, filterarg */
1226 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1227 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1229 &sc->sis_ldata.sis_tx_tag);
1233 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1234 (void **)&sc->sis_ldata.sis_tx_list,
1235 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1236 &sc->sis_ldata.sis_tx_dmamap);
1239 device_printf(dev, "no memory for tx list buffers!\n");
1240 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1241 sc->sis_ldata.sis_tx_tag = NULL;
1245 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1246 sc->sis_ldata.sis_tx_dmamap,
1247 sc->sis_ldata.sis_tx_list,
1248 sizeof(struct sis_desc), sis_dma_map_ring,
1249 &sc->sis_cdata.sis_tx_paddr, 0);
1252 device_printf(dev, "cannot get address of the tx ring!\n");
1253 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1254 sc->sis_ldata.sis_tx_list,
1255 sc->sis_ldata.sis_tx_dmamap);
1256 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1257 sc->sis_ldata.sis_tx_tag = NULL;
1261 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1262 1, 0, /* alignment, boundary */
1263 BUS_SPACE_MAXADDR, /* lowaddr */
1264 BUS_SPACE_MAXADDR, /* highaddr */
1265 NULL, NULL, /* filter, filterarg */
1266 MCLBYTES, 1, /* maxsize, nsegments */
1267 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1273 ifp = &sc->arpcom.ac_if;
1275 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1276 ifp->if_mtu = ETHERMTU;
1277 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1278 ifp->if_ioctl = sis_ioctl;
1279 ifp->if_start = sis_start;
1280 ifp->if_watchdog = sis_watchdog;
1281 ifp->if_init = sis_init;
1282 ifp->if_baudrate = 10000000;
1283 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1284 ifq_set_ready(&ifp->if_snd);
1285 #ifdef DEVICE_POLLING
1286 ifp->if_poll = sis_poll;
1288 ifp->if_capenable = ifp->if_capabilities;
1293 if (mii_phy_probe(dev, &sc->sis_miibus,
1294 sis_ifmedia_upd, sis_ifmedia_sts)) {
1295 device_printf(dev, "MII without any PHY!\n");
1301 * Call MI attach routine.
1303 ether_ifattach(ifp, eaddr);
1306 * Tell the upper layer(s) we support long frames.
1308 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1310 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1312 &sc->sis_intrhand, NULL);
1315 device_printf(dev, "couldn't set up irq\n");
1316 ether_ifdetach(ifp);
1328 * Shutdown hardware and free up resources. It is called in both the error case
1329 * and the normal detach case so it needs to be careful about only freeing
1330 * resources that have actually been allocated.
1333 sis_detach(device_t dev)
1335 struct sis_softc *sc = device_get_softc(dev);
1336 struct ifnet *ifp = &sc->arpcom.ac_if;
1340 if (device_is_attached(dev)) {
1343 ether_ifdetach(ifp);
1346 device_delete_child(dev, sc->sis_miibus);
1347 bus_generic_detach(dev);
1349 if (sc->sis_intrhand)
1350 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1355 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1357 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1359 if (sc->sis_ldata.sis_rx_tag) {
1360 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1361 sc->sis_ldata.sis_rx_dmamap);
1362 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1363 sc->sis_ldata.sis_rx_list,
1364 sc->sis_ldata.sis_rx_dmamap);
1365 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1368 if (sc->sis_ldata.sis_tx_tag) {
1369 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1370 sc->sis_ldata.sis_tx_dmamap);
1371 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1372 sc->sis_ldata.sis_tx_list,
1373 sc->sis_ldata.sis_tx_dmamap);
1374 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1377 bus_dma_tag_destroy(sc->sis_tag);
1378 if (sc->sis_parent_tag)
1379 bus_dma_tag_destroy(sc->sis_parent_tag);
1385 * Initialize the transmit descriptors.
1388 sis_list_tx_init(struct sis_softc *sc)
1390 struct sis_list_data *ld;
1391 struct sis_ring_data *cd;
1394 cd = &sc->sis_cdata;
1395 ld = &sc->sis_ldata;
1397 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1398 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1399 ld->sis_tx_list[i].sis_nextdesc =
1400 &ld->sis_tx_list[nexti];
1401 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1402 sc->sis_ldata.sis_tx_dmamap,
1403 &ld->sis_tx_list[nexti],
1404 sizeof(struct sis_desc), sis_dma_map_desc_next,
1405 &ld->sis_tx_list[i], 0);
1406 ld->sis_tx_list[i].sis_mbuf = NULL;
1407 ld->sis_tx_list[i].sis_ptr = 0;
1408 ld->sis_tx_list[i].sis_ctl = 0;
1411 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1413 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1414 BUS_DMASYNC_PREWRITE);
1420 * Initialize the RX descriptors and allocate mbufs for them. Note that
1421 * we arrange the descriptors in a closed ring, so that the last descriptor
1422 * points back to the first.
1425 sis_list_rx_init(struct sis_softc *sc)
1427 struct sis_list_data *ld;
1428 struct sis_ring_data *cd;
1431 ld = &sc->sis_ldata;
1432 cd = &sc->sis_cdata;
1434 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1435 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1437 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1438 ld->sis_rx_list[i].sis_nextdesc =
1439 &ld->sis_rx_list[nexti];
1440 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1441 sc->sis_ldata.sis_rx_dmamap,
1442 &ld->sis_rx_list[nexti],
1443 sizeof(struct sis_desc), sis_dma_map_desc_next,
1444 &ld->sis_rx_list[i], 0);
1447 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1448 BUS_DMASYNC_PREWRITE);
1450 cd->sis_rx_prod = 0;
1456 * Initialize an RX descriptor and attach an MBUF cluster.
1459 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1462 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1466 m->m_data = m->m_ext.ext_buf;
1470 c->sis_ctl = SIS_RXLEN;
1472 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1473 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1474 sis_dma_map_desc_ptr, c, 0);
1475 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1481 * A frame has been uploaded: pass the resulting mbuf chain up to
1482 * the higher level protocols.
1485 sis_rxeof(struct sis_softc *sc)
1489 struct sis_desc *cur_rx;
1490 int i, total_len = 0;
1493 ifp = &sc->arpcom.ac_if;
1494 i = sc->sis_cdata.sis_rx_prod;
1496 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1498 #ifdef DEVICE_POLLING
1499 if (ifp->if_flags & IFF_POLLING) {
1500 if (sc->rxcycles <= 0)
1504 #endif /* DEVICE_POLLING */
1505 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1506 rxstat = cur_rx->sis_rxstat;
1507 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1508 BUS_DMASYNC_POSTWRITE);
1509 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1510 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1511 m = cur_rx->sis_mbuf;
1512 cur_rx->sis_mbuf = NULL;
1513 total_len = SIS_RXBYTES(cur_rx);
1514 SIS_INC(i, SIS_RX_LIST_CNT);
1517 * If an error occurs, update stats, clear the
1518 * status word and leave the mbuf cluster in place:
1519 * it should simply get re-used next time this descriptor
1520 * comes up in the ring.
1522 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1524 if (rxstat & SIS_RXSTAT_COLL)
1525 ifp->if_collisions++;
1526 sis_newbuf(sc, cur_rx, m);
1530 /* No errors; receive the packet. */
1533 * On the x86 we do not have alignment problems, so try to
1534 * allocate a new buffer for the receive ring, and pass up
1535 * the one where the packet is already, saving the expensive
1536 * copy done in m_devget().
1537 * If we are on an architecture with alignment problems, or
1538 * if the allocation fails, then use m_devget and leave the
1539 * existing buffer in the receive ring.
1541 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1542 m->m_pkthdr.len = m->m_len = total_len;
1547 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1548 total_len + ETHER_ALIGN, 0, ifp, NULL);
1549 sis_newbuf(sc, cur_rx, m);
1554 m_adj(m0, ETHER_ALIGN);
1559 (*ifp->if_input)(ifp, m);
1562 sc->sis_cdata.sis_rx_prod = i;
1566 sis_rxeoc(struct sis_softc *sc)
1573 * A frame was downloaded to the chip. It's safe for us to clean up
1578 sis_txeof(struct sis_softc *sc)
1580 struct sis_desc *cur_tx;
1584 ifp = &sc->arpcom.ac_if;
1587 * Go through our tx list and free mbufs for those
1588 * frames that have been transmitted.
1590 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1591 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1592 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1594 if (SIS_OWNDESC(cur_tx))
1597 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1600 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1602 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1603 ifp->if_collisions++;
1604 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1605 ifp->if_collisions++;
1608 ifp->if_collisions +=
1609 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1612 if (cur_tx->sis_mbuf != NULL) {
1613 m_freem(cur_tx->sis_mbuf);
1614 cur_tx->sis_mbuf = NULL;
1615 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1616 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1620 if (idx != sc->sis_cdata.sis_tx_cons) {
1621 /* we freed up some buffers */
1622 sc->sis_cdata.sis_tx_cons = idx;
1623 ifp->if_flags &= ~IFF_OACTIVE;
1626 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1632 struct sis_softc *sc = xsc;
1633 struct mii_data *mii;
1634 struct ifnet *ifp = &sc->arpcom.ac_if;
1638 mii = device_get_softc(sc->sis_miibus);
1641 if (!sc->sis_link) {
1643 if (mii->mii_media_status & IFM_ACTIVE &&
1644 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1646 if (!ifq_is_empty(&ifp->if_snd))
1650 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1655 #ifdef DEVICE_POLLING
1658 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1660 struct sis_softc *sc = ifp->if_softc;
1664 /* disable interrupts */
1665 CSR_WRITE_4(sc, SIS_IER, 0);
1667 case POLL_DEREGISTER:
1668 /* enable interrupts */
1669 CSR_WRITE_4(sc, SIS_IER, 1);
1673 * On the sis, reading the status register also clears it.
1674 * So before returning to intr mode we must make sure that all
1675 * possible pending sources of interrupts have been served.
1676 * In practice this means run to completion the *eof routines,
1677 * and then call the interrupt routine
1679 sc->rxcycles = count;
1682 if (!ifq_is_empty(&ifp->if_snd))
1685 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1688 /* Reading the ISR register clears all interrupts. */
1689 status = CSR_READ_4(sc, SIS_ISR);
1691 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1694 if (status & (SIS_ISR_RX_IDLE))
1695 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1697 if (status & SIS_ISR_SYSERR) {
1705 #endif /* DEVICE_POLLING */
1710 struct sis_softc *sc;
1715 ifp = &sc->arpcom.ac_if;
1717 /* Supress unwanted interrupts */
1718 if (!(ifp->if_flags & IFF_UP)) {
1723 /* Disable interrupts. */
1724 CSR_WRITE_4(sc, SIS_IER, 0);
1727 /* Reading the ISR register clears all interrupts. */
1728 status = CSR_READ_4(sc, SIS_ISR);
1730 if ((status & SIS_INTRS) == 0)
1734 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1739 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1742 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1745 if (status & (SIS_ISR_RX_IDLE))
1746 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1748 if (status & SIS_ISR_SYSERR) {
1754 /* Re-enable interrupts. */
1755 CSR_WRITE_4(sc, SIS_IER, 1);
1757 if (!ifq_is_empty(&ifp->if_snd))
1762 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1763 * pointers to the fragment pointers.
1766 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1768 struct sis_desc *f = NULL;
1770 int frag, cur, cnt = 0;
1773 * If there's no way we can send any packets, return now.
1775 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1779 * Start packing the mbufs in this chain into
1780 * the fragment pointers. Stop when we run out
1781 * of fragments or hit the end of the mbuf chain.
1784 cur = frag = *txidx;
1786 for (m = m_head; m != NULL; m = m->m_next) {
1787 if (m->m_len != 0) {
1788 if ((SIS_TX_LIST_CNT -
1789 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1791 f = &sc->sis_ldata.sis_tx_list[frag];
1792 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1793 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1794 bus_dmamap_load(sc->sis_tag, f->sis_map,
1795 mtod(m, void *), m->m_len,
1796 sis_dma_map_desc_ptr, f, 0);
1797 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1798 BUS_DMASYNC_PREREAD);
1800 f->sis_ctl |= SIS_CMDSTS_OWN;
1802 SIS_INC(frag, SIS_TX_LIST_CNT);
1810 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1811 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1812 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1813 sc->sis_cdata.sis_tx_cnt += cnt;
1820 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1821 * to the mbuf data regions directly in the transmit lists. We also save a
1822 * copy of the pointers since the transmit list fragment pointers are
1823 * physical addresses.
1827 sis_start(struct ifnet *ifp)
1829 struct sis_softc *sc;
1830 struct mbuf *m_head = NULL;
1839 idx = sc->sis_cdata.sis_tx_prod;
1841 if (ifp->if_flags & IFF_OACTIVE)
1845 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1846 m_head = ifq_poll(&ifp->if_snd);
1850 if (sis_encap(sc, m_head, &idx)) {
1851 ifp->if_flags |= IFF_OACTIVE;
1854 m_head = ifq_dequeue(&ifp->if_snd);
1858 * If there's a BPF listener, bounce a copy of this frame
1861 BPF_MTAP(ifp, m_head);
1868 sc->sis_cdata.sis_tx_prod = idx;
1869 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1872 * Set a timeout in case the chip goes out to lunch.
1880 struct sis_softc *sc = xsc;
1881 struct ifnet *ifp = &sc->arpcom.ac_if;
1882 struct mii_data *mii;
1887 * Cancel pending I/O and free all RX/TX buffers.
1891 mii = device_get_softc(sc->sis_miibus);
1893 /* Set MAC address */
1894 if (sc->sis_type == SIS_TYPE_83815) {
1895 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1896 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1897 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1898 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1899 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1900 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1901 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1902 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1903 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1905 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1906 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1907 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1908 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1909 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1910 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1911 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1912 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1913 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1916 /* Init circular RX list. */
1917 if (sis_list_rx_init(sc) == ENOBUFS) {
1918 if_printf(ifp, "initialization failed: "
1919 "no memory for rx buffers\n");
1926 * Init tx descriptors.
1928 sis_list_tx_init(sc);
1931 * For the NatSemi chip, we have to explicitly enable the
1932 * reception of ARP frames, as well as turn on the 'perfect
1933 * match' filter where we store the station address, otherwise
1934 * we won't receive unicasts meant for this host.
1936 if (sc->sis_type == SIS_TYPE_83815) {
1937 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1938 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1941 /* If we want promiscuous mode, set the allframes bit. */
1942 if (ifp->if_flags & IFF_PROMISC)
1943 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1945 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1948 * Set the capture broadcast bit to capture broadcast frames.
1950 if (ifp->if_flags & IFF_BROADCAST)
1951 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1953 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1956 * Load the multicast filter.
1958 if (sc->sis_type == SIS_TYPE_83815)
1959 sis_setmulti_ns(sc);
1961 sis_setmulti_sis(sc);
1963 /* Turn the receive filter on */
1964 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1967 * Load the address of the RX and TX lists.
1969 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1970 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1972 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1973 * the PCI bus. When this bit is set, the Max DMA Burst Size
1974 * for TX/RX DMA should be no larger than 16 double words.
1976 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1977 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1979 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1981 /* Accept Long Packets for VLAN support */
1982 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1984 /* Set TX configuration */
1985 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1986 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1988 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1990 /* Set full/half duplex mode. */
1991 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1992 SIS_SETBIT(sc, SIS_TX_CFG,
1993 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1994 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1996 SIS_CLRBIT(sc, SIS_TX_CFG,
1997 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1998 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2002 * Enable interrupts.
2004 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2005 #ifdef DEVICE_POLLING
2007 * ... only enable interrupts if we are not polling, make sure
2008 * they are off otherwise.
2010 if (ifp->if_flags & IFF_POLLING)
2011 CSR_WRITE_4(sc, SIS_IER, 0);
2013 #endif /* DEVICE_POLLING */
2014 CSR_WRITE_4(sc, SIS_IER, 1);
2016 /* Enable receiver and transmitter. */
2017 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2018 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2025 * Page 75 of the DP83815 manual recommends the
2026 * following register settings "for optimum
2027 * performance." Note however that at least three
2028 * of the registers are listed as "reserved" in
2029 * the register map, so who knows what they do.
2031 if (sc->sis_type == SIS_TYPE_83815) {
2032 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2033 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2034 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2035 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2036 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2039 ifp->if_flags |= IFF_RUNNING;
2040 ifp->if_flags &= ~IFF_OACTIVE;
2042 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
2048 * Set media options.
2051 sis_ifmedia_upd(struct ifnet *ifp)
2053 struct sis_softc *sc;
2054 struct mii_data *mii;
2058 mii = device_get_softc(sc->sis_miibus);
2060 if (mii->mii_instance) {
2061 struct mii_softc *miisc;
2062 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2063 mii_phy_reset(miisc);
2071 * Report current media status.
2074 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2076 struct sis_softc *sc;
2077 struct mii_data *mii;
2081 mii = device_get_softc(sc->sis_miibus);
2083 ifmr->ifm_active = mii->mii_media_active;
2084 ifmr->ifm_status = mii->mii_media_status;
2088 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2090 struct sis_softc *sc = ifp->if_softc;
2091 struct ifreq *ifr = (struct ifreq *) data;
2092 struct mii_data *mii;
2099 if (ifp->if_flags & IFF_UP) {
2102 if (ifp->if_flags & IFF_RUNNING)
2109 if (sc->sis_type == SIS_TYPE_83815)
2110 sis_setmulti_ns(sc);
2112 sis_setmulti_sis(sc);
2117 mii = device_get_softc(sc->sis_miibus);
2118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2121 error = ether_ioctl(ifp, command, data);
2131 sis_watchdog(struct ifnet *ifp)
2133 struct sis_softc *sc;
2138 if_printf(ifp, "watchdog timeout\n");
2144 if (!ifq_is_empty(&ifp->if_snd))
2149 * Stop the adapter and free any mbufs allocated to the
2153 sis_stop(struct sis_softc *sc)
2158 ifp = &sc->arpcom.ac_if;
2161 callout_stop(&sc->sis_timer);
2163 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2164 CSR_WRITE_4(sc, SIS_IER, 0);
2165 CSR_WRITE_4(sc, SIS_IMR, 0);
2166 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2168 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2169 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2174 * Free data in the RX lists.
2176 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2177 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2178 bus_dmamap_unload(sc->sis_tag,
2179 sc->sis_ldata.sis_rx_list[i].sis_map);
2180 bus_dmamap_destroy(sc->sis_tag,
2181 sc->sis_ldata.sis_rx_list[i].sis_map);
2182 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2183 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2186 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2189 * Free the TX list buffers.
2191 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2192 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2193 bus_dmamap_unload(sc->sis_tag,
2194 sc->sis_ldata.sis_tx_list[i].sis_map);
2195 bus_dmamap_destroy(sc->sis_tag,
2196 sc->sis_ldata.sis_tx_list[i].sis_map);
2197 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2198 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2202 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2206 * Stop all chip I/O so that the kernel's probe routines don't
2207 * get confused by errant DMAs when rebooting.
2210 sis_shutdown(device_t dev)
2212 struct sis_softc *sc;
2214 sc = device_get_softc(dev);