2 /* $OpenBSD: if_iwnreg.h,v 1.37 2010/02/17 18:23:00 damien Exp $ */
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #define IWN_TX_RING_COUNT 256
22 #define IWN_TX_RING_LOMARK 192
23 #define IWN_TX_RING_HIMARK 224
24 #define IWN_RX_RING_COUNT_LOG 6
25 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
27 #define IWN4965_NTXQUEUES 16
28 #define IWN5000_NTXQUEUES 20
30 #define IWN4965_NDMACHNLS 7
31 #define IWN5000_NDMACHNLS 8
33 #define IWN_SRVC_DMACHNL 9
35 #define IWN_ICT_SIZE 4096
36 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
38 /* Maximum number of DMA segments for TX. */
39 #define IWN_MAX_SCATTER 20
41 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
42 #define IWN_RBUF_SIZE (4 * 1024)
45 /* HW supports 36-bit DMA addresses. */
46 #define IWN_LOADDR(paddr) ((uint32_t)(paddr))
47 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
49 #define IWN_LOADDR(paddr) (paddr)
50 #define IWN_HIADDR(paddr) (0)
53 /* Base Address Register. */
54 #define IWN_PCI_BAR0 PCI_MAPREG_START
57 * Control and status registers.
59 #define IWN_HW_IF_CONFIG 0x000
60 #define IWN_INT_COALESCING 0x004
61 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
63 #define IWN_INT_MASK 0x00c
64 #define IWN_FH_INT 0x010
65 #define IWN_RESET 0x020
66 #define IWN_GP_CNTRL 0x024
67 #define IWN_HW_REV 0x028
68 #define IWN_EEPROM 0x02c
69 #define IWN_EEPROM_GP 0x030
70 #define IWN_OTP_GP 0x034
72 #define IWN_GP_DRIVER 0x050
73 #define IWN_UCODE_GP1_CLR 0x05c
75 #define IWN_DRAM_INT_TBL 0x0a0
76 #define IWN_GIO_CHICKEN 0x100
77 #define IWN_ANA_PLL 0x20c
78 #define IWN_HW_REV_WA 0x22c
79 #define IWN_DBG_HPET_MEM 0x240
80 #define IWN_DBG_LINK_PWR_MGMT 0x250
81 #define IWN_MEM_RADDR 0x40c
82 #define IWN_MEM_WADDR 0x410
83 #define IWN_MEM_WDATA 0x418
84 #define IWN_MEM_RDATA 0x41c
85 #define IWN_PRPH_WADDR 0x444
86 #define IWN_PRPH_RADDR 0x448
87 #define IWN_PRPH_WDATA 0x44c
88 #define IWN_PRPH_RDATA 0x450
89 #define IWN_HBUS_TARG_WRPTR 0x460
92 * Flow-Handler registers.
94 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
95 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
96 #define IWN_FH_KW_ADDR 0x197c
97 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
98 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
99 #define IWN_FH_STATUS_WPTR 0x1bc0
100 #define IWN_FH_RX_BASE 0x1bc4
101 #define IWN_FH_RX_WPTR 0x1bc8
102 #define IWN_FH_RX_CONFIG 0x1c00
103 #define IWN_FH_RX_STATUS 0x1c44
104 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
105 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
106 #define IWN_FH_TX_CHICKEN 0x1e98
107 #define IWN_FH_TX_STATUS 0x1eb0
110 * TX scheduler registers.
112 #define IWN_SCHED_BASE 0xa02c00
113 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
114 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
115 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
116 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
117 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
118 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
119 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
120 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
121 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
122 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
123 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
124 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
125 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
126 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
129 * Offsets in TX scheduler's SRAM.
131 #define IWN4965_SCHED_CTX_OFF 0x380
132 #define IWN4965_SCHED_CTX_LEN 416
133 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
134 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
135 #define IWN5000_SCHED_CTX_OFF 0x600
136 #define IWN5000_SCHED_CTX_LEN 520
137 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
138 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
141 * NIC internal memory offsets.
143 #define IWN_APMG_CLK_CTRL 0x3000
144 #define IWN_APMG_CLK_EN 0x3004
145 #define IWN_APMG_CLK_DIS 0x3008
146 #define IWN_APMG_PS 0x300c
147 #define IWN_APMG_DIGITAL_SVR 0x3058
148 #define IWN_APMG_ANALOG_SVR 0x306c
149 #define IWN_APMG_PCI_STT 0x3010
150 #define IWN_BSM_WR_CTRL 0x3400
151 #define IWN_BSM_WR_MEM_SRC 0x3404
152 #define IWN_BSM_WR_MEM_DST 0x3408
153 #define IWN_BSM_WR_DWCOUNT 0x340c
154 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
155 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
156 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
157 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
158 #define IWN_BSM_SRAM_BASE 0x3800
160 /* Possible flags for register IWN_HW_IF_CONFIG. */
161 #define IWN_HW_IF_CONFIG_4965_R (1 << 4)
162 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
163 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
164 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
165 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
166 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
167 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
168 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
170 /* Possible values for register IWN_INT_PERIODIC. */
171 #define IWN_INT_PERIODIC_DIS 0x00
172 #define IWN_INT_PERIODIC_ENA 0xff
174 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
175 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
177 /* Possible values for IWN_BSM_WR_MEM_DST. */
178 #define IWN_FW_TEXT_BASE 0x00000000
179 #define IWN_FW_DATA_BASE 0x00800000
181 /* Possible flags for register IWN_RESET. */
182 #define IWN_RESET_NEVO (1 << 0)
183 #define IWN_RESET_SW (1 << 7)
184 #define IWN_RESET_MASTER_DISABLED (1 << 8)
185 #define IWN_RESET_STOP_MASTER (1 << 9)
186 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31)
188 /* Possible flags for register IWN_GP_CNTRL. */
189 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
190 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
191 #define IWN_GP_CNTRL_INIT_DONE (1 << 2)
192 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
193 #define IWN_GP_CNTRL_SLEEP (1 << 4)
194 #define IWN_GP_CNTRL_RFKILL (1 << 27)
196 /* Possible flags for register IWN_HW_REV. */
197 #define IWN_HW_REV_TYPE_SHIFT 4
198 #define IWN_HW_REV_TYPE_MASK 0x000000f0
199 #define IWN_HW_REV_TYPE_4965 0
200 #define IWN_HW_REV_TYPE_5300 2
201 #define IWN_HW_REV_TYPE_5350 3
202 #define IWN_HW_REV_TYPE_5150 4
203 #define IWN_HW_REV_TYPE_5100 5
204 #define IWN_HW_REV_TYPE_1000 6
205 #define IWN_HW_REV_TYPE_6000 7
206 #define IWN_HW_REV_TYPE_6050 8
208 /* Possible flags for register IWN_GIO_CHICKEN. */
209 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
210 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
212 /* Possible flags for register IWN_GIO. */
213 #define IWN_GIO_L0S_ENA (1 << 1)
215 /* Possible flags for register IWN_GP_DRIVER. */
216 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
217 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
218 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
219 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2)
221 /* Possible flags for register IWN_UCODE_GP1_CLR. */
222 #define IWN_UCODE_GP1_RFKILL (1 << 1)
223 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
224 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
226 /* Possible flags/values for register IWN_LED. */
227 #define IWN_LED_BSM_CTRL (1 << 5)
228 #define IWN_LED_OFF 0x00000038
229 #define IWN_LED_ON 0x00000078
231 /* Possible flags for register IWN_DRAM_INT_TBL. */
232 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
233 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31)
235 /* Possible values for register IWN_ANA_PLL. */
236 #define IWN_ANA_PLL_INIT 0x00880300
238 /* Possible flags for register IWN_FH_RX_STATUS. */
239 #define IWN_FH_RX_STATUS_IDLE (1 << 24)
241 /* Possible flags for register IWN_BSM_WR_CTRL. */
242 #define IWN_BSM_WR_CTRL_START_EN (1 << 30)
243 #define IWN_BSM_WR_CTRL_START (1 << 31)
245 /* Possible flags for register IWN_INT. */
246 #define IWN_INT_ALIVE (1 << 0)
247 #define IWN_INT_WAKEUP (1 << 1)
248 #define IWN_INT_SW_RX (1 << 3)
249 #define IWN_INT_CT_REACHED (1 << 6)
250 #define IWN_INT_RF_TOGGLED (1 << 7)
251 #define IWN_INT_SW_ERR (1 << 25)
252 #define IWN_INT_SCHED (1 << 26)
253 #define IWN_INT_FH_TX (1 << 27)
254 #define IWN_INT_RX_PERIODIC (1 << 28)
255 #define IWN_INT_HW_ERR (1 << 29)
256 #define IWN_INT_FH_RX (1 << 31)
259 #define IWN_INT_MASK_DEF \
260 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
261 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
262 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
264 /* Possible flags for register IWN_FH_INT. */
265 #define IWN_FH_INT_TX_CHNL(x) (1 << (x))
266 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
267 #define IWN_FH_INT_HI_PRIOR (1 << 30)
268 /* Shortcuts for the above. */
269 #define IWN_FH_INT_TX \
270 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
271 #define IWN_FH_INT_RX \
272 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
274 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
275 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
276 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
277 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
279 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
280 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
281 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
282 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3
284 /* Possible flags for register IWN_FH_TX_CHICKEN. */
285 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
287 /* Possible flags for register IWN_FH_TX_STATUS. */
288 #define IWN_FH_TX_STATUS_IDLE(chnl) \
289 (1 << ((chnl) + 24) | 1 << ((chnl) + 16))
291 /* Possible flags for register IWN_FH_RX_CONFIG. */
292 #define IWN_FH_RX_CONFIG_ENA (1 << 31)
293 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
294 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
295 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
296 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12)
297 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
298 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
300 /* Possible flags for register IWN_FH_TX_CONFIG. */
301 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
302 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
304 /* Possible flags for register IWN_EEPROM. */
305 #define IWN_EEPROM_READ_VALID (1 << 0)
306 #define IWN_EEPROM_CMD (1 << 1)
308 /* Possible flags for register IWN_EEPROM_GP. */
309 #define IWN_EEPROM_GP_IF_OWNER 0x00000180
311 /* Possible flags for register IWN_OTP_GP. */
312 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16)
313 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17)
314 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20)
315 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21)
317 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
318 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
319 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
320 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
321 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
322 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
323 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
324 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
326 /* Possible flags for registers IWN_APMG_CLK_*. */
327 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
328 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
330 /* Possible flags for register IWN_APMG_PS. */
331 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
332 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
333 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
334 #define IWN_APMG_PS_PWR_SRC_VAUX 2
335 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
336 #define IWN_APMG_PS_RESET_REQ (1 << 26)
338 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
339 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
340 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \
341 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
342 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \
343 IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
345 /* Possible flags for IWN_APMG_PCI_STT. */
346 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
348 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
349 #define IWN_FW_UPDATED (1 << 31)
351 #define IWN_SCHED_WINSZ 64
352 #define IWN_SCHED_LIMIT 64
353 #define IWN4965_SCHED_COUNT 512
354 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
355 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
356 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
359 uint8_t reserved1[3];
364 } __packed segs[IWN_MAX_SCATTER];
365 /* Pad to 128 bytes. */
369 struct iwn_rx_status {
370 uint16_t closed_count;
371 uint16_t closed_rx_count;
372 uint16_t finished_count;
373 uint16_t finished_rx_count;
374 uint32_t reserved[2];
380 #define IWN_UC_READY 1
381 #define IWN_ADD_NODE_DONE 24
382 #define IWN_TX_DONE 28
383 #define IWN5000_CALIBRATION_RESULT 102
384 #define IWN5000_CALIBRATION_DONE 103
385 #define IWN_START_SCAN 130
386 #define IWN_STOP_SCAN 132
387 #define IWN_RX_STATISTICS 156
388 #define IWN_BEACON_STATISTICS 157
389 #define IWN_STATE_CHANGED 161
390 #define IWN_BEACON_MISSED 162
391 #define IWN_RX_PHY 192
392 #define IWN_MPDU_RX_DONE 193
393 #define IWN_RX_DONE 195
394 #define IWN_RX_COMPRESSED_BA 197
401 /* Possible RX status flags. */
402 #define IWN_RX_NO_CRC_ERR (1 << 0)
403 #define IWN_RX_NO_OVFL_ERR (1 << 1)
404 /* Shortcut for the above. */
405 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
406 #define IWN_RX_MPDU_MIC_OK (1 << 6)
407 #define IWN_RX_CIPHER_MASK (7 << 8)
408 #define IWN_RX_CIPHER_CCMP (2 << 8)
409 #define IWN_RX_MPDU_DEC (1 << 11)
410 #define IWN_RX_DECRYPT_MASK (3 << 11)
411 #define IWN_RX_DECRYPT_OK (3 << 11)
415 #define IWN_CMD_RXON 16
416 #define IWN_CMD_RXON_ASSOC 17
417 #define IWN_CMD_EDCA_PARAMS 19
418 #define IWN_CMD_TIMING 20
419 #define IWN_CMD_ADD_NODE 24
420 #define IWN_CMD_TX_DATA 28
421 #define IWN_CMD_LINK_QUALITY 78
422 #define IWN_CMD_SET_LED 72
423 #define IWN5000_CMD_WIMAX_COEX 90
424 #define IWN5000_CMD_CALIB_CONFIG 101
425 #define IWN5000_CMD_CALIB_RESULT 102
426 #define IWN5000_CMD_CALIB_COMPLETE 103
427 #define IWN_CMD_SET_POWER_MODE 119
428 #define IWN_CMD_SCAN 128
429 #define IWN_CMD_SCAN_RESULTS 131
430 #define IWN_CMD_TXPOWER_DBM 149
431 #define IWN_CMD_TXPOWER 151
432 #define IWN5000_CMD_TX_ANT_CONFIG 152
433 #define IWN_CMD_BT_COEX 155
434 #define IWN_CMD_GET_STATISTICS 156
435 #define IWN_CMD_SET_CRITICAL_TEMP 164
436 #define IWN_CMD_SET_SENSITIVITY 168
437 #define IWN_CMD_PHY_CALIB 176
445 /* Antenna flags, used in various commands. */
446 #define IWN_ANT_A (1 << 0)
447 #define IWN_ANT_B (1 << 1)
448 #define IWN_ANT_C (1 << 2)
450 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B)
451 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C)
452 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
454 /* Structure for command IWN_CMD_RXON. */
456 uint8_t myaddr[IEEE80211_ADDR_LEN];
458 uint8_t bssid[IEEE80211_ADDR_LEN];
460 uint8_t wlap[IEEE80211_ADDR_LEN];
463 #define IWN_MODE_HOSTAP 1
464 #define IWN_MODE_STA 3
465 #define IWN_MODE_IBSS 4
466 #define IWN_MODE_MONITOR 6
470 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
471 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
472 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
473 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
474 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
475 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
476 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
482 #define IWN_RXON_24GHZ (1 << 0)
483 #define IWN_RXON_CCK (1 << 1)
484 #define IWN_RXON_AUTO (1 << 2)
485 #define IWN_RXON_SHSLOT (1 << 4)
486 #define IWN_RXON_SHPREAMBLE (1 << 5)
487 #define IWN_RXON_NODIVERSITY (1 << 7)
488 #define IWN_RXON_ANTENNA_A (1 << 8)
489 #define IWN_RXON_ANTENNA_B (1 << 9)
490 #define IWN_RXON_TSF (1 << 15)
491 #define IWN_RXON_CTS_TO_SELF (1 << 30)
494 #define IWN_FILTER_PROMISC (1 << 0)
495 #define IWN_FILTER_CTL (1 << 1)
496 #define IWN_FILTER_MULTICAST (1 << 2)
497 #define IWN_FILTER_NODECRYPT (1 << 3)
498 #define IWN_FILTER_BSS (1 << 5)
499 #define IWN_FILTER_BEACON (1 << 6)
503 uint8_t ht_single_mask;
504 uint8_t ht_dual_mask;
505 /* The following fields are for >=5000 Series only. */
506 uint8_t ht_triple_mask;
508 uint16_t acquisition;
512 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
513 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
515 /* Structure for command IWN_CMD_ASSOCIATE. */
524 /* Structure for command IWN_CMD_EDCA_PARAMS. */
525 struct iwn_edca_params {
527 #define IWN_EDCA_UPDATE (1 << 0)
528 #define IWN_EDCA_TXOP (1 << 4)
536 } __packed ac[WME_NUM_AC];
539 /* Structure for command IWN_CMD_TIMING. */
540 struct iwn_cmd_timing {
549 /* Structure for command IWN_CMD_ADD_NODE. */
550 struct iwn_node_info {
552 #define IWN_NODE_UPDATE (1 << 0)
554 uint8_t reserved1[3];
556 uint8_t macaddr[IEEE80211_ADDR_LEN];
560 #define IWN5000_ID_BROADCAST 15
561 #define IWN4965_ID_BROADCAST 31
564 #define IWN_FLAG_SET_KEY (1 << 0)
565 #define IWN_FLAG_SET_DISABLE_TID (1 << 1)
566 #define IWN_FLAG_SET_TXRATE (1 << 2)
567 #define IWN_FLAG_SET_ADDBA (1 << 3)
568 #define IWN_FLAG_SET_DELBA (1 << 4)
572 #define IWN_KFLAG_CCMP (1 << 1)
573 #define IWN_KFLAG_MAP (1 << 3)
574 #define IWN_KFLAG_KID(kid) ((kid) << 8)
575 #define IWN_KFLAG_INVALID (1 << 11)
576 #define IWN_KFLAG_GROUP (1 << 14)
578 uint8_t tsc2; /* TKIP TSC2 */
584 /* The following 3 fields are for 5000 Series only. */
590 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19)
591 #define IWN_AMDPU_DENSITY(x) ((x) << 23)
594 uint16_t disable_tid;
602 struct iwn4965_node_info {
604 uint8_t reserved1[3];
605 uint8_t macaddr[IEEE80211_ADDR_LEN];
611 uint8_t tsc2; /* TKIP TSC2 */
619 uint16_t disable_tid;
627 #define IWN_RFLAG_CCK (1 << 1)
628 #define IWN_RFLAG_ANT(x) ((x) << 6)
630 /* Structure for command IWN_CMD_TX_DATA. */
631 struct iwn_cmd_data {
635 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
636 #define IWN_TX_NEED_RTS (1 << 1)
637 #define IWN_TX_NEED_CTS (1 << 2)
638 #define IWN_TX_NEED_ACK (1 << 3)
639 #define IWN_TX_LINKQ (1 << 4)
640 #define IWN_TX_IMM_BA (1 << 6)
641 #define IWN_TX_FULL_TXOP (1 << 7)
642 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
643 #define IWN_TX_AUTO_SEQ (1 << 13)
644 #define IWN_TX_MORE_FRAG (1 << 14)
645 #define IWN_TX_INSERT_TSTAMP (1 << 16)
646 #define IWN_TX_NEED_PADDING (1 << 20)
655 #define IWN_CIPHER_WEP40 1
656 #define IWN_CIPHER_CCMP 2
657 #define IWN_CIPHER_TKIP 3
658 #define IWN_CIPHER_WEP104 9
666 #define IWN_LIFETIME_INFINITE 0xffffffff
677 /* Structure for command IWN_CMD_LINK_QUALITY. */
678 #define IWN_MAX_TX_RETRIES 16
679 struct iwn_cmd_link_quality {
685 uint8_t antmsk_1stream;
686 uint8_t antmsk_2stream;
687 uint8_t ridx[WME_NUM_AC];
688 uint16_t ampdu_limit;
689 uint8_t ampdu_threshold;
696 } __packed retry[IWN_MAX_TX_RETRIES];
700 /* Structure for command IWN_CMD_SET_LED. */
702 uint32_t unit; /* multiplier (in usecs) */
704 #define IWN_LED_ACTIVITY 1
705 #define IWN_LED_LINK 2
712 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
713 struct iwn5000_wimax_coex {
715 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
716 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
717 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
718 #define IWN_WIMAX_COEX_ENABLE (1 << 7)
720 struct iwn5000_wimax_event {
725 } __packed events[16];
728 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
729 struct iwn5000_calib_elem {
737 struct iwn5000_calib_status {
738 struct iwn5000_calib_elem once;
739 struct iwn5000_calib_elem perd;
743 struct iwn5000_calib_config {
744 struct iwn5000_calib_status ucode;
745 struct iwn5000_calib_status driver;
749 /* Structure for command IWN_CMD_SET_POWER_MODE. */
750 struct iwn_pmgt_cmd {
752 #define IWN_PS_ALLOW_SLEEP (1 << 0)
753 #define IWN_PS_NOTIFY (1 << 1)
754 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2)
755 #define IWN_PS_PCI_PMGT (1 << 3)
756 #define IWN_PS_FAST_PD (1 << 4)
766 /* Structures for command IWN_CMD_SCAN. */
767 struct iwn_scan_essid {
770 uint8_t data[IEEE80211_NWID_LEN];
773 struct iwn_scan_hdr {
778 uint16_t quiet_threshold;
779 uint16_t crc_threshold;
781 uint32_t max_svc; /* background scans */
782 uint32_t pause_svc; /* background scans */
786 /* Followed by a struct iwn_cmd_data. */
787 /* Followed by an array of 20 structs iwn_scan_essid. */
788 /* Followed by probe request body. */
789 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */
792 struct iwn_scan_chan {
794 #define IWN_CHAN_ACTIVE (1 << 0)
795 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
800 uint16_t active; /* msecs */
801 uint16_t passive; /* msecs */
804 /* Maximum size of a scan command. */
805 #define IWN_SCAN_MAXSZ (MCLBYTES - 4)
807 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
808 #define IWN_RIDX_MAX 32
809 struct iwn4965_cmd_txpower {
817 } __packed power[IWN_RIDX_MAX + 1];
820 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
821 struct iwn5000_cmd_txpower {
822 int8_t global_limit; /* in half-dBm */
823 #define IWN5000_TXPOWER_AUTO 0x7f
824 #define IWN5000_TXPOWER_MAX_DBM 16
827 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6)
829 int8_t srv_limit; /* in half-dBm */
833 /* Structure for command IWN_CMD_BLUETOOTH. */
834 struct iwn_bluetooth {
836 #define IWN_BT_COEX_CHAN_ANN (1 << 0)
837 #define IWN_BT_COEX_BT_PRIO (1 << 1)
838 #define IWN_BT_COEX_2_WIRE (1 << 2)
841 #define IWN_BT_LEAD_TIME_DEF 30
844 #define IWN_BT_MAX_KILL_DEF 5
851 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
852 struct iwn_critical_temp {
856 /* degK <-> degC conversion macros. */
857 #define IWN_CTOK(c) ((c) + 273)
858 #define IWN_KTOC(k) ((k) - 273)
859 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
862 /* Structure for command IWN_CMD_SET_SENSITIVITY. */
863 struct iwn_sensitivity_cmd {
865 #define IWN_SENSITIVITY_DEFAULTTBL 0
866 #define IWN_SENSITIVITY_WORKTBL 1
869 uint16_t energy_ofdm;
870 uint16_t corr_ofdm_x1;
871 uint16_t corr_ofdm_mrc_x1;
872 uint16_t corr_cck_mrc_x4;
873 uint16_t corr_ofdm_x4;
874 uint16_t corr_ofdm_mrc_x4;
875 uint16_t corr_barker;
876 uint16_t corr_barker_mrc;
877 uint16_t corr_cck_x4;
878 uint16_t energy_ofdm_th;
881 /* Structures for command IWN_CMD_PHY_CALIB. */
882 struct iwn_phy_calib {
884 #define IWN4965_PHY_CALIB_DIFF_GAIN 7
885 #define IWN5000_PHY_CALIB_DC 8
886 #define IWN5000_PHY_CALIB_LO 9
887 #define IWN5000_PHY_CALIB_TX_IQ 11
888 #define IWN5000_PHY_CALIB_CRYSTAL 15
889 #define IWN5000_PHY_CALIB_BASE_BAND 16
890 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17
891 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
892 #define IWN5000_PHY_CALIB_NOISE_GAIN 19
899 struct iwn5000_phy_calib_crystal {
909 struct iwn_phy_calib_gain {
919 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
920 struct iwn_spectrum_cmd {
937 #define IWN_MEASUREMENT_BASIC (1 << 0)
938 #define IWN_MEASUREMENT_CCA (1 << 1)
939 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
940 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
941 #define IWN_MEASUREMENT_FRAME (1 << 4)
942 #define IWN_MEASUREMENT_IDLE (1 << 7)
948 /* Structure for IWN_UC_READY notification. */
949 #define IWN_NATTEN_GROUPS 5
950 struct iwn_ucode_info {
957 #define IWN_UCODE_RUNTIME 0
958 #define IWN_UCODE_INIT 9
966 /* The following fields are for UCODE_INIT only. */
972 int32_t atten[IWN_NATTEN_GROUPS][2];
975 /* Structures for IWN_TX_DONE notification. */
976 #define IWN_TX_SUCCESS 0x00
977 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
978 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
979 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
980 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
981 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
982 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
984 struct iwn4965_tx_stat {
998 struct iwn5000_tx_stat {
1019 /* Structure for IWN_BEACON_MISSED notification. */
1020 struct iwn_beacon_missed {
1021 uint32_t consecutive;
1027 /* Structure for IWN_MPDU_RX_DONE notification. */
1028 struct iwn_rx_mpdu {
1033 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1034 struct iwn4965_rx_phystat {
1040 struct iwn5000_rx_phystat {
1046 struct iwn_rx_stat {
1048 uint8_t cfg_phy_len;
1049 #define IWN_STAT_MAXLEN 20
1056 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2)
1067 #define IWN_RSSI_TO_DBM 44
1069 /* Structure for IWN_RX_COMPRESSED_BA notification. */
1070 struct iwn_compressed_ba {
1071 uint8_t macaddr[IEEE80211_ADDR_LEN];
1081 /* Structure for IWN_START_SCAN notification. */
1082 struct iwn_start_scan {
1091 /* Structure for IWN_STOP_SCAN notification. */
1092 struct iwn_stop_scan {
1100 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1101 struct iwn_spectrum_notif {
1106 #define IWN_MEASUREMENT_START 0
1107 #define IWN_MEASUREMENT_STOP 1
1118 uint8_t reserved2[3];
1123 #define IWN_MEASUREMENT_OK 0
1124 #define IWN_MEASUREMENT_CONCURRENT 1
1125 #define IWN_MEASUREMENT_CSA_CONFLICT 2
1126 #define IWN_MEASUREMENT_TGH_CONFLICT 3
1127 #define IWN_MEASUREMENT_STOPPED 6
1128 #define IWN_MEASUREMENT_TIMEOUT 7
1129 #define IWN_MEASUREMENT_FAILED 8
1132 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1133 struct iwn_rx_phy_stats {
1140 uint32_t good_crc32;
1142 uint32_t bad_fina_sync;
1143 uint32_t sfd_timeout;
1144 uint32_t fina_timeout;
1145 uint32_t no_rts_ack;
1156 struct iwn_rx_general_stats {
1163 uint32_t missed_beacons;
1164 uint32_t adc_saturated; /* time in 0.8us */
1165 uint32_t ina_searched; /* time in 0.8us */
1174 struct iwn_rx_ht_phy_stats {
1178 uint32_t good_crc32;
1181 uint32_t good_ampdu_crc32;
1187 struct iwn_rx_stats {
1188 struct iwn_rx_phy_stats ofdm;
1189 struct iwn_rx_phy_stats cck;
1190 struct iwn_rx_general_stats general;
1191 struct iwn_rx_ht_phy_stats ht;
1194 struct iwn_tx_stats {
1196 uint32_t rx_detected;
1200 uint32_t cts_timeout;
1201 uint32_t ack_timeout;
1205 uint32_t busrt_err1;
1206 uint32_t burst_err2;
1207 uint32_t cts_collision;
1208 uint32_t ack_collision;
1209 uint32_t ba_timeout;
1210 uint32_t ba_resched;
1211 uint32_t query_ampdu;
1213 uint32_t query_ampdu_frag;
1214 uint32_t query_mismatch;
1217 uint32_t bt_ht_kill;
1218 uint32_t rx_ba_resp;
1219 uint32_t reserved[2];
1222 struct iwn_general_stats {
1225 uint32_t burst_check;
1227 uint32_t reserved1[4];
1231 uint32_t ttl_tstamp;
1236 uint32_t reserved2[2];
1237 uint32_t rx_enabled;
1238 uint32_t reserved3[3];
1243 struct iwn_rx_stats rx;
1244 struct iwn_tx_stats tx;
1245 struct iwn_general_stats general;
1249 /* Firmware error dump. */
1250 struct iwn_fw_dump {
1254 uint32_t branch_link[2];
1255 uint32_t interrupt_link[2];
1256 uint32_t error_data[2];
1262 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1263 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1264 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1265 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1266 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
1267 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1268 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1270 #define IWN_FW_API(x) (((x) >> 8) & 0xff)
1273 * Offsets into EEPROM.
1275 #define IWN_EEPROM_MAC 0x015
1276 #define IWN_EEPROM_RFCFG 0x048
1277 #define IWN4965_EEPROM_DOMAIN 0x060
1278 #define IWN4965_EEPROM_BAND1 0x063
1279 #define IWN5000_EEPROM_REG 0x066
1280 #define IWN5000_EEPROM_CAL 0x067
1281 #define IWN4965_EEPROM_BAND2 0x072
1282 #define IWN4965_EEPROM_BAND3 0x080
1283 #define IWN4965_EEPROM_BAND4 0x08d
1284 #define IWN4965_EEPROM_BAND5 0x099
1285 #define IWN4965_EEPROM_BAND6 0x0a0
1286 #define IWN4965_EEPROM_BAND7 0x0a8
1287 #define IWN4965_EEPROM_MAXPOW 0x0e8
1288 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1289 #define IWN4965_EEPROM_BANDS 0x0ea
1290 /* Indirect offsets. */
1291 #define IWN5000_EEPROM_DOMAIN 0x001
1292 #define IWN5000_EEPROM_BAND1 0x004
1293 #define IWN5000_EEPROM_BAND2 0x013
1294 #define IWN5000_EEPROM_BAND3 0x021
1295 #define IWN5000_EEPROM_BAND4 0x02e
1296 #define IWN5000_EEPROM_BAND5 0x03a
1297 #define IWN5000_EEPROM_BAND6 0x041
1298 #define IWN5000_EEPROM_BAND7 0x049
1299 #define IWN6000_EEPROM_ENHINFO 0x054
1300 #define IWN5000_EEPROM_CRYSTAL 0x128
1301 #define IWN5000_EEPROM_TEMP 0x12a
1302 #define IWN5000_EEPROM_VOLT 0x12b
1304 /* Possible flags for IWN_EEPROM_RFCFG. */
1305 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1306 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1307 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1308 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1309 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1311 struct iwn_eeprom_chan {
1313 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1314 #define IWN_EEPROM_CHAN_IBSS (1 << 1)
1315 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1316 #define IWN_EEPROM_CHAN_RADAR (1 << 4)
1321 struct iwn_eeprom_enhinfo {
1323 int8_t chain[3]; /* max power in half-dBm */
1325 int8_t mimo2; /* max power in half-dBm */
1326 int8_t mimo3; /* max power in half-dBm */
1329 struct iwn5000_eeprom_calib_hdr {
1335 #define IWN_NSAMPLES 3
1336 struct iwn4965_eeprom_chan_samples {
1343 } samples[2][IWN_NSAMPLES];
1346 #define IWN_NBANDS 8
1347 struct iwn4965_eeprom_band {
1348 uint8_t lo; /* low channel number */
1349 uint8_t hi; /* high channel number */
1350 struct iwn4965_eeprom_chan_samples chans[2];
1354 * Offsets of channels descriptions in EEPROM.
1356 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1357 IWN4965_EEPROM_BAND1,
1358 IWN4965_EEPROM_BAND2,
1359 IWN4965_EEPROM_BAND3,
1360 IWN4965_EEPROM_BAND4,
1361 IWN4965_EEPROM_BAND5,
1362 IWN4965_EEPROM_BAND6,
1363 IWN4965_EEPROM_BAND7
1366 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1367 IWN5000_EEPROM_BAND1,
1368 IWN5000_EEPROM_BAND2,
1369 IWN5000_EEPROM_BAND3,
1370 IWN5000_EEPROM_BAND4,
1371 IWN5000_EEPROM_BAND5,
1372 IWN5000_EEPROM_BAND6,
1373 IWN5000_EEPROM_BAND7
1376 #define IWN_CHAN_BANDS_COUNT 7
1377 #define IWN_MAX_CHAN_PER_BAND 14
1378 static const struct iwn_chan_band {
1380 uint8_t chan[IWN_MAX_CHAN_PER_BAND];
1382 /* 20MHz channels, 2GHz band. */
1383 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1384 /* 20MHz channels, 5GHz band. */
1385 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1386 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1387 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1388 { 6, { 145, 149, 153, 157, 161, 165 } },
1389 /* 40MHz channels (primary channels), 2GHz band. */
1390 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1391 /* 40MHz channels (primary channels), 5GHz band. */
1392 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1395 #define IWN1000_OTP_NBLOCKS 3
1396 #define IWN6000_OTP_NBLOCKS 4
1397 #define IWN6050_OTP_NBLOCKS 7
1399 /* HW rate indices. */
1400 #define IWN_RIDX_CCK1 0
1401 #define IWN_RIDX_CCK11 3
1402 #define IWN_RIDX_OFDM6 4
1403 #define IWN_RIDX_OFDM54 11
1405 static const struct iwn_rate {
1409 } iwn_rates[IWN_RIDX_MAX + 1] = {
1410 { 2, 10, IWN_RFLAG_CCK },
1411 { 4, 20, IWN_RFLAG_CCK },
1412 { 11, 55, IWN_RFLAG_CCK },
1413 { 22, 110, IWN_RFLAG_CCK },
1425 #define IWN4965_MAX_PWR_INDEX 107
1428 * RF Tx gain values from highest to lowest power (values obtained from
1429 * the reference driver.)
1431 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1432 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
1433 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
1434 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
1435 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
1436 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
1437 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
1438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1440 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1441 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1444 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1445 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
1446 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
1447 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
1448 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
1449 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
1450 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
1451 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
1452 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
1453 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
1454 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1458 * DSP pre-DAC gain values from highest to lowest power (values obtained
1459 * from the reference driver.)
1461 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1462 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1463 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1464 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1465 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1466 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1467 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1468 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
1469 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
1470 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
1471 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
1474 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1475 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1476 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1477 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1478 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1479 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1480 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1481 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1482 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1483 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1484 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
1488 * Power saving settings (values obtained from the reference driver.)
1490 #define IWN_NDTIMRANGES 3
1491 #define IWN_NPOWERLEVELS 6
1492 static const struct iwn_pmgt {
1497 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
1500 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1501 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
1502 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
1503 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
1504 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
1505 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
1507 /* 3 <= DTIM <= 10 */
1509 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1510 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
1511 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
1512 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
1513 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
1514 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
1518 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1519 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
1520 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
1521 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
1522 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
1523 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
1527 struct iwn_sensitivity_limits {
1528 uint32_t min_ofdm_x1;
1529 uint32_t max_ofdm_x1;
1530 uint32_t min_ofdm_mrc_x1;
1531 uint32_t max_ofdm_mrc_x1;
1532 uint32_t min_ofdm_x4;
1533 uint32_t max_ofdm_x4;
1534 uint32_t min_ofdm_mrc_x4;
1535 uint32_t max_ofdm_mrc_x4;
1536 uint32_t min_cck_x4;
1537 uint32_t max_cck_x4;
1538 uint32_t min_cck_mrc_x4;
1539 uint32_t max_cck_mrc_x4;
1540 uint32_t min_energy_cck;
1541 uint32_t energy_cck;
1542 uint32_t energy_ofdm;
1546 * RX sensitivity limits (values obtained from the reference driver.)
1548 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1560 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
1561 120, 120, /* min = max for performance bug in DSP. */
1562 240, 240, /* min = max for performance bug in DSP. */
1572 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
1573 105, 105, /* min = max for performance bug in DSP. */
1574 220, 220, /* min = max for performance bug in DSP. */
1584 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
1596 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
1608 /* Map TID to TX scheduler's FIFO. */
1609 static const uint8_t iwn_tid2fifo[] = {
1610 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1613 /* WiFi/WiMAX coexist event priority table for 6050. */
1614 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
1615 { 0x04, 0x03, 0x00, 0x00 },
1616 { 0x04, 0x03, 0x00, 0x03 },
1617 { 0x04, 0x03, 0x00, 0x03 },
1618 { 0x04, 0x03, 0x00, 0x03 },
1619 { 0x04, 0x03, 0x00, 0x00 },
1620 { 0x04, 0x03, 0x00, 0x07 },
1621 { 0x04, 0x03, 0x00, 0x00 },
1622 { 0x04, 0x03, 0x00, 0x03 },
1623 { 0x04, 0x03, 0x00, 0x03 },
1624 { 0x04, 0x03, 0x00, 0x00 },
1625 { 0x06, 0x03, 0x00, 0x07 },
1626 { 0x04, 0x03, 0x00, 0x00 },
1627 { 0x06, 0x06, 0x00, 0x03 },
1628 { 0x04, 0x03, 0x00, 0x07 },
1629 { 0x04, 0x03, 0x00, 0x00 },
1630 { 0x04, 0x03, 0x00, 0x00 }
1633 /* Firmware errors. */
1634 static const char * const iwn_fw_errmsg[] = {
1639 "NMI_INTERRUPT_WDG",
1643 "HW_ERROR_TUNE_LOCK",
1644 "HW_ERROR_TEMPERATURE",
1645 "ILLEGAL_CHAN_FREQ",
1648 "NMI_INTERRUPT_HOST",
1649 "NMI_INTERRUPT_ACTION_PT",
1650 "NMI_INTERRUPT_UNKNOWN",
1651 "UCODE_VERSION_MISMATCH",
1652 "HW_ERROR_ABS_LOCK",
1653 "HW_ERROR_CAL_LOCK_FAIL",
1654 "NMI_INTERRUPT_INST_ACTION_PT",
1655 "NMI_INTERRUPT_DATA_ACTION_PT",
1657 "NMI_INTERRUPT_TRM",
1658 "NMI_INTERRUPT_BREAKPOINT"
1663 "ADVANCED_SYSASSERT"
1666 /* Find least significant bit that is set. */
1667 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1669 #define IWN_READ(sc, reg) \
1670 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1672 #define IWN_WRITE(sc, reg, val) \
1673 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1675 #define IWN_WRITE_1(sc, reg, val) \
1676 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1678 #define IWN_SETBITS(sc, reg, mask) \
1679 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1681 #define IWN_CLRBITS(sc, reg, mask) \
1682 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
1684 #define IWN_BARRIER_WRITE(sc) \
1685 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1686 BUS_SPACE_BARRIER_WRITE)
1688 #define IWN_BARRIER_READ_WRITE(sc) \
1689 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
1690 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)