2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/spinlock.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <bus/pci/pcireg.h>
44 #include <bus/pci/pcivar.h>
46 #include <bus/mmc/bridge.h>
47 #include <bus/mmc/mmcreg.h>
48 #include <bus/mmc/mmcbrvar.h>
53 #define DMA_BLOCK_SIZE 4096
54 #define DMA_BOUNDARY 0 /* DMA reload every 4K */
56 /* Controller doesn't honor resets unless we touch the clock register */
57 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
58 /* Controller really supports DMA */
59 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
60 /* Controller has unusable DMA engine */
61 #define SDHCI_QUIRK_BROKEN_DMA (1<<2)
62 /* Controller doesn't like to be reset when there is no card inserted. */
63 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
64 /* Controller has flaky internal state so reset it on each ios change */
65 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
66 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
67 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
68 /* Controller needs to be reset after each request to stay stable */
69 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
70 /* Controller has an off-by-one issue with timeout value */
71 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
72 /* Controller has broken read timings */
73 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
75 static const struct sdhci_device {
81 { 0x08221180, 0xffff, "RICOH R5C822 SD",
82 SDHCI_QUIRK_FORCE_DMA },
83 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
84 SDHCI_QUIRK_FORCE_DMA },
85 { 0x05501524, 0xffff, "ENE CB712 SD",
86 SDHCI_QUIRK_BROKEN_TIMINGS },
87 { 0x05511524, 0xffff, "ENE CB712 SD 2",
88 SDHCI_QUIRK_BROKEN_TIMINGS },
89 { 0x07501524, 0xffff, "ENE CB714 SD",
90 SDHCI_QUIRK_RESET_ON_IOS |
91 SDHCI_QUIRK_BROKEN_TIMINGS },
92 { 0x07511524, 0xffff, "ENE CB714 SD 2",
93 SDHCI_QUIRK_RESET_ON_IOS |
94 SDHCI_QUIRK_BROKEN_TIMINGS },
95 { 0x410111ab, 0xffff, "Marvell CaFe SD",
96 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
97 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
98 SDHCI_QUIRK_32BIT_DMA_SIZE |
99 SDHCI_QUIRK_RESET_AFTER_REQUEST },
107 struct sdhci_softc *sc;
108 device_t dev; /* Slot device */
109 u_char num; /* Slot number */
110 u_char opt; /* Slot options */
111 #define SDHCI_HAVE_DMA 1
112 uint32_t max_clk; /* Max possible freq */
113 uint32_t timeout_clk; /* Timeout freq */
114 struct resource *mem_res; /* Memory resource */
116 bus_dma_tag_t dmatag;
119 bus_addr_t paddr; /* DMA buffer address */
120 struct task card_task; /* Card presence check task */
121 struct callout card_callout; /* Card insert delay callout */
122 struct mmc_host host; /* Host parameters */
123 struct mmc_request *req; /* Current request */
124 struct mmc_command *curcmd; /* Current command of current request */
126 uint32_t intmask; /* Current interrupt mask */
127 uint32_t clock; /* Current clock freq. */
128 size_t offset; /* Data buffer offset */
129 uint8_t hostctrl; /* Current host control register */
130 u_char power; /* Current power */
131 u_char bus_busy; /* Bus busy status */
132 u_char cmd_done; /* CMD command part done flag */
133 u_char data_done; /* DAT command part done flag */
134 u_char flags; /* Request execution flags */
135 #define CMD_STARTED 1
136 #define STOP_STARTED 2
137 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */
138 struct lock lock; /* Slot lock */
142 device_t dev; /* Controller device */
143 u_int quirks; /* Chip specific quirks */
144 struct resource *irq_res; /* IRQ resource */
146 void *intrhand; /* Interrupt handle */
148 int num_slots; /* Number of slots on this controller */
149 struct sdhci_slot slots[6];
152 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
155 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
156 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
158 static inline uint8_t
159 RD1(struct sdhci_slot *slot, bus_size_t off)
161 bus_barrier(slot->mem_res, 0, 0xFF,
162 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
163 return bus_read_1(slot->mem_res, off);
167 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val)
169 bus_barrier(slot->mem_res, 0, 0xFF,
170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
171 bus_write_1(slot->mem_res, off, val);
174 static inline uint16_t
175 RD2(struct sdhci_slot *slot, bus_size_t off)
177 bus_barrier(slot->mem_res, 0, 0xFF,
178 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
179 return bus_read_2(slot->mem_res, off);
183 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val)
185 bus_barrier(slot->mem_res, 0, 0xFF,
186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
187 bus_write_2(slot->mem_res, off, val);
190 static inline uint32_t
191 RD4(struct sdhci_slot *slot, bus_size_t off)
193 bus_barrier(slot->mem_res, 0, 0xFF,
194 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
195 return bus_read_4(slot->mem_res, off);
199 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val)
201 bus_barrier(slot->mem_res, 0, 0xFF,
202 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
203 bus_write_4(slot->mem_res, off, val);
206 static int slot_printf(struct sdhci_slot *, const char *, ...)
209 /* bus entry points */
210 static int sdhci_probe(device_t dev);
211 static int sdhci_attach(device_t dev);
212 static int sdhci_detach(device_t dev);
213 static void sdhci_intr(void *);
215 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
216 static void sdhci_start(struct sdhci_slot *slot);
217 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
219 static void sdhci_card_task(void *, int);
221 /* helper routines */
222 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE)
223 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE)
224 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE)
225 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock);
226 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0);
227 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0);
230 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
235 retval = kprintf("%s-slot%d: ",
236 device_get_nameunit(slot->sc->dev), slot->num);
239 retval += kvprintf(fmt, ap);
245 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
248 kprintf("getaddr: error %d\n", error);
251 *(bus_addr_t *)arg = segs[0].ds_addr;
255 sdhci_dumpregs(struct sdhci_slot *slot)
258 "============== REGISTER DUMP ==============\n");
260 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
261 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
262 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
263 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
264 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
265 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
266 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
267 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
268 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
269 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
270 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
271 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
272 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
273 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
274 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
275 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
276 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
277 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
278 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
279 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
282 "===========================================\n");
286 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
291 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
292 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
297 /* Some controllers need this kick or reset won't work. */
298 if ((mask & SDHCI_RESET_ALL) == 0 &&
299 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
302 /* This is to force an update */
305 sdhci_set_clock(slot, clock);
308 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
310 if (mask & SDHCI_RESET_ALL) {
315 /* Wait max 100 ms */
317 /* Controller clears the bits when it's done */
318 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
321 "Reset 0x%x never completed - 0x%x.\n",
322 (int)mask, (int)res);
323 sdhci_dumpregs(slot);
332 sdhci_init(struct sdhci_slot *slot)
335 sdhci_reset(slot, SDHCI_RESET_ALL);
337 /* Enable interrupts. */
338 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
339 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
340 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
341 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
342 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
343 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
345 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
346 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
350 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
356 if (clock == slot->clock)
360 /* Turn off the clock. */
361 WR2(slot, SDHCI_CLOCK_CONTROL, 0);
362 /* If no clock requested - left it so. */
365 /* Looking for highest freq <= clock. */
367 for (clk = 1; clk < 256; clk <<= 1) {
372 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
374 /* Now we have got divider, set it. */
375 clk <<= SDHCI_DIVIDER_SHIFT;
376 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
378 clk |= SDHCI_CLOCK_INT_EN;
379 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
380 /* Wait up to 10 ms until it stabilize. */
382 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
383 & SDHCI_CLOCK_INT_STABLE)) {
386 "Internal clock never stabilised.\n");
387 sdhci_dumpregs(slot);
393 /* Pass clock signal to the bus. */
394 clk |= SDHCI_CLOCK_CARD_EN;
395 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
399 sdhci_set_power(struct sdhci_slot *slot, u_char power)
403 if (slot->power == power)
407 /* Turn off the power. */
409 WR1(slot, SDHCI_POWER_CONTROL, pwr);
410 /* If power down requested - left it so. */
414 switch (1 << power) {
415 case MMC_OCR_LOW_VOLTAGE:
416 pwr |= SDHCI_POWER_180;
418 case MMC_OCR_290_300:
419 case MMC_OCR_300_310:
420 pwr |= SDHCI_POWER_300;
422 case MMC_OCR_320_330:
423 case MMC_OCR_330_340:
424 pwr |= SDHCI_POWER_330;
427 WR1(slot, SDHCI_POWER_CONTROL, pwr);
428 /* Turn on the power. */
429 pwr |= SDHCI_POWER_ON;
430 WR1(slot, SDHCI_POWER_CONTROL, pwr);
434 sdhci_read_block_pio(struct sdhci_slot *slot)
440 buffer = slot->curcmd->data->data;
441 buffer += slot->offset;
442 /* Transfer one block at a time. */
443 left = min(512, slot->curcmd->data->len - slot->offset);
444 slot->offset += left;
446 /* If we are too fast, broken controllers return zeroes. */
447 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
449 /* Handle unalligned and alligned buffer cases. */
450 if ((intptr_t)buffer & 3) {
452 data = RD4(slot, SDHCI_BUFFER);
454 buffer[1] = (data >> 8);
455 buffer[2] = (data >> 16);
456 buffer[3] = (data >> 24);
461 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
462 (uint32_t *)buffer, left >> 2);
465 /* Handle uneven size case. */
467 data = RD4(slot, SDHCI_BUFFER);
477 sdhci_write_block_pio(struct sdhci_slot *slot)
483 buffer = slot->curcmd->data->data;
484 buffer += slot->offset;
485 /* Transfer one block at a time. */
486 left = min(512, slot->curcmd->data->len - slot->offset);
487 slot->offset += left;
489 /* Handle unalligned and alligned buffer cases. */
490 if ((intptr_t)buffer & 3) {
498 WR4(slot, SDHCI_BUFFER, data);
501 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
502 (uint32_t *)buffer, left >> 2);
505 /* Handle uneven size case. */
512 WR4(slot, SDHCI_BUFFER, data);
517 sdhci_transfer_pio(struct sdhci_slot *slot)
520 /* Read as many blocks as possible. */
521 if (slot->curcmd->data->flags & MMC_DATA_READ) {
522 while (RD4(slot, SDHCI_PRESENT_STATE) &
523 SDHCI_DATA_AVAILABLE) {
524 sdhci_read_block_pio(slot);
525 if (slot->offset >= slot->curcmd->data->len)
529 while (RD4(slot, SDHCI_PRESENT_STATE) &
530 SDHCI_SPACE_AVAILABLE) {
531 sdhci_write_block_pio(slot);
532 if (slot->offset >= slot->curcmd->data->len)
539 sdhci_card_delay(void *arg)
541 struct sdhci_slot *slot = arg;
543 taskqueue_enqueue(taskqueue_swi, &slot->card_task);
547 sdhci_card_task(void *arg, int pending)
549 struct sdhci_slot *slot = arg;
552 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
553 if (slot->dev == NULL) {
554 /* If card is present - attach mmc bus. */
555 slot->dev = device_add_child(slot->sc->dev, "mmc", -1);
556 device_set_ivars(slot->dev, slot);
558 device_probe_and_attach(slot->dev);
562 if (slot->dev != NULL) {
563 /* If no card present - detach mmc bus. */
564 device_t d = slot->dev;
567 device_delete_child(slot->sc->dev, d);
574 sdhci_probe(device_t dev)
578 uint8_t class, subclass;
581 model = (uint32_t)pci_get_device(dev) << 16;
582 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
583 subvendor = pci_get_subvendor(dev);
584 class = pci_get_class(dev);
585 subclass = pci_get_subclass(dev);
588 for (i = 0; sdhci_devices[i].model != 0; i++) {
589 if (sdhci_devices[i].model == model &&
590 (sdhci_devices[i].subvendor == 0xffff ||
591 sdhci_devices[i].subvendor == subvendor)) {
592 device_set_desc(dev, sdhci_devices[i].desc);
593 result = BUS_PROBE_DEFAULT;
597 if (result == ENXIO && class == PCIC_BASEPERIPH &&
598 subclass == PCIS_BASEPERIPH_SDHC) {
599 device_set_desc(dev, "Generic SD HCI");
600 result = BUS_PROBE_GENERIC;
607 sdhci_attach(device_t dev)
609 struct sdhci_softc *sc = device_get_softc(dev);
612 uint8_t class, subclass, progif;
613 int err, slots, bar, i;
616 model = (uint32_t)pci_get_device(dev) << 16;
617 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
618 subvendor = pci_get_subvendor(dev);
619 class = pci_get_class(dev);
620 subclass = pci_get_subclass(dev);
621 progif = pci_get_progif(dev);
622 /* Apply chip specific quirks. */
623 for (i = 0; sdhci_devices[i].model != 0; i++) {
624 if (sdhci_devices[i].model == model &&
625 (sdhci_devices[i].subvendor == 0xffff ||
626 sdhci_devices[i].subvendor == subvendor)) {
627 sc->quirks = sdhci_devices[i].quirks;
631 /* Read slots info from PCI registers. */
632 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
633 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
634 slots = PCI_SLOT_INFO_SLOTS(slots);
635 if (slots > 6 || bar > 5) {
636 device_printf(dev, "Incorrect slots information (%d, %d).\n",
642 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
643 RF_SHAREABLE | RF_ACTIVE);
644 if (sc->irq_res == NULL) {
645 device_printf(dev, "Can't allocate IRQ\n");
648 /* Scan all slots. */
649 for (i = 0; i < slots; i++) {
650 struct sdhci_slot *slot = &sc->slots[sc->num_slots];
653 SDHCI_LOCK_INIT(slot);
655 slot->num = sc->num_slots;
656 /* Allocate memory. */
657 slot->mem_rid = PCIR_BAR(bar + i);
658 slot->mem_res = bus_alloc_resource(dev,
659 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
660 if (slot->mem_res == NULL) {
661 device_printf(dev, "Can't allocate memory\n");
662 SDHCI_LOCK_DESTROY(slot);
665 /* Allocate DMA tag. */
666 err = bus_dma_tag_create(NULL,
667 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
668 BUS_SPACE_MAXADDR, NULL, NULL,
669 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
670 BUS_DMA_ALLOCNOW, &slot->dmatag);
672 device_printf(dev, "Can't create DMA tag\n");
673 SDHCI_LOCK_DESTROY(slot);
676 /* Allocate DMA memory. */
677 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
678 BUS_DMA_NOWAIT, &slot->dmamap);
680 device_printf(dev, "Can't alloc DMA memory\n");
681 SDHCI_LOCK_DESTROY(slot);
684 /* Map the memory. */
685 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
686 (void *)slot->dmamem, DMA_BLOCK_SIZE,
687 sdhci_getaddr, &slot->paddr, 0);
688 if (err != 0 || slot->paddr == 0) {
689 device_printf(dev, "Can't load DMA memory\n");
690 SDHCI_LOCK_DESTROY(slot);
693 /* Initialize slot. */
695 caps = RD4(slot, SDHCI_CAPABILITIES);
696 /* Calculate base clock frequency. */
698 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
699 if (slot->max_clk == 0) {
700 device_printf(dev, "Hardware doesn't specify base clock "
703 slot->max_clk *= 1000000;
704 /* Calculate timeout clock frequency. */
706 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
707 if (slot->timeout_clk == 0) {
708 device_printf(dev, "Hardware doesn't specify timeout clock "
711 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
712 slot->timeout_clk *= 1000;
714 slot->host.f_min = slot->max_clk / 256;
715 slot->host.f_max = slot->max_clk;
716 slot->host.host_ocr = 0;
717 if (caps & SDHCI_CAN_VDD_330)
718 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
719 if (caps & SDHCI_CAN_VDD_300)
720 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
721 if (caps & SDHCI_CAN_VDD_180)
722 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
723 if (slot->host.host_ocr == 0) {
724 device_printf(dev, "Hardware doesn't report any "
725 "support voltages.\n");
727 slot->host.caps = MMC_CAP_4_BIT_DATA;
728 if (caps & SDHCI_CAN_DO_HISPD)
729 slot->host.caps |= MMC_CAP_HSPEED;
730 /* Decide if we have usable DMA. */
731 if (caps & SDHCI_CAN_DO_DMA)
732 slot->opt |= SDHCI_HAVE_DMA;
733 if (class == PCIC_BASEPERIPH &&
734 subclass == PCIS_BASEPERIPH_SDHC &&
735 progif != PCI_SDHCI_IFDMA)
736 slot->opt &= ~SDHCI_HAVE_DMA;
737 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA)
738 slot->opt &= ~SDHCI_HAVE_DMA;
739 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA)
740 slot->opt |= SDHCI_HAVE_DMA;
742 if (bootverbose || sdhci_debug) {
743 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
744 slot->max_clk / 1000000,
745 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
746 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
747 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
748 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
749 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
750 sdhci_dumpregs(slot);
753 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
754 callout_init(&slot->card_callout);
757 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
758 /* Activate the interrupt */
759 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, sdhci_intr, sc, &sc->intrhand, NULL);
761 device_printf(dev, "Can't setup IRQ\n");
762 pci_enable_busmaster(dev);
763 /* Process cards detection. */
764 for (i = 0; i < sc->num_slots; i++) {
765 struct sdhci_slot *slot = &sc->slots[i];
767 sdhci_card_task(slot, 0);
774 sdhci_detach(device_t dev)
776 struct sdhci_softc *sc = device_get_softc(dev);
779 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
780 bus_release_resource(dev, SYS_RES_IRQ,
781 sc->irq_rid, sc->irq_res);
783 for (i = 0; i < sc->num_slots; i++) {
784 struct sdhci_slot *slot = &sc->slots[i];
788 /* XXX: need implementation of callout_drain or workaround */
789 callout_drain(&slot->card_callout);
791 taskqueue_drain(taskqueue_swi, &slot->card_task);
798 device_delete_child(dev, d);
801 sdhci_reset(slot, SDHCI_RESET_ALL);
803 bus_dmamap_unload(slot->dmatag, slot->dmamap);
804 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
805 bus_dma_tag_destroy(slot->dmatag);
806 bus_release_resource(dev, SYS_RES_MEMORY,
807 slot->mem_rid, slot->mem_res);
808 SDHCI_LOCK_DESTROY(slot);
814 sdhci_suspend(device_t dev)
816 struct sdhci_softc *sc = device_get_softc(dev);
819 err = bus_generic_suspend(dev);
822 for (i = 0; i < sc->num_slots; i++)
823 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL);
828 sdhci_resume(device_t dev)
830 struct sdhci_softc *sc = device_get_softc(dev);
833 for (i = 0; i < sc->num_slots; i++)
834 sdhci_init(&sc->slots[i]);
835 return (bus_generic_resume(dev));
839 sdhci_update_ios(device_t brdev, device_t reqdev)
841 struct sdhci_slot *slot = device_get_ivars(reqdev);
842 struct mmc_ios *ios = &slot->host.ios;
845 /* Do full reset on bus power down to clear from any state. */
846 if (ios->power_mode == power_off) {
847 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
850 /* Configure the bus. */
851 sdhci_set_clock(slot, ios->clock);
852 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
853 if (ios->bus_width == bus_width_4)
854 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
856 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
857 if (ios->timing == bus_timing_hs)
858 slot->hostctrl |= SDHCI_CTRL_HISPD;
860 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
861 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
862 /* Some controllers like reset after bus changes. */
863 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS)
864 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
871 sdhci_set_transfer_mode(struct sdhci_slot *slot,
872 struct mmc_data *data)
879 mode = SDHCI_TRNS_BLK_CNT_EN;
881 mode |= SDHCI_TRNS_MULTI;
882 if (data->flags & MMC_DATA_READ)
883 mode |= SDHCI_TRNS_READ;
885 mode |= SDHCI_TRNS_ACMD12;
886 if (slot->flags & SDHCI_USE_DMA)
887 mode |= SDHCI_TRNS_DMA;
889 WR2(slot, SDHCI_TRANSFER_MODE, mode);
893 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
895 struct mmc_request *req = slot->req;
897 uint32_t mask, state;
902 cmd->error = MMC_ERR_NONE;
904 /* This flags combination is not supported by controller. */
905 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
906 slot_printf(slot, "Unsupported response type!\n");
907 cmd->error = MMC_ERR_FAILED;
914 /* Read controller present state. */
915 state = RD4(slot, SDHCI_PRESENT_STATE);
916 /* Do not issue command if there is no card, clock or power.
917 * Controller will not detect timeout without clock active. */
918 if ((state & SDHCI_CARD_PRESENT) == 0 ||
921 cmd->error = MMC_ERR_FAILED;
927 /* Always wait for free CMD bus. */
928 mask = SDHCI_CMD_INHIBIT;
929 /* Wait for free DAT if we have data or busy signal. */
930 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
931 mask |= SDHCI_DAT_INHIBIT;
932 /* We shouldn't wait for DAT for stop commands. */
933 if (cmd == slot->req->stop)
934 mask &= ~SDHCI_DAT_INHIBIT;
935 /* Wait for bus no more then 10 ms. */
937 while (state & mask) {
939 slot_printf(slot, "Controller never released "
940 "inhibit bit(s).\n");
941 sdhci_dumpregs(slot);
942 cmd->error = MMC_ERR_FAILED;
950 state = RD4(slot, SDHCI_PRESENT_STATE);
953 /* Prepare command flags. */
954 if (!(cmd->flags & MMC_RSP_PRESENT))
955 flags = SDHCI_CMD_RESP_NONE;
956 else if (cmd->flags & MMC_RSP_136)
957 flags = SDHCI_CMD_RESP_LONG;
958 else if (cmd->flags & MMC_RSP_BUSY)
959 flags = SDHCI_CMD_RESP_SHORT_BUSY;
961 flags = SDHCI_CMD_RESP_SHORT;
962 if (cmd->flags & MMC_RSP_CRC)
963 flags |= SDHCI_CMD_CRC;
964 if (cmd->flags & MMC_RSP_OPCODE)
965 flags |= SDHCI_CMD_INDEX;
967 flags |= SDHCI_CMD_DATA;
968 if (cmd->opcode == MMC_STOP_TRANSMISSION)
969 flags |= SDHCI_CMD_TYPE_ABORT;
971 sdhci_start_data(slot, cmd->data);
973 * Interrupt aggregation: To reduce total number of interrupts
974 * group response interrupt with data interrupt when possible.
975 * If there going to be data interrupt, mask response one.
977 if (slot->data_done == 0) {
978 WR4(slot, SDHCI_SIGNAL_ENABLE,
979 slot->intmask &= ~SDHCI_INT_RESPONSE);
981 /* Set command argument. */
982 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
983 /* Set data transfer mode. */
984 sdhci_set_transfer_mode(slot, cmd->data);
985 /* Set command flags. */
986 WR1(slot, SDHCI_COMMAND_FLAGS, flags);
988 WR1(slot, SDHCI_COMMAND, cmd->opcode);
992 sdhci_finish_command(struct sdhci_slot *slot)
997 /* Interrupt aggregation: Restore command interrupt.
998 * Main restore point for the case when command interrupt
1000 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
1001 /* In case of error - reset host and return. */
1002 if (slot->curcmd->error) {
1003 sdhci_reset(slot, SDHCI_RESET_CMD);
1004 sdhci_reset(slot, SDHCI_RESET_DATA);
1008 /* If command has response - fetch it. */
1009 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1010 if (slot->curcmd->flags & MMC_RSP_136) {
1011 /* CRC is stripped so we need one byte shift. */
1013 for (i = 0; i < 4; i++) {
1014 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
1015 slot->curcmd->resp[3 - i] = (val << 8) + extra;
1019 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1021 /* If data ready - finish. */
1022 if (slot->data_done)
1027 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
1029 uint32_t target_timeout, current_timeout;
1032 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1033 slot->data_done = 1;
1037 slot->data_done = 0;
1039 /* Calculate and set data timeout.*/
1040 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1041 target_timeout = 1000000;
1043 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1044 while (current_timeout < target_timeout) {
1046 current_timeout <<= 1;
1050 /* Compensate for an off-by-one error in the CaFe chip.*/
1051 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
1054 slot_printf(slot, "Timeout too large!\n");
1057 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1062 /* Use DMA if possible. */
1063 if ((slot->opt & SDHCI_HAVE_DMA))
1064 slot->flags |= SDHCI_USE_DMA;
1065 /* If data is small, broken DMA may return zeroes instead of data, */
1066 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1068 slot->flags &= ~SDHCI_USE_DMA;
1069 /* Some controllers require even block sizes. */
1070 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1071 ((data->len) & 0x3))
1072 slot->flags &= ~SDHCI_USE_DMA;
1073 /* Load DMA buffer. */
1074 if (slot->flags & SDHCI_USE_DMA) {
1075 if (data->flags & MMC_DATA_READ) {
1076 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
1078 memcpy(slot->dmamem, data->data,
1079 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE);
1080 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE);
1082 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1083 /* Interrupt aggregation: Mask border interrupt
1084 * for the last page and unmask else. */
1085 if (data->len == DMA_BLOCK_SIZE)
1086 slot->intmask &= ~SDHCI_INT_DMA_END;
1088 slot->intmask |= SDHCI_INT_DMA_END;
1089 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1091 /* Current data offset for both PIO and DMA. */
1093 /* Set block size and request IRQ on 4K border. */
1094 WR2(slot, SDHCI_BLOCK_SIZE,
1095 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
1096 /* Set block count. */
1097 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
1101 sdhci_finish_data(struct sdhci_slot *slot)
1103 struct mmc_data *data = slot->curcmd->data;
1105 slot->data_done = 1;
1106 /* Interrupt aggregation: Restore command interrupt.
1107 * Auxillary restore point for the case when data interrupt
1108 * happened first. */
1109 if (!slot->cmd_done) {
1110 WR4(slot, SDHCI_SIGNAL_ENABLE,
1111 slot->intmask |= SDHCI_INT_RESPONSE);
1113 /* Unload rest of data from DMA buffer. */
1114 if (slot->flags & SDHCI_USE_DMA) {
1115 if (data->flags & MMC_DATA_READ) {
1116 size_t left = data->len - slot->offset;
1117 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD);
1118 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1119 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1121 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
1123 /* If there was error - reset the host. */
1124 if (slot->curcmd->error) {
1125 sdhci_reset(slot, SDHCI_RESET_CMD);
1126 sdhci_reset(slot, SDHCI_RESET_DATA);
1130 /* If we already have command response - finish. */
1136 sdhci_start(struct sdhci_slot *slot)
1138 struct mmc_request *req;
1144 if (!(slot->flags & CMD_STARTED)) {
1145 slot->flags |= CMD_STARTED;
1146 sdhci_start_command(slot, req->cmd);
1149 /* We don't need this until using Auto-CMD12 feature
1150 if (!(slot->flags & STOP_STARTED) && req->stop) {
1151 slot->flags |= STOP_STARTED;
1152 sdhci_start_command(slot, req->stop);
1156 if (sdhci_debug > 1)
1157 slot_printf(slot, "result: %d\n", req->cmd->error);
1158 if (!req->cmd->error &&
1159 (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1160 sdhci_reset(slot, SDHCI_RESET_CMD);
1161 sdhci_reset(slot, SDHCI_RESET_DATA);
1164 /* We must be done -- bad idea to do this while locked? */
1166 slot->curcmd = NULL;
1171 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1173 struct sdhci_slot *slot = device_get_ivars(reqdev);
1176 if (slot->req != NULL) {
1180 if (sdhci_debug > 1) {
1181 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1182 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1183 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1184 (req->cmd->data)?req->cmd->data->flags:0);
1191 while (slot->req != NULL) {
1192 sdhci_intr(slot->sc);
1200 sdhci_get_ro(device_t brdev, device_t reqdev)
1202 struct sdhci_slot *slot = device_get_ivars(reqdev);
1206 val = RD4(slot, SDHCI_PRESENT_STATE);
1208 return (!(val & SDHCI_WRITE_PROTECT));
1212 sdhci_acquire_host(device_t brdev, device_t reqdev)
1214 struct sdhci_slot *slot = device_get_ivars(reqdev);
1218 while (slot->bus_busy)
1219 lksleep(slot, &slot->lock, 0, "sdhciah", 0);
1222 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1228 sdhci_release_host(device_t brdev, device_t reqdev)
1230 struct sdhci_slot *slot = device_get_ivars(reqdev);
1233 /* Deactivate led. */
1234 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1242 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1245 if (!slot->curcmd) {
1246 slot_printf(slot, "Got command interrupt 0x%08x, but "
1247 "there is no active command.\n", intmask);
1248 sdhci_dumpregs(slot);
1251 if (intmask & SDHCI_INT_TIMEOUT)
1252 slot->curcmd->error = MMC_ERR_TIMEOUT;
1253 else if (intmask & SDHCI_INT_CRC)
1254 slot->curcmd->error = MMC_ERR_BADCRC;
1255 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1256 slot->curcmd->error = MMC_ERR_FIFO;
1258 sdhci_finish_command(slot);
1262 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1265 if (!slot->curcmd) {
1266 slot_printf(slot, "Got data interrupt 0x%08x, but "
1267 "there is no active command.\n", intmask);
1268 sdhci_dumpregs(slot);
1271 if (slot->curcmd->data == NULL &&
1272 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1273 slot_printf(slot, "Got data interrupt 0x%08x, but "
1274 "there is no active data operation.\n",
1276 sdhci_dumpregs(slot);
1279 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1280 slot->curcmd->error = MMC_ERR_TIMEOUT;
1281 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1282 slot->curcmd->error = MMC_ERR_BADCRC;
1283 if (slot->curcmd->data == NULL &&
1284 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1285 SDHCI_INT_DMA_END))) {
1286 slot_printf(slot, "Got data interrupt 0x%08x, but "
1287 "there is busy-only command.\n", intmask);
1288 sdhci_dumpregs(slot);
1289 slot->curcmd->error = MMC_ERR_INVALID;
1291 if (slot->curcmd->error) {
1292 /* No need to continue after any error. */
1293 sdhci_finish_data(slot);
1297 /* Handle PIO interrupt. */
1298 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1299 sdhci_transfer_pio(slot);
1300 /* Handle DMA border. */
1301 if (intmask & SDHCI_INT_DMA_END) {
1302 struct mmc_data *data = slot->curcmd->data;
1305 /* Unload DMA buffer... */
1306 left = data->len - slot->offset;
1307 if (data->flags & MMC_DATA_READ) {
1308 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1309 BUS_DMASYNC_POSTREAD);
1310 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1311 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1313 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1314 BUS_DMASYNC_POSTWRITE);
1316 /* ... and reload it again. */
1317 slot->offset += DMA_BLOCK_SIZE;
1318 left = data->len - slot->offset;
1319 if (data->flags & MMC_DATA_READ) {
1320 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1321 BUS_DMASYNC_PREREAD);
1323 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1324 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1325 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1326 BUS_DMASYNC_PREWRITE);
1328 /* Interrupt aggregation: Mask border interrupt
1329 * for the last page. */
1330 if (left == DMA_BLOCK_SIZE) {
1331 slot->intmask &= ~SDHCI_INT_DMA_END;
1332 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1335 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1337 /* We have got all data. */
1338 if (intmask & SDHCI_INT_DATA_END)
1339 sdhci_finish_data(slot);
1343 sdhci_acmd_irq(struct sdhci_slot *slot)
1347 err = RD4(slot, SDHCI_ACMD12_ERR);
1348 if (!slot->curcmd) {
1349 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1350 "there is no active command.\n", err);
1351 sdhci_dumpregs(slot);
1354 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1355 sdhci_reset(slot, SDHCI_RESET_CMD);
1359 sdhci_intr(void *arg)
1361 struct sdhci_softc *sc = (struct sdhci_softc *)arg;
1364 for (i = 0; i < sc->num_slots; i++) {
1365 struct sdhci_slot *slot = &sc->slots[i];
1369 /* Read slot interrupt status. */
1370 intmask = RD4(slot, SDHCI_INT_STATUS);
1371 if (intmask == 0 || intmask == 0xffffffff) {
1375 if (sdhci_debug > 2)
1376 slot_printf(slot, "Interrupt %#x\n", intmask);
1378 /* Handle card presence interrupts. */
1379 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1380 WR4(slot, SDHCI_INT_STATUS, intmask &
1381 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1383 if (intmask & SDHCI_INT_CARD_REMOVE) {
1384 if (bootverbose || sdhci_debug)
1385 slot_printf(slot, "Card removed\n");
1386 callout_stop(&slot->card_callout);
1387 taskqueue_enqueue(taskqueue_swi,
1390 if (intmask & SDHCI_INT_CARD_INSERT) {
1391 if (bootverbose || sdhci_debug)
1392 slot_printf(slot, "Card inserted\n");
1393 callout_reset(&slot->card_callout, hz / 2,
1394 sdhci_card_delay, slot);
1396 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1398 /* Handle command interrupts. */
1399 if (intmask & SDHCI_INT_CMD_MASK) {
1400 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1401 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1403 /* Handle data interrupts. */
1404 if (intmask & SDHCI_INT_DATA_MASK) {
1405 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1406 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1408 /* Handle AutoCMD12 error interrupt. */
1409 if (intmask & SDHCI_INT_ACMD12ERR) {
1410 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1411 sdhci_acmd_irq(slot);
1413 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1414 intmask &= ~SDHCI_INT_ACMD12ERR;
1415 intmask &= ~SDHCI_INT_ERROR;
1416 /* Handle bus power interrupt. */
1417 if (intmask & SDHCI_INT_BUS_POWER) {
1418 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1420 "Card is consuming too much power!\n");
1421 intmask &= ~SDHCI_INT_BUS_POWER;
1423 /* The rest is unknown. */
1425 WR4(slot, SDHCI_INT_STATUS, intmask);
1426 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1428 sdhci_dumpregs(slot);
1436 sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1438 struct sdhci_slot *slot = device_get_ivars(child);
1443 case MMCBR_IVAR_BUS_MODE:
1444 *(int *)result = slot->host.ios.bus_mode;
1446 case MMCBR_IVAR_BUS_WIDTH:
1447 *(int *)result = slot->host.ios.bus_width;
1449 case MMCBR_IVAR_CHIP_SELECT:
1450 *(int *)result = slot->host.ios.chip_select;
1452 case MMCBR_IVAR_CLOCK:
1453 *(int *)result = slot->host.ios.clock;
1455 case MMCBR_IVAR_F_MIN:
1456 *(int *)result = slot->host.f_min;
1458 case MMCBR_IVAR_F_MAX:
1459 *(int *)result = slot->host.f_max;
1461 case MMCBR_IVAR_HOST_OCR:
1462 *(int *)result = slot->host.host_ocr;
1464 case MMCBR_IVAR_MODE:
1465 *(int *)result = slot->host.mode;
1467 case MMCBR_IVAR_OCR:
1468 *(int *)result = slot->host.ocr;
1470 case MMCBR_IVAR_POWER_MODE:
1471 *(int *)result = slot->host.ios.power_mode;
1473 case MMCBR_IVAR_VDD:
1474 *(int *)result = slot->host.ios.vdd;
1476 case MMCBR_IVAR_CAPS:
1477 *(int *)result = slot->host.caps;
1479 case MMCBR_IVAR_TIMING:
1480 *(int *)result = slot->host.ios.timing;
1482 case MMCBR_IVAR_MAX_DATA:
1483 *(int *)result = 65535;
1490 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1492 struct sdhci_slot *slot = device_get_ivars(child);
1497 case MMCBR_IVAR_BUS_MODE:
1498 slot->host.ios.bus_mode = value;
1500 case MMCBR_IVAR_BUS_WIDTH:
1501 slot->host.ios.bus_width = value;
1503 case MMCBR_IVAR_CHIP_SELECT:
1504 slot->host.ios.chip_select = value;
1506 case MMCBR_IVAR_CLOCK:
1508 uint32_t clock = slot->max_clk;
1511 for (i = 0; i < 8; i++) {
1516 slot->host.ios.clock = clock;
1518 slot->host.ios.clock = 0;
1520 case MMCBR_IVAR_MODE:
1521 slot->host.mode = value;
1523 case MMCBR_IVAR_OCR:
1524 slot->host.ocr = value;
1526 case MMCBR_IVAR_POWER_MODE:
1527 slot->host.ios.power_mode = value;
1529 case MMCBR_IVAR_VDD:
1530 slot->host.ios.vdd = value;
1532 case MMCBR_IVAR_TIMING:
1533 slot->host.ios.timing = value;
1535 case MMCBR_IVAR_CAPS:
1536 case MMCBR_IVAR_HOST_OCR:
1537 case MMCBR_IVAR_F_MIN:
1538 case MMCBR_IVAR_F_MAX:
1539 case MMCBR_IVAR_MAX_DATA:
1545 static device_method_t sdhci_methods[] = {
1547 DEVMETHOD(device_probe, sdhci_probe),
1548 DEVMETHOD(device_attach, sdhci_attach),
1549 DEVMETHOD(device_detach, sdhci_detach),
1550 DEVMETHOD(device_suspend, sdhci_suspend),
1551 DEVMETHOD(device_resume, sdhci_resume),
1554 DEVMETHOD(bus_read_ivar, sdhci_read_ivar),
1555 DEVMETHOD(bus_write_ivar, sdhci_write_ivar),
1558 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios),
1559 DEVMETHOD(mmcbr_request, sdhci_request),
1560 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro),
1561 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host),
1562 DEVMETHOD(mmcbr_release_host, sdhci_release_host),
1567 static driver_t sdhci_driver = {
1570 sizeof(struct sdhci_softc),
1572 static devclass_t sdhci_devclass;
1575 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, NULL, NULL);