/*- * Copyright 2003 Eric Anholt. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * $FreeBSD: src/sys/dev/drm2/drm_pci.c,v 1.1 2012/05/22 11:07:44 kib Exp $ */ /** * \file drm_pci.h * \brief PCI consistent, DMA-accessible memory allocation. * * \author Eric Anholt */ #include /**********************************************************************/ /** \name PCI memory */ /*@{*/ static void drm_pci_busdma_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { drm_dma_handle_t *dmah = arg; if (error != 0) return; KASSERT(nsegs == 1, ("drm_pci_busdma_callback: bad dma segment count")); dmah->busaddr = segs[0].ds_addr; } /** * \brief Allocate a physically contiguous DMA-accessible consistent * memory block. */ drm_dma_handle_t * drm_pci_alloc(struct drm_device *dev, size_t size, size_t align, dma_addr_t maxaddr) { drm_dma_handle_t *dmah; int ret; /* Need power-of-two alignment, so fail the allocation if it isn't. */ if ((align & (align - 1)) != 0) { DRM_ERROR("drm_pci_alloc with non-power-of-two alignment %d\n", (int)align); return NULL; } dmah = kmalloc(sizeof(drm_dma_handle_t), DRM_MEM_DMA, M_ZERO | M_NOWAIT); if (dmah == NULL) return NULL; #if 0 /* HT XXX XXX XXX */ /* Make sure we aren't holding locks here */ mtx_assert(&dev->dev_lock, MA_NOTOWNED); if (mtx_owned(&dev->dev_lock)) DRM_ERROR("called while holding dev_lock\n"); mtx_assert(&dev->dma_lock, MA_NOTOWNED); if (mtx_owned(&dev->dma_lock)) DRM_ERROR("called while holding dma_lock\n"); #endif ret = bus_dma_tag_create(NULL, align, 0, /* tag, align, boundary */ maxaddr, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */ NULL, NULL, /* filtfunc, filtfuncargs */ size, 1, size, /* maxsize, nsegs, maxsegsize */ 0, /* flags */ &dmah->tag); if (ret != 0) { drm_free(dmah, DRM_MEM_DMA); return NULL; } ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_NOCACHE, &dmah->map); if (ret != 0) { bus_dma_tag_destroy(dmah->tag); drm_free(dmah, DRM_MEM_DMA); return NULL; } ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr, size, drm_pci_busdma_callback, dmah, BUS_DMA_NOWAIT); if (ret != 0) { bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map); bus_dma_tag_destroy(dmah->tag); drm_free(dmah, DRM_MEM_DMA); return NULL; } return dmah; } /** * \brief Free a DMA-accessible consistent memory block. */ void drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah) { if (dmah == NULL) return; bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map); bus_dma_tag_destroy(dmah->tag); drm_free(dmah, DRM_MEM_DMA); } /*@}*/ int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask) { device_t root; int pos; u32 lnkcap = 0, lnkcap2 = 0; *mask = 0; if (!drm_device_is_pcie(dev)) return -EINVAL; root = device_get_parent(dev->dev); pos = 0; pci_find_extcap(root, PCIY_EXPRESS, &pos); if (!pos) return -EINVAL; /* we've been informed via and serverworks don't make the cut */ if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) return -EINVAL; lnkcap = pci_read_config(root, pos + PCIER_LINKCAP, 4); lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); lnkcap &= PCIEM_LNKCAP_SPEED_MASK; lnkcap2 &= 0xfe; #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ if (lnkcap2) { /* PCIE GEN 3.0 */ if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) *mask |= DRM_PCIE_SPEED_25; if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) *mask |= DRM_PCIE_SPEED_50; if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) *mask |= DRM_PCIE_SPEED_80; } else { if (lnkcap & 1) *mask |= DRM_PCIE_SPEED_25; if (lnkcap & 2) *mask |= DRM_PCIE_SPEED_50; } DRM_INFO("probing gen 2 caps for device %x:%x = %x/%x\n", pci_get_vendor(root), pci_get_device(root), lnkcap, lnkcap2); return 0; }