pc64: An mfence is supposed to suffice for TSC_DEADLINE vs. xAPIC ordering.

pc64: An mfence is supposed to suffice for TSC_DEADLINE vs. xAPIC ordering.

* I accidentally used a too old version of the intel sdm documentation,
  which still described that complicated serialization method, but newest
  documentation claims that an mfence should be used for serializing the
  xAPIC write vs. the wrmsr to the TSC_DEADLINE register.