This commit represents a major revamping of the clock interrupt and timebase

This commit represents a major revamping of the clock interrupt and timebase
infrastructure in DragonFly.

* Rip out the existing 8254 timer 0 code, and also disable the use of
  Timer 2 (which means that the PC speaker will no longer go beep).  Timer 0
  used to represent a periodic interrupt and a great deal of code was in
  place to attempt to obtain a timebase off of that periodic interrupt.

  Timer 0 is now used in software retriggerable one-shot mode to produce
  variable-delay interrupts.  A new hardware interrupt clock abstraction
  called SYSTIMERS has been introduced which allows threads to register
  periodic or one-shot interrupt/IPI callbacks at approximately 1uS
  granularity.

  Timer 2 is now set in continuous periodic mode with a period of 65536
  and provides the timebase for the system, abstracted to 32 bits.

  All the old platform-integrated hardclock() and statclock() code has
  been rewritten.  The old IPI forwarding code has been #if 0'd out and
  will soon be entirely removed (the systimer abstraction takes care of
  multi-cpu registrations now).  The architecture-specific clkintr() now
  simply calls an entry point into the systimer and provides a Timer 0
  reload and Timer 2 timebase function API.

* On both UP and SMP systems, cpus register systimer interrupts for the Hz
  interrupt, the stat interrupt, and the scheduler round-robin interrupt.
  The abstraction is carefully designed to allow multiple interrupts occuring
  at the same time to be processed in a single hardware interrupt.  While
  we currently use IPI's to distribute requested interrupts from other cpu's,
  the intent is to use the abstraction to take advantage of per-cpu timers
  when available (e.g. on the LAPIC) in the future.

  systimer interrupts run OUTSIDE THE MP LOCK.  Entry points may be called
  from the hard interrupt or via an IPI message (IPI messages have always
  run outside the MP lock).

* Rip out timecounters and disable alternative timecounter code for other
  time sources.  This is temporary.  Eventually other time sources, such as
  the TSC, will be reintegrated as independant, parallel-running entities.
  There will be no 'time switching' per-say, subsystems will be able to
  select which timebase they wish to use.  It is desireable to reintegrate
  at least the TSC to improve [get]{micro,nano}[up]time() performance.

  WARNING: PPS events may not work properly.  They were not removed, but
  they have not been retested with the new code either.

* Remove spl protection around [get]{micro,nano}[up]time() calls, they are
  now internally protected.

* Use uptime instead of realtime in certain CAM timeout tests

* Remove struct clockframe.  Use struct intrframe everywhere where clockframe
  used to be used.

* Replace most splstatclock() protections with crit_*() protections, because
  such protections must now also protect against IPI messaging interrupts.

* Add fields to the per-cpu globaldata structure to access timebase related
  information using only a critical section rather then a mutex.  However,
  the 8254 Timer 2 access code still uses spin locks.  More work needs to
  be done here, the 'realtime' correction is still done in a single global
  'struct timespec basetime' structure.

* Remove the CLKINTR_PENDING icu and apic interrupt hacks.

* Augment the IPI Messaging code to make an intrframe available to callbacks.

* Document 8254 timing modes in i386/sai/timerreg.h.  Note that at the
  moment we assume an 8254 instead of an 8253 as we are using TIMER_SWSTROBE
  mode.  This may or may not have to be changed to an 8253 mode.

* Integrate the NTP correction code into the new timebase subsystem.

* Separate boottime from basettime.  Once boottime is believed to be stable
  it is no longer effected by NTP or other time corrections.

CAVETS:

	* PC speaker no longer works

	* Profiling interrupt rate not increased (it needs work to be
	  made operational on a per-cpu basis rather then system-wide).

	* The native timebase API is function-based, but currently hardwired.

	* There might or might not be issues with 486 systems due to the
	  timer mode I am using.