intr: Per-cpu MI interrupt information array

intr: Per-cpu MI interrupt information array

- Interrupt information is only recorded in its target CPU's interrupt
  information array.
- Interrupt threads, emergency polling threads, interrupt livelock
  processing and hardware interrupt threads scheduling only access
  the interrupt information of the CPU they are running on; they have
  already been locked to the interrupt's target CPU.
- Location of SWI information is saved in a global array swi_info_ary,
  since scheduling SWI does not necessarily happens on the CPU that
  SWI thread is running, we need a quick and correct way find the SWI
  information.
- Factor out sched_ithd_intern, which accept interrupt information
  (struct intr_info) instead of interrupt number.  Split the original
  sched_ithd() into sched_ithd_soft(), which schedules SWI thread, and
  sched_ithd_hard() which schedules hardware interrupt thread.
- vmstat(8) interrupt reporting w/ -v is augmented to print the interrupts'
  target CPU.

This paves way to the per-cpu MD interrupt description table