kernel: GC never true CPU_DISABLE_SSE checks from x86_64/vkernel64.
authorSascha Wildner <saw@online.de>
Thu, 12 Jun 2014 21:45:27 +0000 (23:45 +0200)
committerSascha Wildner <saw@online.de>
Thu, 12 Jun 2014 21:45:27 +0000 (23:45 +0200)
It is only an option in i386.

No functional changes.

Reported-by: profmakx
sys/config/LINT64
sys/platform/pc64/x86_64/machdep.c
sys/platform/pc64/x86_64/npx.c
sys/platform/vkernel64/x86_64/cpu_regs.c
sys/platform/vkernel64/x86_64/npx.c

index 7aba3d0..93b599b 100644 (file)
@@ -112,14 +112,11 @@ cpu               HAMMER_CPU
 #
 # Options for CPU features.
 #
-# CPU_DISABLE_SSE disables SSE/MMX2 instructions support.
-#
 # CPU_ENABLE_EST enables support for Enhanced SpeedStep technology
 # found in Pentium(tm) M processors.
 #
 # CPU_DISABLE_AVX disables AVX instruction set.
 # 
-#options       CPU_DISABLE_SSE
 options        CPU_DISABLE_AVX
 options                CPU_ENABLE_EST
 
index 1e27443..c0f7696 100644 (file)
@@ -144,10 +144,8 @@ static void cpu_startup(void *);
 static void pic_finish(void *);
 static void cpu_finish(void *);
 
-#ifndef CPU_DISABLE_SSE
 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
-#endif /* CPU_DISABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -2241,7 +2239,6 @@ set_regs(struct lwp *lp, struct reg *regs)
        return (0);
 }
 
-#ifndef CPU_DISABLE_SSE
 static void
 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
 {
@@ -2285,20 +2282,17 @@ set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
        for (i = 0; i < 8; ++i)
                sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
 }
-#endif /* CPU_DISABLE_SSE */
 
 int
 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
 {
        if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
                return EINVAL;
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
                                (struct save87 *)fpregs);
                return (0);
        }
-#endif /* CPU_DISABLE_SSE */
        bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
        return (0);
 }
@@ -2306,13 +2300,11 @@ fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
 int
 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
 {
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                set_fpregs_xmm((struct save87 *)fpregs,
                               &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
                return (0);
        }
-#endif /* CPU_DISABLE_SSE */
        bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
        return (0);
 }
index 02c7e66..8621419 100644 (file)
 #define        fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
 #define        fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define        frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
-#ifndef CPU_DISABLE_SSE
 #define        fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
 #define        fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
-#endif
 #ifndef  CPU_DISABLE_AVX
 #define xrstor(eax,edx,addr)   __asm __volatile(".byte 0x0f,0xae,0x2f" : : "D" (addr), "a" (eax), "d" (edx))
 #define xsave(eax,edx,addr)    __asm __volatile(".byte 0x0f,0xae,0x27" : : "D" (addr), "a" (eax), "d" (edx) : "memory")
 #define stop_emulating()        __asm("clts")
 
 typedef u_char bool_t;
-#ifndef CPU_DISABLE_SSE
 static void    fpu_clean_state(void);
 #define ldmxcsr(csr)            __asm __volatile("ldmxcsr %0" : : "m" (csr))
-#endif
 
 static struct krate badfprate = { 1 };
 
@@ -377,11 +373,8 @@ npxdna(void)
         * fnsave are broken, so our treatment breaks fnclex if it is the
         * first FPU instruction after a context switch.
         */
-       if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask)
-#ifndef CPU_DISABLE_SSE
-           && cpu_fxsr
-#endif
-       ) {
+       if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) &&
+           cpu_fxsr) {
                krateprintf(&badfprate,
                            "%s: FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
                            td->td_comm, td->td_savefpu->sv_xmm.sv_env.en_mxcsr,
@@ -435,11 +428,9 @@ fpusave(union savefpu *addr)
                xsave(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr);
        else
 #endif
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr)
                fxsave(addr);
        else
-#endif
                fnsave(addr);
 }
 
@@ -472,16 +463,16 @@ npxpush(mcontext_t *mctx)
                bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu));
                td->td_flags &= ~TDF_USINGFP;
 #ifndef CPU_DISABLE_AVX
-       if (cpu_xsave)
-               mctx->mc_fpformat = _MC_FPFMT_YMM;
-       else
+               if (cpu_xsave)
+                       mctx->mc_fpformat = _MC_FPFMT_YMM;
+               else
 #endif
-#ifndef CPU_DISABLE_SSE
-       if (cpu_fxsr)
-               mctx->mc_fpformat = _MC_FPFMT_XMM;
-       else
-#endif
-               mctx->mc_fpformat = _MC_FPFMT_387;
+               {
+                       if (cpu_fxsr)
+                               mctx->mc_fpformat = _MC_FPFMT_XMM;
+                       else
+                               mctx->mc_fpformat = _MC_FPFMT_387;
+               }
        } else {
                mctx->mc_ownedfp = _MC_FPOWNED_NONE;
                mctx->mc_fpformat = _MC_FPFMT_NODEV;
@@ -529,11 +520,8 @@ npxpop(mcontext_t *mctx)
                        npxsave(td->td_savefpu);
                KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs));
                bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
-               if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask)
-#ifndef CPU_DISABLE_SSE
-                   && cpu_fxsr
-#endif
-               ) {
+               if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) &&
+                   cpu_fxsr) {
                        krateprintf(&badfprate,
                                    "pid %d (%s) signal return from user: "
                                    "illegal FP MXCSR %08x\n",
@@ -547,7 +535,6 @@ npxpop(mcontext_t *mctx)
 }
 
 
-#ifndef CPU_DISABLE_SSE
 /*
  * On AuthenticAMD processors, the fxrstor instruction does not restore
  * the x87's stored last instruction pointer, last data pointer, and last
@@ -578,7 +565,6 @@ fpu_clean_state(void)
         */
        __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
 }
-#endif /* CPU_DISABLE_SSE */
 
 static void
 fpurstor(union savefpu *addr)
@@ -588,15 +574,11 @@ fpurstor(union savefpu *addr)
                xrstor(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr);
        else
 #endif
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                fpu_clean_state();
                fxrstor(addr);
        } else {
                frstor(addr);
        }
-#else
-       frstor(addr);
-#endif
 }
 
index 2586af3..92cdf5b 100644 (file)
 
 extern void dblfault_handler (void);
 
-#ifndef CPU_DISABLE_SSE
 static void set_fpregs_xmm (struct save87 *, struct savexmm *);
 static void fill_fpregs_xmm (struct savexmm *, struct save87 *);
-#endif /* CPU_DISABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -774,7 +772,6 @@ set_regs(struct lwp *lp, struct reg *regs)
        return (0);
 }
 
-#ifndef CPU_DISABLE_SSE
 static void
 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
 {
@@ -818,20 +815,17 @@ set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
        for (i = 0; i < 8; ++i)
                sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
 }
-#endif /* CPU_DISABLE_SSE */
 
 int
 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
 {
        if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
                return EINVAL;
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
                                (struct save87 *)fpregs);
                return (0);
        }
-#endif /* CPU_DISABLE_SSE */
        bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
        return (0);
 }
@@ -839,13 +833,11 @@ fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
 int
 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
 {
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                set_fpregs_xmm((struct save87 *)fpregs,
                               &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
                return (0);
        }
-#endif /* CPU_DISABLE_SSE */
        bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
        return (0);
 }
index ccd4b0d..38f45e8 100644 (file)
 #define        fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
 #define        fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define        frstor(addr)            __asm("frstor %0" : : "m" (*(addr)))
-#ifndef CPU_DISABLE_SSE
 #define        fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
 #define        fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
-#endif
 
 typedef u_char bool_t;
-#ifndef CPU_DISABLE_SSE
 static void    fpu_clean_state(void);
 #define ldmxcsr(csr)            __asm __volatile("ldmxcsr %0" : : "m" (csr))
-#endif
 
 int cpu_fxsr = 0;
 
@@ -88,11 +84,9 @@ static       void    fpurstor        (union savefpu *);
 
 uint32_t npx_mxcsr_mask = 0xFFBF;
 
-#ifndef CPU_DISABLE_SSE
 int mmxopt = 1;
 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
        "MMX/XMM optimized bcopy/copyin/copyout support");
-#endif
 
 static int      hw_instruction_sse;
 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
@@ -477,11 +471,7 @@ npxpush(mcontext_t *mctx)
                }
                bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
                td->td_flags &= ~TDF_USINGFP;
-               mctx->mc_fpformat =
-#ifndef CPU_DISABLE_SSE
-                       (cpu_fxsr) ? _MC_FPFMT_XMM :
-#endif
-                       _MC_FPFMT_387;
+               mctx->mc_fpformat = cpu_fxsr ? _MC_FPFMT_XMM : _MC_FPFMT_387;
        } else {
                mctx->mc_ownedfp = _MC_FPOWNED_NONE;
                mctx->mc_fpformat = _MC_FPFMT_NODEV;
@@ -543,8 +533,6 @@ npxpop(mcontext_t *mctx)
        }
 }
 
-
-#ifndef CPU_DISABLE_SSE
 /*
  * On AuthenticAMD processors, the fxrstor instruction does not restore
  * the x87's stored last instruction pointer, last data pointer, and last
@@ -575,19 +563,14 @@ fpu_clean_state(void)
         */
        __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
 }
-#endif /* CPU_DISABLE_SSE */
 
 static void
 fpurstor(union savefpu *addr)
 {
-#ifndef CPU_DISABLE_SSE
        if (cpu_fxsr) {
                fpu_clean_state();
                fxrstor(addr);
        } else {
                frstor(addr);
        }
-#else
-       frstor(addr);
-#endif
 }