drm/i915: Add Coffee Lake support
authorFrançois Tigeot <ftigeot@wolfpond.org>
Tue, 2 Jan 2018 21:25:54 +0000 (22:25 +0100)
committerFrançois Tigeot <ftigeot@wolfpond.org>
Tue, 2 Jan 2018 21:31:18 +0000 (22:31 +0100)
* This commit mostly adds PCI IDs

* Handle all Coffee Lake GPUs as Kaby Lake ones for now

sys/dev/drm/i915/i915_drv.c
sys/dev/drm/include/drm/i915_pciids.h

index 7d69eb7..0e43bfa 100644 (file)
@@ -367,6 +367,19 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+static const struct intel_device_info intel_coffeelake_info = {
+       BDW_FEATURES, \
+       .is_kabylake = 1,
+       .gen = 9,
+};
+
+static const struct intel_device_info intel_coffeelake_gt3_info = {
+       BDW_FEATURES, \
+       .is_kabylake = 1,
+       .gen = 9,
+       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -414,6 +427,9 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_KBL_GT2_IDS(&intel_kabylake_info),
        INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
        INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
        INTEL_KBL_GT2_IDS(&intel_kabylake_info),
        INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
        INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
+       INTEL_CFL_S_IDS(&intel_coffeelake_info),
+       INTEL_CFL_H_IDS(&intel_coffeelake_info),
+       INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
        {0, 0, 0}
 };
 
        {0, 0, 0}
 };
 
index 9094599..cc12f34 100644 (file)
        INTEL_KBL_GT3_IDS(info), \
        INTEL_KBL_GT4_IDS(info)
 
        INTEL_KBL_GT3_IDS(info), \
        INTEL_KBL_GT4_IDS(info)
 
+/* CFL S */
+#define INTEL_CFL_S_IDS(info) \
+       INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
+       INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
+       INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
+       INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
+       INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
+
+/* CFL H */
+#define INTEL_CFL_H_IDS(info) \
+       INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+       INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
+
+/* CFL U */
+#define INTEL_CFL_U_IDS(info) \
+       INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
+       INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
+       INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
+       INTEL_VGA_DEVICE(0x3EA5, info)  /* ULT GT3 */
+
 #endif /* _I915_PCIIDS_H */
 #endif /* _I915_PCIIDS_H */