From 24aa2e44a85bc12e46a45c21451732106bb8f88a Mon Sep 17 00:00:00 2001
From: Aaron LI <aly@aaronly.me>
Date: Sat, 5 Jun 2021 11:57:23 +0800
Subject: [PATCH] pmap: Refactor PG_*_IDX and pmap_bits_default definitions

Refactor PG_*_IDX definitions by using an enumeration, and define the
pmap_bits_default[] array with named indices, making its items more
cleaer.

In addition, drop the unused 'PG_UNUSED10_IDX' item and fix some wrong
comments.

No functional changes.
---
 sys/platform/pc64/include/pmap.h | 37 ++++++++++++++++----------------
 sys/platform/pc64/x86_64/pmap.c  | 30 ++++++++++++--------------
 2 files changed, 33 insertions(+), 34 deletions(-)

diff --git a/sys/platform/pc64/include/pmap.h b/sys/platform/pc64/include/pmap.h
index 2b6d77d6c3..bba7e6b49f 100644
--- a/sys/platform/pc64/include/pmap.h
+++ b/sys/platform/pc64/include/pmap.h
@@ -235,28 +235,29 @@ struct pv_entry_rb_tree;
 RB_PROTOTYPE2(pv_entry_rb_tree, pv_entry, pv_entry,
 	      pv_entry_compare, vm_pindex_t);
 
-/* Types of PMAP (regular, EPT Intel, NPT Amd) */
-#define	REGULAR_PMAP		0
-#define	EPT_PMAP		1
+/* Types of pmap */
+#define	REGULAR_PMAP		0	/* Regular x86 */
+#define	EPT_PMAP		1	/* Intel EPT */
 
 /* Bits indexes in pmap_bits */
-#define	TYPE_IDX		0
-#define	PG_V_IDX		1
-#define	PG_RW_IDX		2
-#define	PG_U_IDX		3
-#define	PG_A_IDX		4
-#define	PG_M_IDX		5
-#define	PG_PS_IDX		6
-#define	PG_G_IDX		7
-#define	PG_W_IDX		8
-#define	PG_MANAGED_IDX		9
-#define	PG_UNUSED10_IDX		10
-#define	PG_N_IDX		11
-#define	PG_NX_IDX		12
-#define	PG_BITS_SIZE		13
+enum {
+	TYPE_IDX = 0,		/* Pmap type */
+	PG_V_IDX,		/* Valid */
+	PG_RW_IDX,		/* Read/Write */
+	PG_U_IDX,		/* User/Supervisor */
+	PG_A_IDX,		/* Accessed */
+	PG_M_IDX,		/* Modified/Dirty */
+	PG_PS_IDX,		/* Page size */
+	PG_G_IDX,		/* Global */
+	PG_W_IDX,		/* Wired */
+	PG_MANAGED_IDX,		/* Managed */
+	PG_N_IDX,		/* Non-cacheable */
+	PG_NX_IDX,		/* Non-execute */
+	PG_BITS_SIZE,
+};
 
 #define PROTECTION_CODES_SIZE	8
-#define PAT_INDEX_SIZE  	8
+#define PAT_INDEX_SIZE		8
 
 #define PM_PLACEMARKS		64		/* 16 @ 4 zones */
 #define PM_NOPLACEMARK		((vm_pindex_t)-1)
diff --git a/sys/platform/pc64/x86_64/pmap.c b/sys/platform/pc64/x86_64/pmap.c
index d9f8a2c991..b4bf39bc5e 100644
--- a/sys/platform/pc64/x86_64/pmap.c
+++ b/sys/platform/pc64/x86_64/pmap.c
@@ -274,23 +274,21 @@ static pt_entry_t *msgbufmap, *ptmmap;
 struct msgbuf *msgbufp=NULL;
 
 /*
- * PMAP default PG_* bits. Needed to be able to add
- * EPT/NPT pagetable pmap_bits for the VMM module
+ * PG_* bits for regular (x86) pmap.
  */
-__read_frequently static uint64_t pmap_bits_default[] = {
-		REGULAR_PMAP,			/* TYPE_IDX		0 */
-		X86_PG_V,			/* PG_V_IDX		1 */
-		X86_PG_RW,			/* PG_RW_IDX		2 */
-		X86_PG_U,			/* PG_U_IDX		3 */
-		X86_PG_A,			/* PG_A_IDX		4 */
-		X86_PG_M,			/* PG_M_IDX		5 */
-		X86_PG_PS,			/* PG_PS_IDX3		6 */
-		X86_PG_G,			/* PG_G_IDX		7 */
-		X86_PG_AVAIL1,			/* PG_AVAIL1_IDX	8 */
-		X86_PG_AVAIL2,			/* PG_AVAIL2_IDX	9 */
-		X86_PG_AVAIL3,			/* PG_AVAIL3_IDX	10 */
-		X86_PG_NC_PWT | X86_PG_NC_PCD,	/* PG_N_IDX		11 */
-		X86_PG_NX,			/* PG_NX_IDX		12 */
+__read_frequently static uint64_t pmap_bits_default[PG_BITS_SIZE] = {
+	[TYPE_IDX]	= REGULAR_PMAP,
+	[PG_V_IDX]	= X86_PG_V,
+	[PG_RW_IDX]	= X86_PG_RW,
+	[PG_U_IDX]	= X86_PG_U,
+	[PG_A_IDX]	= X86_PG_A,
+	[PG_M_IDX]	= X86_PG_M,
+	[PG_PS_IDX]	= X86_PG_PS,
+	[PG_G_IDX]	= X86_PG_G,
+	[PG_W_IDX]	= X86_PG_AVAIL1,
+	[PG_MANAGED_IDX] = X86_PG_AVAIL2,
+	[PG_N_IDX]	= X86_PG_NC_PWT | X86_PG_NC_PCD,
+	[PG_NX_IDX]	= X86_PG_NX,
 };
 
 /*
-- 
2.41.0