2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
32 #ifndef _SIBA_SIBAVAR_H_
33 #define _SIBA_SIBAVAR_H_
35 #include <sys/param.h>
37 #include <sys/limits.h>
39 #include <machine/bus.h>
45 * Internal definitions shared by siba(4) driver implementations.
48 struct siba_addrspace;
53 int siba_probe(device_t dev);
54 int siba_attach(device_t dev);
55 int siba_detach(device_t dev);
57 uint16_t siba_get_bhnd_mfgid(uint16_t ocp_vendor);
59 struct siba_core_id siba_parse_core_id(uint32_t idhigh, uint32_t idlow,
60 u_int core_idx, int unit);
62 int siba_add_children(device_t bus,
63 const struct bhnd_chipid *chipid);
65 struct siba_devinfo *siba_alloc_dinfo(device_t dev,
66 const struct siba_core_id *core_id);
67 void siba_free_dinfo(device_t dev,
68 struct siba_devinfo *dinfo);
70 struct siba_port *siba_dinfo_get_port(struct siba_devinfo *dinfo,
71 bhnd_port_type port_type, u_int port_num);
73 struct siba_addrspace *siba_find_port_addrspace(struct siba_port *port,
76 int siba_append_dinfo_region(struct siba_devinfo *dinfo,
77 bhnd_port_type port_type, u_int port_num,
78 u_int region_num, uint8_t sid, uint32_t base,
79 uint32_t size, uint32_t bus_reserved);
81 u_int siba_admatch_offset(uint8_t addrspace);
82 int siba_parse_admatch(uint32_t am, uint32_t *addr,
85 /* Sonics configuration register blocks */
86 #define SIBA_CFG_NUM_2_2 1 /**< sonics <= 2.2 maps SIBA_CFG0. */
87 #define SIBA_CFG_NUM_2_3 2 /**< sonics <= 2.3 maps SIBA_CFG0 and SIBA_CFG1 */
88 #define SIBA_CFG_NUM_MAX SIBA_CFG_NUM_2_3 /**< maximum number of supported config
91 /** siba(4) address space descriptor */
92 struct siba_addrspace {
93 uint32_t sa_base; /**< base address */
94 uint32_t sa_size; /**< size */
95 u_int sa_region_num; /**< bhnd region id */
96 uint8_t sa_sid; /**< siba-assigned address space ID */
97 int sa_rid; /**< bus resource id */
99 STAILQ_ENTRY(siba_addrspace) sa_link;
102 /** siba(4) port descriptor */
104 bhnd_port_type sp_type; /**< port type */
105 u_int sp_num; /**< port number */
106 u_int sp_num_addrs; /**< number of address space mappings */
108 STAILQ_HEAD(, siba_addrspace) sp_addrs; /**< address spaces mapped to this port */
112 * siba(4) per-core identification info.
114 struct siba_core_id {
115 struct bhnd_core_info core_info; /**< standard bhnd(4) core info */
116 uint16_t sonics_vendor; /**< OCP vendor identifier used to generate
117 * the JEDEC-106 bhnd(4) vendor identifier. */
118 uint8_t sonics_rev; /**< sonics backplane revision code */
119 uint8_t num_addrspace; /**< number of address ranges mapped to
121 uint8_t num_cfg_blocks; /**< number of Sonics configuration register
122 blocks mapped to the core's enumeration
127 * siba(4) per-device info
129 struct siba_devinfo {
130 struct resource_list resources; /**< per-core memory regions. */
131 struct siba_core_id core_id; /**< core identification info */
133 struct siba_port device_port; /**< device port holding ownership
134 * of all siba address space
135 * entries for this core. */
137 /** SIBA_CFG* register blocks */
138 struct bhnd_resource *cfg[SIBA_CFG_NUM_MAX];
140 /** SIBA_CFG* resource IDs */
141 int cfg_rid[SIBA_CFG_NUM_MAX];
145 /** siba(4) per-instance state */
147 struct bhnd_softc bhnd_sc; /**< bhnd state */
150 #endif /* _SIBA_SIBAVAR_H_ */